LTC1264-7_技术文档

LTC1264-7

Linear Phase, Group Delay

Equalized, 8th Order

Lowpass Filter

U

DESCRIPTIO

EATURE

S

F

■

Steeper Roll-Off Than Bessel Filters

High Speed: f_C≤ 200kHz

Phase Equalized Filter in a 14-Pin Package

Phase and Group Delay Response Fully Tested

Transient Response Exhibits 5% Overshoot and

No Ringing

The LTC1264-7 is a clock-tunable monolithic 8th order

lowpass filter with linear passband phase and flat group

delay. The amplitude response approximates a maximally

flat passband and exhibits steeper roll-off than an equiva-

lent 8th order Bessel filter. For instance, at twice the cutoff

frequency the filter attains 28dB attenuation (vs 12dB for

Bessel), while at three times the cutoff frequency the filter

attains 55dB attenuation (vs 30dB for Bessel). The cutoff

frequencyoftheLTC1264-7istunedviaanexternalTTLor

CMOS clock.

■

65dB THD or Better Throughout a 100kHz Passband

No External Components Needed

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PPLICATI

S

A

■

The clock-to-cutoff frequency ratio of the LTC1264-7 can

be set to 25:1 (pin 10 to V⁺) or 50:1 (pin 10 to V^–).

Data Communication Filters

Time Delay Networks

Phase Matched Filters

When the filter operates at clock-to-cutoff frequency ratio

of 25:1, the input is double-sampled to lower the risk of

aliasing.

The LTC1264-7 is optimized for speed. Depending on the

operating conditions, cutoff frequencies between 200kHz

and250kHzcanbeobtained.(PleaserefertothePassband

vs Clock Frequency graphs.)

The LTC1264-7 is pin-compatible with the LTC1064-X

series.

U

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TYPICAL APPLICATI

4-Level PAM Eye Diagram

200kHz Linear Phase Lowpass Filter

1

2

3

4

5

6

7

14

13

12

11

10

9

V

IN

–8V

LTC1264-7

f

= 5MHz

8V

CLK

8V

V

OUT

8

1264-7 TA01

NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A

0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED

CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE

OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT

1264-7 TA02

500ns/DIV

PIN AND THE f

LINE.

f_CLK= 5MHz

CLK

f

_C= 200kHz

1

LTC1264-7

W W W

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(Note 1)

ABSOLUTE AXI U RATI GS

Total Supply Voltage (V⁺to V^–) .......................... 16.5V

Power Dissipation............................................. 400mW

Burn-In Voltage ................................................... 16.5V

Voltage at Any Input ..... (V^–– 0.3V) ≤ V_IN≤ (V⁺+ 0.3V)

Storage Temperature Range ............... – 65°C to 150°C

Operating Temperature Range

LTC1264-7C ...................................... – 40°C to 85°C

LTC1264-7M ................................... – 55°C to 125°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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/O

PACKAGE RDER I FOR ATIO

TOP VIEW

ORDER PART

NUMBER

NC

1

2

3

4

5

6

7

8

16 OUT (C)

1

2

3

4

5

6

7

OUT (C)

NC

14

13

12

11

10

9

NC

V

15 NC

–

IN

V

IN

–

GND

14

V

GND

+

LTC1264-7CN

LTC1264-7CJ

LTC1264-7MJ

LTC1264-7CS

+

V

13 NC

12

f

V

CLK

NC

f

CLK

25/50

NC

11 25/50

10 NC

V

LP (A)

OUT

LP (A)

NC

8

R

(A)

IN

R

(A)

9

V

OUT

IN

J PACKAGE

N PACKAGE

14-LEAD CERAMIC DIP 14-LEAD PLASTIC DIP

S PACKAGE

16-LEAD PLASTIC SOL

T_JMAX= 150°C, θ_JA= 65°C/W (J )

T_JMAX= 110°C, θ_JA= 65°C/W (N )

T_JMAX= 110°C, θ_JA= 85°C/W

ELECTRICAL CHARACTERISTICS

V_S= ±7.5V, R_L= 10k, T_A= 25°C, f_CUTOFF= 100kHz or 50kHz, f_CLK= 2.5MHz, TTL or CMOS level (maximum clock rise or fall

time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Passband Gain

0.1Hz ≤ f ≤ 0.25 f

CUTOFF

f

= 25kHz, (f / f ) = 25:1

●

–0.50

–0.10

0.50

dB

TEST

CLK

C

Gain at 0.50 f

Gain at 0.75 f

(Note 3)

f

= 50kHz, (f / f ) = 25:1

●

–0.50

–0.65

–1.5

0.20

0.30

0.1

dB

CUTOFF

TEST

CLK

C

= 25kHz, (f / f ) = 50:1

–0.15

–1.0

CLK

C

= 75kHz, (f / f ) = 25:1

●

CUTOFF

TEST

CLK

C

Gain at f

f

= 100kHz, (f / f ) = 25:1

●

– 3.7

– 4.5

– 3.0

–1.9

– 2.3

dB

CUTOFF

TEST

CLK

C

= 50kHz, (f / f ) = 50:1

CLK

C

Gain at 2.0 f

f

= 200kHz, (f / f ) = 25:1

●

–34

–28

–30

–20

–27

dB

CUTOFF

TEST

CLK

C

= 100kHz, (f / f ) = 50:1

CLK

C

Gain with f

= 20kHz

= 400kHz, V = ±2.375V

f

= 200Hz, (f / f ) = 50:1

–0.7

–0.2

–3.5

–0.3

0.15

–2.70

0.1

0.5

–1.4

dB

CLK

TEST

CLK

C

= 8kHz, (f / f ) = 25:1

S

TEST

CLK

C

= 16kHz, (f / f ) = 25:1

CLK

C

Gain with f

= 4MHz

f

= 160kHz, V = 1V

TEST IN RMS

CLK

(f /f ) = 25:1, T = 0°C to 70°C

0.00±1.0

dB

CLK

C

A

(f /f ) = 25:1

●

3.0

CLK

C

Phase Factor (F )

Phase = 180° – F (f/f )

(Note 1)

(f / f ) = 25:1, f ≤ f

407 ± 2

388 ± 2

Deg

CLK

C

CUTOFF

(f / f ) = 50:1, f ≤ f

C

CLK C

(f / f ) = 25:1, f ≤ f

●

392

374

423

414

CLK

C

(f / f ) = 50:1, f ≤ f

CLK

C

Phase Nonlinearity

(Note 1)

(f / f ) = 25:1, f ≤ f

±1.0

%

CLK

C

CUTOFF

(f / f ) = 50:1, f ≤ f

CLK

C

(f / f ) = 25:1, f ≤ f

●

±2.0

CLK

C

(f / f ) = 50:1, f ≤ f

CLK

C

2

LTC1264-7

ELECTRICAL CHARACTERISTICS

V_S= ±7.5V, R_L= 10k, T_A= 25°C, f_CUTOFF= 100kHz or 50kHz, f_CLK= 2.5MHz, TTL or CMOS level (maximum clock rise or fall

time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified.

PARAMETER

Group Delay (t )

CONDITIONS

(f / f ) = 25:1, f ≤ f

MIN

TYP

11.3

21.6

MAX

UNITS

µs

d

CLK

C

CUTOFF

t = (F/360)(1/f );

(f / f ) = 50:1, f ≤ f

d

C

CLK C

(Note 2, 3)

(f / f ) = 25:1, f ≤ f

●

10.9

20.8

11.7

22.9

CLK

C

(f / f ) = 50:1, f ≤ f

CLK

C

Group Delay Ripple

(Note 2)

(f / f ) = 25:1, f ≤ f

±1.0

%

CLK

C

CUTOFF

(f / f ) = 50:1, f ≤ f

CLK

C

(f / f ) = 25:1, f ≤ f

●

±2.0

CLK

C

(f / f ) = 50:1, f ≤ f

CLK

C

Input Frequency Range

(Table 9, 10)

(f / f ) = 25:1

<f

CLK

<f /2

CLK

kHz

CLK

C

(f / f ) = 50:1

CLK

C

Maximum f

V = Single 5V (GND = 2V)

2

3

5

MHz

CLK

S

V = ±5V

S

V = ±7.5V

S

Clock Feedthrough

Wideband Noise

25:1, ±7.5V, f = f

120

µV

CLK

RMS

V = Single 5V

140 ± 5%

160 ± 5%

175 ± 5%

µV

S

RMS

kΩ

(1Hz ≤ f < f

)

CLK

V = ±5V

S

V = ±7.5V

S

Input Impedance

30

50

75

Output DC Voltage Swing

(Note 4)

V = ±2.375V

±1.0

±2.3

±3.8

V

S

V = ±5V

●

±2.0

±3.0

S

V = ±7.5V

S

Output DC Offset

25:1, V = ±5V

±100

±220

mV

S

(f

CLK

= 1MHz)

50:1, V = ±5V

S

Output DC Offset TempCo

25:1, V = ±5V

±200

µV/°C

S

50:1, V = ±5V

S

Power Supply Current

V = ±2.375V

11

14

17

22

23

26

28

32

mA

S

(f

CLK

= 1MHz)

●

V = ±5V

S

V = ±7.5V

S

Power Supply Range

The denotes specifications which apply over the full operating temperature range.

Note 1: Input frequencies, f, are linearly phase shifted through the filter as long as f ≤ f ;

±2.375

±8

V

●

180

C

f

= 2.5MHz

CLK

f = cutoff frequency.

C

(f /f ) = 25:1

C

90

Figure 1 curve (A) shows the typical phase response of an LTC1264-7 operating at

f

= 2.5MHz, f = 100kHz. An endpoint straight line, curve (B), depicts the ideal linear

CLK

C

0

phase response of the filter. It is described by: phase shift = 180° – F (f/f ); f ≤ f .

C

F is arbitrarily called the “phase factor” expressed in degrees. The phase factor together

with the specified deviation from the ideal straight line allows the calculation of the phase

at a given frequency. Note, the maximum phase nonlinearity, Figure 1, occurs at the vicinity

B

–90

A

–180

–270

–360

of f = 0.25 f and = 0.75 f . Example: The phase shift at 70kHz of the LTC1264-7 shown in

C

Figure 1 is: phase shift = 180° – 407° (70kHz/100kHz) ± nonlinearity

= –

104.9° ± 1% or –104.9° ± 1.05°.

Note 2: Group delay and group delay deviation are calculated from the measured phase

factor and phase deviation specifications.

0

10 20 30 40 50 60 70 80 90 100

FREQUENCY (kHz)

Note 3: The filter cutoff frequency is abbreviated as f

or f .

C

CUTOFF

LTC1264-7 F01

Note 4: The AC swing is typically 9V , 5.6V , 1.8V with ±7.5V, ±5V, ±2.5V supply

P-P

respectively. For more information refer to the THD + Noise vs Input graphs.

Figure 1. Phase Response in the Passband (Note 1)

3

LTC1264-7

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TYPICAL PERFOR A CE CHARACTERISTICS

Phase Factor vs f_CLK

(Typical Unit)

Phase Factor vs f_CLK

(Typical Unit)

Gain vs Frequency

10

0

460

450

440

V

= ±7.5V

S

V

= ±7.5V

V = ±7.5V

S

f

= 1MHz

CLK

(f /f ) = 25:1

(f /f ) = 50:1

CLK C

CLK

C

T

= 25°C

A

70°C

0°C

–10

–20

–30

–40

–50

–60

–70

–80

430

420

410

400

390

380

370

440

25°C

430

420

410

400

50:1

25:1

0°C

–90

–100

390

1

10

100

1000

0

5

0

5

1

2

3

4

1

2

3

4

f

(MHz)

f

(MHz)

CLK

FREQUENCY (kHz)

CLK

1264-7 G01

1264-7 G02

1264-7 G03

Phase Factor vs f_CLK(Min and

Max Representative Units)

Phase Factor vs f_CLK(Min and

Max Representative Units)

425

450

445

440

V

= ±5V

V

= ±7.5V

S

(f /f ) = 25:1

CLK

C

CLK

C

420

415

410

405

400

395

T

= 25°C

T

= 25°C

A

435

430

425

420

415

410

405

400

395

0

1.0

1.5

(MHz)

2.0

2.5

3.0

0.5

0

3

4

5

1

2

f

(MHz)

CLK

1264-7 G05

1264-7 G04

Passband Gain and Phase

3

2

3

180

135

90

180

135

90

2

1

45

0

GAIN

0

–1

–2

–1

–2

–45

–90

–3

–4

–5

–6

–7

–3

–4

–5

–6

–7

PHASE

–135

V

= ±7.5V

V

= ±7.5V

S

–180

–225

–270

–180

–225

–270

f

= 2.5MHz

f

= 2.5MHz

CLK

C

CLK

= 100kHz

= 50kHz

C

(f /f ) = 25:1

(f /f ) = 50:1

CLK C

CLK

C

10 20 30 40 50 60 70 80 90 100 110

5

10 15 20 25 30 35 40 45 50 55

FREQUENCY (kHz)

1264-7 G06

1264-7 G07

4

LTC1264-7

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Passband Gain vs f_CLK

Passband Gain vs f_CLKat 85°C

5

4

5

4

5

4

V

= ±7.5V

V

= ±7.5V

V = ±7.5V

S

A. f

B. f

C. f

D. f

E. f

= 1MHz

= 2MHz

= 3MHz

= 4MHz

= 5MHz

A. f

B. f

C. f

D. f

E. f

= 1MHz

= 2MHz

= 3MHz

= 4MHz

= 5MHz

A. f

B. f

= 4MHz

= 5MHz

S

CLK

(f /f ) = 25:1

(f /f ) = 50:1

(f /f ) = 25:1

CLK C

CLK

A

C

CLK

A

C

T

= 25°C

T

= 25°C

3

2

3

2

3

2

CLK

1

0

A

B

–1

–2

–3

–4

–5

–1

–2

–3

–4

–5

–1

–2

–3

–4

–5

C

D

E

A

B

C

B

D E

100

10

100

1000

10

1000

10

100

FREQUENCY (kHz)

1000

FREQUENCY (kHz)

1264-7 G08

1264-7 G09

1264-7 G10

Gain vs Frequency

Passband Gain vs f_CLKat 85°C

Gain vs Frequency

10

0

10

0

5

4

V

= ±5V

A. f

B. f

C. f

= 1MHz

= 2MHz

= 3MHz

S

CLK

(f /f ) = 25:1

CLK

C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

3

2

1

0

–1

–2

–3

–4

–5

V

f

= ±7.5V

= 5MHz

V

f

= ±5V

A

B

C

S

CLK

S

= 3MHz

CLK

(f /f ) = 25:1

CLK

C

CLK

C

T

= 25°C

T

= 25°C

A

10

100

1000

10

100

1000

10

100

1000

FREQUENCY (kHz)

1264-7 G12

1264-7 G13

1264-7 G11

Maximum Passband vs

Temperature

Gain vs f_CLK

Passband Gain vs f_CLK

2

1

10

0

5

4

A. f

B. f

C. f

D. f

= 0.5MHz

= 1.0MHz

= 1.5MHz

= 2.0MHz

V

= SINGLE 5V

CLK

S

(f /f ) = 25:1

CLK

C

AGND = 2V

= 25°C

A

B

–10

–20

–30

–40

–50

–60

–70

–80

–90

3

T

A

B

C

0

2

1

–1

A. f

B. f

C. f

= 0.5MHz

= 1MHz

= 2MHz

0

CLK

A. T = 70°C

A

–2 B. T = –40°C

A

–1

–2

–3

–4

–5

–3

V

= SINGLE 5V

V

f

= SINGLE 5V

= 2MHz

S

C

D

S

CLK

A

B

(f /f ) = 25:1

CLK

C

–4

–5

AGND = 2V

= 25°C

(f /f ) = 25:1

CLK

C

T

AGND = 2V

A

1

10

FREQUENCY (kHz)

100

10

100

200

10

100

200

FREQUENCY (kHz)

1264-7 G16

1264-7 G14

1264-7 G15

5

LTC1264-7

TYPICAL PERFOR A CE CHARACTERISTICS

U W

Maximum Passband vs

Temperature

Gain vs f_CLK

Passband Gain vs f_CLK

10

0

1.0

0.5

5

4

A. f

B. f

C. f

= 0.5MHz

= 1MHz

= 2MHz

CLK

A. f

B. f

C. f

D. f

= 0.5MHz

= 1.0MHz

= 1.5MHz

= 2.0MHz

V

= SINGLE 5V

C

CLK

S

A

B

(f /f ) = 50:1

CLK

AGND = 2V

= 25°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

3

2

0

T

A

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

A

B

C

1

A. T = 70°C

A

0

B. T = –40°C

A

–1

–2

–3

–4

–5

V =SINGLE 5V

S

V

f

= SINGLE 5V

= 2MHz

S

CLK

(f /f ) = 50:1

CLK

C

B

A

C

D

AGND = 2V

(f /f ) = 50:1

CLK

C

T

= 25°C

AGND = 2V

A

10

100

200

5

10

100

1

10

FREQUENCY (kHz)

50

FREQUENCY (kHz)

1264-7 G17

1264-7 G18

1264-7 G19

Delay vs f_CLK

THD vs Frequency

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

30

25

60

50

V

f

= ±5V

= 1V

V

= ±7.5V

V

= ±7.5V

S

IN

S

A

(f /f ) = 25:1

CLK

(f /f ) = 50:1

CLK

RMS

C

= 1MHz

T

= 25°C

T

A

= 25°C

CLK

A

(f /f ) = 25:1

CLK

C

(5 REPRESENTA-

TIVE UNITS)

A. f

B. f

C. f

D. f

= 1MHz

= 2MHz

= 3MHz

= 4MHz

20

15

40

30

CLK

A. f

B. f

C. f

D. f

= 1MHz

= 2MHz

= 3MHz

= 4MHz

CLK

B

C

D

C

D

10

5

20

10

0

20 40 60 80 100 120 140 160 180 200 220

INPUT FREQUENCY (kHz)

1

10

FREQUENCY (kHz)

50

10 20 30 40 50 60 70 80 90 100 110

INPUT FREQUENCY (kHz)

1264-7 G22

1264-7 G20

1264-7 G21

THD vs Frequency

THD + Noise vs Input

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

–40

–45

A

B

f

= 1kHz

IN

A. V = ±5V

S

B. V = ±7.5V

S

V

f

= ±7.5V

= 1V

V

f

= SINGLE 5V

S

IN

S

f

= 1MHz

= 0.5V

CLK

RMS

IN

RMS

= 500kHz

(f /f ) = 25:1

= 2.5MHz

CLK C

–50

–55

–60

–65

–70

–75

–80

–85

–90

CLK

(f /f ) = 25:1

CLK

C

(f /f ) = 25:1

CLK C

(5 REPRESENTA-

TIVE UNITS)

AGND = 2V

(5 REPRESENTA-

TIVE UNITS)

1

10

FREQUENCY (kHz)

100

1

10

20

0.1

1

5

FREQUENCY (kHz)

INPUT AMPLITUDE (V

)

RMS

1264-7 G23

1264-7 G24

1264-7 G25

6

LTC1264-7

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Power Supply Current vs Power

Supply Voltage

THD + Noise vs Input

Phase Matching vs Frequency

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

48

44

40

36

32

28

24

20

16

12

8

5

4

3

2

1

0

A

B

A. PIN 3 AT 2.5V

B. PIN 3 AT 2V

PHASE DIFFERENCE BETWEEN

ANY TWO UNITS (SAMPLE OF

50 REPRESENTATIVE UNITS)

f

= 1MHz

CLK

V

CLK

≥ ±5V

S

f

≤ 2.5MHz

(f /f ) = 25:1 OR 50:1

CLK

C

T

= 0°C TO 70°C

A

–55°C

25°C

125°C

V

= SINGLE 5V

S

f

= 500kHz

CLK

IN

4

= 1kHz

0

6

8

10 12 14 16 18 20 22 24

50m

0.1

INPUT AMPLITUDE (V

1

0 2

4

0

0.2

0.4

0.6

0.8

1.0

)

TOTAL POWER SUPPLY VOLTAGE (V)

RMS

FREQUENCY (f

/FREQUENCY)

CUTOFF

1264-7 G26

1264-7 G28

1264-7 G27

Table 1. Passband Gain and Phase

V_S= ±7.5V, (f_CLK/f_C) = 25:1, T_A= 25°C

Table 2. Passband Gain and Phase

V_S= ±7.5V, (f_CLK/f_C) = 50:1, T_A= 25°C

FREQUENCY (kHz)

GAIN (dB)

PHASE (DEG)

FREQUENCY (kHz)

GAIN (dB)

PHASE (DEG)

f

= 1MHz (Typical Unit)

f

= 1MHz (Typical Unit)

CLK

0.000

10.000

20.000

30.000

40.000

0.064

180.00

81.14

–19.18

–120.63

–221.78

0.000

5.000

10.000

15.000

20.000

– 0.048

– 0.351

– 1.253

– 3.348

180.00

84.51

–10.87

–105.53

–199.61

0.058

– 0.639

– 2.741

= 2MHz (Typical Unit)

0.000

20.000

40.000

60.000

80.000

– 0.006

– 0.164

– 0.958

– 3.003

180.00

79.42

–22.13

–124.09

–225.01

0.000

10.000

20.000

30.000

40.000

– 0.008

– 0.237

– 1.105

– 3.238

180.00

83.39

–13.09

–108.91

–204.09

= 3MHz (Typical Unit)

0.000

15.000

30.000

45.000

60.000

0.044

– 0.065

– 0.863

– 3.022

180.00

81.04

–18.64

–118.48

–217.67

0.000

30.000

60.000

90.000

120.000

– 0.067

– 0.287

– 0.944

– 2.545

180.00

77.49

–25.54

–128.51

–230.19

= 4MHz (Typical Unit)

0.000

20.000

40.000

60.000

80.000

0.071

0.039

– 0.664

– 2.755

180.00

78.04

–25.06

–128.54

–231.42

0.000

40.000

80.000

120.000

160.000

– 0.031

– 0.078

– 0.332

– 1.275

180.00

75.23

–30.06

–135.27

–239.76

= 5MHz (Typical Unit)

0.000

25.000

50.000

75.000

100.000

0.089

180.00

74.36

–32.41

–139.33

–246.01

0.000

50.000

100.000

150.000

200.000

0.073

0.365

0.686

0.521

180.00

71.77

–37.11

–146.19

–255.85

0.141

– 1.437

– 2.421

7

LTC1264-7

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Table 3. Passband Gain and Phase

V_S= ±5V, (f_CLK/f_C) = 25:1, T_A= 25°C

Table 4. Passband Gain and Phase

V_S= ±5V, (f_CLK/f_C) = 50:1, T_A= 25°C

FREQUENCY (kHz)

GAIN (dB)

PHASE (DEG)

FREQUENCY (kHz) GAIN (dB)

PHASE (DEG)

f

= 1MHz (Typical Unit)

f

= 1MHz (Typical Unit)

CLK

0.000

10.000

20.000

30.000

40.000

0.081

180.00

80.94

–19.54

–121.10

–222.28

0.000

5.000

10.000

15.000

20.000

0.032

– 0.249

– 1.135

– 3.225

180.00

84.60

–10.65

–105.20

–199.22

0.071

– 0.631

– 2.732

= 2MHz (Typical Unit)

0.000

20.000

40.000

60.000

80.000

– 0.016

– 0.211

– 0.968

– 2.864

180.00

78.78

–23.21

–125.42

–226.47

0.000

10.000

20.000

30.000

40.000

0.101

– 0.043

– 0.864

– 3.021

180.00

82.47

–15.45

–113.28

–210.54

= 3MHz (Typical Unit)

0.000

30.000

60.000

90.000

120.000

– 0.006

– 0.044

– 0.369

– 1.507

180.00

76.07

–28.54

–133.27

–237.35

0.000

15.000

30.000

45.000

60.000

0.125

180.00

77.88

–25.31

–128.74

–231.29

0.043

– 0.753

– 2.987

Table 6. Passband Gain and Phase

V_S= Single 5V, (f_CLK/f_C) = 50:1, T_A= 25°C

Table 5. Passband Gain and Phase

V_S= Single 5V, (f_CLK/f_C) = 25:1, T_A= 25°C

FREQUENCY (kHz)

GAIN (dB)

PHASE (DEG)

FREQUENCY (kHz)

GAIN (dB)

PHASE (DEG)

f

= 0.5MHz (Typical Unit)

f

= 0.5MHz (Typical Unit)

CLK

0.000

2.500

5.000

7.500

10.000

0.075

– 0.217

– 1.108

– 3.198

180.00

84.79

–10.40

–105.10

–199.26

0.000

5.000

10.000

15.000

20.000

0.161

180.00

81.47

–18.52

–119.79

–220.82

0.166

– 0.515

– 2.598

= 1MHz (Typical Unit)

f

= 1MHz (Typical Unit)

0.000

5.000

10.000

15.000

20.000

0.114

– 0.122

– 0.988

– 3.111

180.00

83.96

–11.88

–107.02

–201.63

0.000

10.000

20.000

30.000

40.000

0.125

0.043

– 0.706

– 2.781

180.00

80.23

–20.75

–122.53

–223.59

= 1.5MHz (Typical Unit)

f

= 1.5MHz (Typical Unit)

0.000

7.500

15.000

22.500

30.000

0.174

0.066

– 0.744

– 2.949

180.00

81.36

–17.84

–117.12

–215.79

0.000

15.000

30.000

45.000

60.000

0.061

– 0.096

– 0.741

– 2.432

180.00

78.49

–23.82

–126.47

–228.12

= 2MHz (Typical Unit)

0.000

10.000

20.000

30.000

40.000

0.232

180.00

75.98

–29.26

–134.63

–239.09

0.000

20.000

40.000

60.000

80.000

0.151

180.00

75.03

–31.15

–137.86

–244.58

0.219

0.321

– 0.599

– 3.031

0.203

– 0.838

8

LTC1264-7

U

PI FU CTIO S

age is recommended. The analog ground plane should be

connected to any digital ground at a single point. For dual

supply operation, pin 3 should be connected to the analog

ground plane. For single supply operation pin 3 should be

biased at 1/2 supply and should be bypassed to the analog

ground plane with at least a 1µF capacitor (Figure 3). For

single 5V operation at the highest f_CLKof 2MHz, pin 3

should be biased at 2V. This minimizes passband gain and

phase variations.

Power Supply Pins (4, 12)

The V⁺(pin 4) and the V ^–(pin 12) should each be

bypassed with a 0.1µF capacitor to an adequate analog

ground. The filter’s power supplies should be isolated

from other digital or high voltage analog supplies. A low

noise linear supply is recommended. Using a switching

power supply will lower the signal-to-noise ratio of the

filter. The supply during power-up should have a slew rate

less than 1V/µs. When V⁺is applied before V^–and V^–is

allowed to go above ground, a signal diode should clamp

V^–to prevent latch-up. Figures 2 and 3 show typical

connections for dual and single supply operation.

Ratio Input Pin (10)

The DC level at this pin determines the ratio of the clock

frequency to the cutoff frequency of the filter. Pin 10 at V⁺

gives a 25:1 ratio and pin 10 at V^–gives a 50:1 ratio. For

single supply operation the ratio is 25:1 when pin 10 is at

V⁺and 50:1 when pin 10 is at ground. When pin 10 is not

tied to ground, it should be bypassed to analog ground

with a 0.1µF capacitor. If the DC level at pin 10 is switched

mechanically or electrically at slew rates greater than

1V/µs while the device is operating, a 10k resistor should

be connected between pin 10 and the DC source.

Clock Input Pin (11)

Any TTL or CMOS clock source with a square-wave output

and 50% duty cycle (±10%) is an adequate clock source

for the device. The power supply for the clock source

should not be the filter’s power supply. The analog ground

for the filter should be connected to clock’s ground at a

single point only. Table 7 shows the clock’s low and high

levelthresholdvaluesforadualorsinglesupplyoperation.

A pulse generator can be used as a clock source provided

thehighlevelONtimeisgreaterthan0.1µs.Sinewavesare

not recommended for clock input frequencies less than

100kHz, since excessively slow clock rise or fall times

generate internal clock jitter (maximum clock rise or fall

time ≤ 1µs). The clock signal should be routed from the

rightsideoftheICpackageandperpendiculartoittoavoid

couplingtoanyinputoroutputanalogsignalpath. A200Ω

resistor between clock source and pin 11 will slow down

the rise and fall times of the clock to further reduce charge

coupling (Figures 2 and 3).

–

V

1

2

3

4

5

6

7

14

13

12

11

10

9

V

0.1µF

IN

200Ω

+

LTC1264-7

CLOCK SOURCE

+

V

0.1µF

+

GND

DIGITAL SUPPLY

8

V

1264-7 F02

OUT

Figure 2. Dual Supply Operation for an f_{CLK CUTOFF}

/f

= 25:1

1

2

3

4

5

6

7

14

13

12

11

10

9

Table 7. Clock Source High and Low Threshold Levels

V

IN

POWER SUPPLY

HIGH LEVEL

LOW LEVEL

Dual Supply = ±7.5V

Dual Supply = ±5V

Dual Supply = ±2.5V

Single Supply = 12V

Single Supply = 5V

≥ 2.18V

≥ 1.45V

≥ 0.73V

≥ 7.80V

≥ 1.45V

≤ 0.5V

≤ –2.0V

≤ 6.5V

200Ω

+

V

LTC1264-7

CLOCK SOURCE

+

0.1µF

V

+

GND

DIGITAL SUPPLY

10k

≤ 0.5V

8

+

Analog Ground Pins (3, 5)

1µF

V

OUT

The filter performance depends on the quality of the

analog signal ground. For either dual or single supply

operation, an analog ground plane surrounding the pack-

1264-7 F03

Figure 3. Single Supply Operation for an f_CLK/f_CUTOFF= 25:1

9

LTC1264-7

U

PI FU CTIO S

distortion an output buffer is required. A noninverting

buffer, Figure 4, can be used provided that its input

common-mode range is well within the filter’s output

swing. Pin 6 is an intermediate filter output providing an

unspecified 6th order lowpass filter. Pin 6 should not be

loaded.

Filter Input Pin (2)

Theinputpinisconnectedinternallythrougha50kresistor

tied to the inverting input of an op amp.

Filter Output Pins (9, 6)

Pin 9 is the specified output of the filter; it can typically

source 3mA and sink 1mA. Driving coaxial cables or

resistive loads less than 20k will degrade the total har-

monic distortion of the filter. When evaluating the device’s

External Connection Pins (7, 14)

Pins 7 and 14 should be connected together. In a printed

circuit board the connection should be done under the IC

package through a short trace surrounded by the analog

ground plane.

–

LT1220

NC Pin (1, 5, 8, 13)

1k

+

Pins 1, 5, 8 and 13 are not connected to any internal circuit

point on the device and should be preferably tied to analog

ground.

1264-7 F04

Figure 4. Buffer for Filter Output

O U

W

U

PPLICATI

A

S I FOR ATIO

Clock Feedthrough

clock feedthrough, if bothersome, can be greatly reduced

by adding a simple R/C lowpass network at the output of

the filter pin (9). This R/C will completely eliminate any

switching transients.

ClockfeedthroughisdefinedastheRMSvalueoftheclock

frequency and its harmonics that are present at the filter’s

output pin (9). The clock feedthrough is tested with the

input pin (2) grounded and it depends on PC board layout

and on the value of the power supplies. With proper layout

techniques the values of the clock feedthrough are shown

in Table 8.

Wideband Noise

The wideband noise of the filter is the total RMS value of

the device’s noise spectral density and it is used to

determine the operating signal-to-noise ratio. Most of its

frequency contents lie within the filter passband and it

cannot be reduced with post filtering. For instance, the

Table 8. Clock Feedthrough

V

25:1

50:1

S

LTC1264-7 wideband noise at ±5V supply is 160µV_RMS

,

Single 5V

±5V

±7.5V

100µV

120µV

100µV

400µV

RMS

145µV_RMSof which have frequency contents from DC up

to the filter’s cutoff frequency. The total wideband noise

(µV_RMS) is nearly independent of the value of the clock.

The clock feedthrough specifications are not part of the

wideband noise.

1000µV

RMS

Note: The clock feedthrough at 25:1 is imbedded in the wideband

noise of the filter. Clock waveform is a square wave.

Any parasitic switching transients during the rise and fall

edges of the incoming clock are not part of the clock

feedthroughspecifications. Switchingtransientshavefre-

quency contents much higher than the applied clock; their

amplitude strongly depends on scope probing techniques

as well as grounding and power supply bypassing. The

Speed Limitations

To avoid op amp slew rate limiting at maximum clock

frequencies, the signal amplitude should be kept below a

specified level as shown in Table 9.

10

LTC1264-7

O U

W

U

PPLICATI

S I FOR ATIO

A

Table 9. Maximum V_INvs V_Sand Clock

Aliasing

POWER SUPPLY

±7.5V

MAXIMUM f

MAXIMUM V

CLK

IN

Aliasing is an inherent phenomenon of sampled data

systems and it occurs when input frequencies close to the

sampling frequency are applied. For the LTC1264-7 case

at 50:1, an input signal whose frequency is in the range of

5.0MHz

4.5MHz

4.0MHz

≥ 3.5MHz

3.0MHz

≥ 3.0MHz

2.0MHz

1.6V

2.0V

2.5V

1.6V

(f ≥ 160kHz)

RMS IN

(f ≥ 160kHz)

RMS IN

(f ≥ 160kHz)

RMS IN

(f ≥ 500kHz)

RMS IN

±5V

1.6V

0.7V

(f ≥ 100kHz)

RMS IN

(f ≥ 500kHz)

RMS IN

f

_CLK±10%, will be aliased back into the filter’s passband.

If, for instance, an LTC1264-7 operating with a 100kHz

clock and 2kHz cutoff frequency receives a 95kHz 10mV

input signal, a 5kHz 56µV_RMSalias signal will appear at its

output. When the LTC1264-7 operates with a clock-to-

cutoff frequency of 25:1, aliasing occurs at twice the clock

frequency. Table 10 shows details.

Single 5V

0.5V

(f ≥ 400kHz)

RMS IN

Transient Response

Table 10. Aliasing (f_CLK= 100kHz )

INPUT FREQUENCY

(V = 1V

OUTPUT LEVEL

OUTPUT FREQUENCY

(Aliased Frequency

,

RMS

(Relative to Input,

IN

f

= f

± f

)

0dB = 1V

(dB)

)

f

= ABS [f

± f ])

CLK IN

IN

CLK

(kHz)

OUT

RMS

OUT

(kHz)

25:1, f

= 4kHz

CUTOFF

175 (or 225)

180 (or 220)

185 (or 215)

190 (or 210)

–76

– 69

– 62

– 43

25

20

15

10

10µs/DIV

195 (or 205)

– 7

5

INPUT = 10kHz ± 3V

f

_CLK= 2.5MHz

50:1, f

= 2kHz

CUTOFF

RATIO = 25:1

75 (or 125)

80 (or 120)

85 (or 115)

90 (or 110)

95 (or 105)

99 (or 101)

–96

– 90

– 82

– 72

– 45

0

25

20

15

10

5

Figure 5.

1

t

s

OUTPUT

INPUT

90%

50%

10%

Table 11. Transient Response of LTC Lowpass Filters

DELAY

TIME*

(SEC)

RISE

SETTLING OVER-

TIME** TIME*** SHOOT

t

d

LOWPASS FILTER

(SEC)

(%)

0.5

0

LTC1064-3 Bessel

LTC1164-5 Bessel

LTC1164-6 Bessel

0.50/f

0.43/f

0.34/f

0.80/f

0.85/f

1.15/f

C

1

t

r

LTC1264-7 Linear Phase

LTC1164-7 Linear Phase

LTC1064-7 Linear Phase

1.15/f

1.20/f

0.36/f

0.39/f

2.05/f

2.20/f

5

C

0.36

CUTOFF

RISE TIME (t ) =

±5%

r

f

LTC1164-5 Butterworth

0.80/f

0.48/f

2.40/f

11

C

2

SETTLING TIME (t ) =

s

(TO 1% of OUTPUT)

±5%

f

LTC1164-6 Elliptic

LTC1064-4 Elliptic

LTC1064-1 Elliptic

0.85/f

0.90/f

0.85/f

0.54/f

4.30/f

4.50/f

6.50/f

18

20

CUTOFF

C

1.15

CUTOFF

TIME DELAY (t ) = GROUP DELAY ≈

(TO 50% OF OUTPUT)

d

1164-7 F06

f

C

* To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5%

Figure 6.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

11

LTC1264-7

U

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTIO

J Package

14-Lead Ceramic DIP

0.785

0.200

(5.080)

MAX

(19.939)

MAX

0.005

(0.127)

MIN

0.290 – 0.320

(7.366 – 8.128)

14

13

12

11

10

9

8

0.015 – 0.060

(0.381 – 1.524)

0.220 – 0.310

0.025

(5.588 – 7.874)

(0.635)

RAD TYP

0.008 – 0.018

0° – 15°

(0.203 – 0.460)

2

3

4

5

6

1

7

0.098

(2.489)

MAX

0.385 ± 0.025

0.038 – 0.068

0.100 ± 0.010

(2.540 ± 0.254)

0.125

(3.175)

MIN

(9.779 ± 0.635)

(0.965 – 1.727)

0.014 – 0.026

J14 0392

(0.360 – 0.660)

N Package

14-Lead Plastic DIP

0.770

0.065

(19.558)

MAX

(1.651)

TYP

0.300 – 0.325

(7.620 – 8.255)

0.045 – 0.065

(1.143 – 1.651)

0.015

(0.380)

MIN

14

13

12

11

10

9

8

7

0.130 ± 0.005

(3.302 ± 0.127)

0.260 ± 0.010

(6.604 ± 0.254)

0.009 – 0.015

(0.229 – 0.381)

+0.025

1

2

3

5

6

4

0.325

–0.015

0.075 ± 0.015

(1.905 ± 0.381)

0.018 ± 0.003

(0.457 ± 0.076)

0.125

(3.175)

MIN

+0.635

8.255

(

)

–0.381

0.100 ± 0.010

(2.540 ± 0.254)

S Package

16-Lead Plastic SOL

0.398 – 0.413

(10.109 – 10.490)

0.291 – 0.299

(7.391 – 7.595)

15 14

12

10

11

9

16

13

0.037 – 0.045

(0.940 – 1.143)

0.093 – 0.104

(2.362 – 2.642)

0.005

0.010 – 0.029

(0.254 – 0.737)

× 45°

(0.127)

RAD MIN

0° – 8° TYP

0.394 – 0.419

(10.007 – 10.643)

SEE NOTE

0.050

(1.270)

TYP

0.004 – 0.012

(0.102 – 0.305)

0.009 – 0.013

(0.229 – 0.330)

SEE NOTE

0.014 – 0.019

0.016 – 0.050

(0.406 – 1.270)

(0.356 – 0.482)

TYP

NOTE:

PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.

2

3

5

7

8

1

4

6

SOL16 0392

LT/GP 1292 10K REV 0

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

12

●

(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977

LINEAR TECHNOLOGY CORPORATION 1992


型号：	LTC1264-7
厂家：	Linear
描述：	Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter 线性相位，群延迟扳平，第8阶低通滤波器
文件：	总12页 (文件大小：302K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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