LT4351CMS [Linear]
MOSFET Diode-OR Controller; MOSFET二极管或控制器
| 型号： | LT4351CMS |
| 厂家： | 
Linear |
| 描述： | MOSFET Diode-OR Controller |
| 文件： | 总20页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4351
MOSFET Diode-OR Controller
U
FEATURES
DESCRIPTIO
■
Low Loss Replacement for ORing Diode in Multiple
The LT4351 creates a near-ideal diode using external
single or back-to-back N-channel MOSFETs. This ideal
diode function permits low loss ORing of multiple power
sources. Power sources can easily be ORed together to
increase total system power and reliability with minimal
effect on supply voltage or efficiency. Disparate power
supplies can be efficiently ORed together.
Sourced Power Supplies
■
External N-Channel MOSFETs for High Current
Capability
■
Internal Boost Regulator Supply for MOSFET
Gate Drive
Wide Input Range: 1.2V to 18V
■
■
Fast Switching MOSFET Gate Control
The IC monitors the input supply with respect to the load
and turns on the MOSFET(s) when the input supply is
higher. If the MOSFET’s RDS(ON) is sufficiently small, the
LT4351 will regulate the voltage across the MOSFET(s) to
15mV. A STATUS pin indicates the MOSFET on state.
■
Input Under and Overvoltage Detection
■
STATUS and FAULT Outputs for Monitoring
■
Internal MOSFET Gate Clamp
Available in a 10-pin MSOP
■
U
An internal boost regulator generates the MOSFET gate
drive voltage. Low operating voltage allows for OR’ing of
supplies as low as 1.2V.
APPLICATIO S
■
Paralleled Power Supplies
■
The LT4351 will disable power passage during undervolt-
age or overvoltage conditions. These voltages are set by
resistivedividersontheUVandOVpins. Theundervoltage
threshold has user programmable hysteresis. Overvolt-
age detection is filtered to reduce false triggering.
Uninterrupted Supplies
■
High Availability Systems
■
N + 1 Redundant Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LT4351 is available in a 10-pin MSOP.
U
TYPICAL APPLICATIO
Dual 5V Redundant Supply
Si4862DY
Si4862DY
5V COMMON
5V
10µF
5V
10µF
C
LOAD
R
LOAD
POWER
SUPPLY
1
POWER
SUPPLY
2
V
GATE
OUT
OUT
GATE
V
IN
1µF
IN
1µF
V
DD
V
DD
MBR0530
MBR0530
LT4351
LT4351
24.9k
24.9k
SW
UV
SW
UV
1%
1%
4.7µH
4.7µH
STATUS
FAULT
STATUS
FAULT
232Ω
1%
232Ω
1%
GND
GND
OV
OV
1.47k
1%
1.47k
1%
4351 TA01
sn4351 4351fs
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LT4351
W W U W
U W
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ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
VIN Voltage ............................................... –0.3V to 19V
OUT Voltage ............................................ –0.3V to 19V
VDD Voltage ............................................. –0.3V to 30V
FAULT, STATUS Voltages ........................ –0.3V to 30V
FAULT, STATUS Current ........................................ 8mA
UV, OV Voltages ........................................ –0.3V to 9V
SW Voltage .............................................. –0.3V to 32V
Operating Temperature Range
LT4351C.................................................. 0°C to 70°C
LT4351I .............................................. –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
GATE
DD
1
2
3
4
5
10 OUT
LT4351CMS
LT4351IMS
V
9
8
7
6
STATUS
V
FAULT
UV
OV
IN
SW
GND
MS PACKAGE
10-LEAD PLASTIC MSOP
MS PART MARKING
TJMAX = 125°C, θJA = 120°C/W
LTZZ
LTA1
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open,
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply and Protection
V
Operating Range
Supply Current
●
1.2
18
V
IN
I
V
V
V
= 1.2V, V
= 1.1V, V = 12.3V
●
●
1.41
1.71
2.0
2.1
mA
mA
VIN
IN
IN
IN
OUT
OUT
DD
= 18V, V
= 17.9V, V = 29.1V
DD
V
Undervoltage Turn-Off Voltage Threshold UV Falling
Hysteresis Difference Between I at V + 10mV
UV(TH)
●
●
290
7
300
10
310
13
mV
UV(TH)
I
I
µA
UV(HYST)
UV
UV
and V
– 10mV
UV(TH)
I
UV Input Bias Current
Overvoltage Threshold
OV Input Bias Current
FAULT Pin On Voltage
FAULT Pin Leakage Current
V
= V + 10mV
UV(TH)
●
●
●
●
●
–100
300
–400
310
–400
0.25
1
nA
mV
nA
V
UV
UV
V
OV Rising
= V – 10mV
OV(TH)
290
OV(TH)
I
V
–100
0.14
0.04
OV
OV
V
I = 5mA In Fault Condition
F
F(ON)
I
V = 30V, V = 4.9V
µA
F(OFF)
F
IN
Boost Supply
V
Boost Regulation Trip Voltage
Boost Supply Off Time
Measured as V to V , Rising Edge
●
●
10.2
350
4
10.7
600
450
11.1
650
V
ns
BR
DD
IN
t
I
OFF
Boost Supply Switch Current Limit
mA
SWLIM
Gate Drive
V
Input to Output Regulated Voltage
Gate Voltage Limit
●
●
15
25
–3
mV
V
IOR
∆V
V
= 5V, V
= 4.9V, V = 13V Measured with
–2.3
GL
IN
OUT
DD
Respect to V
DD
∆V
Maximum Gate Voltage
V
= 5V, V
= 4.9V, V = 16.1V Measured with
OUT
●
●
7
7.4
7.8
V
G(MAX)
IN
OUT
DD
Respect to V
V
Gate Off Voltage
V
V
V
= 5.1V
0.16
0.670
0.670
0.30
V
A
A
GOFF
OUT
OUT
OUT
I
I
Gate Source Current
Gate Sink Current
= 4.9V, V
= 4.9V, V
= 9V
= 9V
GSO
GSK
GATE
GATE
sn4351 4351fs
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LT4351
ELECTRICAL CHARACTERISTICS
unless otherwise specified.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open,
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Operating Range
●
30
V
I
V
DD
Supply Current
V
IN
V
IN
= 1.2V, V
= 1.1V, V = 12.3V, GATE Open
●
●
3.0
3.6
4.0
5.6
mA
mA
VDD
OUT
OUT
DD
= 18V, V
= 17.9V, V = 29.1V, GATE Open
DD
Status Functions
∆V
Min Gate Voltage for Turning On Status
V
V
= 4.9V, I = 1mA
STATUS
●
0.75
210
1
V
GIS
OUT
V
IOGF
V
IN
to V
Fault Voltage
Falling, Measured with Respect to V
IN
185
230
mV
OUT
OUT
with Open Gate
V
Status Pin On Voltage
Status Pin Leakage Current
I
= 5mA, V = 4.9V, Status On
OUT
●
●
0.13
0.04
0.25
1
V
STON
ST
I
V
= 30V, Status Off, V = 4.9V
µA
STOFF
ST
IN
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T is calculated from the ambient temperature T and power
J A
dissipation P according to the following formula:
D
T = T + (P • 120°C/W)
J
A
D
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise specified.
Undervoltage Threshold
vs Temperature
Overvoltage Threshold
vs Temperature
Undervoltage Threshold vs VIN
310
308
306
304
302
300
298
296
294
292
290
305
303
301
299
297
295
293
310
308
306
304
302
300
298
296
294
292
290
V
IN
V
IN
V
IN
V
IN
= 1.2V
= 5V
= 12V
= 20V
V
IN
V
IN
V
IN
V
IN
= 1.2V
= 5V
= 12V
= 20V
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
0
2
4
6
8
10 12 14 16 18 20
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
V
IN
4351 G01
4351 G02
4351 G03
sn4351 4351fs
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LT4351
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise specified.
Overvoltage Hysteresis
vs Temperature
Overvoltage Turn-Off Delay
vs Overvoltage Overdrive
Overvoltage Threshold vs VIN
25
20
15
10
5
20
18
16
14
12
10
8
310
308
306
304
302
300
298
296
294
292
290
V
IN
= 5V
V
IN
= 5V
6
4
2
0
0
–50 –25
0
25
50
75 100 125
0
10
15
20
25
30
35
5
0
2
4
6
8
10 12 14 16 18 20
(V)
TEMPERATURE (°C)
OV VOLTAGE ABOVE THRESHOLD (mV)
V
IN
4351 G05
3451 G06
4351 G04
IVIN vs Temperature
Gate Off Voltage vs Temperature
IVDD vs Temperature
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
4.5
4.0
3.5
3.0
2.5
2.0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
IN
V
IN
V
IN
V
IN
= 1.2V
= 5V
= 12V
= 20V
V
V
V
V
= 1.2V
= 5V
= 12V
= 20V
IN
IN
IN
IN
V
OUT
= 5V
IN
V
= 5V
V
OUT
= 5V
= 5.1V
IN
V
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
–25
0
25
50
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4351 G07
4351 G08
4351 G09
GATE Pin Turn On and Off
Waveform with 10nF Capacitor
Load
Typical SW Pin Waveform
TURN ON
VSW
2V/DIV
VSW
5V/DIV
TURN OFF
VIN = 5V
50ns/DIV
3451 G10
V
IN = 5V
500ns/DIV
3451 G11
VOUT = 4.9V to 5.1V SQUARE WAVE
L = 4.7µH
sn4351 4351fs
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LT4351
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TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise specified.
SW Pin Waveform at Maximum
Boost Regulator Output
Typical SW Pin Waveform
VSW
5V/DIV
VSW
5V/DIV
VIN = 5V
4.7µH INDUCTOR
10µs/DIV
3451 G12
VIN = 5V
4.7µH INDUCTOR
10µs/DIV
3451 G13
U
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PI FU CTIO S
GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to
the gate(s) of the external N-channel MOSFET(s). The
GATE pin drives high when UV is above the VUV(TH)
threshold, OV is below the VOV(TH) threshold and VIN is
greater than OUT by 15mV. When not driven high, GATE
actively pulls to GND. GATE can sink or source up to
600mA.
VIN (Pin 3): Input Supply Pin. This pin is the supply pin for
the control circuitry and the boost regulator. It is also one
input in conjunction with OUT for controlling the
MOSFET(s). Bypassing should include a low ESR/ESL
capacitor placed in close proximity to the part.
SW (Pin 4): Boost Regulator Switch Pin. This pin is the
boost regulator switch output. It is connected to the boost
inductor and the boost diode. Peak switch current is
limited internally to 450mA. If an external VDD supply is
used, leave this pin open.
VDD (Pin 2): Gate Drive Supply Pin. This is the supply pin
for the gate drive amplifier. It is either generated by the
onboard boost regulator or supplied externally. When
turningontheMOSFET(s),alargehighcurrentpulseflows
through this pin. Bypass the pin with a 1µF capacitor
placed in close proximity to the part. The voltage on this
pin is also the feedback for the boost regulator. If the VDD
voltageexceedstheVIN voltageby10.7V, theboostswitch
is held off.
GND (Pin 5): Device Ground Pin. This pin is ground for the
boost switch, gate driver as well as the control circuitry.
Tie the VIN and VDD bypass capacitors and ground plane
close to this pin to minimize the effects of switching
currents on part performance.
sn4351 4351fs
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LT4351
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PI FU CTIO S
OV (Pin 6): Overvoltage Shutdown Pin. This pin is used
for input overvoltage detection. It is connected to a
resistive divider from VIN. When the voltage exceeds the
OV threshold (0.3V), GATE is pulled to GND disabling
power transfer. In addition, the FAULT pin pulls low
indicating a fault. Overvoltage detection has filtering on it
to prevent false triggering. The filtering depends on the
level of overdrive. Filtered tripping will occur when OV
exceeds 0.3V. If OV exceeds 0.33V, the gate immediately
turns off (no filtering). If overvoltage detection is not
required, ground the OV pin. See Applications Informa-
tion for further information.
FAULT(Pin8):FaultComparatorStatusPin. Thispinpulls
low when a fault occurs. A fault has occured if the UV pin
is below threshold or the OV pin is above threshold. The
FAULT pin low indicates that there is a problem with the
VIN (source) supply. GATE is pulled to GND during a fault,
disabling the MOSFET(s) and prohibits common supply
contamination. If the GATE pin goes to compliance (GATE
equals the lesser of VDD – 2.3V or OUT + 7.4V) and VIN is
greater than OUT by more than 0.21V, FAULT turns on as
an indicator that the MOSFETs are probably not function-
ing. Leave this pin open if not used.
STATUS (Pin 9): MOSFET Status Pin. This pin pulls low
when GATE is above VIN by more than 0.7V and VIN is
greater than OUT by 15mV. This indicates the MOSFET is
on. Leave this pin open if not used.
UV (Pin 7): Undervoltage Shutdown Pin. This pin is used
for the undervoltage detect function. It is connected to a
resistive divider from VIN. When the voltage is below the
UVthreshold,GATEpullstoGNDdisablingpowertransfer.
Inaddition,theFAULTpinpullslowindicatingafault.When
theUVpinvoltagedropsbelowthethreshold,a10µAcurrent
is pulled from the divider to provide hysteresis. If under-
voltagedetectionisnotrequired, tietheUVpintoavoltage
greater than 320mV and not greater than VIN. Do not force
more than 9V on UV due to an internal clamp. See Appli-
cations Information for further information.
OUT (Pin 10): Common Supply Pin. This pin is connected
to the supply common and is used in conjunction with VIN
as one input controlling the MOSFET(s).
sn4351 4351fs
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LT4351
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BLOCK DIAGRA
TO COMMON SUPPLY
FROM INDIVIDUAL SUPPLY
V
V
IN
OUT
4
2
3
1
V
DD
V
GATE
SW
IN
10.7V
REG
–
+
ENABLE
+
–
600ns
ONE
SHOT
ENABLE
DRIVER
QSW
+
–
+
–
15mV
OUT
10
9
R2
OPEN
MOSFET
DETECT
V
OUT
UV
IN
C
UV
7
6
+
–
R
B
STATUS
FAULT
+
R1
0.3V
OV
ST
C
–
+
OVF
–
R
A
C
OV
8
–
+
0.33V
0.3V
GND
5
4351 BD
sn4351 4351fs
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LT4351
U
OPERATIO
Increasingly, system designers have to deal with multiple
supply sources. The multiplicity may provide parallel, re-
dundantsuppliesforincreasedreliabilityorprovideameans
of connecting disparate supplies. In all cases the desire is
for behavior like a diode but with no loss or voltage drop.
When OV just exceeds the reference, an internal capacitor
starts charging, delaying the signal to turn off the
MOSFET(s).
The second occurs when the OV pin exceeds 330mV. The
OVF comparator will immediately trip pulling GATE to
GND. This affords a delay inversely proportional to the
amount of overdrive. This also provides for glitch immu-
nity without compromising response time in the event of
a serious overvoltage condition.
ORing diodes have been the conventional means of
connecting these supplies. The disadvantage of this ap-
proach is that diodes introduce efficiency loss because of
theirforwardvoltagedrop. Thisvariablevoltagedropalso
degenerates supply tolerance. Additionally, diodes pro-
vide no information concerning the status of the sourcing
supply. Separate control must also be added to ensure
that a supply that is out of range is not allowed to affect
the common supply.
TheFAULToutputindicatesthestatusoftheCOV,COVF and
C
UV comparators. It pulls low during a fault condition. It
also pulls low when GATE is at compliance and VIN > OUT
by more than 0.21V indicating a probable nonfunctioning
MOSFET. Compliance occurs when GATE is at the lesser
of OUT + 7.4V or VDD – 2.3V. FAULT derives its drive from
thegreaterofVIN orOUT. ItisactiveifVIN orOUTisgreater
than 0.9V. If VIN or OUT is below this level, the output state
is not guaranteed.
TheLT4351eliminatestheseproblemsbyusingN-channel
MOSFETs as the pass elements. The MOSFET is turned on
when power is being passed, allowing for a low voltage
drop from the supply to the load. When the input source
voltage drops below the output common supply voltage it
turns off the MOSFET, thereby matching the function and
performance of an ideal diode.
The gate drive consists of a high current, wide bandwidth
amplifier (Driver). When the amplifier is enabled, it at-
tempts to regulate the GATE voltage such that the voltage
across the MOSFET(s) is approximately 15mV. If the
MOSFET(s) on resistance is so high as to prevent regula-
tion, then GATE goes to compliance and the MOSFET(s)
fully turns on. The inputs to the amplifier are VIN and OUT.
The GATE pin sources current from VDD and sinks current
to GND. The maximum GATE to VIN voltage is the lesser of
VDD – 2.3V or 7.4V above VOUT or VIN (internal clamp
voltage).
The LT4351 drives either a single MOSFET or dual back-
to-back MOSFETs. Dual MOSFETs are chosen to eliminate
current flow from the input supply to the output supply
when the VIN voltage is greater than OUT.
A driver amplifier monitors the input (VIN) and output
(OUT) and controls the MOSFETs. If VIN exceeds OUT by
15mV, GATE goes high and turns on the MOSFET(s)
allowing for power passage.
The STATUS comparator, ST, pulls low when GATE ex-
ceeds VIN by 0.7V. This occurs when VIN > OUT + 15mV.
The STATUS pin pulls low as an indication that power is
passing through the MOSFET(s).
Undervoltage and overvoltage comparators CUV, COV and
COVF also control power passage. A resistive divider in
conjunction with the UV and OV pins sets appropriate
thresholdssuchthattheMOSFET(s)isoffwhentheUVpin
is below 300mV or OV pin is above 300mV.
If VIN is greater than OUT by 0.21V and GATE > VIN + 7.4V
or at compliance (GATE = VDD – 2.3V), STATUS will go
high as an indication of a likely open MOSFET. FAULT will
pull low in this state indicating the probable fault.
To help deal with the transients on the supply lines, the UV
input has current hysteresis. When the UV voltage drops
below the 300mV threshold, a 10µA current is pulled from
the pin. Thus the user can set the hysteresis level through
appropriate values in the divider.
The gate drive amplifier and STATUS function derive
power from VDD. The circuit requires VDD > 2.5V. If VDD is
present, the gate drive amplifier and STATUS are active
independent of the state of VIN. If in a fault, GATE pulls
Overvoltage shutdown occurs in two stages. The first
occurs when the OV pin exceeds the 300mV reference.
sn4351 4351fs
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LT4351
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OPERATIO
actively low. In the event of VDD collapse there still is an
active pull-down (though of lesser strength) of GATE
powered from OUT, guaranteeing turn off.
and the inductor’s current flows through the external
diode to charge up the VDD capacitor. If VDD is still too low,
the switch turns on again after a fixed off-time of 600ns.
The on-chip boost regulator uses a constant off-time
control scheme. When VDD is below the regulation trip
voltage, the switch turns on after a 600ns off-time. When
the switch turns on current ramps up in the inductor until
the current limit is reached (450mA). The switch turns off
The boost regulator regulates VDD to approximately 10.7V
above VIN. When VDD is above this level, the SW transistor
turn-on is disabled. When VDD falls below this level by the
hysteresis level, the SW transistor is allowed to turn on.
There is approximately 0.15V of hysteresis.
W U U
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APPLICATIO S I FOR ATIO
at the input. VUV is the part undervoltage trip point (0.3V)
andIHYSTUV istheundervoltagehysteresiscurrent(10µA).
See Figure 1.
Setting Fault Thresholds
The gate drive amplifier implements the ideal diode func-
tion. The fault comparators (UV and OV) prevent out of
rangeinputvoltagesfromaffectingtheoutputbydisabling
the amplifier during these conditions. Think of the UV and
OV as gating the ideal diode function, something a regular
diode can’t do.
The divider on the OV pin is a straightforward resistive
divider (Figure 2):
OV
FAULT
RB =
RA =
– 1 RA
VOV
A resistive divider from VIN to UV and one from VIN to OV
are the usual way of setting the FAULT thresholds. For UV
the resistor values are set by:
0.3V
RA,RB Divider Current
UVHYST
R2 =
where OVFAULT is the desired overvoltage trip point at the
input and VOV is the OV pin threshold (0.3V). The OV pin
has 7mV of voltage hysteresis at room.
IUVHYST
VUV
R1=
•R2
It is possible to do both dividers together using only three
resistors though with more interdependence in compo-
nents (Figure 3). The input bias current for UV and OV is
less than 200nA, so keep resistor values less than 10k.
UVFAULT – VUV
where UVHYST is the desired undervoltage hysteresis at
the input. UVFAULT is the desired undervoltage trip voltage
V
IN
V
IN
V
IN
V
IN
R2B
R2A
R3
R2
V
IN
R2
UV
R2
UV
UV
OV
V
V
UV
300mV
UV
300mV
R
B
OV
V
OV
C1
300mV
UV
R1
R1
I
I
HYS
10µA
HYS
10µA
R1
R
A
R1
4351 F02
4351 F01
4351 F04
4351 F03
UV TURNING ON
UV TURNING OFF
Figure 1
Figure 3
Figure 4
Figure 2
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LT4351
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APPLICATIO S I FOR ATIO
In that case the resistor values are set by:
Boost Regulator
The boost regulator will start working as soon as VIN is
greaterthan0.85V.Theregulatorwillsupplyallthecurrent
for the gate drive amplifier. While the amplifier itself
requires only about 3mA, larger current pulses are re-
quired when charging the MOSFET gate. The reservoir
capacitor on VDD will provide this current (Figure 6).
UVHYST
R3 =
IUVHYST
UV
OV
FAULT
VUV –
• VOV
FAULT
R2 =
R1=
•R3
UVFAULT – VUV
VOV •UV
FAULT
• UVFAULT – VUV
(
V
•R3
IN
OV
)
FAULT
L1
LT4351
D1
Hysteresis helps prevent erratic behavior due to the noise
on VIN. Two of the most common noise sources are: VIN
dippingwhentheMOSFETsfirstturnonanddrawdownthe
voltageontheVINcapacitors,andtheboostregulatorswitch
turning on and drawing current from the VIN capacitors.
Use low ESR capacitors for VIN and OUT filtering.
SW
V
DD
QSW
D2
C
DD
GND
4351 F06
Figure 6
Note that because the UV pin uses current hysteresis,
placing a capacitor on UV to ground to filter noise will
reduce the effective hysteresis. Filtering can be achieved
by splitting the R2 resistor as shown in Figure 4.
The regulator performance is relatively insensitive to the
inductor value. The inductor value does control the fre-
quency of operation. A 4.7µH inductor is recommended
for VIN voltages less than 10V and 10µH for VIN voltages
greaterthan10V. Severalinductorsthatworkwellwiththe
LT4351 are listed in Table 1. Many different sizes and
shapes are available. Consult each manufacturer for more
detailedinformationandfortheirentireselectionofrelated
parts. The switching frequency for the boost regulator is
around 1MHz so ferrite core inductors should be used to
obtainthebestefficiency.Theinductormusthandleapeak
current of 0.7A minimum and have a DC resistance of
0.5Ω or less. Shielded inductors are recommended to
reduce the noise due to inductive switching.
To defeat undervoltage fault detection, the UV pin should
be tied higher than 0.33V. UV can be tied to VIN provided
VIN < 9V. Overvoltage fault detection can be defeated by
grounding the OV pin. Do not exceed VIN.
INPUT
REFERRED
OV
UV
REFERRED REFERRED
OVERVOLTAGE FAULT:
GATE LOW
V
V
= 0.33V
= 0.3V
UV
UV
OVERVOLTAGE FILTERED FAULT
OV
FAULT
GATE CONTROLLED
V
V
> 0.3V
= 0.3V
V
< 0.3V
OV
UV
BY V – V
IN
OUT
UV
+ UV
UV
Table 1. Recommended Inductors
MAX
FAULT
HYST
UNDERVOLTAGE HYSTERESIS
OV
FAULT
UNDERVOLTAGE FAULT:
GATE LOW
IND
(µH)
DCR
(mΩ)
4351 F05
PART NUMBER
VENDOR
DS1608C-472
DS1608C-103
4.7
10
90
160
Coilcraft
(847) 639-6400
www.coilcraft.com
Figure 5. Graphical Representation of the UV and OV Functions
CDRH4D18-4R7
CDRH4D28-100
4.7
10
125
95
Sumida
(847) 956-0666
www.sumida.com
External Shutdown
To externally turn off the MOSFETs, such as to disable the
supply, use an open-collector transistor pulling down on
the UV pin. Note this will not turn off the boost regulator
which will continue to operate.
LMNP045B4R7N
LMNP045B100M
4.7
10
50
52
Taiyo Yuden
(408) 573-4150
www.t-yuden.com
sn4351 4351fs
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LT4351
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APPLICATIO S I FOR ATIO
U
For VIN less than 2V, choose a DC resistance less than
0.2Ω.
VDD Capacitor Selection
LowESR(EquivalentSeriesResistance)capacitorsshould
be used on VDD to minimize the output ripple voltage.
Multilayer ceramic capacitors are the best choice, as they
have a very low ESR and are available in very small
packages. Always use a capacitor with a voltage rating at
least 12V greater than VIN.
NotethatVDD currentreferredtotheinputsupplyishigher.
A first order approximation of the input current is:
10.6 IVDD
IVINVDD = 1+
•
V
IN
80%
Under normal operation, the VDD current is under 10mA
and the boost regulator operates in Burst Mode operation.
If any additional load is added, you must ensure that the
regulator is capable of supplying that load. As the load is
increased, the boost regulator will switch into continuous
mode operation. Further increases in load will collapse the
boost regulator voltage.
Capacitors
Two types of input capacitors are generally needed for the
LT4351. The first is a large bulk capacitor that takes care
of ringing associated with inductance of the input supply
lines and provides charge for the load when switching the
MOSFET.Theinputparasiticinductanceinconjunctionwith
CB and its ESR create an LCR network. The input LCR can
bestimulatedbytheboostregulatorswitchcurrentorload
current transients when the MOSFETs are on. To reduce
ringing associated with input inductance, CB should be:
Operating the regulator with increased load will cause
increased IC power dissipation and temperature, which
must be taken into consideration.
A 100ns delay from detecting the switch current limit to
turning off the power switch produces an overshoot of the
inductor current from the 0.45A switch limit. The amount
of overshoot depends on the boost regulator inductance.
Choosing an inductor that can handle 0.75A peak current
will be sufficient for the recommended inductors.
4 •LIN
CB ≥
2
RESR
where CB is the capacitor value, RESR is the capacitor’s
ESR and LIN is the inductance of the input lines.
While damped ringing is not necessarily bad, it may
produce unexpected results as the LT4351 ideal diode
reacts to the varying VIN to OUT voltage. Typically an
electrolytic or tantalum low ESR capacitor would be used.
Figure 7a illustrates VIN for a low value of CB and Figure 7b
shows it with a correctly sized value.
Diode Selection
Schottky diodes, with their low forward voltage drop and
fast switching speed, are the best match for the LT4351
boost regulator. Select a diode that can handle 0.75A peak
current and a reverse breakdown of 15V greater than the
maximum VIN.
VIN
200mV
VIN
200mV
10µs/DIV
4351 F07a
10µs/DIV
4351 F07b
Figure 7a. Example of Input Voltage Ringing
with Low CIN Capacitor at MOSFET Turn Off
Figure 7b. Example of Input Voltage with
Sufficient CIN Capacitor at MOSFET Turn Off
sn4351 4351fs
11
LT4351
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APPLICATIO S I FOR ATIO
Asanexample, for500nHofinductanceandRESR ofabout
100mΩ, then:
Back-to-back MOSFETs prevent the MOSFET body diode
from passing current.
Use a single MOSFET if current flow is allowable from
input to output when the input supply is above the output
(limited overvoltage protection). In this case the MOSFET
should have a source on the input side so the body diode
conducts current to the load. Back-to-back MOSFETs are
normally connected with their sources tied together to
provide added protection against exceeding maximum
gate to source voltage.
4 • 500nF
C ≥
= 200µF
0.12
Check vendor data for ESR and iterate to get the best
value. Additional CB capacitance may be required for load
concerns.
If the boost regulator is being used, place a 10µF low ESR
ceramic capacitor from VIN to GND. Place a 10µF and a
0.1µF ceramic capacitor close to VIN and GND. These
capacitors should have low ESR (less than 10mΩ for the
10µF and 40mΩ for the 0.1µF). These capacitors help to
eliminateproblemsassociatedwithnoiseproducedbythe
boost regulator. They are decoupled from the VIN supply
by a small 1Ω resistor as shown in Figure 8. The LT4351
will perform better with a small ceramic capacitor (10µF)
on OUT to GND.
SelectionofMOSFETsshouldbebasedonRDS(ON), BVDSS
and BVGSS. BVDSS should be high enough to prevent
breakdown when VIN or OUT are at their maximum value.
RDS(ON) should be selected to keep within the MOSFET
power rating at the maximum load current (I2 • RDS(ON)
)
BVGSS should be at least 8V. The LT4351 will clamp the
GATE to 7.5V above the lesser of VIN or OUT. For back-to-
back MOSFETs where sources are tied together, this
allows the use of MOSFETs with a VGS max rating of 8V or
more. If a single MOSFET is used, care must be taken to
ensure the VGS max rating is not exceeded. When the
MOSFETisturnedoff,theGATEvoltageisnearground,the
source at VIN. Thus, MOSFET VGS max must be greater
V
IN
L
IN
PARASITIC
C
V3
1Ω
10µF
GATE
IN
V
C
10µF
V1
C
B
LT4351
than VIN(MAX)
.
C
V2
0.1µF
If a single MOSFET is used with source to VIN, then BVGSS
shouldbegreaterthanthemaximumVINsincetheMOSFET
gate is at 0.2V when off.
GND
4351 F08
Figure 8. VIN Capacitors
The gate drive amplifier will attempt to regulate the
voltage across the MOSFETs to 15mV. Regulation will be
achieved if:
External Boost Supply
The VDD pin may be powered by an external supply. In this
case, simply omit the boost regulator inductor and diode
and leave the SW pin open. Suitable VDD capacitance
(minimumofa1µFceramic)shouldremainduetothecur-
rent pulses required for the gate driver.
15mV
2 •ILOAD
RDS
RDS
<
for two MOSFETs and
15mV
ILOAD
<
for a single MOSFET
The VDD current consists of 3.5mA of DC current with the
currentrequiredtochargetheMOSFET’sgatewhichisde-
pendent on the gate charge required and frequency of
switching.Typicallytheaveragecurrentwillbeunder10mA.
This requires very low RDS values. This may be achieved
by paralleling MOSFETs, but be careful to keep intercon-
nection trace resistance low. In the event that regulation
cannot be achieved, the gate drive amplifier will drive
GATEtoitsclampandachievethebestRDS possibleatthat
level.
MOSFET Selection
The LT4351 uses either a single N-channel MOSFET or
back-to-back N-channel MOSFETs as the pass element.
sn4351 4351fs
12
LT4351
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APPLICATIO S I FOR ATIO
U
STATUS
ORing can be done either at the load or at the source.
Figure 9 shows some examples. ORing at the load is
usually the safest method since it protects against shorts
in interconnects.
The STATUS pin sinks current when the input (VIN) is
above output (OUT) by 15mV and GATE is above VIN by
0.7V. This will normally indicate that power is being
passed though the MOSFETs.
The LT4351 tighter forward voltage tolerance makes it
easier to balance current between similar supplies using
the droop method. The droop method uses the supply
voltage and series resistance in the power path to provide
load sharing. In this case, size the MOSFET’s RDS(ON) low
to allow for regulation.
In the event of a nonfunctional MOSFET, the GATE voltage
will be driven high (to the GATE clamp voltage). If VIN is
greater than OUT by more than 0.21V, the FAULT pin will
sink current to signal the potential problem.
Thereisnodirectmeasurementorconfirmationofcurrent
flowingintheMOSFETs.Currentissharedbetweensources
based on their voltage and series resistance. If precision
load sharing is desired, the LTC4350 may be a more
suitable part.
ORing Disparate Supplies
The LT4351 provides an easy solution for connecting
together different types of power sources. Again because
of the low forward drop, the efficiency of the system is
improved and the voltage transition between supplies is
moreaccurate. Inaddition, theundervoltageandovervolt-
age features of the LT4351 provide options for enabling
and disabling the supplies that are not available from a
common diode. Figure 10 shows some examples of con-
necting disparate supplies.
Redundant Supplies
The LT4351 is an improved solution for ORing redundant
suppliesbecauseofitslowerforwarddropversusconven-
tional diodes. The lower forward drop significantly im-
proves overall efficiency, improves the voltage tolerance
at the load and provides for a more accurate transition
from supply to supply and more accurate load sharing
between supplies.
Isolated System Supply
BACKPLANE
SOURCE 1
LT4351
from Wall Adapter
Isolated Battery Backup
BOARD
LOAD
WALL
ADAPTER
WALL
ADAPTER
LT4351
LT4351
LT4351
+
SYSTEM
SUPPLY
BATTERY
LOAD
LOAD
SOURCE 2
Three Source ORing Provides Protection
Against Out of Range Supplies
BACKPLANE
SOURCE 1
BOARD
LT4351
LT4351
LT4351
WALL
ADAPTER
LT4351
LT4351
LOAD
+
SOURCE 2
SYSTEM
SUPPLY
BATTERY
LOAD
4351 F09
4351 F10
Figure 9. Redundant Backplane Supplies
Figure 10
sn4351 4351fs
13
LT4351
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U
APPLICATIO S I FOR ATIO
Start-Up Considerations
Figure 11 shows the internal dissipation of the boost
regulatorasafunctionofVIN andinductorvalue. Figure11
represents the worst-case condition with the regulator on
all the time, which does not occur in normal practice.
Thereisnoinherentshutdowninthepart.AsVIN rampsup,
theboostregulatorstartsatabout0.85Vandbecomesfully
operational by 1.1V. The undervoltage and overvoltage
comparators become accurate by 1.2V. The gate drive
amplifier keeps GATE low during this period with either a
passivepull-down,aweakactivepull-downifOUTisgreater
than0.8VorwiththefullgatedrivesinkifVDD isabove2.2V.
Since the boost regulator supplies current for VDD, the
currentistheVDD supplycurrent(3.5mA)plustheaverage
current to charge the gate. For a gate charge of 50nC at a
10kHz rate, this adds 0.5mA of current. The power dissi-
pated by the boost regulator to supply the 4mA is shown
in Figure 12, representing a more typical situation.
Once VIN is greater than 1.2V and VDD is up, the part then
operates normally. The UV and OV pins will control the
enabling of the gate driver and once enabled, the VIN to
OUT voltage controls MOSFET turn on.
Finally, the gate driver dissipates power internally when
charging and discharging the gate of the MOSFETs. This
power depends on the input capacitance of the MOSFETs
and the frequency of charge and discharge. The power
associated with this can be approximated by:
If VDD is still being charged when the gate driver turns on
the MOSFET, the GATE pin tracks with the VDD increase
until it reaches either the gate clamp voltage or the
compliance of the gate driver. If VDD is present without VIN
or OUT, the GATE pin actively sinks low.
V
16
IN
PGATE = fG • VDD •QG • 1–
Power Dissipation
where QG is the required gate charge to charge the
MOSFET to the clamp voltage (7.4V) and fG is the fre-
quency at which the gate is charged and discharged.
Normally fG is low and the resulting power would be very
low. Figure 13 shows PGATE for a 50nC gate charge at a
1kHz rate.
TheinternalpowerdissipationoftheLT4351iscomprised
of the following four major components: DC power dissi-
pation from VIN, DC power dissipation from VDD, the
dissipation in the boost switch including the base drive,
and dynamic power dissipation due to current used to
charge and discharge the MOSFETs. The DC components
are:
TotalpowerdissipationisthesumofallofPDCVIN,PDCVDD
,
PBOOST and PGATE. Figure 14 is representative of the total
power dissipation of a typical application at steady state.
PDCVIN = IVIN • VIN
PDCVDD = IVDD • VDD
0.30
0.25
0.025
L = 4.7µH
0.020
0.015
0.010
0.005
L = 10µH
0.20
L = 4.7µH
0.15
0.10
10
(V)
15
10
(V)
15
0
20
0
20
5
5
V
IN
V
IN
4351 F11
4351 F12
Figure 12. PBOOST(TYP)
Figure 11. PBOOST(MAX)
sn4351 4351fs
14
LT4351
W U U
APPLICATIO S I FOR ATIO
U
0.004
0.003
0.002
0.001
0
0.16
f
= 1kHz
V
= V + 10
DD IN
GATE
G
Q
= 50nC
0.5mA GATE CURRENT
0.14
0.12
0.10
0.08
0.06
L = 10µH
L = 4.7µH
10
(V)
15
0
20
10
(V)
5
0
5
15
20
V
IN
V
IN
4351 F13
4351 F14
Figure 14. Total Power (Typical)
Figure 13. PGATE vs VIN (VDD = VIN + 10.7)
The die junction temperature is then computed as:
The OV resistors are set as a straight resistive divider.
If the current in the RA, RB divider is 200µA, then:
TJ = TA + θJA • PTOTAL
where TJ is the die junction temperature, TA is the ambient
temperature, θJA is the thermal resistance of the part
(120°C/W) and PTOTAL is ascertained from the above.
Therefore, a 0.1W power dissipation causes a 12 degree
temperature rise above ambient.
0.3V
200µA
RA =
= 1.5k use 1.47k (1%)
then
RB =
OV
5.5
FAULT
– 1 RA =
– 1 1.47k
VOV
0.3
Design Example
RB = 25.48k use 25.5k
The following demonstrates the calculations involved for
setting design components for a 5V system that requires
5A. Two supplies are used to do this. The VIN supply will
bedeemedinspecwhenitiswithin±5%ofnominal. Allow
5% of hysteresis for UV.
For regulation, the MOSFETs must have:
15mV
RDS
<
= 1.5mΩ
2 • 5A
This very low value cannot be accomplished with a single
set of MOSFETs so a decision must be made whether to
use multiple MOSFETs or to live with an unregulated
offset. Since low mΩ RDS(ON) is available, the IR drop
So,
UVFAULT = 4.75V, UVHYST = 0.25V
OVFAULT = 5.5
using a single FET would still be acceptable. For RDS(ON)
=
Two separate resistive dividers are used.
For the UV divider:
4mΩ the drop is 2 • 5A • 4mΩ = 40mV. The finished
schematic is shown in Figure 15.
UVHYST 0.25V
IUVHYST 10µA
R2 =
R1=
=
= 25k Use 24.9k
(
)
R2 • VUV
UVFAULT – VUV 4.75V – 0.3V
24.9k • 0.3V
=
R1 = 1.68k. The closest 1% value is 1.69k
sn4351 4351fs
15
LT4351
W U U
U
APPLICATIO S I FOR ATIO
Si4838DY
V
IN
OUT
5V
1Ω
10µF
10µF
3
1
10
OUT
0.1µF
5V
R2
24.9k
1%
V
GATE
IN
7
UV
R
25.5k
1%
R1
1.69k
1%
B
4.7µH
LT4351
6
4
2k
2k
OV
9
8
SW
STATUS
FAULT
MBR0530
2
R
A
V
MBR0530
DD
10µF
220µF
1.47k
1%
GND
5
1µF
4351 F15
Figure 15. 5V/5A Design Example
Layout Considerations
Take care that current flow to the load (both through VIN
and GND), does not inadvertently produce errors due to IR
drops in PCB traces.
There are two considerations for board layout. The first is
that VIN and VDD bypass capacitors should be as close to
the part as possible. The GND pin should represent the
common tie point. The resistive dividers for UV and OV
should tie here as well.
Keep the traces to the MOSFETs wide and short and close
to the part. The PCB traces associated with the power path
through the MOSFETs should have low resistance.
sn4351 4351fs
16
LT4351
U
TYPICAL APPLICATIO S
Lead Acid Battery Backup
14V
POWER
SUPPLY
Si4408DY
CHARGER
OUT
10µF
+
1Ω
12V
LOAD
LEAD-ACID
BATTERY
3
1
10
OUT
10µF
R2
12.7k
1%
V
GATE
0.1µF
IN
7
UV
R
73.2k
1%
R1
365Ω
1%
B
10µH
LT4351
6
4
10k
10k
OV
9
8
SW
STATUS
FAULT
MBR0530
MBR0530
10µF
2
V
DD
+
R
1.5k
1%
A
GND
5
1µF
UV
OV
= 10.8V
FAULT
FAULT
220µF
= 15V
4351TA02
sn4351 4351fs
17
LT4351
U
TYPICAL APPLICATIO S
5V Redundant Supply with External VDD
Si4838DY
5V
SOURCE
1Ω
10µF
3
1
10
OUT
10µF
0.1µF
R2
24.9k
1%
V
GATE
10µF
IN
7
UV
R
25.5k
1%
R1
B
1.69k
1%
LT4351
+
6
4
2k
2k
100µF
OV
R
A
1.47k
1%
9
8
SW
STATUS
FAULT
2
12V
SOURCE
V
DD
GND
5
1µF
4351 F15
1ST SOURCE
2ND
5V SOURCE
COMMON
2ND LT4351
CIRCUIT
LOAD
2ND
12V SOURCE
4351 TA03
sn4351 4351fs
18
LT4351
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn4351 4351fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT4351
U
TYPICAL APPLICATIO
Primary Battery with Secondary Battery Backup
Si4408DY
CHARGER
OUT
+
12.6V
1Ω
10µF
BATTERY1
3
1
10
OUT
10µF
0.1µF
R2
40.1k
1%
V
GATE
IN
7
UV
R1
1.07k
1%
10µH
LT4351
6
4
10k
5%
10k
5%
OV
9
8
SW
STATUS
FAULT
+
MBR0530
MBR0530
100µF
2
V
DD
GND
5
100k
5%
10µF
1µF
UV
= 11.8V
FAULT
Si4408DY
CHARGER
OUT
+
120k
5%
1Ω
LOAD
100µF
12.6V
BATTERY2
10µF
3
1
10
10µF
0.1µF
V
GATE
OUT
IN
7
UV
10µH
300k
5%
1N914
LT4351
6
4
10k
10k
OV
9
8
SW
STATUS
FAULT
+
MBR0530
MBR0530
100µF
2
V
DD
GND
5
1µF
10µF
4351TA04
POWER IS SWITCHED TO BATTERY2 WHEN BATTERY1 DROPS TO 11.8V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Switches and Isolates Sources Up to 30V
LTC1473
Dual PowerPathTM Switch Driver
Hot Swappable Load Sharing Controller
Low Loss PowerPath Controller in ThinSOTTM
LTC4350
Output Voltage 1.2V to 12V, Equal Load Sharing
P-Channel MOSFET, 3V to 28V Range
LTC4412
PowerPath and ThinSOT are trademarks of Linear Technology Corporation.
sn4351 4351fs
LT/TP 1203 1K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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