LT4275_技术文档

LT4275

++

+

LTPoE /PoE /PoE

PD Controller

FeaTures

DescripTion

n

++

IEEE 802.3af/at and LTPoE ™ Powered Device

(PD) Controller

The LT^®4275 is a pin-for-pin compatible family of IEEE

++

802.3 and LTPoE powered device (PD) controllers.

n

++

LTPoE Supports Power Levels Up to 90W

++

TheLT4275AemploysaproprietaryLTPoE classification

LT4275A Supports All of the Following Standards:

scheme, delivering 38.7W, 52.7W, 70W or 90W of power

at the PD RJ45 connector. The LT4275A is fully compat-

ible with IEEE 802.3. The LT4275B is an IEEE 802.3at

n

++

LTPoE 38.7W, 52.7W, 70W and 90W

n

IEEE 802.3at 25.5W Compliant

IEEE 802.3af Up to 13W Compliant

+

compliant, Type 2 (PoE ) PD delivering up to 25.5W. The

n

LT4275B is IEEE 802.3at/af Compliant

LT4275C is IEEE 802.3af Compliant

LT4275C is an IEEE 802.3af compliant, Type 1 (PoE) PD

delivering up to 13W.

100V Absolute Maximum Input Voltage

Wide Junction Temperature Range (–40°C to 125°C)

Overtemperature Protection

The LT4275 internal charge pump provides an N-channel

MOSFET solution, eliminating a larger and more costly

P-channel MOSFET. A low R

MOSFET also maxi-

DS(ON)

Integrated Signature Resistor

mizes power delivery and efficiency, reduces power and

heatdissipation, andeasesthermaldesign. Startupinrush

currentisadjustablewithanexternalcapacitor.TheLT4275

also includes a power good output, on-board signature

resistor,undervoltagelockout,andthermalprotection.The

LT4275A/LT4275Bdrivesasingleopto-couplertoindicate

the power level of the attached PSE. Pin-selectable sup-

port for non-standard low voltage operation is provided.

Auxiliary power override is supported with the AUX pin.

External Hot Swap™ N-Channel MOSFET for Lowest

Power Dissipation and Highest System Efficiency

Programmable Aux Power Support as Low as 9V

Optional Support of Non-Standard Low Voltage PoE

Available in 10-Lead MSOP and 3mm × 3mm DFN

Packages

n

applicaTions

n

High Power Wireless Data Systems

The LT4275A can be configured to support all possible

n

Outdoor Security Camera Equipment

++

LTPoE , 802.3at and 802.3af power levels with external

n

Commercial and Public Information Displays

High Temperature Industrial Applications

component changes.

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

++

LTPoE and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

Typical applicaTion

++

LTPoE 90W Powered Device Interface

V

AUX

(9V TO 60V)

LT4275 Family

+

C

PORT

LT4275 GRADE

B

FDMC86102

MAX DELIVERED

POWER

~

+

–

+

–

DATA

PAIR

C

PD

0.1µF

A

C

V

PORT

3.3k

++

l

LTPoE 90W

V

IN

47nF

++

LTPoE 70W

ISOLATED

POWER

SUPPLY

+

SPARE

PAIR

++

LTPoE 52.7W

VPORT HSGATE

AUX

HSSRC

V

OUT

PWRGD

RUN

–

++

LTPoE 38.7W

LT4275A

l

25.5W

13W

RCLASS

++

PSE TYPE

(TO µP)

OPTO

l

T2P

GND IEEEUVLO

R

CLS++

CLS

4275 TA01a

4275f

1

LT4275

absoluTe MaxiMuM raTings

(Notes 1, 3)

VPORT, HSSRC Voltages ......................... –0.3V to 100V

HSGATE Current.................................................. 20mA

IEEEUVLO, RCLASS,

Operating Junction Temperature Range (Note 4)

LT4275AI/LT4275BI/LT4275CI..............–40°C to 85°C

LT4275AH/LT4275BH/LT4275CH ....... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec.)..................300°C

++

RCLASS Voltages ....... –0.3V to 8V (and ≤ VPORT)

AUX Current........................................................ 1.4mA

T2P, PWRGD Voltage ............................... –0.3V to 100V

T2P, PWRGD Current ...............................................5mA

pin conFiguraTion

TOP VIEW

IEEEUVLO

AUX

1

2

3

4

5

10 VPORT

IEEEUVLO

AUX

1

2

3

4

5

10 VPORT

9

8

7

6

HSGATE

HSSRC

9

8

7

6

HSGATE

HSSRC

PWRGD

T2P/NC*

11

GND

RCLASS

++

RCLASS /NC*

PWRGD

T2P/NC*

RCLASS /NC*

GND

MS PACKAGE

10-LEAD PLASTIC MSOP

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

T

= 150°C, θ = 45°C/W

JC

JMAX

T

= 150°C, θ = 5°C/W

JC

JMAX

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND

++

* RCLASS is not connected in the LT4275B/C versions. T2P is not connected in the LT4275C version.

orDer inForMaTion

MAX PD

LEAD FREE FINISH

LT4275AIDD#PBF

LT4275AHDD#PBF

LT4275AIMS#PBF

LT4275AHMS#PBF

LT4275BIDD#PBF

LT4275BHDD#PBF

LT4275BIMS#PBF

LT4275BHMS#PBF

LT4275CIDD#PBF

LT4275CHDD#PBF

LT4275CIMS#PBF

LT4275CHMS#PBF

TAPE AND REEL

PART MARKING*

LGBS

POWER PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

LT4275AIDD#TRPBF

LT4275AHDD#TRPBF

LT4275AIMS#TRPBF

LT4275AHMS#TRPBF

LT4275BIDD#TRPBF

LT4275BHDD#TRPBF

LT4275BIMS#TRPBF

LT4275BHMS#TRPBF

LT4275CIDD#TRPBF

LT4275CHDD#TRPBF

LT4275CIMS#TRPBF

LT4275CHMS#TRPBF

90W

10-Lead (3mm × 3mm) Plastic DFN

10-Lead Plastic MSOP

LGBS

LTGBT

LGBV

90W

10-Lead Plastic MSOP

25.5W

13W

10-Lead (3mm × 3mm) Plastic DFN

10-Lead Plastic MSOP

LGBV

LTGBW

LGBX

10-Lead Plastic MSOP

10-Lead (3mm × 3mm) Plastic DFN

10-Lead Plastic MSOP

LGBX

13W

LTGBY

13W

10-Lead Plastic MSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

4275f

2

LT4275

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL PARAMETER

VPORT Operating Input Voltage

CONDITIONS

MIN

23

TYP

MAX

60

UNITS

l

At VPORT Pin

V

VPORT Signature Range

VPORT Classification Range

VPORT Mark Range

At VPORT Pin

1.5

12.5

5.6

8

10

SIG

At VPORT Pin

21

CLASS

MARK

At VPORT Pin, Preceded by V

10

CLASS

VPORT Aux Mode Range

Signature/Class Hysteresis Window

Reset Threshold

At VPORT Pin, AUX > V

60

AUXT

1.0

2.6

V

5.6

RESET

HSON

l

Hot Swap Turn-On Voltage

IEEEUVLO = 0V

IEEEUVLO Open

35

27

37

29

V

l

V

Hot Swap Turn-Off Voltage

IEEEUVLO = 0V

IEEEUVLO Open

30

21.5

31

22.5

V

HSOFF

l

Hot Swap On/Off Hysteresis Window

3

V

Supply Current

l

VPORT = HSSRC = 57V

++

VPORT = 17.5V, RCLASS and RCLASS Open

2

mA

Supply Current During Classification

Supply Current During Mark Event

0.4

0.5

0.7

1.1

2.2

V

MARK

Signature and Classification

l

Signature Resistance

V

(Note 2)

23.7

5.8

24.4

8.3

25.2

11

kΩ

V

SIG

Signature Resistance During Mark Event

(Note 2)

MARK

++

V

RCLASS/RCLASS Operating Voltage

–10mA ≥ I

≥ –36mA, V

CLASS

1.32

1.40

1.43

2

RCLS

RCLASS

Classification Stability Time

VPORT Step to 17.5V, RCLASS = 34.8Ω

ms

Analog/Digital Interface

l

V

AUX Threshold

6.1

4

6.3

5.8

6.5

8

V

µA

V

AUXT

AUXH

I

AUX Pin Hysteresis Current

T2P Output Low

AUX = 6.1V

1mA Load (LT4275A/LT4275B Only)

1mA Load

0.8

5

PWRGD Output Low

PWRGD Leakage Current

T2P Leakage Current

V

PWRGD = 60V

µA

T2P = 60V

5

Hot Swap Control

l

I

HSGATE Pull-Up Current

V

– V

= 5V, V > 42V, Out of Pin

PORT

18

10

22

27

18

µA

V

GPU

HSGATE

HSSRC

V

HSGATE Open Circuit Voltage

, 0µA to 10µA Load with Respect

GOC

HSSRC

to HSSRC

l

HSGATE Pull-Down Current

V

– V

= 5V

200

690

µA

Hz

HSGATE

HSSRC

Timing

++

f

T2P Frequency

After PWRGD Valid, if LTPoE PSE Is Mutually

Identified

840

990

T2P

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Signature resistance specifications do not include resistance

added by the external diode bridge which can add as much as 1.1k to the

port resistance.

Note 3: All voltages with respect to GND unless otherwise noted. Positive

currents are into pins; negative currents are out of pins unless otherwise

noted.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

4275f

3

LT4275

Typical perForMance characTerisTics

VPORT Current vs VPORT Voltage

25k Detection Range

VPORT Hot Swap Thresholds

Supply Current During Power-On

2.0

1.5

1.0

0.5

0

0.5

0.4

0.3

0.2

0.1

0

37

36

35

34

33

32

31

30

T = –40°C

T = 25°C

T = 75°C

T = 125°C

T = –40°C

T = 25°C

T = 75°C

T = 125°C

IEEEUVLO = 0V

Hot Swap ON

Hot Swap OFF

35

40

45

50

55

60

0

2

4

6

8

10

–50 –25

0

25

50

75 100 125

VPORT VOLTAGE (V)

TEMPERATURE (°C)

4275 G03

4275 G01

4275 G02

Signature Resistance

vs Input Voltage

VPORT Hot Swap Thresholds

Reset Threshold

26.25

25.75

25.25

24.75

24.25

23.75

29.0

27.5

26.0

24.5

23.0

21.5

5.6

5.1

4.6

4.1

3.6

3.1

2.6

T = –40°C

T = 25°C

T = 75°C

T = 125°C

IEEEUVLO = FLOAT

Hot Swap ON

Hot Swap OFF

1

3

5

7

9

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

VPORT VOLTAGE (V)

TEMPERATURE (°C)

4275 G04

4275 G05

4275 G06

PWRGD, T2P Output Low

Voltage vs Current

VPORT Classification Thresholds

T2P Frequency

4

3

2

1

0

12.5

12.0

11.5

11.0

10.5

10.0

990

940

890

840

790

740

690

T = –40°C

T = 25°C

T = 75°C

T = 125°C

DETECT OR MARK TO CLASS

CLASS TO MARK

0

1

2

3

4

5

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

CURRENT (mA)

TEMPERATURE (°C)

4275 G07

4275 G08

4275 G09

4275f

4

LT4275

pin FuncTions

IEEEUVLO (Pin 1): Hot Swap Turn-on Threshold Level

Control. Connect to ground for IEEE compliant turn-on

and turn-off (UVLO) voltage thresholds. Leave open for

lower turn-on and turn-off voltage thresholds.

T2P (Pin 6, LT4275A/LT4275B Only): PSE Type Indica-

tor, Open-Drain Output. T2P floats for a 13W PSE. T2P

pulls down for a 25.5W PSE. T2P pulls down at f with

T2P

a 50% (typical) duty cycle to indicate the presence of an

++

LTPoE PSE. T2P is valid after PWRGD is active. This pin

AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive

divider from the auxiliary power input to set the voltage

at which the auxiliary supply takes over. Asserting AUX

pulls down HSGATE, disconnects the signature resistor,

disables classification and floats the PWRGD pin. The

is not connected on the LT4275C. See the Applications

Information section for behavior when using the AUX pin.

PWRGD(Pin7):PowerGoodIndicator,Open-DrainOutput.

Pulls down during V

and inrush.

CLASS

AUX pin sinks I

AUXT

when below its threshold voltage of

AUXH

HSSRC (Pin 8): External Hot Swap MOSFET Source. Con-

nect to source of the external MOSFET.

V

to provide hysteresis. Tie to GND when not used.

RCLASS(Pin3):ProgrammablePoEClassificationResis-

tor. See Table 1.

HSGATE(Pin9):ExternalHotSwapMOSFETGateControl,

Output. Connect to gate of the external MOSFET.

++

RCLASS

(Pin 4, LT4275A Only): Programmable

VPORT(Pin10): PDinterfaceupperpowerrailandexternal

Hot Swap MOSFET drain connection.

++

LTPoE ClassificationResistor. Thispinisnot connected

on the LT4275B/LT4275C. See Table 1.

Exposed Pad (Pin 11, DFN Package Only): GND. Must

be soldered to PCB GND.

GND (Pin 5): Ground Pin. Must be soldered to PCB GND.

block DiagraM

V

PORT

VPORT

VOLTAGE AND

CURRENT REFERENCES

PWRGD

IEEEUVLO

CONTROL

LOGIC

HSGATE

CHARGE

PUMP

ON

V

GOC

HSSRC

AUX

+

–

OVERTEMP

T2P

6.3V

V

PORT

V

PORT

CLASSIFICATION

LOGIC

1.4V

+

–

+

–

1.4V

EN

RCLASS++

RCLASS

GND

4275 BD

4275f

5

LT4275

applicaTions inForMaTion

OVERVIEW

POWER ON

Power over Ethernet (PoE) continues to gain popularity as

products take advantage of DC power and high speed data

available from a single RJ45 connector. Powered device

(PD)equipmentvendorsarerunningintothe25.5Wpower

limitestablishedbytheIEEE802.3standard.TheLT4275A

allows higher power while maintaining backwards com-

patibility with existing PSE systems. The LT4275 utilizes

V

HSON

V

HSOFF

CLASS

V

CLASSMIN

V

SIGMAX

DETECT

a low R

N-channel MOSFET to maximize efficiency

DS(ON)

V

RESET

and delivered power. Heat is also reduced, easing thermal

design.

V

SIGMIN

4275 F01

MODES OF OPERATION

Figure 1. Type 1 Detect/Class Signaling Waveform

The LT4275 has several modes of operation depending

on the input voltage sequence applied to the VPORT pin.

Thesemodesinclude25kΩsignaturedetection,classifica-

tion, mark, inrush and powered on.

A Type 2 PSE may declare the availability of high power

by performing 2-event (Physical Layer) classification

or by communicating over the (Data Link Layer) high

speed data line. A Type 2 PD must recognize both types

of communication. Since Layer 2 communications takes

place directly between the PSE and the PD application, the

LT4275A/LT4275B responsibility ends with supporting

2-event classification.

DETECTION

During detection, the PSE looks for a 25kΩ signature

resistor which identifies the device as a PD. The PSE will

applytwovoltagesintherangeof2.8Vto10Vandmeasure

the corresponding currents. Figure 1 shows the detection

voltages.ThePSEcalculatesthesignatureresistanceusing

a ∆V/∆I measurement technique.

In 2-event classification, a Type 2 PSE probes for power

classification twice as shown in Figure 2. The LT4275A or

LT4275B recognizes this and pulls the T2P pin down to

signaltheloadthatType2powerisavailable.IfanLT4275A

The LT4275 presents its precision, temperature-compen-

sated 24.4k resistor between the VPORT and GND pins,

allowing thePSE to recognizea PD ispresentand request-

ing power to be applied. The LT4275 signature resistor is

smaller than 25k to compensate for the additional series

resistance introduced by the IEEE required bridge.

++

senses an LTPoE PSE it alternates between pulling T2P

down and floating T2P at a rate of f

.

T2P

POWER ON

V

HSON

V

HSOFF

1ST CLASS 2ND CLASS

CLASSIFICATION

V

CLASSMIN

The detection/classification process varies depending on

++

whether the PSE is Type 1, Type 2, or LTPoE . A Type 2

V

SIGMAX

PSE may use Type 1 classification signaling and later

renegotiate a higher power classification with the PD over

the data layer.

DETECT

1ST MARK 2ND MARK

V

RESET

V

SIGMIN

A Type 1 PSE, after a successful detection, may apply a

classification probe voltage of 15.5V to 20.5V and mea-

sure current.

4275 F01

Figure 2. Type 2 Detect/Class Signaling Waveform

4275f

6

LT4275

applicaTions inForMaTion

Table 1. Classification Codes, Power Levels and Resistor Selection

LT4275 GRADE CAPABILITY

RESISTOR

PD POWER

AVAILABLE

13W

3.84W

6.49W

13W

25.5W

38.7W

52.7W

70W

NOMINAL CLASS

CURRENT

++

CLASS

0

1

2

3

PD TYPE

Type 1

Type 2

A

B

C

R

CLS

R

CLS

<0.4mA

10.5mA

18.5mA

28mA

40mA

Open

140Ω

76.8Ω

49.9Ω

34.8Ω

Open

140Ω

76.8Ω

49.9Ω

Open

34.8Ω

46.4Ω

64.9Ω

118Ω



4

++

4*

LTPoE

90W

++

*An LTPoE PD will be classified as class 4 by an IEEE 802.3 compliant PSE.

++

LTPoE CLASSIFICATION

power delivery and efficiency, reduces power and heat

dissipation, and eases thermal design.

The LT4275A allows higher power allocation while main-

tainingbackwardscompatibilitywithexistingPSEsystems

by extending the classification signaling of IEEE 802.3.

Linear Technology PSE controllers that are capable of

The PWRGD pin is held low by its open drain output until

HSGATE charges up to approximately 7V above HSSRC.

The PWRGD pin is used to hold off the isolated power

supply until inrush is complete and the external MOSFET

is fully enhanced. The HSGATE pin will remain high and

the PWRGD pin pulled down until the port voltage falls

++

LTPoE are listed in the Related Parts section. IEEE PSEs

++

will classify an LTPoE PD as a Type 2 PD.

below V

or the AUX pin is above V

.

HSOFF

AUXT

SIGNATURE CORRUPT DURING MARK

I

INRUSH

During the mark state, the LT4275 presents <11kΩ to the

port as required by the IEEE specification.

VPORT

+

3.3k

C

PORT

C

GATE

INRUSH AND POWERED ON

HSGATE

Once the PSE detects and optionally classifies the PD, the

PSE then powers on the PD. When the port voltage rises

VPORT

HSSRC

above the V

threshold, it begins to source I

out of

LT4275A

GND

HSON

GPU

theHSGATEpin.Thiscurrentflowsintoanexternalcapaci-

tor (C in Figure 3) that causes a voltage to ramp up the

GATE

4275 F03

gateoftheexternalMOSFET. TheexternalMOSFETactsas

a source follower and ramps the voltage up on the output

Figure 3. Programming I_INRUSH

bulk capacitor (C

inrush current (I

in Figure 3) thereby determining the

PORT

INRUSH

in Figure 3).

AUXILIARY SUPPLY OVERRIDE

To meet IEEE requirements, design I

to be approxi-

INRUSH

If the AUX pin is held above V

, the LT4275 enters

AUXT

mately 100mA. See equation below:

auxiliary power supply override mode. In this mode

the signature resistor is disconnected, classification is

disabled, HSGATE is pulled down, and the PWRGD pin is

allowed to float. The T2P pin pulls down on the LT4275A/

C_PORT

C_GATE

I_INRUSH= I_GPU

•

++

The LT4275 internal charge pump provides an N-channel

MOSFET solution, eliminating a larger and more costly

LT4275B when no R

resistor is present. The T2P pin

CLS

alternatesbetweenpullingdownandfloatingatf onthe

T2P

++

resistor is present.

P-channel FET. The low R

MOSFET also maximizes

LT4275A when the R

DS(ON)

CLS

4275f

7

LT4275

applicaTions inForMaTion

The AUX pin allows for setting the auxiliary supply turn on

Transient Voltage Suppressor

(V

) and turn off (V

) voltage thresholds. The

AUXON

AUXOFF

The LT4275 specifies an absolute maximum voltage of

100V and is designed to tolerate brief overvoltage events.

However, the pins that interface to the outside world can

routinely see excessive peak voltages. To protect the

LT4275, install a unidirectional transient voltage suppres-

sor (TVS) such as an SMAJ58A between the port voltage

and GND. This TVS must be mounted near the LT4275.

auxiliary supply hysteresis voltage (V

) is set by

AUXHYS

sinking current (I

lessthanV

and V

) only when the AUX pin voltage is

AUXH

.UsethefollowingequationstosetV

AUXT

AUXON

via R1 and R2 in Figure 4.

AUXOFF

V_AUXON− V_AUXOFFV_AUXHYS

+

R1=

R2 =

=

I_AUXH

R1

I_AUXH

LT4275A

For extremely high cable discharge and surge protection

contact Linear Technology Applications.

R1

R2

V

AUX





V_AUXOFF

V_AUXT

AUX

−1









++

)

Classification Resistor (R

and R

CLS

GND

V_AUX(MAX)− V_AUXT

–

R1≥

4275 F04

The R

resistors set the classification load current cor-

1.4mA

CLS

respondingtothePDpowerclassification.Selectthevalue

of R from Table 1 and connect the resistor between the

Figure 4. AUX Threshold and Hysteresis Calculation

CLS

RCLASS pin and GND, or float the RCLASS pin if class 0

is required. The resistor tolerance must be 1% or better to

avoid degrading the overall accuracy of the classification

THERMAL PROTECTION

The IEEE 802.3 specification requires a PD to withstand

any applied voltage from 0V to 57V indefinitely. During

classification,however,thepowerdissipationintheLT4275

may be as high as 1.5W. The LT4275 can easily tolerate

this power for the maximum IEEE timing but will overheat

if this condition persists abnormally.

++

circuit. For LTPoE use the LT4275A and select the value

++

of R

from Table 1 in addition to R

.

CLS

Power Good Interface

The LT4275 provides a power good signal (PWRGD) to

simplifytheisolatedpowersupplydesign.Thepowergood

signal is used to delay isolated power supply startup until

The LT4275 includes a thermal protection feature which

protects itself from excessive heating. If the junction

temperature exceeds the overtemperature threshold, the

LT4275 pulls down the HSGATE and PWRGD pins and

disables classification.

the C

capacitor is fully charged.

PORT

Exposed Pad

The LT4275A/LT4275B/LT4275C DFN package has an

exposed pad that is internally electrically connected to

GND. The exposed pad may only be connected to GND

on the printed circuit board.

EXTERNAL INTERFACE AND COMPONENT SELECTION

Input Diode Bridge

Theinputdiodebridgeintroducesavoltagedropthataffects

the voltage range for each mode of operation. The LT4275

is designed to tolerate these voltage drops. The voltages

shown in the Electrical Specifications are measured at the

LT4275 package pins.

LAYOUT CONSIDERATIONS

Avoid excessive parasitic capacitance on the RCLASS

pin and place resistor R

close to the LT4275. For the

CLS

LT4275A, place R ++ nearby as well.

CLS

It is strictly required for maximum protection to place the

Input Capacitor

input capacitor (C ) and transient voltage suppressor as

PD

close to the LT4275 as possible.

A 0.1µF capacitor is needed from VPORT to GND to meet

an input impedance requirement in IEEE 802.3.

4275f

8

LT4275

Typical applicaTions

IEEE 802.3af (Type 1) 13W Powered Device

FDN8601

~

+

–

+

–

C

PD

+

V

PORT

SMAJ58A

0.1µF

3.3k

C

PORT

ETHERNET

MAGNETICS

V

IN

47nF

ISOLATED

POWER

SUPPLY

+

VPORT HSGATE

HSSRC

PWRGD

LT4275A/LT4275B/LT4275C

RCLASS

V

OUT

RUN

–

++

RCLASS

T2P

GND IEEEUVLO AUX

R

CLS

4275 TA02

IEEE 802.3at (Type 2) 25.5W Powered Device

FDN8601

~

+

–

+

–

C

PD

+

V

PORT

SMAJ58A

0.1µF

3.3k

C

PORT

ETHERNET

MAGNETICS

V

IN

47nF

ISOLATED

POWER

SUPPLY

+

VPORT HSGATE

HSSRC

V

OUT

PWRGD

RUN

–

LT4275A/LT4275B

RCLASS

++

PSE TYPE

(TO µP)

OPTO

T2P

GND IEEEUVLO AUX

R

CLS

4275 TA03

++

LTPoE 38.7W to 90W Powered Device

FDMC86102

~

+

–

+

–

C

PD

+

V

PORT

SMAJ58A

0.1µF

3.3k

C

PORT

WÜRTH

749022016

V

IN

47nF

ISOLATED

POWER

SUPPLY

+

VPORT HSGATE

HSSRC

V

OUT

PWRGD

RUN

–

LT4275A

RCLASS

++

PSE TYPE

(TO µP)

OPTO

T2P

GND IEEEUVLO AUX

R

CLS++

CLS

4275 TA04

4275f

9

LT4275

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

0.70 ±0.05

3.55 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50

BSC

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.125

0.40 ±0.10

TYP

6

10

3.00 ±0.10

(4 SIDES)

1.65 ±0.10

(2 SIDES)

PIN 1 NOTCH

R = 0.20 OR

PIN 1

TOP MARK

(SEE NOTE 6)

0.35 × 45°

CHAMFER

(DD) DFN REV C 0310

5

1

0.25 ±0.05

0.50 BSC

0.75 ±0.05

0.200 REF

2.38 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

4275f

10

LT4275

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661 Rev E)

0.889 0.ꢀꢁ7

(.035 .005)

5.ꢁ3

3.ꢁ0 – 3.45

(.ꢁ0ꢂ)

(.ꢀꢁꢂ – .ꢀ3ꢂ)

MIN

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 3)

0.497 0.07ꢂ

(.0ꢀ9ꢂ .003)

REF

0.50

(.0ꢀ97)

BSC

0.305 0.038

(.0ꢀꢁ0 .00ꢀ5)

TYP

ꢀ0 9

8

7 ꢂ

RECOMMENDED SOLDER PAD LAYOUT

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 4)

4.90 0.ꢀ5ꢁ

(.ꢀ93 .00ꢂ)

DETAIL “A”

0.ꢁ54

(.0ꢀ0)

0° – ꢂ° TYP

GAUGE PLANE

ꢀ

ꢁ

3

4 5

0.53 0.ꢀ5ꢁ

(.0ꢁꢀ .00ꢂ)

0.8ꢂ

(.034)

REF

ꢀ.ꢀ0

(.043)

MAX

DETAIL “A”

0.ꢀ8

(.007)

SEATING

PLANE

0.ꢀ7 – 0.ꢁ7

(.007 – .0ꢀꢀ)

TYP

0.ꢀ0ꢀꢂ 0.0508

(.004 .00ꢁ)

0.50

(.0ꢀ97)

BSC

MSOP (MS) 0307 REV E

NOTE:

ꢀ. DIMENSIONS IN MILLIMETER/(INCH)

ꢁ. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.ꢀ0ꢁmm (.004") MAX

4275f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

11

LT4275

Typical applicaTion

25W PD Solution with 12VDC and 24VAC Auxiliary Input

B2100

(4plcs)

~

V

AUX

9V TO 57VDC

OR 24VAC

~

+

TO ISOLATED

POWER SUPPLY

MMSD4148

(2plcs)

470µF

MMSD4148

0.1µF

158k

FDN8601

13

8.2Ω

WÜRTH

7499511001

15

SMAJ58A

0.1µF

3.3k

VPORT

HSGATE

HSSRC

AUX

RCLASS

16

47nF

931k

LT4275A/LT4275B

34.8Ω

TO ISOLATED

POWER SUPPLY RUN

IEEEUVLO

GND

PWRGD

14

OPTO

T2P

PSE TYPE

(TO µP)

1–12

B2100

(8plcs)

4275 TA05

TO PHY

relaTeD parTs

PART NUMBER

LTC4257-1

LTC4263

DESCRIPTION

COMMENTS

IEEE 802.3af PD Interface Controller

Single IEEE 802.3af PSE Controller

IEEE 802.3at PD Interface Controller

Quad IEEE 802.3at PoE PSE Controller

Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class

Internal FET Switch

LTC4265

Internal 100V, 1A Switch, 2-Event Classification Recognition

LTC4266

With Programmable I /I , 2-Event Classification

CUT LIM

++

LTC4266A

Quad LTPoE PSE Controller

Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE 802.3at PDs.

With Programmable I /I , 2-Event Classification

CUT LIM

LTC4266C

LTC4267-3

Quad IEEE 802.3af PSE Controller

With Programmable I /I , 1-Event Classification

CUT LIM

IEEE 802.3af PD Interface with Integrated

Switching Regulator

Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM

LTC4269-1

LTC4269-2

IEEE 802.3af PD Interface with Integrated

Flyback Switching Regulator

2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

50kHz to 250kHz, Aux Support

IEEE 802.3af PD Interface with Integrated

Forward Switching Regulator

2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz

to 500kHz, Aux Support

+

++

Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs

LTC4270/LTC4271 12-Port PoE/PoE /LTPoE PSE Controller

LTC4274

Single IEEE 802.3at PoE PSE Controller

With Programmable I /I , 2-Event Classification

CUT LIM

++

LTC4274A

Single LTPoE PSE Controller

Provides Up to 90W. Backwards Compatible with IEEE 802.3 PDs. With Programmable

CUT LIM

I

/I , 2-Event Classification

LTC4274C

LTC4278

Single IEEE 802.3af PSE Controller

With Programmable I /I , 1-Event Classification

CUT LIM

IEEE 802.3af PD Interface with Integrated

Flyback Switching Regulator

2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

50kHz to 250kHz, 12V Aux Support

+

++

Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs

LTC4290/LTC4271 8-Port PoE/PoE /LTPoE PSE Controller

4275f

LT 0712 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

12

●

 LINEAR TECHNOLOGY CORPORATION 2012

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT4275
厂家：	Linear
描述：	LTPoE/PoE/PoE PD Controller LTPoE / POE / POE PD控制器光电二极管控制器
文件：	总12页 (文件大小：222K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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