LT4320-1_15 [Linear]
Ideal Diode Bridge Controller;
| 型号： | LT4320-1_15 |
| 厂家： | 
Linear |
| 描述： | Ideal Diode Bridge Controller |
| 文件： | 总14页 (文件大小：960K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4320/LT4320-1
Ideal Diode Bridge
Controller
Features
Description
The LT®4320/LT4320-1 are ideal diode bridge controllers
that drive four N-channel MOSFETs, supporting voltage
rectification from DC to 600Hz typical. By maximizing
available voltage and reducing power dissipation (see
thermograph comparison below), the ideal diode bridge
simplifies power supply design and reduces power supply
cost, especially in low voltage applications.
n
Maximizes Power Efficiency
n
Eliminates Thermal Design Problems
n
DC to 600Hz
n
9V to 72V Operating Voltage Range
n
I = 1.5mA (Typical)
Q
n
n
Maximizes Available Voltage
Available in 8-Lead (3mm × 3mm) DFN, 12-Lead
MSOP and 8-Lead PDIP Packages
An ideal diode bridge also eliminates thermal design
problems, costly heat sinks, and greatly reduces PC board
area. The LT4320’s internal charge pump supports an all-
NMOS design, which eliminates larger and more costly
PMOS switches. If the power source fails or is shorted, a
fast turn-off minimizes reverse current transients.
applications
n
Security Cameras
n
Terrestrial or Airborne Power Distribution Systems
n
Power-over-Ethernet Powered Device with a
Secondary Input
The LT4320 is designed for DC to 60Hz typical voltage
rectification, while the LT4320-1 is designed for DC to
600Hz typical voltage rectification. Higher frequencies of
operation are possible depending on MOSFET size and
operating load current.
n
Polarity-Agnostic Power Input
n
Diode Bridge Replacement
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Patent pending.
typical application
Thermograph of Passive Diode Bridge
+
Temperature Rise
DIODE
OUTP
TG1
IN1
TG2
IN2
MOSFET SBM
CURRENT 2.5mΩ
1040
15°C
32°C
49°C
66°C
84°C
LT4320
4320 TA01b
SBM1040 (×4)
OUTPUT
9V TO 72V
2A
4A
0.6°C
3.5°C
6.7°C
11°C
16°C
~
Thermograph of LT4320
Driving Four MOSFETs
BG2
BG1
6A
OUTN
8A
INPUT
DC TO 600Hz (TYP)
10A
DC Input, On Same PCB
–
~
4320 TA01a
4320 TA01c
LT4320+2.5mΩ FET (×4)
CONDITIONS: 24V AC , 9.75A DC LOAD ON SAME PCB
IN
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For more information www.linear.com/LT4320
LT4320/LT4320-1
absolute MaxiMuM ratings (Notes 1, 2)
Supply Voltages
Operating Junction Temperature Range
IN1, IN2.................................................... –3V to 80V
OUTP ..................................................... –0.3V to 80V
Output Voltages (Note 3)
LT4320I................................................–40°C to 85°C
LT4320H ............................................ –40°C to 125°C
LT4320MP ......................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
BG1, BG2, TG1, TG2............................... –0.3V to 80V
TG1-IN1, TG2-IN2....................................–0.3V to 12V
MSE, PDIP Packages ........................................300°C
pin conFiguration
TOP VIEW
TOP VIEW
TOP VIEW
1
2
3
4
5
6
IN2
TG2
NC
NC
BG2
BG1
12 IN1
11 TG1
10 NC
IN2
TG2
BG2
BG1
1
2
3
4
8
7
6
5
IN1
IN2
TG2
BG2
BG1
1
2
3
4
IN1
8
7
6
5
TG1
9
13
TG1
9
8
7
OUTP
NC
OUTN
OUTP
OUTN
OUTP
OUTN
MSE PACKAGE
DD PACKAGE
N8 PACKAGE
8-LEAD PLASTIC DIP
12-LEAD PLASTIC MSOP
8-LEAD (3mm × 3mm) PLASTIC DFN
T
= 150°C, θ = 10°C/W
JC
JMAX
T
= 150°C, θ = 5.5°C/W
JC
EXPOSED PAD (PIN 9) MUST BE
CONNECTED TO OUTN (PIN 5)
JMAX
T
= 150°C, θ = 45°C/W
JC
EXPOSED PAD (PIN 13) MUST BE
CONNECTED TO OUTN (PIN 7)
JMAX
orDer inForMation
OPERATING JUNCTION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
LT4320IDD#PBF
LT4320IDD#TRPBF
LT4320HDD#TRPBF
LT4320IDD-1#TRPBF
LT4320HDD-1#TRPBF
LT4320IMSE#TRPBF
LT4320HMSE#TRPBF
LT4320MPMSE#TRPBF
LT4320IMSE-1#TRPBF
LT4320HMSE-1#TRPBF
LT4320MPMSE-1#TRPBF
NA
LGCV
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic MSOP
8-Lead PDIP
LT4320HDD#PBF
LT4320IDD-1#PBF
LT4320HDD-1#PBF
LT4320IMSE#PBF
LT4320HMSE#PBF
LT4320MPMSE#PBF
LT4320IMSE-1#PBF
LT4320HMSE-1#PBF
LT4320MPMSE-1#PBF
LT4320IN8#PBF
LGCV
LGCW
LGCW
4320
4320
4320
43201
43201
43201
LT4320N8
LT4320N8
LT4320N8-1
LT4320N8-1
LT4320HN8#PBF
NA
8-Lead PDIP
LT4320IN8-1#PBF
LT4320HN8-1#PBF
NA
8-Lead PDIP
NA
8-Lead PDIP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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For more information www.linear.com/LT4320
LT4320/LT4320-1
electrical characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL PARAMETER
OUTP Voltage Range
CONDITIONS
MIN
9
TYP
6.6
1.0
MAX
72
UNITS
l
l
l
l
V
V
OUTP Undervoltage Lockout (UVLO) Threshold
INn Turn-On/Off Threshold
INn = OUTP, Other IN = 0V
OUTP = 9V, Other IN = 0V
6.2
1.3
7.0
3.7
1.5
V
I
V
INT
OUTP Pin Current
mA
INn = OUTP+ ∆V
INn = OUTP+ ∆V
+ 5mV, Other IN = 0V
OUTP
INn
SD(MAX)
SD(MAX)
I
INn Pin Current
at 9V
+ 5mV, Other IN = 0V
l
l
44
0.3
63
0.4
µA
mA
at 72V
Topside Source-Drain Regulation Voltage (INn – OUTP)
∆V
∆V
SD
l
l
LT4320
8
20
40
35
55
mV
mV
LT4320-1
26
l
Top Gate Drive (TGn – INn)
6.6
10.8
V
INn = OUTP+ ∆V
+ 5mV, 10μA Out of
TGATE
SD(MAX)
TGn, Other IN = 0V
l
V
Bottom Gate Drive (BGn)
Top Gate Pull-Up Current
INn = OUTP, 10μA Out of BGn, Other IN = 0V
7.0
12
V
BGATE
l
l
I
TGn – INn = 0V, INn = OUTP + 0.1V
TGn – INn = 5V, INn = OUTP + 0.1V
Current Flows Out of TGn, Other IN = 0V
425
120
µA
µA
TGUn
l
l
l
l
I
I
I
I
Top Gate Pull-Down Current to INn
Top Gate Pull-Down Current to OUTN
Bottom Gate Pull-Up Current
TGn – INn = 5V, INn = OUTP – 0.25V
Current Flows Into TGn, Other IN = 0V
1.25
6.0
mA
mA
mA
mA
TGSn
TGGn
BGUn
BGDn
INn = 0V, Other IN = OUTP = 9.0V, TGn = 5V
Current Flows Into TGn
BGn = 5V; INn = OUTP = 9.0V, Other IN = 0V
Current Flows Out of BGn
1.9
Bottom Gate Pull-Down Current
BGn = 5V; INn = 0V, Other IN = OUTP = 9.0V
Current Flows Into BGn
12.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Unless otherwise specified,
exposure to any Absolute Maximum Rating condition for extended periods
may affect device reliability and lifetime.
Note 2: All voltages are referenced to OUTN = 0V unless otherwise specified.
Note 3: Externally forced voltage absolute maximums. The LT4320 may
exceed these limits during normal operation.
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LT4320/LT4320-1
typical perForMance characteristics
IINn and IOUTP vs OUTP
IOUTP vs OUTP
∆VTGATE vs OUTP
1200
1000
1200
1000
11
10
9
OTHER IN = 0V
OUTP
IN1 AND IN2 FLOATING
OTHER IN = 0V
800
600
800
600
8
400
200
0
400
200
0
INn
7
∆V = 100mV
SD
SD
∆V = 40mV
6
0
20
40
60
80
0
20
40
OUTP (V)
60
80
9
13
17
OUTP (V)
21
25
INn = OUTP (V)
4320 G01
4320 G02
4320 G03
VBGATE vs OUTP
TGn Pull-Up Strength
TGn Pull-Down Strength to INn
12
11
5
4
3
2
1000
900
800
700
600
500
400
300
200
100
0
INn = OUTP + 100mV
OTHER IN = 0V
INn = OUTP – 250mV
OTHER IN = 0V
10
9
8
7
6
1
0
OUTP = 9V
OUTP = 12V
OUTP = 72V
OUTP = 9V
OUTP = 72V
OTHER IN = 0V
21 25
9
13
17
0
4
6
8
10
12
0
2
6
8
10
12
2
4
∆V
TGATE
(V)
OUTP (V)
∆V
TGATE
(V)
4320 G04
4320 G06
4320 G05
TGn Pull-Down Strength to OUTN
BGn Pull-Up Strength
BGn Pull-Down Strength
5
4
3
2
1
0
60
50
40
30
20
10
0
35
30
25
20
15
10
5
OTHER IN = 0V
INn = 0V
OTHER IN = OUTP
V
V
V
= 9V
= 12V
= 72V
OUTP = 9V
OUTP = 12V
OUTP = 72V
INn
INn
INn
0
0
4
6
8
10
12
0
4
6
8
10
12
8
12
2
2
14
0
2
4
6
10
TGn (V)
V
(V)
V
(V)
BGATE
BGATE
4320 G07
4320 G08
4320 G09
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For more information www.linear.com/LT4320
LT4320/LT4320-1
pin Functions (DFN, PDIP/MSOP)
IN2 (Pin 1/Pin 1): Bridge Rectifier Input. IN2 connects to
the external NMOS transistors MTG2 source, MBG1 drain
and the power input.
OUTP (Pin 6/Pin 9): OUTP is the rectified positive output
voltagethatpowerstheLT4320andconnectstothedrains
of MTG1 and MTG2.
TG2 (Pin 2/Pin 2): Topside Gate Driver Output. TG2 pin
drives MTG2 gate.
TG1 (Pin 7/Pin 11): Topside Gate Driver Output. TG1 pin
drives MTG1 gate.
BG2 (Pin 3/Pin 5): Bottom-Side Gate Driver Output. BG2
IN1 (Pin 8/Pin 12): Bridge Rectifier Input. IN1 connects
to the external NMOS transistors MTG1 source, MBG2
drain, and the power input.
pin drives MBG2 gate.
BG1 (Pin 4/Pin 6): Bottom-Side Gate Driver Output. BG1
pin drives MBG1 gate.
NC (Pins 3, 4, 8, 10, MSOP Only): No Connections. Not
internally connected.
OUTN (Pin 5/Pin 7): OUTN is the rectified negative output
voltage, and connects to the sources of MBG1 and MBG2.
ExposedPad(Pin9/Pin13):ExposedPad,DFNandMSOP.
Must be connected to OUTN.
block DiagraM
MTG1
~
+
MTG2
LT4320
TG1
TG2
OUTP
IN1
IN2
CONTROL
OUTN
BG2
BG1
MBG2
~
–
LT4320 BD
MBG1
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For more information www.linear.com/LT4320
LT4320/LT4320-1
operation
Electronic systems that receive power from an AC power
source or a DC polarity-agnostic power source often em-
ploya4-dioderectifier.Thetraditionaldiodebridgecomes
with an efficiency loss due to the voltage drop generated
across two conducting diodes. The voltage drop reduces
the available supply voltage and dissipates significant
power especially in low voltage applications.
bridge also eliminates thermal design problems, costly
heat sinks, and greatly reduces PC board area.
The LT4320 is designed for DC to 60Hz typical voltage
rectification, while the LT4320-1 is designed for DC to
600Hz typical voltage rectification. Higher frequencies of
operation are possible depending on MOSFET size and
operating load current.
By maximizing available voltage and reducing power dis-
sipation, the ideal diode bridge simplifies power supply
design and reduces power supply cost. An ideal diode
Figure 2 presents sample waveforms illustrating the gate
pins in an AC voltage rectification design.
MTG1
+
~
MTG2
INPUT
TO LOAD
TG2
TG1
OUTP
IN1
IN2
C
LT4320
LOAD
OUTN
BG1
BG2
MBG2
~
–
4320 F01
MBG1
Figure 1. LT4320 with Four N-Channel MOSFETS, Illustrating Current
Flow When IN1 Is Positive
40V
30V
20V
10V
0V
V
V
V
V
V
V
V
TG1
TG2
BG1
BG2
IN1
OUTP
IN2
4320 F02
Figure 2. 24V AC Sample Waveform
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LT4320/LT4320-1
applications inForMation
MOSFET Selection
the maximum operating frequency, creates unintended
efficiency losses, adversely increases turn-on/turn-off
times, and increases the total solution cost. The LT4320
gate pull-up/pull-down current strengths specified in the
Electrical Characteristics section, and the MOSFET total
A good starting point is to reduce the voltage drop of the
ideal bridge to 30mV per MOSFET with the LT4320 (50mV
perMOSFETwiththeLT4320-1).Giventheaverageoutput
load current, I , select R
to be:
AVG
DS(ON)
gatecharge(Q ),determinetheMOSFETturn-on/offtimes
g
30mV
IAVG
and the maximum operating frequency in an AC applica-
tion. Choosing the lowest gate capacitance while meeting
RDS(ON)
=
=
for a DC power input
R
speedsuptheresponsetimeforfullenhancement,
DS(ON)
or
regulation, turn-off and input shorting events.
30mV
3 •IAVG
RDS(ON)
for an AC power input
V
must be a minimum of 2V or higher. A gate thresh-
GS(th)
old voltage lower than 2V is not recommended since too
much time is needed to discharge the gate below the
threshold and halt current conduction during a hot plug
or input short event.
In the AC power input calculation, 3 • I
assumes the
AVG
duration of current conduction occupies 1/3 of the AC
period.
Selectthemaximumallowabledrain-sourcevoltage,V
to be higher than the maximum input voltage.
,
DSS
C
Selection
LOAD
A 1μF ceramic and a 10μF minimum electrolytic capacitor
must be placed across the OUTP and OUTN pins with the
1µF ceramic placed as close to the LT4320 as possible.
Downstream power needs and voltage ripple tolerance
determine how much additional capacitance between
OUTP and OUTN is required. C
thousands of microfarads is common.
Design Example
For a 24W, 12V DC/24V AC application, I
DC. To cover the 12V DC case:
= 2A for 12V
AVG
30mV
2A
in the hundreds to
LOAD
RDS(ON)
=
= 15mΩ
A good starting point is selecting C
such that:
LOAD
For the 24V AC operation, I
AC case:
= 1A. To cover the 24V
AVG
C
LOAD
≥ I /(V
• 2 • Freq)
AVG RIPPLE
30mV
3 •1A
where I
is the average output load current, V
is
AVG
RIPPLE
RDS(ON)
=
= 10mΩ
the maximum tolerable output ripple voltage, and Freq
is the frequency of the input AC source. For example, in
a 60Hz, 24VAC application where the load current is 1A
This provides a starting range of R
from.
values to choose
DS(ON)
and the tolerable ripple is 15V, choose C
• 2 • 60Hz) = 556µF.
≥ 1A/(15V
LOAD
Ensure the MOSFET can handle a continuous current of
3 •I to cover theexpected peak currents during AC rec-
AVG
C
LOAD
must also be selected so that the rectified output
tification. That is, select I ≥ 3A. Since a 24V AC waveform
D
voltage,OUTP-OUTN,mustbewithintheLT4320/LT4320-1
specified OUTP voltage range.
can reach 34V peak, select a MOSFET with V
>>34V.
DSS
A good choice of V
is 60V in a 24V AC application.
DSS
Transient Voltage Suppressor
Other Considerations in MOSFET Selection
For applications that may encounter brief overvoltage
events higher than the LT4320 absolute maximum rating,
install a unidirectional transient voltage suppressor (TVS)
between the OUTP and OUTN pins as close as possible
Practical MOSFET considerations for the LT4320-based
ideal bridge application include selecting the lowest avail-
able total gate charge (Q ) for the desired R
. Avoid
g
DS(ON)
oversizingtheMOSFET, sinceanoversizedMOSFETlimits
to the LT4320.
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LT4320/LT4320-1
typical applications
B360B
4 COMPACT FETs*
CONDITION: 13VDC , 3A LOAD ON SAME PCB
IN
*19mΩ, 60V EACH FET
Figure 3. Thermograph: B360B vs LT4320 +4 Compact FETs
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LT4320/LT4320-1
typical applications
Figure 4. Demonstration Circuit 1902A Used in Figure 3 Thermograph
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For more information www.linear.com/LT4320
LT4320/LT4320-1
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
2.10 ±0.05 (2 SIDES)
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.125
0.40 ±0.10
TYP
5
8
3.00 ±0.10
(4 SIDES)
1.65 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C
4
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.38 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
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LT4320/LT4320-1
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
(.112 ±.004)
1
6
0.35
REF
1.651 ±0.102
(.065 ±.004)
5.10
(.201)
MIN
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
DETAIL “B”
12
7
0.65
(.0256)
BSC
0.42 ±0.038
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0165 ±.0015)
TYP
0.406 ±0.076
RECOMMENDED SOLDER PAD LAYOUT
(.016 ±.003)
12 11 10 9 8 7
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1
2 3 4 5 6
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE12) 0213 REV G
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
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LT4320/LT4320-1
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
.400*
(10.160)
MAX
8
7
6
5
4
.255 ±.015*
(6.477 ±0.381)
1
2
3
.130 ±.005
.300 – .325
.045 – .065
(3.302 ±0.127)
(1.143 – 1.651)
(7.620 – 8.255)
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
.120
.020
(0.508)
MIN
(3.048)
MIN
+.035
.325
–.015
.018 ±.003
(0.457 ±0.076)
.100
(2.54)
BSC
+0.889
8.255
N8 REV I 0711
(
)
–0.381
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
4320fb
12
For more information www.linear.com/LT4320
LT4320/LT4320-1
revision history
REV
DATE
DESCRIPTION
PAGE NUMBER
1, 6
A
11/13 Clarified that input frequency ranges use typical numbers (60Hz, 600Hz)
Added PDIP package
2, 12
Reduced MOSFET drop to 30mV from 70mV in “MOSFET Selection” and “Design Example” sections
Provided additional guidance in “Other Considerations in MOSFET Selection” section
Updated MSE package drawing
7
7
10
2
B
2/14
Added H- and MP-grade information
4320fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
13
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT4320/LT4320-1
typical application
MTG1
+
~
MTG2
DIODE
BRIDGE
LT4320 IDEAL BRIDGE
MTG1,MTG2
MBG1, MBG2
OPERATING
VOLTAGE
LOAD
C1
POWER POWER
TG2
TG1
OUTP
CURRENT
(MIN)
LOSS
0.22W
0.13W
4.5W
LOSS
4.2W
1.9W
36W
IN1
IN2
+
55V DC
24V AC
55V DC
24V AC
72V DC
3.5A
1.5A
30A
10A
2A
10µF
560µF
10µF
1µF
C1
INPUT
LT4320
TO LOAD
BSZ110N06NS3
OUTN
BG1
BG2
BSC031N06NS3
3.3mF
10µF
1.6W
12W
PSMN040-100MSE
0.24W
2.4W
MBG2
~
–
4320 TA02
MBG1
relateD parts
PART NUMBER DESCRIPTION
COMMENTS
LT4321
PoE Ideal Diode Bridge Controller
Replaces 8 Diodes with 8 N-Channel MOSFETs, Reduces Heat,
Maximizes Efficiency
LTC4352
LTC4353
LTC4354
LTC4355
LTC4357
LTC4358
LTC4359
LTC4370
LTC4415
Low Voltage Ideal Diode Controller with Monitoring
Dual Low Voltage Ideal Diode Controller
N-Channel, 0V to 18V, UV, OV, MSOP-12 and DFN-12 Packages
Dual N-Channel, 0V to 18V, MSOP-16 and DFN-16 Packages
Controls Two N-Channel MOSFETs, 1μs Turn-Off, –80V Operation
Controls Two N-Channel MOSFETs, 0.5μs Turn-Off, 9V to 80V Operation
Negative Voltage Diode-OR Controller and Monitor
Positive Voltage Diode-OR Controller and Monitor
Positive High Voltage Ideal Diode Controller
5A Ideal Diode
Controls Single N-Channel MOSFETs, 0.5μs Turn-Off, 9V to 80V Operation
Positive Voltage Ideal Diode with Integrated MOSFET, 9V to 26.5V Operation
N-Channel, 4V to 80V, MSOP-8 and DFN-6 Packages
Ideal Diode Controller with Reverse Input Protection
2-Supply Diode-OR Current Balancing Controller
Dual 4A ideal Diodes with Adjustable Current Limit
Dual N-Channel, 0V to 18V, MSOP-16 and DFN-16 Packages
1.7V to 5.5V Operating Range
4320fb
LT 0214 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
14
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT4320
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