LT3957EUHE#TRPBF [Linear]
LT3957 - Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C;
| 型号： | LT3957EUHE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3957 - Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总28页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3957
Boost, Flyback, SEPIC and
Inverting Converter
with 5A, 40V Switch
FEATURES
DESCRIPTION
The LT®3957 is a wide input range, current mode DC/DC
converter which is capable of generating either positive
or negative output voltages. It can be configured as either
a boost, flyback, SEPIC or inverting converter. It features
an internal low side N-channel power MOSFET rated for
40V at 5A and driven from an internal regulated 5.2V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.
n
Wide Input Voltage Range: 3V to 40V
n
Single Feedback Pin for Positive or Negative
Output Voltage
n
Internal 5A/40V Power Switch
n
Current Mode Control Provides Excellent Transient
Response
n
Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
n
Synchronizable to an External Clock
n
Low Shutdown Current < 1μA
The operating frequency of LT3957 can be set with an
external resistor over a 100kHz to 1MHz range, and can
be synchronized to an external clock using the SYNC pin.
A minimum operating supply voltage of 3V, and a low
shutdown quiescent current of less than 1μA, make the
LT3957 ideally suited for battery-powered systems.
n
Internal 5.2V Low Dropout Voltage Regulator
n
Programmable Input Undervoltage Lockout with
Hysteresis
Programmable Soft-Start
n
n
Thermally Enhanced QFN (5mm × 6mm) Package
The LT3957 features soft-start and frequency foldback
functions to limit inductor current during start-up.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
APPLICATIONS
n
Automotive
No R
and ThinSOT are trademarks of Linear Technology Corporation.
SENSE
n
Telecom
All other trademarks are the property of their respective owners. Patents pending.
n
Industrial
TYPICAL APPLICATION
High Efficiency Output Boost Converter
Efficiency vs Output Current
10μH
V
OUT
100
95
90
85
80
75
70
V
IN
V
= 12V
24V
IN
4.5V TO 16V
600mA
10μF
s2
10μF
200k
V
SW
IN
EN/UVLO
GND
95.3k
LT3957
SGND
SYNC
SENSE1
226k
SENSE2
FBX
INTV
CC
RT SS
VC
6.8k
22nF
15.8k
41.2k
300kHz
4.7μF
0.33μF
0
400
OUTPUT CURRENT (mA)
500
600
100
200
300
3957 TA01b
3957 TA01a
3957f
1
LT3957
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , EN/UVLO (Note 5), SW......................................40V
IN
INTV ......................................................V + 0.3V, 8V
CC
IN
SYNC ..........................................................................8V
36 35 34 33 32 31 30
VC, SS.........................................................................3V
NC
NC
1
2
3
4
28 INTV
CC
RT
1.5V
27
V
IN
...............................................................................................
SENSE2
SGND
SENSE1, SGND .................. Internally Connected to GND
SENSE2.................................................................. 0.3V
FBX ................................................................. –6V to 6V
Operating Junction Temperature Range
SGND
37
EN/UVLO
25
24 SGND
SGND
23
SENSE1
6
(Note 2).................................................. –40°C to 125°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range .................. –65°C to 125°C
SW
38
SW
SW
8
9
21 SW
20 SW
NC 10
12 13 14 15 16 17
UHE PACKAGE
36-LEAD (5mm s 6mm) PLASTIC QFN
= 125°C, θ = 42°C/W, θ = 3°C/W
T
JMAX
JA
JC
EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE
ORDER INFORMATION
LEAD FREE FINISH
LT3957EUHE#PBF
LT3957IUHE#PBF
TAPE AND REEL
PART MARKING*
3957
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LT3957EUHE#TRPBF
LT3957IUHE#TRPBF
36-Lead (5mm × 6mm) Plastic QFN
36-Lead (5mm × 6mm) Plastic QFN
3957
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3957f
2
LT3957
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Operating Range
3
40
V
IN
IN
Shutdown I
EN/UVLO = 0V
EN/UVLO = 1.15V
0.1
1
6
μA
μA
Q
V
V
Operating I
VC = 0.3V, R = 41.2k
1.7
350
5.9
2.3
400
6.8
mA
μA
A
IN
IN
Q
T
Operating I with Internal LDO Disabled
VC = 0.3V, R = 41.2k, INTV = 5.5V
T CC
Q
l
SW Pin Current Limit
SW Pin On Voltage
SENSE2 Input Bias Current
Error Amplifier
5
I
= 3A
100
–65
mV
μA
SW
Current Out of Pin
l
l
FBX Regulation Voltage (V
FBX Overvoltage Lockout
FBX Pin Input Current
)
FBX > 0V (Note 3)
FBX < 0V (Note 3)
1.569
1.6
1.631
V
V
FBX(REG)
–0.816 –0.800 –0.784
FBX > 0V (Note 4)
FBX < 0V (Note 4)
6
7
8
11
10
14
%
%
FBX = 1.6V (Note 3)
FBX = –0.8V (Note 3)
70
100
10
nA
nA
–10
(Note 3)
(Note 3)
230
5
μS
Transconductance g (ΔI /ΔFBX)
m
VC
VC Output Impedance
MΩ
FBX > 0V, 3V < V < 40V (Notes 3, 6)
0.04
0.03
0.06
0.06
%/V
%/V
V
Line Regulation (ΔV /[ΔV • V
])
IN
FBX
FBX
IN
FBX(REG)
FBX < 0V, 3V < V < 40V (Notes 3, 6)
IN
10
V/V
μA
VC Current Mode Gain (ΔV /ΔV
)
VC
SENSE
VC Source Current
VC Sink Current
VC = 1.5V, FBX = 0V, Current Out of Pin
–15
FBX = 1.7V
FBX = –0.85V
12
11
μA
μA
Oscillator
Switching Frequency
R = 140k to SGND, FBX = 1.6V, V = 1.5V
80
270
850
100
300
1000
120
330
1200
kHz
kHz
kHz
T
C
R = 41.2k to SGND, FBX = 1.6V, V = 1.5V
T
C
R = 10.5k to SGND, FBX = 1.6V, V = 1.5V
T
C
RT Voltage
FBX = 1.6V
1.2
220
240
V
ns
ns
SW Minimum Off-Time
SW Minimum On-Time
SYNC Input Low
275
320
0.4
SYNC Input High
1.5
SS Pull-Up Current
Low Dropout Regulator
SS = 0V, Current Out of Pin
–10
5.2
μA
V
l
INTV Regulation Voltage
5
5.45
2.85
CC
INTV Undervoltage Lockout Threshold
Falling INTV
2.6
2.7
0.15
V
V
CC
CC
UVLO Hysteresis
3957f
3
LT3957
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INTV Current Limit
V
IN
V
IN
= 40V
= 15V
32
40
95
55
mA
mA
CC
0 < I
< 20mA, V = 8V
–1
–0.5
0.02
450
17
%
%/V
mV
μA
INTV Load Regulation (ΔV
/V
)
INTVCC
IN
CC
INTVCC INTVCC
6V < V < 40V
0.05
INTV Line Regulation (ΔV
/[ΔV • V
])
INTVCC
IN
CC
INTVCC
IN
Dropout Voltage (V – V
)
V
IN
= 5V, I
= 20mA, VC = 0V
INTVCC
IN
INTVCC
INTV Current in Shutdown
EN/UVLO = 0V, INTV = 6V
CC
CC
INTV Voltage to Bypass Internal LDO
5.5
V
CC
Logic Inputs
l
EN/UVLO Threshold Voltage Falling
EN/UVLO Voltage Hysteresis
EN/UVLO Input Low Voltage
EN/UVLO Pin Bias Current Low
EN/UVLO Pin Bias Current High
V
= INTV = 6V
1.17
1.7
1.22
20
1.27
V
mV
V
IN
CC
I
Drops Below 1μA
0.4
2.5
100
VIN
EN/UVLO = 1.15V
EN/UVLO = 1.33V
2
μA
nA
20
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LT3957 is tested in a feedback loop which servos V to the
reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
FBX
Note 4: FBX overvoltage lockout is measured at V
relative
FBX(OVERVOLTAGE)
to regulated V
.
FBX(REG)
Note 2: The LT3957E is guaranteed to meet performance specifications
from the 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3957I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 5: For 3V ≤ V < 6V, the EN/UVLO pin must not exceed V .
IN
IN
Note 6: EN/UVLO = 1.33V when V = 3V.
IN
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
Quiescent Current
vs Temperature, VIN
1605
1600
1590
1585
1580
–788
–790
–792
–794
–796
–798
–800
–802
–804
1.8
1.7
1.6
1.5
1.4
V
= INTV = 3V
CC
IN
V
= 40V
SHDN/UVLO = 1.33V
IN
V
= 24V
IN
V
= 40V
IN
V = 24V
IN
V
= 8V
IN
V
V
= 8V
IN
V
= INTV = 3V,
V
= INTV = 3V
IN CC
= 40V
IN
CC
IN
V
= 24V
IN
SHDN/UVLO = 1.33V
–50
0
25
50
75 100 125
–50
0
25
50
75
125
–25
–25
100
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3957 G01
3957 G02
3957 G03
3957f
4
LT3957
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.
Dynamic Quiescent Current
vs Switching Frequency
Normalized Switching
Frequency vs FBX
RT vs Switching Frequency
1000
120
100
80
60
40
20
0
12
10
8
6
100
4
2
0
10
–0.8
0
0.4
0.8
1.2
1.6
–0.4
100
300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
3957 G04
0
100 200 300
400 500 600 700 800 900 1000
200
FBX VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
3957 G05
3957 G06
Switching Frequency
vs Temperature
SW Pin Current Limit
vs Temperature
SW Pin Current Limit
vs Duty Cycle
325
320
315
310
305
6.6
6.4
6.2
6.0
5.8
5.6
5.4
6.6
6.4
6.2
6.0
5.8
5.6
5.4
R
= 41.2k
T
300
295
290
285
280
275
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
125
–50
0
25
75 100
–25
0
20
40
60
80
100
TEMPERATURE (°C)
DUTY CYCLE (%)
3957 G08
3957 G09
3957 G07
EN/UVLO Hysteresis Current
vs Temperature
EN/UVLO Threshold
vs Temperature
EN/UVLO Current vs Voltage
1.28
1.26
1.24
1.22
1.20
1.18
40
30
20
10
0
2.4
2.2
2.0
1.8
1.6
EN/UVLO RISING
EN/UVLO FALLING
50
75 100 125
0
10
20
30
40
–50
0
25
–25
50
TEMPERATURE (°C)
125
–50
0
25
75 100
–25
EN/UVLO VOLTAGE (V)
TEMPERATURE (°C)
3957 G11
3957 G10
3957 G12
3957f
5
LT3957
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.
INTVCC Minimum Output
Current Limit vs VIN
INTVCC vs Temperature
INTVCC Load Regulation
5.4
5.3
5.2
5.1
5.0
90
80
70
60
50
40
30
20
10
0
5.3
5.2
V
= 6V
T
= 125°C
CC
IN
J
INTV = 3V
5.1
5.0
4.9
4.8
1
10
IN
100
50
60
–50
0
25
50
75 100 125
0
30
40
INTV LOAD (mA)
–25
10
20
V
(V)
TEMPERATURE (°C)
CC
3957 G14
3957 G13
3957 G15
INTVCC Dropout Voltage
vs Current, Temperature
Internal Switch On-Resistance
vs Temperature
INTVCC Line Regulation
700
600
500
400
300
200
100
0
50
45
40
35
30
25
20
15
10
5
5.30
5.25
5.20
5.15
5.10
V
= 5V
125°C
IN
75°C
25°C
0°C
–40°C
0
–50 –25
0
25
50
75 100 125
5
10
15
20
0
30 35 40
0
5
10 15 20 25
(V)
INTV LOAD (mA)
CC
TEMPERATURE (°C)
V
IN
3957 G16
3957 G17
3957 G18
SEPIC FBX Frequency Foldback
Waveforms During Overcurrent
SEPIC Typical Start-Up
Waveforms
Internal Switch On-Resistance
vs INTVCC
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
26.6
V
= 12V
V
= 12V
IN
IN
V
OUT
10V/DIV
V
OUT
V
SW
5V/DIV
20V/DIV
I
+ I
L1A L1B
I
+ I
L1A L1B
5A/DIV
2A/DIV
3957 G20
3957 G21
5ms/DIV
50μs/DIV
SEE TYPICAL APPLICATION: 5V TO 16V INPUT,
12V OUTPUT SEPIC CONVERTER
SEE TYPICAL APPLICATION: 5V TO 16V INPUT,
12V OUTPUT SEPIC CONVERTER
4
5
6
7
8
3
INTV (V)
CC
3957 G19
3957f
6
LT3957
PIN FUNCTIONS
NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave
these pins open or connect them to the adjacent pins.
INTV (Pin 28): Regulated Supply for Internal Loads
CC
and Gate Driver. Supplied from V and regulated to
IN
5.2V (typical). INTV must be bypassed to SGND with a
CC
SENSE2 (Pin 3): The Current Sense Input for the Control
Loop. Connect this pin to SENSE1 pin directly or through
a low pass filter (connect this pin to SENSE1 pin through
a resistor, and to SGND through a capacitor).
minimum of 4.7μF capacitor placed close to pin. INTV
CC
can be connected directly to V , if V is less than 8V.
IN
IN
INTV can also be connected to a power supply whose
CC
voltage is higher than 5.5V, and lower than V , provided
IN
SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal
Ground. All small-signal components should connect to
this ground. SGND is connected to GND inside the IC to
ensure Kelvin connection for the internal switch current
sensing. Do not connect SGND and GND externally.
that supply does not exceed 8V.
VC (Pin 30): Error Amplifier Compensation Pin. Used to
stabilize the voltage loop with an external RC network.
Place compensation components between the VC pin
and SGND.
SENSE1 (Pin 6): The Current Sense Output of the Inter-
nal N-channel MOSFET. Connect this pin to SENSE2 pin
directly or through a low pass filter (connect this pin to
SENSE1 pin through a resistor, then connect SENSE2 to
SGND through a capacitor).
FBX (Pin 31): Positive and Negative Feedback Pin. Re-
ceives the feedback voltage from the external resistor
divider between the output and SGND. Also modulates the
switching frequency during start-up and fault conditions
when FBX is close to SGND.
SW (Pins 8, 9, 20, 21, Exposed Pad Pin 38): Drain of
Internal Power N-channel MOSFET.
SS (Pin 32): Soft-Start Pin. This pin modulates compen-
sation pin voltage (VC) clamp. The soft-start interval is
set with an external capacitor between SS pin and SGND.
The pin has a 10μA (typical) pull-up current source to
an internal 2.5V rail. The soft-start pin is reset to SGND
GND (Pins 12, 13, 14, 15, 16, 17): Ground. These pins
connecttothesourceterminalofinternalpowerN-channel
MOSFET through an internal sense resistor. GND is con-
nected to SGND inside the IC to ensure Kelvin connection
for the internal switch current sensing. Do not connect
GND and SGND externally.
by an undervoltage condition at EN/UVLO, an INTV
CC
undervoltage or overvoltage condition or an internal
thermal lockout.
EN/UVLO (Pin 25): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
isokayto enable switching. Risinghysteresis is generated
by the external resistor divider and an accurate internal
2μA pull-down current. An undervoltage condition resets
soft-start. Tie to 0.4V, or less, to disable the device and
RT (Pin 33): Switching Frequency Adjustment Pin. Set
the frequency using a resistor to SGND. Do not leave this
pin open.
SYNC (Pin 34): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an R resistor should be chosen
T
to program a switching frequency 20% slower than the
SYNC pulse frequency. Tie the SYNC pin to SGND if this
feature is not used. SYNC is bypassed when FBX is close
to SGND.
reduce V quiescent current below 1μA.
IN
V (Pin 27): Input Supply Pin. The V pin can be locally
IN
IN
bypassed with a capacitor to GND (not SGND).
3957f
7
LT3957
BLOCK DIAGRAM
C
L1
DC
D1
V
V
OUT
IN
R4
R3
C
IN
L2
C
OUT
•
EN/UVLO
V
SW
IN
25
27
8, 9, 20,
21, 38
A10
–
+
I
S1
2μA
1.22V
2.5V
INTERNAL
REGULATOR
AND UVLO
CURRENT
LIMIT
I
S2
10μA
UVLO
M2
5.2V LDO
A8
Q3
INTV
CC
2.5V
28
G4
2.7V
C
VCC
I
S3
A11
A12
1.72V
–
+
TLO
165˚C
DRIVER
G6
SR1
S
V
C
–
+
–
+
G5
G2
A7
R
O
M1
–0.88V
SENSE1
GND
6
Q2
PWM
COMPARATOR
R
SENSE
48mV
–
+
1.6V
+
A6
A5
A1
12, 13, 14,
15, 16, 17
V
SLOPE
RAMP
–
ISENSE
SENSE
SENSE2
3
+
–
+
–
A2
RAMP
GENERATOR
–0.8V
1.28V
–
A3
100kHz-1MHz
OSCILLATOR
+
G1
1.2V
+
FREQUENCY
FOLDBACK
+
A4
Q1
–
FREQ
PROG
FBX
VC
SS
SYNC
RT
SGND
31
30
32
34
33
3957 F01
4, 23,
24, 37
R2
V
OUT
C
C
SS
R
R
T
C2
C
R1
C
C1
Figure 1. LT3957 Block Diagram Working as a SEPIC Converter
3957f
8
LT3957
APPLICATIONS INFORMATION
Main Control Loop
The LT3957 has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
The LT3957 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation. Op-
eration can be best understood by referring to the Block
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1)
andturnsontheinternalpowerMOSFETswitchM1through
driver G2. The switch current flows through the internal
current sensing resistor R
and generates a voltage
SENSE
proportional to the switch current. This current sense
voltage V (amplified by A5) is added to a stabilizing
ISENSE
slope compensation ramp and the resulting sum (SLOPE)
isfedintothepositiveterminalofthePWMcomparatorA7.
When SLOPE exceeds the level at the negative input of A7
(VC pin), SR1 is reset, turning off the power switch. The
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
Programming Turn-On and Turn-Off Thresholds with
the EN/UVLO Pin
The EN/UVLO pin controls whether the LT3957 is enabled
or is in shutdown state. A micropower 1.22V reference,
a comparator A10 and a controllable current source I
S1
allow the user to accurately program the supply voltage
at which the IC turns on and off. The falling value can be
accurately set by the resistor dividers R3 and R4. When
EN/UVLO is above 0.4V, and below the 1.22V threshold,
TheLT3957hasaswitchcurrentlimitfunction.Thecurrent
sense voltage is input to the current limit comparator A6.
If the SENSE2 pin voltage is higher than the sense current
the small pull-down current source I (typical 2μA) is
S1
active.
limit threshold V
(48mV, typical), A6 will reset
SENSE(MAX)
SR1 and turn off M1 immediately.
The purpose of this current is to allow the user to program
therisinghysteresis.TheBlockDiagramofthecomparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
The LT3957 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost, flyback or SEPIC converter to gen-
erate positive output voltage, or as an inverting converter
to generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
(R3 +R4)
VVIN,FALLING =1.22•
R4
VVIN,RISING = 2µA • R3 + VIN,FALLING
age divider (R1 and R2) connected from V
to SGND.
OUT
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
Comparator A2 becomes inactive and comparator A1
performs the inverting amplification from FBX to VC.
When the LT3957 is in an inverting configuration, the
FBX pin is pulled down to –0.8V by a voltage divider
to the input voltage V for always-on operation.
IN
connected from V
to SGND. Comparator A1 becomes
OUT
inactive and comparator A2 performs the noninverting
amplification from FBX to VC.
3957f
9
LT3957
APPLICATIONS INFORMATION
INTV Regulator Bypassing and Operation
In SEPIC or flyback applications, the INTV pin can be
CC
CC
connected to the output voltage V
through a blocking
OUT
Aninternal,lowdropout(LDO)voltageregulatorproduces
diode, as shown in Figure 2, if V
conditions:
meets the following
OUT
the 5.2V INTV supply which powers the gate driver, as
CC
shown in Figure 1. The LT3957 contains an undervoltage
lockout comparator A8 for the INTV supply. The INTV
1. V
2. V
< V (pin voltage)
CC
CC
OUT
OUT
IN
undervoltage (UV) threshold is 2.7V (typical), with 0.1V
< 8V
hysteresis, to ensure that the internal MOSFET has suf-
A resistor R can be connected, as shown in Figure 2, to
ficient gate drive voltage before turning on. When INTV
VCC
CC
limit the inrush current from V . Regardless of whether
is below the UV threshold, the internal power switch will
be turned off and the soft-start operation will be triggered.
The logic circuitry within the LT3957 is also powered from
OUT
or not the INTV pin is connected to an external voltage
CC
source, it is always necessary to have the driver circuitry
bypassedwitha4.7μFlowESRceramiccapacitortoground
the internal INTV supply.
CC
immediately adjacent to the INTV and SGND pins.
CC
The INTV regulator must be bypassed to SGND imme-
CC
If LT3957 operates at a low V and high switching fre-
diately adjacent to the IC pins with a minimum of 4.7μF
ceramic capacitor. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
driver.
IN
quency,thevoltagedropacrossthedrainandthesourceof
the LDO PMOS (M2 in Figure 1) could push INTV to be
CC
below the UV threshold. To prevent this from happening,
the INTV pin can be shorted directly to the V pin. V
CC
IN
IN
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the internal power
MOSFET. The on-chip power dissipation can be significant
when the internal power MOSFET is being driven at a high
must not exceed the INTV Absolute Maximum Rating
CC
(8V). In this condition, the internal LDO will be turned off
and the gate driver will be powered directly from V . It is
IN
recommended that INTV pin be shorted to the V pin if
CC
IN
frequency and the V voltage is high.
IN
V is lower than 3.5V at 1MHz switching frequency, or V
IN
IN
Aneffectiveapproachtoreducethepowerconsumptionof
theinternalLDOforgatedriveandtoimprovetheefficiency
is lower than 3.2V at 100kHz switching frequency. With
the INTV pin shorted to V , however, a small current
CC
IN
is to tie the INTV pin to an external voltage source high
(around 16μA) will load the INTV in shutdown mode.
CC
CC
enough to turn off the internal LDO regulator.
D
VCC
R
VCC
V
INTV
OUT
CC
LT3957
C
VCC
4.7μF
SGND
3957 F02
Figure 2. Connecting INTVCC to VOUT
3957f
10
LT3957
APPLICATIONS INFORMATION
Operating Frequency and Synchronization
Duty Cycle Consideration
The choice of operating frequency may be determined by
on-chippowerdissipation(alowswitchingfrequencymay
be required to ensure IC junction temperature does not
exceed125°C),otherwiseitisatrade-offbetweenefficiency
and component size. Low frequency operation improves
efficiency by reducing gate drive current and MOSFET
and diode switching losses. However, lower frequency
operation requires a physically larger inductor. Switching
frequency also has implications for loop compensation.
The LT3957 uses a constant-frequency architecture that
can be programmed over a 100kHz to 1000kHz range
with a single external resistor from the RT pin to SGND,
Switching duty cycle is a key variable defining con-
verter operation. As such, its limits must be considered.
Minimum on-time is the smallest time duration that the
LT3957 is capable of turning on the power MOSFET. This
time is typically about 240ns (see Minimum On-Time in
the Electrical Characteristics table). In each switching
cycle, the LT3957 keeps the power switch off for at least
220ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
Theminimumon-time,minimumoff-timeandtheswitching
frequency define the minimum and maximum switching
duty cycles a converter is able to generate:
as shown in Figure 1. A table for selecting the value of R
T
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
for a given operating frequency is shown in Table 1.
Table 1. Timing Resistor (RT) Value
SWITCHING FREQUENCY (kHz)
R (kΩ)
T
Programming the Output Voltage
100
200
300
400
500
600
700
800
900
1000
140
63.4
41.2
30.9
24.3
19.6
16.5
14
The output voltage V
is set by a resistor divider, as
OUT
shown in Figure 1. The positive and negative V
by the following equations:
are set
OUT
R2
R1
⎛
⎞
VOUT,POSITIVE =1.6V • 1+
⎜
⎟
⎠
⎝
R2
R1
⎛
⎞
VOUT,NEGATIVE = –0.8V • 1+
⎜
⎟
⎠
⎝
12.1
10.5
The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
TheoperatingfrequencyoftheLT3957canbesynchronized
to an external clock source. By providing a digital clock
signal into the SYNC pin, the LT3957 will operate at the
SYNC clock frequency. The LT3957 detects the rising edge
of each clock cycle. If this feature is used, an R resistor
T
should be chosen to program a switching frequency 20%
slowerthanSYNCpulsefrequency.Itisrecommendedthat
the SYNC pin has a minimum pulse width of 200ns. Tie
the SYNC pin to SGND if this feature is not used.
3957f
11
LT3957
APPLICATIONS INFORMATION
Soft-Start
FBX Frequency Foldback
When V is very low during start-up, or an output short-
The LT3957 contains several features to limit peak switch
OUT
circuit on a SEPIC, an inverting, or a flyback converter, the
switchingregulatormustoperateatlowdutycyclestokeep
the power switch current below the current limit, since
the inductor current decay rate is very low during switch
off time. The minimum on-time limitation may prevent the
switcher from attaining a sufficiently low duty cycle at the
programmed switching frequency. So, the switch current
may keep increasing through each switch cycle, exceed-
ing the programmed current limit. To prevent the switch
peak currents from exceeding the programmed value, the
LT3957 contains a frequency foldback function to reduce
the switching frequency when the FBX voltage is low (see
the Normalized Switching Frequency vs FBX graph in the
Typical Performance Characteristics section).
currents and output voltage (V ) overshoot during
OUT
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since V
is far from its final value,
OUT
the feedback loop is saturated and the regulator tries to
chargetheoutputcapacitorasquicklyaspossible,resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT3957 addresses this mechanism with the SS pin.
As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the VC pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its final value while limiting the
start-up peak currents. The typical start-up waveforms
are shown in the Typical Performance Characteristics
During frequency foldback, external clock synchroniza-
tion is disabled to prevent interference with frequency
reducing operation.
section. The inductor current I slewing rate is limited by
L
Loop Compensation
the soft-start function.
Loop compensation determines the stability and transient
performance. The LT3957 uses current mode control to
regulate the output which simplifies loop compensation.
Theoptimumvaluesdependontheconvertertopology,the
componentvaluesandtheoperatingconditions(including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3957, a series resistor-capacitor
network is usually connected from the VC pin to SGND.
Figure 1 shows the typical VC compensation network.
For most applications, the capacitor should be in the
range of 470pF to 22nF, and the resistor should be in the
range of 5k to 50k. A small capacitor is often connected
in parallel with the RC compensation network to attenu-
ate the VC voltage ripple induced from the output voltage
ripple through the internal error amplifier. The parallel
capacitor usually ranges in value from 10pF to 100pF. A
practical approach to design the compensation network
is to start with one of the circuits in this data sheet that
is similar to your application, and tune the compensation
network to optimize the performance. Stability should
thenbecheckedacrossalloperatingconditions, including
load current, input voltage and temperature. Application
Besides start-up (with EN/UVLO), soft-start can also be
triggered by the following faults:
1. INTV < 2.85V
CC
2. Thermal lockout (TLO > 165°C)
Any of these three faults will cause the LT3957 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10μA current source I starts
S2
charging the SS pin, initiating a soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
1.25V
10µA
TSS =CSS
•
Note 76 is a good reference on loop compensation.
3957f
12
LT3957
APPLICATIONS INFORMATION
The Internal Power Switch Current
On-Chip Power Dissipation and Thermal Lockout (TLO)
Theon-chippowerdissipationofLT3957canbeestimated
using the following equation:
For control and protection, the LT3957 measures the
internal power MOSFET current by using a sense resistor
(R ) between GND and the MOSFET source. Figure 3
SENSE
2
2
P ≈ I
IC
• D • R
+ V
• I • ƒ • 200pF/A +
PEAK SW
SW
DS(ON)
shows a typical waveform of the internal switch current
(I ).
SW
V • (1.6mA + ƒ • 10nC)
IN
where R
is the internal switch on-resistance which
DS(ON)
Duetothecurrentlimit(minimum5A)oftheinternalpower
switch, the LT3957 should be used in the applications
canbeobtainedfromtheTypicalPerformanceCharacteris-
ticssection.V isthepeakswitchoff-statevoltage.
SW(PEAK)
ThemaximumpowerdissipationP
that the switch peak current I
during steady state
SW(PEAK)
canbeobtained
IC(MAX)
IN
normal operation is lower than 5A by a sufficient margin
(10% or higher is recommended).
by comparing P across all the V range at the maximum
IC
output current . The highest junction temperature can be
estimated using the following equation:
The LT3957 switching controller incorporates 100ns
timing interval to blank the ringing on the current sense
T
≈ T + P
• 42°C/W
IC(MAX)
J(MAX)
A
signal across R
immediately after M1 is turned on.
SENSE
ItisrecommendedtomeasuretheICtemperatureinsteady
state to verify that the junction temperature limit is not
exceeded. A low switching frequency may be required to
This ringing is caused by the parasitic inductance and
capacitance of the PCB trace, the sense resistor, the diode,
and the MOSFET. The 100ns timing interval is adequate
for most of the LT3957 applications. In the applications
that have very large and long ringing on the current sense
signal,asmallRCfiltercanbeaddedtofilterouttheexcess
ringing. Figure 4 shows the RC filter on the SENSE1 and
SENSE2 pins. It is usually sufficient to choose 22Ω for
ensure T
does not exceed 125°C.
J(MAX)
If LT3957 die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start operation will be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
R
and 2.2nF to 10nF for C . Keep R ’s resistance
FLT
FLT FLT
low. Remember that there is 65μA (typical) flowing out of
the SENSE2 pin. Adding R will affect the internal power
switch current limit threshold:
FLT
LT3957
SENSE1
65µA •RFLT
48mV
⎛
⎞
R
FLT
ISW _ILIM = 1−
•5A
⎜
⎟
⎠
⎝
SENSE2
C
FLT
SGND
3957 F04
I
SW
$I
SW
Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin
I
SW(PEAK)
t
DT
S
T
S
3957 F03
Figure 3. The Switch Current During a Switching Cycle
3957f
13
LT3957
APPLICATIONS INFORMATION
APPLICATION CIRCUITS
Due to the current limit of its internal power switch, the
LT3957 should be used in a boost converter whose maxi-
The LT3957 can be configured as different topologies. The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.
mum output current (I
) is less than the maximum
O(MAX)
output current capability by a sufficient margin (10% or
higher is recommended):
Boost Converter: Switch Duty Cycle and Frequency
VIN(MIN)
IO(MAX)
<
• 5A − 0.5• ΔI
SW
(
)
The LT3957 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
VOUT
The inductor ripple current ΔI has a direct effect on the
SW
choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of
ΔI
increases output current capability, but requires
SW
large inductances and reduces the current loop gain (the
converter will approach voltage mode). Accepting larger
values of ΔI
provides fast transient response and
SW
allows the use of low inductances, but results in higher
input current ripple and greater core losses, and reduces
output current capability.
The conversion ratio as a function of duty cycle is
VOUT
VIN 1−D
1
=
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalueoftheboostconvertercanbedetermined
using the following equation:
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
VIN(MIN)
voltage (V ) and the input voltage (V ). The maximum
OUT
duty cycle (D
minimum input voltage:
IN
L =
•DMAX
ΔISW • ƒ
) occurs when the converter has the
MAX
The peak inductor current is the switch current limit (5.9A
typical), and the RMS inductor current is approximately
VOUT − VIN(MIN)
DMAX
=
equal to I
. The user should choose the inductors
VOUT
L(MAX)
having sufficient saturation and RMS current ratings.
Discontinuous conduction mode (DCM) provides higher
conversionratiosatagivenfrequencyatthecostofreduced
efficiencies and higher switching currents.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current.
Boost Converter: Maximum Output Current Capability
and Inductor Selection
For the boost topology, the maximum average inductor
current is:
1
IL(MAX)= IO(MAX)
•
1−DMAX
It is recommended that the peak repetitive reverse voltage
is higher than V
safety margin is usually sufficient).
rating V
by a safety margin (a 10V
RRM
OUT
3957f
14
LT3957
APPLICATIONS INFORMATION
The power dissipated by the diode is:
t
ON
t
OFF
$V
COUT
P = I
• V
D
D
O(MAX)
V
OUT
(AC)
where V is diode’s forward voltage drop, and the diode
D
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
junction temperature is:
$V
ESR
3957 F05
T = T + P • R
θJA
J
A
D
The R to be used in this equation normally includes the
Figure 5. The Output Ripple Waveform of a Boost Converter
θJA
R
forthedeviceplusthethermalresistancefromtheboard
θJC
to the ambient temperature in the enclosure. T must not
Theoutputcapacitorinaboostregulatorexperienceshigh
RMSripplecurrents, asshowninFigure5. TheRMSripple
current rating of the output capacitor can be determined
using the following equation:
J
exceed the diode maximum junction temperature rating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
thesethreeparameters(ESR,ESLandbulkC)ontheoutput
voltage ripple waveform for a typical boost converter is
illustrated in Figure 5.
DMAX
1−DMAX
IRMS(COUT) ≥IO(MAX)
•
MultiplecapacitorsareoftenparalleledtomeetESRrequire-
ments.Typically,oncetheESRrequirementissatisfied,the
capacitance is adequate for filtering and has the required
RMS current rating. Additional ceramic capacitors in par-
allel are commonly used to reduce the effect of parasitic
inductance in the output capacitor, which reduces high
frequency switching noise on the converter output.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ΔV
and the charging/discharg-
ESR
Boost Converter: Input Capacitor Selection
ing ΔV
. For the purpose of simplicity, we will choose
COUT
2% for the maximum output ripple, to be divided equally
between ΔV and ΔV . This percentage ripple will
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 1μF to 100μF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
ESR
COUT
change,dependingontherequirementsoftheapplication,
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
0.01• VOUT
ID(PEAK)
ESRCOUT
≤
The RMS input capacitor ripple current for a boost con-
verter is:
For the bulk C component, which also contributes 1% to
the total ripple:
I
= 0.3 • ΔI
L
RMS(CIN)
IO(MAX)
COUT
≥
0.01• VOUT • ƒ
3957f
15
LT3957
APPLICATIONS INFORMATION
FLYBACK CONVERTER APPLICATIONS
Figure 7 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
TheLT3957canbeconfiguredasaflybackconverterforthe
applications where the converters have multiple outputs,
high output voltages or isolated outputs. Due to the 40V
ratingoftheinternalpowerswitch, LT3797shouldbeused
in low input voltage flyback converters. Figure 6 shows a
simplified flyback converter.
period T , three subintervals occur: DT , D2T , D3T .
S
S
S
S
During DT , M is on, and D is reverse-biased. During
S
D2T , M is off, and L is conducting current. Both L and
S
S
P
L currents are zero during D3T .
S
S
V
SW
SW
The flyback converter has a very low parts count for mul-
tipleoutputs, andwithprudentselectionofturnsratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
thehighpeakcurrents,highpeakvoltagesandconsequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.
I
I
SW(MAX)
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency.
I
D
I
D(MAX)
DT
S
D2T
D3T
S
t
S
T
S
3957 F07
SUGGESTED
RCD SNUBBER
D
Figure 7. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
N :N
P
S
V
IN
+
–
+
–
SN
+
V
I
D
C
C
C
+
R
IN
SN
SN
V
OUT
L
L
S
P
OUT
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
D
SN
VOUT NS
VIN NP D2
D
I
SW
=
•
SW
LT3957
GND
According to Figure 6, the peak SW voltage is:
V
= V
+ V
3957 F06
SW(PEAK)
IN(MAX) SN
where V is the snubber capacitor voltage. A smaller V
SN
SN
Figure 6. A Simplified Flyback Converter
results in a larger snubber loss. A reasonable V is 1.5
SN
to 2 times of the reflected output voltage:
Flyback Converter: Switch Duty Cycle and Turns Ratio
VOUT •NP
The flyback converter conversion ratio in the continuous
mode operation is:
VSN =k •
NS
VOUT NS
VIN NP 1−D
D
k = 1.5 ~ 2
=
•
where N /N is the second to primary turns ratio. D is
S
P
duty cycle.
3957f
16
LT3957
APPLICATIONS INFORMATION
AccordingtotheAbsoluteMaximumRatingstable,theSW
voltage Absolute Maximum value is 40V. Therefore, the
maximum primary to secondary turns ratio (for both the
continuous and the discontinuous operation) should be.
output current capability by a sufficient margin (10% or
higher is recommended):
VIN(MIN)
IO(MAX)
<
•DMAX • 5A − 0.5• ΔI
SW
(
)
VOUT
40V − V
NP
NS
IN(MAX)
≤
The transformer ripple current ΔI has a direct effect on
k • VOUT
SW
the design/choice of the transformer and the converter’s
Accordingtotheprecedingequations,theuserhasrelative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select-
ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
output current capability. Choosing smaller values of
ΔI increases the output current capability, but requires
SW
large primary and secondary inductances and reduce the
current loop gain (the converter will approach voltage
mode). Accepting larger values of ΔI allows the use
SW
of low primary and secondary inductances, but results
in higher input current ripple, greater core losses, and
reduces the output current capability.
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the primary
winding,theprimarywindinginductancecanbecalculated
using the following equation:
• Lower MOSFET RMS current I
, but higher
SW(RMS)
MOSFET V peak voltage
SW
• Lower diode peak reverse voltage, but higher diode
RMS current I
VIN(MIN)
D(RMS)
L =
•DMAX
ΔISW • ƒ
• Higher transformer turns ratio (N /N )
P
S
The primary winding peak current is the switch current
limit (typical 5.9A). The primary and secondary maximum
RMS currents are:
It is recommended to choose a duty cycle between 20%
and 80%.
Flyback Converter: Maximum Output Current
Capability and Transformer Design
POUT(MAX)
ILP(RMS)
≈
≈
DMAX • VIN(MIN) • η
The maximum output current capability and transformer
design for continuous conduction mode (CCM) is chosen
as presented here.
IOUT(MAX)
ILS(RMS)
1−DMAX
Themaximumdutycycle(D )occurswhentheconverter
MAX
where η is the converter efficiency.
has the minimum V :
IN
Based on the preceding equations, the user should de-
sign/choose the transformer having sufficient saturation
and RMS current ratings.
⎛
⎞
NP
VOUT
•
⎜
⎟
N
⎝
⎠
S
DMAX
=
⎛
⎞
NP
N
VOUT
•
+ V
Flyback Converter: Snubber Design
IN(MIN)
⎜
⎟
⎝
⎠
S
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOS-
FET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
Due to the current limit of its internal power switch, the
LT3957shouldbeusedinaflybackconverterwhosemaxi-
mum output current (I
) is less than the maximum
O(MAX)
3957f
17
LT3957
APPLICATIONS INFORMATION
In some cases a snubber circuit will be required to avoid
overvoltagebreakdownattheMOSFET’sdrainnode.There
are different snubber circuits (such as RC snubber, RCD
snubber, Zener clamp, etc.), and Application Note 19 is a
good reference on snubber design. An RC snubber circuit
can be connected between SW and GND to damp the
ringing on SW pins. The snubber resistor values should
be close to the impedance of the parasitic resonance. The
snubber capacitor value should be larger than the circuit
parasitic capacitance, but be small enough to keep the
snubber resistor power dissipation low.
Approximate the required peak repetitive reverse voltage
rating V using:
RRM
NS
VRRM
>
• VIN(MAX) + VOUT
NP
The power dissipated by the diode is:
P = I • V
D
O(MAX)
D
and the diode junction temperature is:
T = T + P • R
J
A
D
θJA
The R to be used in this equation normally includes the
θJA
If the RC snubber is insufficient to prevent SW pins over-
voltage, the RCD snubber can be used to limit the peak
voltage on the SW pins, which is shown in Figure 6.
R
forthedevice,plusthethermalresistancefromtheboard
θJC
to the ambient temperature in the enclosure. T must not
J
exceed the diode maximum junction temperature rating.
The snubber resistor value (R ) can be calculated by the
SN
following equation:
Flyback Converter: Output Capacitor Selection
NP
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
V2SN − VSN • VOUT
•
NS
I2SW(PEAK) •LLK • ƒ
RSN = 2 •
for the calculation of C
and ESR
.
OUT
COUT
The RMS ripple current rating of the output capacitors
in continuous operation can be determined using the
following equation:
L
is the leakage inductance of the primary winding,
LK
which is usually specified in the transformer character-
istics. L can be obtained by measuring the primary
LK
inductance with the secondary windings shorted. The
DMAX
snubber capacitor value (C ) can be determined using
SN
IRMS(COUT),CONTINUOUS ≈ IO(MAX)
•
1−DMAX
the following equation:
VSN
ΔVSN •RSN • ƒ
Flyback Converter: Input Capacitor Selection
CCN
=
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
continuous operation can be determined using the fol-
lowing equation:
where ΔV is the voltage ripple across C . A reasonable
SN
SN
ΔV is 5% to 10% of V . The reverse voltage rating of
SN
SN
D
should be higher than the sum of V and V
.
SN
SN
IN(MAX)
A Zener clamp can also be connected between SW and
GND to ensure SW voltage does not exceed 40V.
Flyback Converter: Output Diode Selection
POUT(MAX)
1−DMAX
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
IRMS(CIN),CONTINUOUS
≈
•
VIN(MIN) • η
DMAX
3957f
18
LT3957
APPLICATIONS INFORMATION
SEPIC CONVERTER APPLICATIONS
can also be wound on the same core, since identical volt-
ages are applied to L1 and L2 throughout the switching
cycle.
The LT3957 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
VOUT + VD
D
1−D
=
DMAX
1−DMAX
VIN
IL1(MAX) =IIN(MAX) =IO(MAX)
•
in continuous conduction mode (CCM).
IL2(MAX) =IO(MAX)
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
Due to the current limit of its internal power switch,
the LT3957 should be used in a SEPIC converter whose
maximum output current (I
) is less than the output
O(MAX)
Compared to the flyback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
output diode voltages are clamped by the capacitors (C ,
current capability by a sufficient margin (10% or higher
is recommended):
IN
IO(MAX) < 1−D
• 5A − 0.5• ΔI
)
(
SW
(
)
MAX
C
and C ), therefore, there is less voltage ringing
DC
OUT
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the current through inductor
L1 (which is series with the input) is continuous.
The inductor ripple currents ΔI and ΔI are identical:
L1
L2
ΔI = ΔI = 0.5 • ΔI
SW
L1
L2
The inductor ripple current ΔI has a direct effect on the
SW
choice of the inductor value and the converter’s maximum
outputcurrentcapability.ChoosingsmallervaluesofΔI
SW
SEPIC Converter: Switch Duty Cycle and Frequency
requires large inductances and reduces the current loop
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
gain(theconverterwillapproachvoltagemode).Accepting
larger values of ΔI allows the use of low inductances,
SW
voltage (V ), the input voltage (V ) and the diode
OUT
IN
but results in higher input current ripple and greater core
forward voltage (V ).
D
losses and reduces output current capability.
Themaximumdutycycle(D )occurswhentheconverter
MAX
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the induc-
tor, the inductor value (L1 and L2 are independent) of the
SEPIC converter can be determined using the following
equation:
has the minimum input voltage:
VOUT + VD
DMAX
=
VIN(MIN) + VOUT + VD
VIN(MIN)
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
L1 = L2 =
•DMAX
0.5• ΔISW • ƒ
As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but
For most SEPIC applications, the equal inductor values
will fall in the range of 1μH to 100μH.
3957f
19
LT3957
APPLICATIONS INFORMATION
BymakingL1=L2,andwindingthemonthesamecore,the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPICconverteraresimilartothoseoftheboostconverter.
Please refer to the Boost Converter: Output Capacitor
Selection and Boost Converter: Input Capacitor Selection
sections.
VIN(MIN)
L =
•DMAX
ΔISW • ƒ
Thismaintainsthesameripplecurrentandenergystorage
in the inductors. The peak inductor currents are:
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (C ,
DC
I
I
= I
= I
+ 0.5 • ΔI
+ 0.5 • ΔI
L1(PEAK)
L2(PEAK)
L1(MAX)
L2(MAX)
L1
L2
as shown in Figure 1) should be larger than the maximum
input voltage:
V
> V
IN(MAX)
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
CDC
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
Basedontheprecedingequations,theusershouldchoose
the inductors having sufficient saturation and RMS cur-
rent ratings.
DC
IN
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
lowing equation:
SEPIC Converter: Output Diode Selection
VOUT + VD
VIN(MIN)
IRMS(CDC) >IO(MAX)
•
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
It is recommended that the peak repetitive reverse voltage
rating V
is higher than V
+ V
by a safety
RRM
OUT
IN(MAX)
INVERTING CONVERTER APPLICATIONS
margin (a 10V safety margin is usually sufficient).
TheLT3957canbeconfiguredasadual-inductorinverting
topology, as shown in Figure 8. The V
The power dissipated by the diode is:
to V ratio is:
OUT
IN
P = I
• V
D
D
O(MAX)
VOUT − V
D
1−D
D = −
where V is diode’s forward voltage drop, and the diode
VIN
D
junction temperature is:
in continuous conduction mode (CCM).
T = T + P • R
θJA
J
A
D
The R used in this equation normally includes the R
C
+
DC
θJA
θJC
L1
L2
–
for the device, plus the thermal resistance from the board,
V
IN
+
–
to the ambient temperature in the enclosure. T must not
C
J
IN
C
OUT
V
OUT
exceed the diode maximum junction temperature rating.
SW
LT3957
+
D1
+
3757 F10
GND
Figure 8. A Simplified Inverting Converter
3957f
20
LT3957
APPLICATIONS INFORMATION
Inverting Converter: Switch Duty Cycle and Frequency
Inverting Converter: Selecting the DC Coupling Capacitor
ForaninvertingconverteroperatinginCCM,thedutycycle
of the main switch can be calculated based on the negative
output voltage (V ) and the input voltage (V ).
The DC voltage rating of the DC coupling capacitor
(C , as shown in Figure 10) should be larger than the
DC
maximum input voltage minus the output voltage (nega-
tive voltage):
OUT
IN
Themaximumdutycycle(D )occurswhentheconverter
MAX
has the minimum input voltage:
V
> V
– V
IN(MAX) OUT
CDC
VOUT − VD
VOUT − VD − VIN(MIN)
C
has nearly a rectangular current waveform. During
DC
DMAX
=
the switch off-time, the current through C is I , while
DC
IN
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
lowing equation:
Inverting Converter: Output Diode and Input Capacitor
Selections
DMAX
1−DMAX
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those
of the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
IRMS(CDC) >IO(MAX)
•
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
Inverting Converter: Output Capacitor Selection
Board Layout
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
convertersforsimilaroutputripples. Thisisduetothefact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
outputcapacitorsarecontinuous.Theoutputripplevoltage
isproducedbytheripplecurrentofL2flowing throughthe
ESR and bulk capacitance of the output capacitor:
The high power and high speed operation of the LT3957
demands careful attention to board layout and component
placement. Careful attention must be paid to the internal
power dissipation of the LT3957 at high input voltages,
highswitchingfrequencies,andhighinternalpowerswitch
currents to ensure that a junction temperature of 125°C is
not exceeded. This is especially important when operating
at high ambient temperatures. Exposed pads on the bot-
tom of the package are SGND and SW terminals of the IC,
and must be soldered to a SGND ground plane and a SW
plane respectively. It is recommended that multiple vias
in the printed circuit board be used to conduct heat away
from the IC and into the copper planes with as much as
area as possible.
⎛
⎜
⎝
⎞
⎠
1
ΔVOUT(P–P) = ΔIL2 • ESRCOUT
+
⎟
8 • ƒ •COUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
To prevent radiation and high frequency resonance
problems, proper layout of the components connected
to the IC is essential, especially the power paths with
higher di/dt. The following high di/dt loops of different
topologies should be kept as tight as possible to reduce
inductive ringing:
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
• In boost configuration, the high di/dt loop contains the
output capacitor, the internal power MOSFET and the
Schottky diode.
I
> 0.3 • ΔI
L2
RMS(COUT)
3957f
21
LT3957
APPLICATIONS INFORMATION
Make sure the inductive ringing does not exceed the
maximum rating of the internal power MOSFET (40V).
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
internal power MOSFET. The high di/dt secondary loop
contains the output capacitor, the secondary winding
and the output diode.
Thesmall-signalcomponentsshouldbeplacedawayfrom
highfrequencyswitchingnodes.Foroptimumloadregula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
thetopoftheoutputcapacitor(Kelvinconnection),staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3957 in order to keep the high impedance
FBX node short.
• In SEPIC configuration, the high di/dt loop contains
the internal power MOSFET, output capacitor, Schottky
diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop contains
internalpowerMOSFET,Schottkydiodeandthecoupling
capacitor.
Figure 9 shows the suggested layout of the 4.5V to16V
input, 24V output boost converter in the Typical Applica-
tion section.
CheckthestressontheinternalpowerMOSFETbymeasur-
ingtheSW-to-GNDvoltagedirectlyacrosstheICterminals.
R1
VIA TO V
OUT
R2
C
SS
R
R
C
C
T
C
36 35 34 33 32 31 30
C
VCC
1
2
3
4
28
27
R3
37
25
24
23
R4
LT3957
38
6
8
9
21
20
10
12 13 14 15 16 17
L1
D1
C
C
OUT
OUT
C
IN
VIA TO V
OUT
GND
V
OUT
V
IN
3958 F09
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
Figure 9. Suggested Layout of the 4.5V to 16V Input. 24V Output Boost Converter in the Typical Application Section
3957f
22
LT3957
APPLICATIONS INFORMATION
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.
Table 2. Recommended Component Manufacturers
VENDOR
AVX
COMPONENTS
WEB ADDRESS
avx.com
Capacitors
BH Electronics
Inductors,
Transformers
bhelectronics.com
Coilcraft
Inductors
Inductors
Diodes
coilcraft.com
bussmann.com
diodes.com
Cooper Bussmann
Diodes, Inc
General Semiconductor
Diodes
generalsemiconductor.
com
International Rectifier
Kemet
Diodes
Tantalum Capacitors
Toroid Cores
Diodes
irf.com
kemet.com
Magnetics Inc
Microsemi
Murata-Erie
Nichicon
mag-inc.com
microsemi.com
murata.co.jp
nichicon.com
onsemi.com
panasonic.com
pulseeng.com
sanyo.co.jp
Inductors, Capacitors
Capacitors
On Semiconductor
Panasonic
Pulse
Diodes
Capacitors
Inductors
Sanyo
Capacitors
Sumida
Inductors
sumida.com
t-yuden.com
Taiyo Yuden
TDK
Capacitors
Capacitors, Inductors component.tdk.com
Thermalloy
Tokin
Heat Sinks
Capacitors
aavidthermalloy.com
nec-tokinamerica.com
tokoam.com
Toko
Inductors
United Chemi-Con
Vishay
Capacitors
chemi-com.com
vishay.com
Inductors
Würth Elektronik
Vishay/Sprague
Zetex
Inductors
we-online.com
vishay.com
Capacitors
Small-Signal Discretes
zetex.com
3957f
23
LT3957
TYPICAL APPLICATIONS
4.5V to 16V Input, 24V Output Boost Converter
L1
10μH
D1
V
OUT
V
IN
24V
4.5V TO 16V
C
C
OUT
600mA
IN
R3
10μF
25V
X5R
10μF
50V
X5R
s2
V
SW
200k
IN
EN/UVLO
GND
R4
95.3k
LT3957
SGND
SYNC
SENSE1
R2
226k
SENSE2
FBX
R1
15.8k
INTV
CC
RT SS
VC
C
R
VCC
R
T
C
C
SS
4.7μF
10V
X5R
41.2k
6.8k
0.33μF
300kHz
C
C
22nF
3957 TA02a
C
C
: MURATA GRM31ER61H106KA12
IN
: TAIYO YUDEN UMK325BJ106MM
OUT
D1: VISHAY SILICONIX 10BQ040
L1: VISHAY SILICONIX IHLP-5050CE-1
Efficiency vs Output Current
100
95
90
85
80
75
70
V
= 12V
IN
0
400
OUTPUT CURRENT (mA)
500
600
100
200
300
3957 TA02b
3957f
24
LT3957
TYPICAL APPLICATIONS
5V to 16V Input, 12V Output SEPIC Converter
C
DC
4.7μF, 25V
X5R
L1A
D1
V
12V
1A
OUT
V
IN
5V TO 16V
C
C
OUT
IN
4.7μF
25V
22μF
16V
X5R
s2
L1B
V
SW
200k
IN
•
X5R
EN/UVLO
GND
82.5k
LT3957
SGND
SYNC
SENSE1
105k
SENSE2
FBX
INTV
CC
RT SS
VC
10k
10nF
15.8k
41.2k
300kHz
C
VCC
4.7μF
10V
0.47μF
X5R
3957 TA03a
C
C
, C : MURATA GRM21BR61E475KA12L
IN DC
: MURATA GRM32ER61C226KE20
OUT
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100
Efficiency vs Output Current
Load Step Waveforms
100
95
90
85
80
75
70
65
60
55
50
V
= 12V
V
= 12V
IN
IN
V
OUT
0.5V/DIV
(AC)
0.8A
I
OUT
0.5A/DIV
0.2A
3957 TA03c
500μs/DIV
0
800
1000
200
400
600
OUTPUT CURRENT (mA)
3957 TA03b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
V
= 12V
V
= 12V
IN
IN
V
OUT
10V/DIV
V
OUT
V
5V/DIV
SW
20V/DIV
I
+ I
L1A L1B
I
+ I
L1A L1B
5A/DIV
2A/DIV
3957 TA03e
3957 TA03d
50μs/DIV
5ms/DIV
3957f
25
LT3957
TYPICAL APPLICATIONS
5V to 16V Input, –12V Output Inverting Converter
C
DC
4.7μF, 50V
X7R
L1A
L1B
V
–12V
1A
OUT
V
IN
5V TO 16V
C
C
OUT
IN
4.7μF
25V
22μF
16V
X5R
s2
D1
V
SW
200k
IN
X5R
EN/UVLO
GND
82.5k
LT3957
SGND
SYNC
SENSE1
105k
7.5k
SENSE2
FBX
INTV
CC
RT SS
VC
10k
10nF
41.2k
300kHz
C
VCC
4.7μF
10V
0.47μF
X5R
3957 TA04a
C
C
C
: MURATA GRM21BR61E475KA12L
IN
: TAIYO YUDEN UMK316BJ475KL
DC
OUT
: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100
Efficiency vs Output Current
Load Step Waveforms
100
95
90
85
80
75
70
65
60
55
50
V
= 12V
IN
V
= 12V
IN
V
OUT
1V/DIV
(AC)
0.8A
I
OUT
0.5A/DIV
0.2A
3957 TA04c
500μs/DIV
0
800
1000
200
400
600
OUTPUT CURRENT (mA)
3957 TA04b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
V
= 12V
IN
V
= 12V
IN
V
OUT
10V/DIV
V
OUT
5V/DIV
V
SW
20V/DIV
I
+ I
L1A L1B
2A/DIV
I
+ I
L1A L1B
5A/DIV
3957 TA04d
3957 TA04e
5ms/DIV
50μs/DIV
3957f
26
LT3957
PACKAGE DESCRIPTION
UHE Package
Variation: UHE28MA
36-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1836 Rev B)
28 27
25 24 23
21 20
0.70 p0.05
17
16
15
14
30
1.88
p 0.05
1.53
31
p 0.05
5.50 p 0.05
3.00 p 0.05
3.00 p 0.05
32
4.10 p 0.05
33
0.12
p 0.05
PACKAGE OUTLINE
0.48 p 0.05
13
34
1.50 REF
35
12
36
1
2
3
4
6
8
9
10
0.25 p0.05
2.00 REF
0.50 BSC
5.10 p 0.05
6.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 p 0.05
PIN 1 NOTCH
R = 0.30 OR
0.35 s 45o
CHAMFER
R = 0.10
1.50 REF
33 34 35
5.00 p 0.10
TYP
30 31 32
36
PIN 1
TOP MARK
(NOTE 6)
28
1
2
3
4
27
1.88 p 0.10
2.00 REF
3.00 p 0.10
0.12
p 0.10
25
24
6.00 p 0.10
6
23
0.48 p 0.10
1.53 p 0.10
8
R = 0.125
TYP
21
20
3.00 p 0.10
9
10
0.40 p 0.10
17 16 15
0.25 p 0.05
0.50 BSC
14 13 12
0.200 REF
(UHE28MA) QFN 0409 REV B
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3957f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3957
TYPICAL APPLICATIONS
4V to 6V Input, 180V Output Flyback Converter
DANGER! HIGH VOLTAGE!
T1
D1
V
OUT
1:10
V
IN
180V
4V TO 6V
15mA
•
C
IN
100μF
6.3V
s2
•
C
OUT
D2
68nF
s2
220pF
22ꢀ
75k
V
SW
GND
FBX
IN
1.80M
15.8k
EN/UVLO
SENSE1
37.4k
LT3957
22ꢀ
SGND
SYNC
SENSE2
10nF
INTV
VC
CC
RT SS
4.7μF
10V
X5R
140k
100kHz
0.1μF
100pF
10k
10nF
3957 TA05
T1: TDK DCT15EFD-U44S003
C
C
: GRM31CR60J107ME39L
OUT
IN
: GRM43QR72J683KW01L
D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: DIODES MMSZ5258B
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3958
High Input Voltage, Boost, Flyback, SEPIC and
Inverting Converter with 3.5A/80V Switch
5V ≤ V < 80V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 5mm × 6mm QFN-36 Package
LT3580
LT3573
LT3574
LT3757
LT3758
Boost/Inverting DC/DC Converter with 2A Switch, Soft-
Start and Synchronization
2.5V ≤ V ≤ 32V, Current Mode Control, 200kHz to 2.5MHz, 3mm × 3mm
IN
DFN-8, MSOP-8E
Isolated Flyback Converter with 1.25A/60V Integrated
Switch
3V ≤ V ≤ 40V, No Opto-Isolator or "Third Winding" Required, Up to 7W,
IN
MSOP-16E
Isolated Flyback Converter with 0.65A/60V Integrated
Switch
3V ≤ V ≤ 40V, No Opto-Isolator or “Third Winding” Required, Up to 3W,
IN
MSOP-16
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
Boost, Flyback, SEPIC and Inverting Controller
5.5V ≤ V ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
LTC1871/LTC1871-1/ Wide Input Range, No R
™ Low Quiescent Current Adjustable Switching Frequency, 2.5V ≤ V ≤ 36V, Burst Mode Operation
IN
SENSE
LTC1871-7
Flyback, Boost and SEPIC Controller
at Light Load
and V Limited Only by External Components, ThinSOT™ Package
OUT
LTC3803/LTC3803-3/ 200kHz/300kHz Flyback DC/DC Controller
LTC3803-5
V
IN
3957f
LT 0610 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
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© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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