LT3957AEUHE#PBF [Linear]
LT3957A - Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C;
| 型号： | LT3957AEUHE#PBF |
| 厂家： | 
Linear |
| 描述： | LT3957A - Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总28页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3957A
Boost, Flyback, SEPIC and
Inverting Converter
with 5A, 40V Switch
FEATURES
DESCRIPTION
The LT®3957A is a wide input range, current mode DC/DC
converter which is capable of generating either positive or
negative output voltages. It can be configured as either a
boost, flyback, SEPIC or inverting converter. It features
an internal low side N-channel power MOSFET rated for
40V at 5A and driven from an internal regulated 5.2V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.
n
Wide Input Voltage Range: 3V to 40V
n
Single Feedback Pin for Positive or Negative
Output Voltage
n
Internal 5A/40V Power Switch
n
Current Mode Control Provides Excellent Transient
Response
n
Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
n
Synchronizable to an External Clock
n
Low Shutdown Current < 1μA
The operating frequency of LT3957A can be set with an
external resistor over a 100kHz to 1MHz range, and can
be synchronized to an external clock using the SYNC pin.
A minimum operating supply voltage of 3V, and a low
shutdown quiescent current of less than 1μA, make the
LT3957A ideally suited for battery-powered systems.
n
Internal 5.2V Low Dropout Voltage Regulator
n
Programmable Input Undervoltage Lockout with
Hysteresis
Programmable Soft-Start
n
n
Thermally Enhanced QFN (5mm × 6mm) Package
The LT3957A features soft-start and frequency foldback
functions to limit inductor current during start-up. The
LT3957A has improved load transient performance com-
pared to the LT3957.
APPLICATIONS
n
Automotive
n
Telecom
n
Industrial
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No R
and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
SENSE
are the property of their respective owners. Protected by U.S. Patents, including 7825665.
TYPICAL APPLICATION
High Efficiency Output Boost Converter
Efficiency vs Output Current
10μH
V
OUT
100
95
90
85
80
75
70
V
IN
V
= 12V
24V
IN
4.5V TO 16V
600mA
10μF
w2
10μF
200k
V
SW
IN
EN/UVLO
GND
95.3k
LT3957A
SGND
SYNC
SENSE1
226k
SENSE2
FBX
INTV
CC
RT SS
V
C
15.8k
41.2k
300kHz
6.8k
22nF
4.7μF
0.33μF
0
400
OUTPUT CURRENT (mA)
500
600
100
200
300
3957A TA01b
3957A TA01a
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LT3957A
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , EN/UVLO (Note 5), SW ......................................40V
IN
INTV ......................................................V + 0.3V, 8V
CC
IN
SYNC ..........................................................................8V
36 35 34 33 32 31 30
V , SS.........................................................................3V
C
NC
NC
1
2
3
4
28 INTV
CC
RT............................................................................1.5V
SENSE1, SGND................... Internally Connected to GND
SENSE2.................................................................. 0.3V
FBX ................................................................. –6V to 6V
Operating Junction Temperature Range
27
V
IN
SENSE2
SGND
SGND
37
EN/UVLO
25
24 SGND
SGND
23
SENSE1
6
(Note 2).................................................. –40°C to 125°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range .................. –65°C to 125°C
SW
38
SW
SW
8
9
21 SW
20 SW
NC 10
12 13 14 15 16 17
UHE PACKAGE
36-LEAD (5mm w 6mm) PLASTIC QFN
= 125°C, θ = 42°C/W, θ = 3°C/W
T
JMAX
JA
JC
EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE
ORDER INFORMATION
LEAD FREE FINISH
LT3957AEUHE#PBF
LT3957AIUHE#PBF
TAPE AND REEL
PART MARKING*
3957A
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LT3957AEUHE#TRPBF
LT3957AIUHE#TRPBF
36-Lead (5mm × 6mm) Plastic QFN
36-Lead (5mm × 6mm) Plastic QFN
3957A
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT3957A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Range
3
40
V
IN
IN
V
Shutdown I
EN/UVLO = 0V
EN/UVLO = 1.15V
0.1
1
6
μA
μA
Q
V
V
Operating I
V = 0.3V, R = 41.2k
1.7
350
5.9
2.3
400
6.8
mA
μA
A
IN
IN
Q
C
T
Operating I with Internal LDO Disabled
V = 0.3V, R = 41.2k, INTV = 5.5V
Q
C
T
CC
l
SW Pin Current Limit
SW Pin On Voltage
SENSE2 Input Bias Current
Error Amplifier
5
I
= 3A
100
–65
mV
μA
SW
Current Out of Pin
l
l
FBX Regulation Voltage (V
FBX Overvoltage Lockout
FBX Pin Input Current
)
FBX > 0V (Note 3)
FBX < 0V (Note 3)
1.569
1.6
1.631
V
V
FBX(REG)
–0.816 –0.800 –0.784
FBX > 0V (Note 4)
FBX < 0V (Note 4)
6
7
8
11
10
14
%
%
FBX = 1.6V (Note 3)
FBX = –0.8V (Note 3)
70
100
10
nA
nA
–10
(Note 3)
(Note 3)
230
5
μS
Transconductance g (ΔI /ΔFBX)
m
VC
V Output Impedance
C
MΩ
FBX > 0V, 3V < V < 40V (Notes 3, 6)
0.04
0.03
0.06
0.06
%/V
%/V
V
FBX
Line Regulation (ΔV /[ΔV • V
])
FBX(REG)
IN
FBX
IN
FBX < 0V, 3V < V < 40V (Notes 3, 6)
IN
10
V/V
μA
V Current Mode Gain (ΔV /ΔV
)
C
VC
SENSE
V Source Current
C
V = 1.5V, FBX = 0V, Current Out of Pin
C
–15
V Sink Current
C
FBX = 1.7V
FBX = –0.85V
12
11
μA
μA
V Low Side Clamp Voltage
C
FBX = 1.65V
0.8
V
Oscillator
Switching Frequency
R = 140k to SGND, FBX = 1.6V, V = 1.5V
80
270
850
100
300
1000
120
330
1200
kHz
kHz
kHz
T
C
R = 41.2k to SGND, FBX = 1.6V, V = 1.5V
T
C
R = 10.5k to SGND, FBX = 1.6V, V = 1.5V
T
C
RT Voltage
FBX = 1.6V
1.2
220
240
V
ns
ns
SW Minimum Off-Time
SW Minimum On-Time
SYNC Input Low
275
320
0.4
SYNC Input High
1.5
SS Pull-Up Current
Low Dropout Regulator
SS = 0V, Current Out of Pin
–10
5.2
μA
V
l
INTV Regulation Voltage
5
5.45
2.85
CC
INTV Undervoltage Lockout Threshold
Falling INTV
2.6
2.7
0.15
V
V
CC
CC
UVLO Hysteresis
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LT3957A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA ≈ TJ = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INTV Current Limit
V
IN
V
IN
= 40V
= 15V
32
40
95
55
mA
mA
CC
0 < I
< 20mA, V = 8V
–1
–0.5
0.02
450
17
%
%/V
mV
μA
INTV Load Regulation (ΔV
/V
)
INTVCC
IN
CC
INTVCC INTVCC
6V < V < 40V
0.05
INTV Line Regulation (ΔV
/[ΔV • V
])
INTVCC
IN
CC
INTVCC
IN
Dropout Voltage (V – V
)
V
IN
= 5V, I
= 20mA, V = 0V
INTVCC C
IN
INTVCC
INTV Current in Shutdown
EN/UVLO = 0V, INTV = 6V
CC
CC
INTV Voltage to Bypass Internal LDO
5.5
V
CC
Logic Inputs
l
EN/UVLO Threshold Voltage Falling
EN/UVLO Voltage Hysteresis
EN/UVLO Input Low Voltage
EN/UVLO Pin Bias Current Low
EN/UVLO Pin Bias Current High
V
= INTV = 6V
1.17
1.7
1.22
20
1.27
V
mV
V
IN
CC
I
Drops Below 1μA
0.4
2.5
100
VIN
EN/UVLO = 1.15V
EN/UVLO = 1.33V
2
μA
nA
20
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LT3957A is tested in a feedback loop which servos V to the
FBX
reference voltages (1.6V and –0.8V) with the V pin forced to 1.3V.
C
Note 4: FBX overvoltage lockout is measured at V
relative
FBX(OVERVOLTAGE)
to regulated V
.
FBX(REG)
Note 2: The LT3957AE is guaranteed to meet performance specifications
from the 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3957AI is guaranteed over the full –40°C to 125°C operating
junction temperature range.
Note 5: For 3V ≤ V < 6V, the EN/UVLO pin must not exceed V .
IN
IN
Note 6: EN/UVLO = 1.33V when V = 3V.
IN
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
Quiescent Current
vs Temperature, VIN
1605
1600
1590
1585
1580
–788
–790
–792
–794
–796
–798
–800
–802
–804
1.8
1.7
1.6
1.5
1.4
V
= INTV = 3V
CC
IN
V
= 40V
SHDN/UVLO = 1.33V
IN
V
= 24V
IN
V
= 40V
IN
V
IN
= 24V
V
= 8V
IN
V
V
= 8V
IN
V
= INTV = 3V
CC
V
= INTV = 3V,
CC
= 40V
IN
IN
IN
V
= 24V
IN
SHDN/UVLO = 1.33V
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75
125
–25
–25
–25
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3957A G01
3957A G02
3957A G03
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LT3957A
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.
Dynamic Quiescent Current
vs Switching Frequency
Normalized Switching
Frequency vs FBX
RT vs Switching Frequency
12
10
8
1000
120
100
80
60
40
20
0
6
100
4
2
0
10
–0.8
0
0.4
0.8
1.2
1.6
100
300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
3957A G04
0
100 200 300
400 500 600 700 800 900 1000
–0.4
200
FBX VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
3957A G05
3957A G06
Switching Frequency
vs Temperature
SW Pin Current Limit
vs Temperature
SW Pin Current Limit
vs Duty Cycle
6.6
6.4
6.2
6.0
5.8
5.6
5.4
325
320
315
310
305
6.6
6.4
6.2
6.0
5.8
5.6
5.4
R
= 41.2k
T
300
295
290
285
280
275
–50
0
25
50
75 100 125
50
TEMPERATURE (°C)
125
0
20
40
60
80
100
–25
–50
0
25
75 100
–25
TEMPERATURE (°C)
DUTY CYCLE (%)
3957A G09
3957A G08
3957A G07
EN/UVLO Hysteresis Current
vs Temperature
EN/UVLO Threshold
vs Temperature
EN/UVLO Current vs Voltage
1.28
1.26
1.24
1.22
1.20
1.18
2.4
2.2
2.0
1.8
1.6
40
30
20
10
0
EN/UVLO RISING
EN/UVLO FALLING
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
0
10
20
30
–25
40
TEMPERATURE (°C)
TEMPERATURE (°C)
EN/UVLO VOLTAGE (V)
3957A G10
3957A G12
3957A G11
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LT3957A
TYPICAL PERFORMANCE CHARACTERISTICS TA ≈ TJ = 25°C, unless otherwise noted.
INTVCC Minimum Output
INTVCC vs Temperature
Current Limit vs VIN
INTVCC Load Regulation
5.3
5.2
5.4
5.3
5.2
5.1
5.0
90
80
70
60
50
40
30
20
10
0
V
= 6V
T
= 125°C
CC
IN
J
INTV = 3V
5.1
5.0
4.9
4.8
0
30
40
50
60
1
10
IN
100
10
20
–50
0
25
50
75 100 125
–25
V
(V)
INTV LOAD (mA)
TEMPERATURE (°C)
CC
3957A G14
3957A G15
3957A G13
INTVCC Dropout Voltage
vs Current, Temperature
Internal Switch On-Resistance
vs Temperature
INTVCC Line Regulation
5.30
5.25
5.20
5.15
5.10
700
600
500
400
300
200
100
0
50
45
40
35
30
25
20
15
10
5
V
= 5V
125°C
IN
75°C
25°C
0°C
–40°C
0
–50 –25
0
25
50
75 100 125
30 35 40
5
10
INTV LOAD (mA)
15
20
0
5
10 15 20 25
(V)
0
V
TEMPERATURE (°C)
IN
CC
3957A G16
3957A G17
3957A G18
SEPIC FBX Frequency Foldback
Waveforms During Overcurrent
SEPIC Typical Start-Up
Waveforms
Internal Switch On-Resistance
vs INTVCC
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
26.6
V
IN
= 12V
V
= 12V
IN
V
OUT
10V/DIV
V
OUT
V
SW
5V/DIV
20V/DIV
I
+ I
L1A L1B
I
+ I
L1A L1B
5A/DIV
2A/DIV
3957A G20
3957A G21
5ms/DIV
50μs/DIV
SEE TYPICAL APPLICATION: 5V TO 16V INPUT,
12V OUTPUT SEPIC CONVERTER
SEE TYPICAL APPLICATION: 5V TO 16V INPUT,
12V OUTPUT SEPIC CONVERTER
4
5
6
7
8
3
INTV (V)
CC
3957A G19
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LT3957A
PIN FUNCTIONS
NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave
these pins open or connect them to the adjacent pins.
INTV (Pin 28): Regulated Supply for Internal Loads
CC
and Gate Driver. Supplied from V and regulated to
IN
5.2V (typical). INTV must be bypassed to SGND with a
CC
SENSE2 (Pin 3): The Current Sense Input for the Control
Loop. Connect this pin to SENSE1 pin directly or through
a low pass filter (connect this pin to SENSE1 pin through
a resistor, and to SGND through a capacitor).
minimum of 4.7μF capacitor placed close to pin. INTV
CC
can be connected directly to V , if V is less than 8V.
IN
IN
INTV can also be connected to a power supply whose
CC
voltage is higher than 5.5V, and lower than V , provided
IN
SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal
Ground. All small-signal components should connect to
this ground. SGND is connected to GND inside the IC to
ensure Kelvin connection for the internal switch current
sensing. Do not connect SGND and GND externally.
that supply does not exceed 8V.
V (Pin 30): Error Amplifier Compensation Pin. Used to
C
stabilizethevoltageloopwithanexternalRCnetwork.Place
compensationcomponentsbetweentheV pinandSGND.
C
FBX (Pin 31): Positive and Negative Feedback Pin. Re-
ceives the feedback voltage from the external resistor
divider between the output and SGND. Also modulates the
switching frequency during start-up and fault conditions
when FBX is close to SGND.
SENSE1 (Pin 6): The Current Sense Output of the Inter-
nal N-channel MOSFET. Connect this pin to SENSE2 pin
directly or through a lowpass filter (connect this pin to
SENSE1 pin through a resistor, then connect SENSE2 to
SGND through a capacitor).
SS (Pin 32): Soft-Start Pin. This pin modulates compen-
SW (Pins 8, 9, 20, 21, Exposed Pad Pin 38): Drain of
Internal Power N-channel MOSFET.
sation pin voltage (V ) clamp. The soft-start interval is
C
set with an external capacitor between SS pin and SGND.
The pin has a 10μA (typical) pull-up current source to an
internal 2.5V rail. The soft-start pin is reset to SGND by an
GND (Pins 12, 13, 14, 15, 16, 17): Ground. These pins
connecttothesourceterminalofinternalpowerN-channel
MOSFET through an internal sense resistor. GND is con-
nected to SGND inside the IC to ensure Kelvin connection
for the internal switch current sensing. Do not connect
GND and SGND externally.
undervoltageconditionatEN/UVLO,anINTV undervolt-
CC
ageorovervoltageconditionoraninternalthermallockout.
RT (Pin 33): Switching Frequency Adjustment Pin. Set
the frequency using a resistor to SGND. Do not leave this
pin open.
EN/UVLO (Pin 25): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
isokayto enable switching. Rising hysteresisisgenerated
by the external resistor divider and an accurate internal
2μA pull-down current. An undervoltage condition resets
soft-start. Tie to 0.4V, or less, to disable the device and
SYNC (Pin 34): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an R resistor should be chosen
T
to program a switching frequency 20% slower than the
SYNC pulse frequency. Tie the SYNC pin to SGND if this
feature is not used. SYNC is bypassed when FBX is close
to SGND.
reduce V quiescent current below 1μA.
IN
V (Pin 27): Input Supply Pin. The V pin can be locally
IN
IN
bypassed with a capacitor to GND (not SGND).
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LT3957A
BLOCK DIAGRAM
C
L1
DC
D1
V
V
OUT
IN
R4
R3
C
IN
L2
C
OUT
t
EN/UVLO
V
SW
IN
25
27
8, 9, 20,
21, 38
A10
–
+
I
S1
2μA
1.22V
2.5V
INTERNAL
REGULATOR
AND UVLO
CURRENT
LIMIT
I
S2
10μA
UVLO
M2
5.2V LDO
A8
Q3
INTV
CC
2.5V
28
G4
2.7V
C
VCC
I
S3
A11
A12
1.72V
–
+
TLO
165˚C
DRIVER
G6
SR1
S
V
C
–
+
–
G5
G2
A7
R
O
M1
–0.88V +
SENSE1
GND
6
Q2
PWM
COMPARATOR
R
SENSE
48mV
–
+
1.6V
+
A6
A5
A1
12, 13, 14,
15, 16, 17
SLOPE
RAMP
V
ISENSE
–
SENSE
SENSE2
3
+
–
+
–
A2
RAMP
GENERATOR
–0.8V
1.28V
–
A3
100kHz-1MHz
OSCILLATOR
+
G1
1.2V
+
FREQUENCY
FOLDBACK
+
A4
Q1
–
FREQ
PROG
LOW SIDE
CLAMP
V
C
RT
FBX
SS
SYNC
SGND
31
30
32
34
33
3957A F01
4, 23,
24, 37
R2
V
OUT
C
C
SS
R
R
T
C2
C
R1
C
C1
Figure 1. LT3957A Block Diagram Working as a SEPIC Converter
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LT3957A
APPLICATIONS INFORMATION
Main Control Loop
The LT3957A has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
The LT3957A uses a fixed frequency, current mode con-
trol scheme to provide excellent line and load regulation.
OperationcanbebestunderstoodbyreferringtotheBlock
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1)
andturnsontheinternalpowerMOSFETswitchM1through
driver G2. The switch current flows through the internal
current sensing resistor R
and generates a voltage
SENSE
proportional to the switch current. This current sense
voltage V (amplified by A5) is added to a stabilizing
ISENSE
slope compensation ramp and the resulting sum (SLOPE)
isfedintothepositiveterminalofthePWMcomparatorA7.
When SLOPE exceeds the level at the negative input of A7
Programming Turn-On and Turn-Off Thresholds with
the EN/UVLO Pin
(V pin), SR1 is reset, turning off the power switch. The
C
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
TheEN/UVLOpincontrolswhethertheLT3957Aisenabled
or is in shutdown state. A micropower 1.22V reference,
a comparator A10 and a controllable current source I
S1
allow the user to accurately program the supply voltage
at which the IC turns on and off. The falling value can be
accurately set by the resistor dividers R3 and R4. When
EN/UVLOisabove0.4V,andbelowthe1.22Vthreshold,the
The LT3957A has a switch current limit function. The cur-
rent sense voltage is input to the current limit comparator
A6. If the SENSE2 pin voltage is higher than the sense
small pull-down current source I (typical 2μA) is active.
S1
The purpose of this current is to allow the user to program
therisinghysteresis.TheBlockDiagramofthecomparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
current limit threshold V
(48mV, typical), A6
SENSE(MAX)
will reset SR1 and turn off M1 immediately.
The LT3957A is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost, flyback or SEPIC converter to gen-
erate positive output voltage, or as an inverting converter
to generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
(R3+R4)
VVIN,FALLING = 1.22 •
R4
VVIN,RISING = 2μA • R3+ V
IN,FALLING
age divider (R1 and R2) connected from V
to SGND.
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
OUT
Comparator A2 becomes inactive and comparator A1
performs the inverting amplification from FBX to V .
to the input voltage V for always-on operation.
C
IN
When the LT3957A is in an inverting configuration, the
INTV Regulator Bypassing and Operation
FBX pin is pulled down to –0.8V by a voltage divider
CC
connected from V
to SGND. Comparator A1 becomes
OUT
Aninternal,lowdropout(LDO)voltageregulatorproduces
inactive and comparator A2 performs the noninverting
amplification from FBX to V .
the 5.2V INTV supply which powers the gate driver, as
CC
C
showninFigure1. TheLT3957Acontainsanundervoltage
lockout comparator A8 for the INTV supply. The INTV
CC
CC
3957afa
9
LT3957A
APPLICATIONS INFORMATION
undervoltage (UV) threshold is 2.7V (typical), with 0.1V
recommended that INTV pin be shorted to the V pin if
CC IN
hysteresis, to ensure that the internal MOSFET has suf-
V islowerthan3.5Vat1MHzswitchingfrequency, orV
IN
IN
ficient gate drive voltage before turning on. When INTV
is lower than 3.2V at 100kHz switching frequency. With
the INTV pin shorted to V , however, a small current
CC
is below the UV threshold, the internal power switch will
be turned off and the soft-start operation will be triggered.
The logic circuitry within the LT3957A is also powered
CC
IN
(around 16μA) will load the INTV in shutdown mode.
CC
D
VCC
R
VCC
from the internal INTV supply.
CC
V
INTV
OUT
CC
The INTV regulator must be bypassed to SGND imme-
LT3957A
C
CC
VCC
4.7μF
diately adjacent to the IC pins with a minimum of 4.7μF
ceramic capacitor. Good bypassing is necessary to sup-
ply the high transient currents required by the MOSFET
gate driver.
SGND
3957A F02
Figure 2. Connecting INTVCC to VOUT
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the internal power
MOSFET.Theon-chippowerdissipationcanbesignificant
when the internal power MOSFET is being driven at a high
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation (a low switching frequency
may be required to ensure IC junction temperature does
not exceed 125°C), otherwise it is a trade-off between
efficiency and component size. Low frequency operation
improves efficiency by reducing gate drive current and
MOSFET and diode switching losses. However, lower
frequency operation requires a physically larger induc-
tor. Switching frequency also has implications for loop
compensation. The LT3957A uses a constant-frequency
architecture that can be programmed over a 100kHz to
1000kHz range with a single external resistor from the RT
pin to SGND, as shown in Figure 1. A table for selecting
frequency and the V voltage is high.
IN
Aneffectiveapproachtoreducethepowerconsumptionof
theinternalLDOforgatedriveandtoimprovetheefficiency
is to tie the INTV pin to an external voltage source high
CC
enough to turn off the internal LDO regulator.
In SEPIC or flyback applications, the INTV pin can be
CC
connected to the output voltage V
diode, as shown in Figure 2, if V
through a blocking
meets the following
OUT
OUT
conditions:
1. V
2. V
< V (pin voltage)
OUT
OUT
IN
< 8V
the value of R for a given operating frequency is shown
T
in Table 1.
A resistor R can be connected, as shown in Figure 2, to
VCC
limit the inrush current from V . Regardless of whether
OUT
Table 1. Timing Resistor (RT) Value
or not the INTV pin is connected to an external voltage
CC
SWITCHING FREQUENCY (kHz)
R (kΩ)
T
source, it is always necessary to have the driver circuitry
100
200
300
400
500
600
700
800
900
1000
140
63.4
41.2
30.9
24.3
19.6
16.5
14
bypassedwitha4.7μFlowESRceramiccapacitortoground
immediately adjacent to the INTV and SGND pins.
CC
If LT3957A operates at a low V and high switching fre-
IN
quency, the voltage drop across the drain and the source
of the LDO PMOS (M2 in Figure 1) could push INTV to
CC
bebelowtheUVthreshold.Topreventthisfromhappening,
the INTV pin can be shorted directly to the V pin. V
CC
IN
IN
must not exceed the INTV Absolute Maximum Rating
CC
12.1
10.5
(8V). In this condition, the internal LDO will be turned off
and the gate driver will be powered directly from V . It is
IN
3957afa
10
LT3957A
APPLICATIONS INFORMATION
The operating frequency of the LT3957A can be synchro-
nized to an external clock source. By providing a digital
clock signal into the SYNC pin, the LT3957A will operate
at the SYNC clock frequency. The LT3957A detects the
rising edge of each clock cycle. If this feature is used,
Soft-Start
TheLT3957Acontainsseveralfeaturestolimitpeakswitch
currents and output voltage (V ) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
OUT
an R resistor should be chosen to program a switching
T
frequency 20% slower than SYNC pulse frequency. It is
recommended that the SYNC pin has a minimum pulse
width of 200ns. Tie the SYNC pin to SGND if this feature
is not used.
High peak switch currents during start-up may occur in
switching regulators. Since V
the feedback loop is saturated and the regulator tries to
chargetheoutputcapacitorasquicklyaspossible,resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
is far from its final value,
OUT
Duty Cycle Consideration
Switching duty cycle is a key variable defining converter
operation.Assuch,itslimitsmustbeconsidered.Minimum
on-time is the smallest time duration that the LT3957A
is capable of turning on the power MOSFET. This time
is typically about 240ns (see Minimum On-Time in the
Electrical Characteristics table). In each switching cycle,
the LT3957A keeps the power switch off for at least
220ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The LT3957A addresses this mechanism with the SS
pin. As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the V pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its final value while limiting the
start-up peak currents. The typical start-up waveforms
are shown in the Typical Performance Characteristics
C
section. The inductor current I slewing rate is limited by
the soft-start function.
L
Theminimumon-time,minimumoff-timeandtheswitching
frequency define the minimum and maximum switching
duty cycles a converter is able to generate:
Besides start-up (with EN/UVLO), soft-start can also be
triggered by the following faults:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
1. INTV < 2.85V
CC
2. Thermal lockout (TLO > 165°C)
Any of these three faults will cause the LT3957A to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
Programming the Output Voltage
The output voltage V
is set by a resistor divider, as
OUT
shown in Figure 1. The positive and negative V
by the following equations:
are set
discharged below 0.2V, a 10μA current source I starts
OUT
S2
charging the SS pin, initiating a soft-start operation.
⎛
⎞
⎟
⎠
R2
R1
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
VOUT,POSITIVE = 1.6V • 1+
⎜
⎝
⎛
1.25V
⎞
⎟
⎠
R2
R1
TSS = CSS
•
VOUT,NEGATIVE = –0.8V • 1+
⎜
10μA
⎝
The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
FBX Frequency Foldback
When V is very low during start-up, or an output short-
OUT
circuit on a SEPIC, an inverting, or a flyback converter, the
switchingregulatormustoperateatlowdutycyclestokeep
the power switch current below the current limit, since
3957afa
11
LT3957A
APPLICATIONS INFORMATION
the inductor current decay rate is very low during switch
off time. The minimum on-time limitation may prevent
the switcher from attaining a sufficiently low duty cycle
at the programmed switching frequency. So, the switch
current may keep increasing through each switch cycle,
exceeding the programmed current limit. To prevent the
switch peak currents from exceeding the programmed
value,theLT3957Acontainsafrequencyfoldbackfunction
to reduce the switching frequency when the FBX voltage
is low (see the Normalized Switching Frequency vs FBX
graphintheTypicalPerformanceCharacteristicssection).
The Internal Power Switch Current
For control and protection, the LT3957A measures the
internal power MOSFET current by using a sense resistor
(R
) between GND and the MOSFET source. Figure 3
SENSE
shows a typical waveform of the internal switch current
(I ).
SW
Duetothecurrentlimit(minimum5A)oftheinternalpower
switch, the LT3957A should be used in the applications
that the switch peak current I
during steady state
SW(PEAK)
normal operation is lower than 5A by a sufficient margin
(10% or higher is recommended).
During frequency foldback, external clock synchroniza-
tion is disabled to prevent interference with frequency
reducing operation.
The LT3957A switching controller incorporates 100ns
timing interval to blank the ringing on the current sense
signal across R
immediately after M1 is turned on.
SENSE
Loop Compensation
This ringing is caused by the parasitic inductance and
capacitanceofthePCBtrace, thesenseresistor, thediode,
and the MOSFET. The 100ns timing interval is adequate
for most of the LT3957A applications. In the applications
that have very large and long ringing on the current sense
signal,asmallRCfiltercanbeaddedtofilterouttheexcess
ringing. Figure 4 shows the RC filter on the SENSE1 and
SENSE2 pins. It is usually sufficient to choose 22Ω for
Loop compensation determines the stability and transient
performance. The LT3957A uses current mode control to
regulate the output which simplifies loop compensation.
TheLT3957Aimprovestheno-loadtoheavyloadtransient
response, compared to the LT3957. New internal circuits
ensure that the transition from not switching to switching
at high current can be made in a few cycles. The optimum
values depend on the converter topology, the component
values and the operating conditions (including the input
voltage, load current, etc.). To compensate the feedback
loop of the LT3957A, a series resistor-capacitor network
R
and 2.2nF to 10nF for C . Keep R ’s resistance
FLT
FLT FLT
low. Remember that there is 65μA (typical) flowing out of
the SENSE2 pin. Adding R will affect the internal power
FLT
switch current limit threshold:
is usually connected from the V pin to SGND. Figure 1
C
⎛
⎝
⎞
⎟
⎠
65μA •RFLT
48mV
shows the typical V compensation network. For most
ISW _ILIM = 1−
• 5A
C
⎜
applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range
of 5k to 50k. A small capacitor is often connected in
parallel with the RC compensation network to attenuate
I
SW
)I
SW
the V voltage ripple induced from the output voltage
C
ripple through the internal error amplifier. The parallel
capacitor usually ranges in value from 10pF to 100pF. A
practical approach to design the compensation network
is to start with one of the circuits in this data sheet that
is similar to your application, and tune the compensation
network to optimize the performance. Stability should
thenbecheckedacrossalloperatingconditions, including
load current, input voltage and temperature. Application
Note 76 is a good reference on loop compensation.
I
SW(PEAK)
t
DT
S
T
S
3957A F03
Figure 3. The Switch Current During a Switching Cycle
3957afa
12
LT3957A
APPLICATIONS INFORMATION
On-Chip Power Dissipation and Thermal Lockout (TLO)
is higher than the input voltage. Remember that boost
convertersarenotshort-circuitprotected.Underashorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
Theon-chippowerdissipationofLT3957Acanbeestimated
using the following equation:
2
2
P ≈ I
IC
• D • R
+ V
• I • ƒ • 200pF/A +
PEAK SW
SW
DS(ON)
V • (1.6mA + ƒ • 10nC)
IN
where R
is the internal switch on-resistance which
DS(ON)
canbeobtainedfromtheTypicalPerformanceCharacteris-
ticssection.V isthepeakswitchoff-statevoltage.
The conversion ratio as a function of duty cycle is
SW(PEAK)
ThemaximumpowerdissipationP
VOUT
V
IN
1
1−D
canbeobtained
=
IC(MAX)
by comparing P across all the V range at the maximum
IC
IN
output current . The highest junction temperature can be
in continuous conduction mode (CCM).
estimated using the following equation:
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
T
≈ T + P
• 42°C/W
J(MAX)
A
IC(MAX)
ItisrecommendedtomeasuretheICtemperatureinsteady
state to verify that the junction temperature limit is not
exceeded. A low switching frequency may be required to
voltage (V ) and the input voltage (V ). The maximum
OUT
duty cycle (D
minimum input voltage:
IN
) occurs when the converter has the
MAX
ensure T
does not exceed 125°C.
J(MAX)
VOUT − V
IN(MIN)
DMAX
=
If LT3957A die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start operation will be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
VOUT
Discontinuous conduction mode (DCM) provides higher
conversionratiosatagivenfrequencyatthecostofreduced
efficiencies and higher switching currents.
Boost Converter: Maximum Output Current Capability
and Inductor Selection
LT3957A
SENSE1
For the boost topology, the maximum average inductor
current is:
R
FLT
SENSE2
1
C
FLT
IL(MAX)= IO(MAX)
•
SGND
1−DMAX
3957A F04
Due to the current limit of its internal power switch, the
LT3957Ashouldbeusedinaboostconverterwhosemaxi-
Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin
mum output current (I
) is less than the maximum
O(MAX)
output current capability by a sufficient margin (10% or
higher is recommended):
APPLICATION CIRCUITS
TheLT3957Acanbeconfiguredasdifferenttopologies.The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.
VIN(MIN)
IO(MAX)
<
• 5A −0.5 • ΔI
(
SW
)
VOUT
Boost Converter: Switch Duty Cycle and Frequency
The inductor ripple current ΔI has a direct effect on the
SW
choice of the inductor value and the converter’s maximum
The LT3957A can be configured as a boost converter
for the applications where the converter output voltage
output current capability. Choosing smaller values of
3957afa
13
LT3957A
APPLICATIONS INFORMATION
Boost Converter: Output Capacitor Selection
ΔI
increases output current capability, but requires
SW
large inductances and reduces the current loop gain (the
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
thesethreeparameters(ESR,ESLandbulkC)ontheoutput
voltage ripple waveform for a typical boost converter is
illustrated in Figure 5.
converter will approach voltage mode). Accepting larger
values of ΔI
provides fast transient response and
SW
allows the use of low inductances, but results in higher
input current ripple and greater core losses, and reduces
output current capability.
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalueoftheboostconvertercanbedetermined
using the following equation:
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ΔV
and the charging/discharg-
VIN(MIN)
ΔISW • ƒ
ESR
L =
•DMAX
ing ΔV
. For the purpose of simplicity, we will choose
COUT
2% for the maximum output ripple, to be divided equally
between ΔV and ΔV . This percentage ripple will
The peak inductor current is the switch current limit (5.9A
typical), and the RMS inductor current is approximately
ESR
COUT
change,dependingontherequirementsoftheapplication,
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
equal to I
. The user should choose the inductors
L(MAX)
having sufficient saturation and RMS current ratings.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current.
0.01• VOUT
ID(PEAK)
ESRCOUT
≤
For the bulk C component, which also contributes 1% to
the total ripple:
IO(MAX)
COUT
≥
0.01• VOUT • ƒ
It is recommended that the peak repetitive reverse voltage
t
t
OFF
ON
rating V
is higher than V
by a safety margin (a 10V
RRM
OUT
)V
COUT
safety margin is usually sufficient).
V
OUT
(AC)
The power dissipated by the diode is:
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
P = I
D
• V
D
)V
ESR
O(MAX)
3957A F05
where V is diode’s forward voltage drop, and the diode
D
Figure 5. The Output Ripple Waveform of a Boost Converter
junction temperature is:
T = T + P • R
θJA
J
A
D
Theoutputcapacitorinaboostregulatorexperienceshigh
RMSripplecurrents, asshowninFigure5. TheRMSripple
current rating of the output capacitor can be determined
using the following equation:
The R to be used in this equation normally includes the
θJA
R
for the device plus the thermal resistance from the
θJC
board to the ambient temperature in the enclosure. T must
J
notexceedthediodemaximumjunctiontemperaturerating.
DMAX
1−DMAX
IRMS(COUT) ≥IO(MAX)
•
3957afa
14
LT3957A
APPLICATIONS INFORMATION
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
therequiredRMScurrentrating.Additionalceramiccapaci-
tors in parallel are commonly used to reduce the effect of
parasiticinductanceintheoutputcapacitor,whichreduces
high frequency switching noise on the converter output.
SUGGESTED
RCD SNUBBER
D
N :N
P
S
V
IN
+
+
–
SN
+
V
I
C
D
+
IN
C
R
SN
SN
V
OUT
L
L
S
P
C
OUT
–
D
SN
I
SW
SW
Boost Converter: Input Capacitor Selection
LT3957A
GND
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 1μF to 100μF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
3957A F06
Figure 6. A Simplified Flyback Converter
Flyback Converter: Switch Duty Cycle and Turns Ratio
The flyback converter conversion ratio in the continuous
mode operation is:
The RMS input capacitor ripple current for a boost con-
verter is:
VOUT NS
D
=
•
V
NP 1−D
IN
I
= 0.3 • ΔI
L
RMS(CIN)
where N /N is the second to primary turns ratio. D is
S
P
duty cycle.
FLYBACK CONVERTER APPLICATIONS
Figure 7 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
The LT3957A can be configured as a flyback converter
for the applications where the converters have multiple
outputs, high output voltages or isolated outputs. Due
to the 40V rating of the internal power switch, LT3957A
should be used in low input voltage flyback converters.
Figure 6 shows a simplified flyback converter.
period T , three subintervals occur: DT , D2T , D3T .
S
S
S
S
During DT , M is on, and D is reverse-biased. During
S
D2T , M is off, and L is conducting current. Both L and
S
S
P
L currents are zero during D3T .
S
S
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
The flyback converter has a very low parts count for mul-
tipleoutputs, andwithprudentselectionofturnsratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
thehighpeakcurrents,highpeakvoltagesandconsequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.
VOUT NS
D
=
•
V
NP D2
According to Figure 6, the peak SW voltage is:
= V + V
IN
V
SW(PEAK)
IN(MAX)
SN
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency.
where V is the snubber capacitor voltage. A smaller V
SN
SN
results in a larger snubber loss. A reasonable V is 1.5
SN
to 2 times of the reflected output voltage:
VOUT •NP
VSN = k •
NS
k = 1.5 ~ 2
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15
LT3957A
APPLICATIONS INFORMATION
It is recommended to choose a duty cycle between 20%
and 80%.
V
SW
Flyback Converter: Maximum Output Current
Capability and Transformer Design
I
SW
The maximum output current capability and transformer
design for continuous conduction mode (CCM) is chosen
as presented here.
I
SW(MAX)
Themaximumdutycycle(D )occurswhentheconverter
MAX
I
D
has the minimum V :
IN
⎛
⎞
I
NP
N
S
D(MAX)
VOUT
•
⎜
⎟
⎠
⎝
DT
D2T
D3T
S
t
S
S
DMAX
=
⎛
⎞
T
NP
N
S
S
3957A F07
VOUT
•
+ V
IN(MIN)
⎜
⎝
⎟
⎠
Figure 7. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
Due to the current limit of its internal power switch, the
LT3957A should be used in a flyback converter whose
maximum output current (I
maximum output current capability by a sufficient margin
(10% or higher is recommended):
) is less than the
AccordingtotheAbsoluteMaximumRatingstable,theSW
voltage Absolute Maximum value is 40V. Therefore, the
maximum primary to secondary turns ratio (for both the
continuous and the discontinuous operation) should be.
O(MAX)
VIN(MIN)
IO(MAX)
<
•DMAX • 5A −0.5 • ΔI
SW
(
)
40V − V
NP
NS
IN(MAX)
VOUT
≤
k • VOUT
The transformer ripple current ΔI has a direct effect on
SW
Accordingtotheprecedingequations,theuserhasrelative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select-
ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
the design/choice of the transformer and the converter’s
output current capability. Choosing smaller values of
ΔI increases the output current capability, but requires
SW
large primary and secondary inductances and reduce the
current loop gain (the converter will approach voltage
mode). Accepting larger values of ΔI allows the use
SW
of low primary and secondary inductances, but results
in higher input current ripple, greater core losses, and
reduces the output current capability.
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the primary
winding,theprimarywindinginductancecanbecalculated
using the following equation:
• Lower MOSFET RMS current I
, but higher
SW(RMS)
MOSFET V peak voltage
SW
• Lower diode peak reverse voltage, but higher diode
RMS current I
D(RMS)
VIN(MIN)
L =
•DMAX
• Higher transformer turns ratio (N /N )
P
S
ΔISW • ƒ
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16
LT3957A
APPLICATIONS INFORMATION
The primary winding peak current is the switch current
limit (typical 5.9A). The primary and secondary maximum
RMS currents are:
L istheleakageinductanceoftheprimarywinding,which
LK
is usually specified in the transformer characteristics. L
LK
canbeobtainedbymeasuringtheprimaryinductancewith
the secondary windings shorted. The snubber capacitor
POUT(MAX)
value(C )canbedeterminedusingthefollowingequation:
ILP(RMS)
≈
SN
DMAX • VIN(MIN) • η
VSN
ΔVSN •RSN • ƒ
CCN
=
IOUT(MAX)
ILS(RMS)
≈
where ΔV is the voltage ripple across C . A reasonable
1−DMAX
SN
SN
ΔV is 5% to 10% of V . The reverse voltage rating of
SN
SN
where η is the converter efficiency.
D
should be higher than the sum of V and V
.
SN
SN
IN(MAX)
A Zener clamp can also be connected between SW and
GND to ensure SW voltage does not exceed 40V.
Basedontheprecedingequations,theusershoulddesign/
choose the transformer having sufficient saturation and
RMS current ratings.
Flyback Converter: Output Diode Selection
Flyback Converter: Snubber Design
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
Transformer leakage inductance (on either the primary
or secondary) causes a voltage spike to occur after the
MOSFET turn-off. This is increasingly prominent at higher
load currents, where more stored energy must be dissi-
pated. In some cases a snubber circuit will be required to
avoidovervoltagebreakdownattheMOSFET’sdrainnode.
There are different snubber circuits (such as RC snubber,
RCD snubber, Zener clamp, etc.), and Application Note 19
is a good reference on snubber design. An RC snubber
circuit can be connected between SW and GND to damp
theringingonSWpins.Thesnubberresistorvaluesshould
be close to the impedance of the parasitic resonance. The
snubber capacitor value should be larger than the circuit
parasitic capacitance, but be small enough to keep the
snubber resistor power dissipation low.
Approximate the required peak repetitive reverse voltage
rating V
using:
RRM
NS
VRRM
>
• VIN(MAX) + VOUT
NP
The power dissipated by the diode is:
P = I • V
D
O(MAX)
D
and the diode junction temperature is:
T = T + P • R
J
A
D
θJA
The R to be used in this equation normally includes the
θJC
If the RC snubber is insufficient to prevent SW pins over-
voltage, the RCD snubber can be used to limit the peak
voltage on the SW pins, which is shown in Figure 6.
θJA
R
for the device, plus the thermal resistance from the
board to the ambient temperature in the enclosure. T must
J
notexceedthediodemaximumjunctiontemperaturerating.
The snubber resistor value (R ) can be calculated by the
SN
following equation:
Flyback Converter: Output Capacitor Selection
NP
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer
totheBoostConverter:OutputCapacitorSelectionsection
VS2N − VSN • VOUT
•
NS
IS2W(PEAK) •LLK • ƒ
RSN = 2 •
for the calculation of C
and ESR
.
OUT
COUT
3957afa
17
LT3957A
APPLICATIONS INFORMATION
The RMS ripple current rating of the output capacitors
in continuous operation can be determined using the
following equation:
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (V ), the input voltage (V ) and the diode
OUT
IN
DMAX
1−DMAX
IRMS(COUT),CONTINUOUS ≈ IO(MAX)
•
forward voltage (V ).
D
Themaximumdutycycle(D )occurswhentheconverter
MAX
Flyback Converter: Input Capacitor Selection
has the minimum input voltage:
Theinputcapacitorinaflybackconverterissubjecttoalarge
RMS current due to the discontinuous primary current.
To prevent large voltage transients, use a low ESR input
capacitor sized for the maximum RMS current. The RMS
ripple current rating of the input capacitors in continuous
operationcanbedeterminedusingthefollowingequation:
VOUT + VD
IN(MIN) + VOUT + VD
DMAX
=
V
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
As shown in Figure 1, the SEPIC converter contains two
inductors:L1andL2.L1andL2canbeindependent,butcan
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
POUT(MAX)
1−DMAX
DMAX
IRMS(CIN),CONTINUOUS
≈
•
VIN(MIN) • η
SEPIC CONVERTER APPLICATIONS
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
The LT3957A can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
DMAX
1−DMAX
IL1(MAX) =IIN(MAX) =IO(MAX)
•
VOUT + VD
D
=
IL2(MAX) =IO(MAX)
V
IN
1−D
in continuous conduction mode (CCM).
Due to the current limit of its internal power switch, the
LT3957A should be used in a SEPIC converter whose
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
maximum output current (I
) is less than the output
O(MAX)
current capability by a sufficient margin (10% or higher
is recommended):
IO(MAX) < 1−D
• 5A −0.5 • ΔI
SW
(
MAX ) (
)
Compared to the flyback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
The inductor ripple currents ΔI and ΔI are identical:
L1
L2
output diode voltages are clamped by the capacitors (C ,
IN
C
DC
and C ), therefore, there is less voltage ringing
OUT
ΔI = ΔI = 0.5 • ΔI
SW
L1
L2
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the current through inductor
L1 (which is series with the input) is continuous.
The inductor ripple current ΔI has a direct effect on the
SW
choice of the inductor value and the converter’s maximum
outputcurrentcapability.ChoosingsmallervaluesofΔI
SW
requires large inductances and reduces the current loop
gain(theconverterwillapproachvoltagemode).Accepting
larger values of ΔI allows the use of low inductances,
SW
3957afa
18
LT3957A
APPLICATIONS INFORMATION
but results in higher input current ripple and greater core
losses and reduces output current capability.
where V is diode’s forward voltage drop, and the diode
D
junction temperature is:
T = T + P • R
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalue(L1andL2areindependent)oftheSEPIC
convertercanbedeterminedusingthefollowingequation:
J
A
D
θJA
The R used in this equation normally includes the R
θJA
θJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. T must not
J
exceed the diode maximum junction temperature rating.
V
IN(MIN)
L1 = L2 =
•DMAX
0.5 • ΔISW • ƒ
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPICconverteraresimilartothoseoftheboostconverter.
Please refer to the Boost Converter: Output Capacitor
Selection and Boost Converter: Input Capacitor Selection
sections.
For most SEPIC applications, the equal inductor values
will fall in the range of 1μH to 100μH.
BymakingL1=L2,andwindingthemonthesamecore,the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
SEPIC Converter: Selecting the DC Coupling Capacitor
V
IN(MIN)
L =
•DMAX
The DC voltage rating of the DC coupling capacitor (C ,
ΔISW • ƒ
DC
as shown in Figure 1) should be larger than the maximum
input voltage:
Thismaintainsthesameripplecurrentandenergystorage
in the inductors. The peak inductor currents are:
V
CDC
> V
IN(MAX)
I
I
= I
= I
+ 0.5 • ΔI
+ 0.5 • ΔI
L1(PEAK)
L2(PEAK)
L1(MAX)
L2(MAX)
L1
L2
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
DC
IN
approximately –I flows during the on-time. The RMS
O
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
rating of the coupling capacitor is determined by the fol-
lowing equation:
Basedontheprecedingequations,theusershouldchoose
the inductors having sufficient saturation and RMS cur-
rent ratings.
VOUT + VD
IRMS(CDC) >IO(MAX)
•
V
IN(MIN)
SEPIC Converter: Output Diode Selection
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
INVERTING CONVERTER APPLICATIONS
TheLT3957Acanbeconfiguredasadual-inductorinverting
topology, as shown in Figure 8. The V
to V ratio is:
It is recommended that the peak repetitive reverse voltage
OUT
IN
rating V
is higher than V
+ V
by a safety
RRM
OUT
IN(MAX)
VOUT − V
D
1−D
D = −
margin (a 10V safety margin is usually sufficient).
V
IN
The power dissipated by the diode is:
in continuous conduction mode (CCM).
P = I
D
• V
D
O(MAX)
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19
LT3957A
APPLICATIONS INFORMATION
C
+
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
DC
L1
L2
–
V
IN
+
–
C
IN
C
V
OUT
OUT
SW
LT3957A
+
D1
The RMS ripple current rating of the output capacitor
needs to be greater than:
+
3757A F08
GND
I
> 0.3 • ΔI
L2
RMS(COUT)
Figure 8. A Simplified Inverting Converter
Inverting Converter: Selecting the DC Coupling Capacitor
Inverting Converter: Switch Duty Cycle and Frequency
The DC voltage rating of the DC coupling capacitor (C ,
DC
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
asshowninFigure10)shouldbelargerthanthemaximum
input voltage minus the output voltage (negative voltage):
negativeoutputvoltage(V )andtheinputvoltage(V ).
OUT
IN
V
CDC
> V
– V
IN(MAX) OUT
Themaximumdutycycle(D )occurswhentheconverter
MAX
C
has nearly a rectangular current waveform. During
DC
has the minimum input voltage:
the switch off-time, the current through C is I , while
DC
IN
VOUT − VD
approximately –I flows during the on-time. The RMS
O
DMAX
=
rating of the coupling capacitor is determined by the fol-
lowing equation:
VOUT − VD − V
IN(MIN)
Inverting Converter: Output Diode and Input Capacitor
Selections
DMAX
1−DMAX
IRMS(CDC) >IO(MAX)
•
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those of
the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
Board Layout
Inverting Converter: Output Capacitor Selection
The high power and high speed operation of the LT3957A
demands careful attention to board layout and component
placement. Careful attention must be paid to the internal
power dissipation of the LT3957A at high input voltages,
highswitchingfrequencies,andhighinternalpowerswitch
currents to ensure that a junction temperature of 125°C is
not exceeded. This is especially important when operat-
ing at high ambient temperatures. Exposed pads on the
bottom of the package are SGND and SW terminals of the
IC, and must be soldered to a SGND ground plane and a
SW plane respectively. It is recommended that multiple
vias in the printed circuit board be used to conduct heat
away from the IC and into the copper planes with as much
area as possible.
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
convertersforsimilaroutputripples. Thisisduetothefact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
outputcapacitorsarecontinuous.Theoutputripplevoltage
is produced by the ripple current of L2 flowing through
the ESR and bulk capacitance of the output capacitor:
⎛
⎞
1
ΔVOUT(P–P) = ΔI • ESR
+
⎜
⎟
⎠
L2
COUT
8 • ƒ •COUT
⎝
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
3957afa
20
LT3957A
APPLICATIONS INFORMATION
ICisessential, especiallythepowerpathswithhigherdi/dt.
Thefollowinghighdi/dtloopsofdifferenttopologiesshould
be kept as tight as possible to reduce inductive ringing:
Check the stress on the internal power MOSFET by
measuring the SW-to-GND voltage directly across the IC
terminals.Makesuretheinductiveringingdoesnot exceed
the maximum rating of the internal power MOSFET (40V).
• In boost configuration, the high di/dt loop contains the
output capacitor, the internal power MOSFET and the
Schottky diode.
The small-signal components should be placed away
from high frequency switching nodes. For optimum load
regulation and true remote sensing, the top of the output
voltage sensing resistor divider should connect indepen-
dently to the top of the output capacitor (Kelvin connec-
tion), staying away from any high dV/dt traces. Place the
divider resistors near the LT3957A in order to keep the
high impedance FBX node short.
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
internal power MOSFET. The high di/dt secondary loop
contains the output capacitor, the secondary winding
and the output diode.
• In SEPIC configuration, the high di/dt loop contains
the internal power MOSFET, output capacitor, Schottky
diode and the coupling capacitor.
Figure 9 shows the suggested layout of the 4.5V to16V
input, 24V output boost converter in the Typical Applica-
tion section.
• In inverting configuration, the high di/dt loop contains
internalpowerMOSFET,Schottkydiodeandthecoupling
capacitor.
R1
VIA TO V
OUT
R2
C
SS
R
R
C
C
T
C
36 35 34 33 32 31 30
C
VCC
1
2
3
4
28
27
R3
37
25
24
23
R4
LT3957A
38
6
8
9
21
20
10
12 13 14 15 16 17
L1
D1
C
C
OUT
OUT
C
IN
VIA TO V
OUT
GND
V
OUT
V
IN
3958A F09
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
Figure 9. Suggested Layout of the 4.5V to 16V Input. 24V Output Boost Converter in the Typical Application Section
3957afa
21
LT3957A
APPLICATIONS INFORMATION
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.
Table 2. Recommended Component Manufacturers
VENDOR
AVX
COMPONENTS
WEB ADDRESS
avx.com
Capacitors
BH Electronics
Inductors,
Transformers
bhelectronics.com
Coilcraft
Inductors
Inductors
Diodes
coilcraft.com
bussmann.com
diodes.com
Cooper Bussmann
Diodes, Inc
General Semiconductor
Diodes
generalsemiconductor.
com
International Rectifier
Kemet
Diodes
Tantalum Capacitors
Toroid Cores
Diodes
irf.com
kemet.com
Magnetics Inc
Microsemi
Murata-Erie
Nichicon
mag-inc.com
microsemi.com
murata.co.jp
nichicon.com
onsemi.com
panasonic.com
pulseeng.com
sanyo.co.jp
Inductors, Capacitors
Capacitors
On Semiconductor
Panasonic
Pulse
Diodes
Capacitors
Inductors
Sanyo
Capacitors
Sumida
Inductors
sumida.com
t-yuden.com
Taiyo Yuden
TDK
Capacitors
Capacitors, Inductors component.tdk.com
Thermalloy
Tokin
Heat Sinks
Capacitors
aavidthermalloy.com
nec-tokinamerica.com
tokoam.com
Toko
Inductors
United Chemi-Con
Vishay
Capacitors
chemi-com.com
vishay.com
Inductors
Würth Elektronik
Vishay/Sprague
Zetex
Inductors
we-online.com
vishay.com
Capacitors
Small-Signal Discretes
zetex.com
3957afa
22
LT3957A
TYPICAL APPLICATIONS
4.5V to 16V Input, 24V Output Boost Converter
L1
10μH
D1
V
OUT
V
IN
24V
4.5V TO 16V
C
C
OUT
600mA
IN
R3
10μF
25V
X5R
10μF
50V
X5R
w2
V
SW
200k
IN
EN/UVLO
GND
R4
95.3k
LT3957A
SGND
SYNC
SENSE1
R2
226k
SENSE2
FBX
R1
15.8k
INTV
CC
RT SS
V
C
C
R
VCC
R
T
C
C
SS
4.7μF
10V
X5R
41.2k
6.8k
0.33μF
300kHz
C
C
22nF
3957A TA02a
C
C
: MURATA GRM31ER61H106KA12
IN
: TAIYO YUDEN UMK325BJ106MM
OUT
D1: VISHAY SILICONIX 10BQ040
L1: VISHAY SILICONIX IHLP-5050CE-1
Efficiency vs Output Current
100
95
90
85
80
75
70
V
= 12V
IN
0
400
OUTPUT CURRENT (mA)
500
600
100
200
300
3957A TA02b
3957afa
23
LT3957A
TYPICAL APPLICATIONS
5V to 16V Input, 12V Output SEPIC Converter
C
DC
4.7μF, 25V
X5R
L1A
D1
V
12V
1A
OUT
V
IN
5V TO 16V
C
C
OUT
IN
4.7μF
25V
22μF
16V
X5R
w2
L1B
V
SW
200k
IN
t
X5R
EN/UVLO
GND
82.5k
LT3957A
SGND
SYNC
SENSE1
105k
SENSE2
FBX
INTV
CC
RT SS
V
C
15.8k
41.2k
300kHz
C
VCC
10k
10nF
4.7μF
10V
0.47μF
X5R
3957A TA03a
C
C
, C : MURATA GRM21BR61E475KA12L
IN DC
: MURATA GRM32ER61C226KE20
OUT
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100
Efficiency vs Output Current
Load Step Waveforms
100
95
90
85
80
75
70
65
60
55
50
V
= 12V
V
= 12V
IN
IN
V
OUT
1V/DIV
(AC)
1A
I
OUT
0.5A/DIV
0A
3957 TA03c
2ms/DIV
0
800
1000
200
400
600
OUTPUT CURRENT (mA)
3957A TA03b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
V
= 12V
IN
V
= 12V
IN
V
OUT
10V/DIV
V
OUT
V
SW
5V/DIV
20V/DIV
I
+ I
L1A L1B
I
+ I
L1A L1B
5A/DIV
2A/DIV
3957A TA03e
3957A TA03d
50μs/DIV
5ms/DIV
3957afa
24
LT3957A
TYPICAL APPLICATIONS
5V to 16V Input, –12V Output Inverting Converter
C
DC
4.7μF, 50V
X7R
L1A
L1B
V
–12V
1A
OUT
V
IN
5V TO 16V
C
C
OUT
IN
4.7μF
25V
22μF
16V
X5R
w2
D1
V
SW
200k
IN
X5R
EN/UVLO
GND
82.5k
LT3957A
SGND
SYNC
SENSE1
105k
7.5k
SENSE2
FBX
INTV
CC
RT SS
V
C
41.2k
300kHz
C
VCC
10k
10nF
4.7μF
10V
0.47μF
X5R
395A7 TA04a
C
C
C
: MURATA GRM21BR61E475KA12L
IN
: TAIYO YUDEN UMK316BJ475KL
DC
OUT
: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 30BQ040
L1A, L1B: COILTRONICS DRQ127-100
Efficiency vs Output Current
Load Step Waveforms
100
95
90
85
80
75
70
65
60
55
50
V = 12V
IN
V
= 12V
IN
V
OUT
1V/DIV
(AC)
0.6A
I
OUT
0.2A/DIV
0A
3957A TA04c
2ms/DIV
0
800
1000
200
400
600
OUTPUT CURRENT (mA)
3957A TA04b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
V
= 12V
IN
V
= 12V
IN
V
OUT
10V/DIV
V
OUT
5V/DIV
V
SW
20V/DIV
I
+ I
L1A L1B
2A/DIV
I
+ I
L1A L1B
5A/DIV
3957A TA04d
3957A TA04e
5ms/DIV
50μs/DIV
3957afa
25
LT3957A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UHE Package
Variation: UHE36(28)MA
36(28)-Lead Plastic QFN (5mm w 6mm)
(Reference LTC DWG # 05-08-1836 Rev D)
28 27
25 24 23
21 20
0.70 t0.05
17
16
15
14
30
31
1.88
t 0.05
1.53
t 0.05
5.50 t 0.05
4.10 t 0.05
3.00 t 0.05
3.00 t 0.05
32
33
0.12
t 0.05
PACKAGE OUTLINE
0.48 t 0.05
13
34
1.50 REF
35
36
12
1
2
3
4
6
8
9
10
0.25 t0.05
2.00 REF
0.50 BSC
5.10 t 0.05
6.50 t 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 t 0.05
PIN 1 NOTCH
R = 0.30 OR
0.35 w 45s
CHAMFER
R = 0.10
1.50 REF
33 34 35
5.00 t 0.10
TYP
30 31 32
36
PIN 1
TOP MARK
(NOTE 6)
28
1
2
3
4
27
1.88 t 0.10
2.00 REF
3.00 t 0.10
0.12
t 0.10
25
24
6.00 t 0.10
6
8
23
0.48 t 0.10
1.53 t 0.10
R = 0.125
TYP
21
20
3.00 t 0.10
9
10
0.40 t 0.10
17 16 15
0.25 t 0.05
0.50 BSC
14 13 12
0.200 REF
(UHE36(28)MA) QFN 0112 REV D
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3957afa
26
LT3957A
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/12 V Low Side Clamp Voltage line item added
3
C
3957afa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3957A
TYPICAL APPLICATIONS
4V to 6V Input, 180V Output Flyback Converter
DANGER! HIGH VOLTAGE!
T1
D1
V
OUT
1:10
V
IN
180V
4V TO 6V
15mA
t
C
IN
100μF
6.3V
w2
t
C
OUT
D2
68nF
w2
220pF
22ꢀ
75k
V
SW
GND
FBX
IN
1.80M
15.8k
EN/UVLO
SENSE1
37.4k
LT3957A
22ꢀ
SGND
SYNC
SENSE2
10nF
INTV
CC
RT SS
V
C
4.7μF
10V
X5R
140k
100kHz
0.1μF
100pF
10k
10nF
3957A TA05
T1: TDK DCT15EFD-U44S003
C
C
: GRM31CR60J107ME39L
OUT
IN
: GRM43QR72J683KW01L
D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
D2: DIODES MMSZ5258B
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3957
Boost, Flyback, SEPIC and Inverting Converter with
5A/40V Switch
3V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 5mm × 6mm QFN-36 Package
LT3958
LT3757
LT3758
LT3759
High Input Voltage, Boost, Flyback, SEPIC and
Inverting Converter with 3.5A/80V Switch
5V ≤ V < 80V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 5mm × 6mm QFN-36 Package
Boost, Flyback, SEPIC and Inverting Controller
Boost, Flyback, SEPIC and Inverting Controller
Boost, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
5.5V ≤ V ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
1.6V ≤ V ≤ 42V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, MSOP-12E Package
3957afa
LT 1012 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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© LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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