LT1947 [Linear]
Adjustable Output TFT-LCD Triple Switching Regulator; 可调输出TFT -LCD三重开关稳压器
| 型号： | LT1947 |
| 厂家： | 
Linear |
| 描述： | Adjustable Output TFT-LCD Triple Switching Regulator |
| 文件： | 总8页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1947
Adjustable Output TFT-LCD
Triple Switching Regulator
U
DESCRIPTIO
FEATURES
The LT®1947 is a highly integrated multiple output DC/DC
converter designed for use in TFT-LCD panels. The device
contains two independent switching regulators. The main
regulator has an adjustable output voltage with an internal
1.1A switch that can generate a boosted voltage as high as
30V. The second regulator’s output is also adjustable up
to 30V and can deliver 10mA for positive bias. A simple
level-shift charge pump off the main switch node gener-
ates the negative bias voltage. An external capacitor sets
the delay time from AVDD’s final value to the rising edge at
the VON pin. The 3MHz switching frequency allows the use
of tiny low profile chip inductors and capacitors through-
out, providing a low noise, low cost total solution with all
components under 1.2mm in height. The device operates
from an input range of 2.7V to 8V and is available in a
10-lead MSOP package.
■
Complete Solution Under 1.2mm
■
Develops Three Outputs from a 3.3V or 5V Supply
■
Externally Programmable VON Delay
■
Fixed Frequency Low Noise Outputs
■
All Ceramic Capacitors
■
3MHz Switching Frequency
■
Fast Transient Response
■
Few External Components Required
■
2.7V to 8V Input Range
■
Adjustable AVDD and VON Voltages
■
Tiny 10-Lead MSOP Package
U
APPLICATIO S
■
TFT-LCD Notebook Display Panels
■
TFT-LCD Desktop Monitor Display Panels
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Digital Cameras
Handheld Computers
■
U
TYPICAL APPLICATIO
D3
D4
V
OFF
–8V
10mA
C4
0.68µF
CERAMIC
AV
8V
200mA
C6
L1
0.68µF
3.3µH
DD
V
IN
D1
Start-Up Waveforms
L2
4.7µH
R1
53.6k
V
SW1
FB1
C2
IN
VSHDN
5V/DIV
3.3µF
CERAMIC
×2
SW2
C1
2.2µF
D2
VON
R2
10k
CERAMIC
V
LT1947
20V/DIV
O2
R3
182k
V
ON
C3
220nF
FB2
V
GND
24V
ON
AVDD
10V/DIV
10mA
R4
10k
C
T
SHDN
SHUTDOWN
C5
10nF
VOFF
10V/DIV
C1: TAIYO YUDEN LMK316BJ225MD
C2: TAIYO YUDEN LMK325BJ335MD ×2
C3: AVX 0.22µF 25V X7R
D1: MBRM120LT3
D2: CMDSH-3
D3, D4: BAT54S DUAL DIODE
L1: SUMIDA CLQ4D103R3
L2: TAIYO YUDEN LB2012B4R7M
2ms/DIV
1947 TA01.tif
1947 F01
C4, C6: TAIYO YUDEN LMK107BJ684MA
Figure 1. 3.3V Powered TFT-LCD Bias Generator
1947f
1
LT1947
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
VIN Voltage ................................................................ 8V
CT Voltage.................................................................. 6V
SW1, SW2 Voltage .................................................. 36V
VON, VO2 Voltage ..................................................... 30V
FB1, FB2 .................................................................... 3V
SHDN......................................................................... 8V
Operating Temperature Range (Note 2) .. –40°C to 85°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
NUMBER
FB1
FB2
T
SW1
GND
1
2
3
4
5
10
9
V
V
ON
O2
LT1947EMS
C
8
SHDN
SW2
7
6
V
IN
MS PACKAGE
10-LEAD PLASTIC MSOP
MS PART MARKING
LTUE
TJMAX = 125°C, θJA = 120°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, VSHDN = 3.3V unless otherwise specified.
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range
Supply Current
2.7
8
V
SHDN = 2.4V
SHDN = 0V
9.5
12.5
1
mA
µA
FB1 Voltage
FB2 Voltage
1.240
1.225
1.26
1.26
1.280
1.295
V
V
●
●
1.225
1.210
1.295
1.310
V
V
Reference Line Regulation
Error Amplifier Voltage Gain
V
= 2.7V to 8V
0.01
100
5.5
0.05
%/V
V/V
µA
V
IN
EA1 and EA2
= 1.3V
C Current Source
T
V
4
6.5
1.30
1.23
2
FB1
C Threshold to Turn On Q3
T
1.25
1.17
1.1
1.28
1.2
FB1 Voltage to Begin C Charge
V
T
SW1 Current Limit
(Note 3)
(Note 3)
1.4
A
SW2 Current Limit
0.35
0.6
1
A
SW1 Saturation Voltage
SW2 Saturation Voltage
SW1 Maximum Duty Cycle
SW2 Maximum Duty Cycle
Oscillator Frequency
I
I
= 800mA
= 300mA
0.230
0.3
0.280
0.36
V
SW1
SW2
V
82
%
85
3
%
●
2.3
3.5
200
5
MHz
mV
µA
µA
µA
V
V
Switch Drop
I
= 7mA
Q3
160
0.01
0.01
10
ON
SW1 Leakage Current
SW2 Leakage Current
SHDN Pin Bias Current
SHDN Pin High
Switch Off, SW1 = 3.3V
Switch Off, SW2 = 3.3V
5
V
= 2.4V
25
SHDN
Active Mode
2.4
SHDN Pin Low
Shutdown Mode
0.4
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 2: The LT1947 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
Note 3: Switch current limit guaranteed by design and/or correlation to
static tests.
1947f
2
LT1947
U W
TYPICAL PERFOR A CE CHARACTERISTICS
3.3V TFT-LCD Converter Efficiency
Supply Current
CT Current Source
12
10
8
–2
–4
85
80
75
70
65
60
55
50
45
40
35
SHDN = 2.4V
V
IN
= 3.3V
V
IN
= 3V
V
IN
= 2.7V
–6
6
–8
4
–10
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
125 200
150 175
0
100
25 50 75
TEMPERATURE (°C)
TEMPERATURE (°C)
AV LOAD CURRENT (mA)
DD
1947 G02
1947 G03
1947 G01
SW1 Current Limit
SW2 Current Limit
Switch 1 Saturation Voltage
1.8
1.0
0.8
0.6
0.4
0.2
0
500
400
300
200
100
0
1.6
1.4
1.2
1.0
0.8
25°C
90°C
–45°C
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
0
0.2 0.4 0.6 0.8
1
1.2 1.4
TEMPERATURE (°C)
TEMPERATURE (°C)
SWITCH CURRENT (A)
1947 G04
1947 G05
1947 G06
Switch 2 Saturation Voltage
SW1 Maximum Duty Cycle
Oscillator Frequency
3.2
3.0
2.8
2.6
2.4
2.2
800
600
400
200
0
100
90
80
70
60
50
25°C
90°C
–45°C
–50
–25
0
25
50
75
100
0
0.1
0.2
0.3
0.4
0.5
0.6
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
SWITCH CURRENT (A)
TEMPERATURE (°C)
1947 G09
1947 G07
1947 G08
1947f
3
LT1947
U
U
U
PI FU CTIO S
FB1 (Pin 1): Feedback Pin for First Switcher. Connect
resistor divider tap here. Set AVDD according to:
AVDD = 1.26V(1 + R1/R2).
VIN (Pin 6): Input Supply Pin. Must be bypassed with a
ceramic capacitor close to the pin.
SW2 (Pin 7): VO2 Switch Node. Connect L2 and D2 here.
Minimize trace area at this pin to keep EMI down.
FB2 (Pin 2): Feedback Pin for Second Switcher. Connect
resistor divider 2 here and set VON using:
VON = 1.26V (1 + R3/R4) – 160mV.
SHDN (Pin 8): Pull this pin low for shutdown mode. For
normal operation, tie to a voltage between 2.4V and 8V.
CT (Pin3):TimingCapacitorPin.Connecta10nFcapacitor
from CT to ground to program a 2.3ms delay from FB1
reaching 1.26V to VON turning on.
VO2 (Pin 9): SW2 Output. This node is also internally
connected to the emitter of Q3 (see Block Diagram), the
high side switch between VO2 and VON.
SW1 (Pin 4): AVDD Switch Node. Connect L1 and D1 here
(see Figure 1). Minimize trace area at this pin to keep EMI
down.
VON (Pin 10): This is the delayed output for SW2. VON
reaches its programmed voltage after the internal timer
times out.
GND (Pin 5): Ground. Connect directly to local ground
plane.
W
BLOCK DIAGRA
V
GND
SHDN
IN
V
IN
SHUTDOWN
SW1
OSC
S
FB1
–
+
5.5µA
–
+
28mV
+ –
Q1
R
Q
C
T
–
+
Q4
V
ON
REF
REF
–
+
+
Q3
0.01Ω
∑
REF
+
V
O2
SLOPE 1
OSC
S
SW2
Q2
FB2
–
+
–
R
Q
+
OSC
1.26V REFERENCE
AND
UNDERVOLTAGE
LOCKOUT
3MHz
OSCILLATOR
SLOPE 1
SLOPE 2
REF
REF
+
0.03Ω
∑
+
1947BD
SLOPE 2
1947f
4
LT1947
U
OPERATIO
To best understand operation of the LT1947, please refer
to the LT1947 Block Diagram. The device contains two
switchingregulators, atimerandahighsideswitch. Three
outputs can be generated: an adjustable AVDD output, a
connecting VO2 to VON. Capacitor value can be calculated
using the following formula:
C = (5.5µA • tDELAY)/1.28V
A 10nF capacitor results in approximately 2.3ms of delay.
charge-pumped inversion of the AVDD output called VOFF
,
and a time delayed adjustable output called VON. Q3 keeps
VON offforanexternallysettimeinterval,setbyacapacitor
connected to the CT pin.
Layout Hints
The high speed operation of the LT1947 mandates careful
attentiontolayoutforproperperformance.Besuretokeep
input capacitor C1 as close as possible to the IC and
minimize trace area and length at the SW and FB pins.
Always use a ground plane under the switching regulator
to minimize interplane coupling. Figure 2 shows the rec-
ommended component placement.
The switching frequency of both switchers is 3MHz, set
internally. The switchers are current mode and are inter-
nally compensated. The main AVDD switcher is current
limited at 1.1A, while the second VON switcher is limited to
350mA. They share the same 1.26V reference voltage.
When the input voltage is below approximately 2.7V, an
undervoltage lockout circuit disables switching.
Soft-Start
When AVDD is less than its final voltage, Q4 is turned on,
holding the CT pin at ground. When AVDD reaches final
value, Q4 lets go of the CT pin, allowing the 5.5µA current
source to charge the external capacitor, CT. When the
voltage on the CT pin reaches 1.28V, Q3 turns on,
Forapplicationsrequiringsoft-start, acircuitconsistingof
R
SS and CSS tied to the SHDN pin can be used, as shown
in Figure 3. For a combination of 33.2k/33nF, AVDD rises
to its final value in approximately 3ms.
R3
GND
R4
R2
V
ON
R1
1
2
3
4
5
10
9
LT1947
C5
8
SHDN
7
L1
6
C1
L2
D2
V
IN
C6
V
IN
C3
D1
D3
D4
GND
C4
C2
AV
DD
V
OFF
1947 F02
Figure 2. Recommended Component Placement
1947f
5
LT1947
U
OPERATIO
D3
D4
V
OFF
–8V
10mA
C4
0.68µF
CERAMIC
AV
8V
200mA
C6
L1
0.68µF
3.3µH
DD
VSS
5V/DIV
V
IN
D1
L2
4.7µH
R1
53.6k
VON
20V/DIV
V
SW1
FB1
C2
IN
3.3µF
CERAMIC
×2
SW2
C1
2.2µF
D2
AVDD
R2
10k
CERAMIC
V
LT1947
O2
10V/DIV
R3
182k
V
ON
C3
220nF
FB2
SHDN
V
GND
24V
VOFF
10V/DIV
ON
10mA
R4
10k
C
R
T
SS
33.2k
5ms/DIV
1947 F04.tif
V
SS
C5
10nF
C
Figure 4. Start-Up Waveforms
with Soft-Start Circuit Added
SS
33nF
V
OFF
1947 F03
C1: TAIYO YUDEN LMK316BJ225MD
C2: TAIYO YUDEN LMK325BJ335MD ×2
C3: AVX 0.22µF 25V X7R
D1: MBRM120LT3
D2: CMDSH-3
D3, D4: BAT54S DUAL DIODE
L1: SUMIDA CLQ4D103R3
L2: TAIYO YUDEN LB2012B4R7M
C4, C6: TAIYO YUDEN LMK107BJ684MA
Figure 3. RSS and CSS at SHDN Pin Provide Soft-Start
U
TYPICAL APPLICATIO S
TFT-LCD Bias Generator: 10V, 24V, –6V Output
BAT54S
D3
D4
V
OFF
–6V
10mA
C4
C6
0.68µF
L1
220nF
3.3µH
AV
10V
150mA
DD
V
IN
3.3V
D1
L2
R1
69.8k
4.7µH
V
IN
SW1
FB1
C2
3.3µF
CERAMIC
×2
SW2
C1
2.2µF
D2
R2
10k
CERAMIC
V
LT1947
O2
R3
182k
V
ON
C3
220nF
FB2
SHDN
V
GND
24V
ON
10mA
R4
10k
C
T
SHUTDOWN
C5
10nF
1947 TA04
C1: TAIYO YUDEN LMK316BJ225MD 2.2µF X7R
C2: TAIYO YUDEN LMK325BJ335MD 3.3µF X5R
C3, C6: AVX 0.22µF CERAMIC X7R
D1: MBRM120
D2: CMDSH-3
L1: SUMIDA CLQ4DI03R3
L2: TAIYO YUDEN LB2012B-4R7M
C4: TAIYO YUDEN EMK212BJ684MD
1947f
6
LT1947
U
TYPICAL APPLICATIO S
TFT-LCD Bias Generator: 12V, 20V, –6V Output
34k
V
OFF
–6V
Q1
20mA
BAT54S
Q2
D3
D4
34k
C4
L1
4.7µH
C6
AV
DD
V
IN
3.3V
12V
120mA
L2
D1
R1
4.7µH
V
SW1
FB1
C2
IN
SW2
86.6k
3.3µF
CERAMIC
×2
C1
4.7µF
D2
R2
10k
V
LT1947
O2
R3
147k
V
ON
C3
0.22µF
FB2
SHDN
V
20V
ON
GND
10mA
R4
10k
C
T
SHUTDOWN
C5
10nF
C1: TAIYO YUDEN JMK316BJ475MD
4.7µF 6.3V X7R
C2: TAIYO YUDEN LMK325BJ335MD
3.3µF 10V X7R ×2
C3: AVX 0.22µF 25V X7R
C4, C6: TAIYO YUDEN LMK107BJ684MA
0.68µF 10V X7R
D1: MBRM120
D2: CMDSH-3
1947 TA02
L1: SUMIDA CLQ4DI04R7
L2: TAIYO YUDEN LB2012B4R7M
Q1: MMBT3904 NPN
Q2: MMBT3906 PNP
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
REF
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.88 ± 0.10
(.192 ± .004)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.01
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
0.13 ± 0.05
(.005 ± .002)
MSOP (MS) 0402
0.50
(.0197)
TYP
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1947f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
7
LT1947
U
TYPICAL APPLICATIO
TFT-LCD Bias Generator: 7.5V, 15V, –10V Output
L1
3.3µH
AV
DD
V
IN
3.3V
7.5V
34k
V
C7
0.68µF
C6
0.68µF
200mA
OFF
D7
L2
D1
–10V
R1
4.7µH
20mA
V
SW1
FB1
C2
IN
SW2
49.9k
C8
Q1
3.3µF
CERAMIC
×2
C1
34k
D3
D4
D5
D6
1µF
CERAMIC
×2
D2
R2
10k
V
LT1947
O2
C4
0.68µF
R3
BAT54S
BAT54S
105k
V
ON
C3
0.68µF
FB2
SHDN
V
15V
ON
GND
10mA
R4
10k
C
T
SHUTDOWN
C5
10nF
C1: TAIYO YUDEN JMK107BJ105MA
1 µF 6.3V X7R ×2
C2: TAIYO YUDEN LMK325BJ335MD
3.3µF 10V X7R ×2
D1: MBRM120
D2: CMDSH-3
D7: MMBZ5240 10V ZENER
L1: SUMIDA CLQ4D103R3
1947 TA03
C3, C7, C8: TAIYO YUDEN EMK212BJ684MD L2: TAIYO YUDEN LB2012B-4R7M
0.68µF 16V X7R
C4, C6: TAIYO YUDEN LMK107BJ684MA
0.68µF 10V X5R
Q1: MMBT3906 PNP
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Q
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LTC3402
LTC3423
1A I , 3MHz, Synchronous Step-Up DC/DC Converter V = 0.5V to 5V, V
Max = 6V, I = 38µA, I
= <1µA, MS10
= <1µA, MS10
= <1µA, MS10
SW
IN
OUT
OUT
OUT
Q
SHDN
SHDN
SHDN
2A I , 3MHz, Synchronous Step-Up DC/DC Converter V = 0.5V to 5V, V
Max = 6V, I = 38µA, I
Q
SW
IN
IN
1A I , 3MHz, Low V , Synchronous Step-Up
V
= 0.5V to 5V, V
Max = 6V, I = 38µA, I
Q
SW
OUT
DC/DC Converter
LTC3424
2A I , 3MHz, Low V , Synchronous Step-Up
DC/DC Converter
V
= 0.5V to 5V, V
Max = 6V, I = 38µA, I
= <1µA, MS10
SW
OUT
IN
OUT
Q
SHDN
1947f
LT/TP 0802 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
8
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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