LT1947_1 [Linear]
Adjustable Output TFT-LCD Triple Switching Regulator; 可调输出TFT -LCD三重开关稳压器
| 型号： | LT1947_1 |
| 厂家： | 
Linear |
| 描述： | Adjustable Output TFT-LCD Triple Switching Regulator |
| 文件： | 总12页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1947
Adjustable Output TFT-LCD
Triple Switching Regulator
U
DESCRIPTIO
FEATURES
The LT®1947 is a highly integrated multiple output DC/DC
converter designed for use in TFT-LCD panels. The device
contains two independent switching regulators. The main
regulator has an adjustable output voltage with an internal
1.1A switch that can generate a boosted voltage as high as
30V. The second regulator’s output is also adjustable up
to 30V and can deliver 10mA for positive bias. A simple
level-shift charge pump off the main switch node gener-
ates the negative bias voltage. An external capacitor sets
the delay time from AVDD’s final value to the rising edge at
the VON pin. The 3MHz switching frequency allows the use
of tiny low profile chip inductors and capacitors through-
out, providing a low noise, low cost total solution with all
components under 1.2mm in height. The device operates
from an input range of 2.7V to 8V and is available in
10-lead MSOP and thermally enhanced 10-lead MSOP
packages.
■
Complete Solution Under 1.2mm
■
Develops Three Outputs from a 3.3V or 5V Supply
■
Externally Programmable VON Delay
■
Fixed Frequency Low Noise Outputs
■
All Ceramic Capacitors
■
3MHz Switching Frequency
■
Fast Transient Response
■
Few External Components Required
■
2.7V to 8V Input Range
■
Adjustable AVDD and VON Voltages
■
Tiny 10-Lead MSOP and Thermally Enhanced
10-Lead MSOP Packages
U
APPLICATIO S
■
TFT-LCD Notebook Display Panels
■
TFT-LCD Desktop Monitor Display Panels
■
Digital Cameras
Handheld Computers
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
D3
D4
V
OFF
–8V
10mA
C4
0.68µF
CERAMIC
AV
8V
200mA
C6
L1
0.68µF
3.3µH
DD
V
IN
D1
Start-Up Waveforms
L2
4.7µH
R1
53.6k
V
SW1
FB1
C2
IN
VSHDN
5V/DIV
3.3µF
CERAMIC
×2
SW2
C1
D2
2.2µF
VON
20V/DIV
R2
10k
CERAMIC
V
O2
LT1947
R3
182k
V
ON
C3
220nF
FB2
V
24V
ON
GND
AVDD
10V/DIV
10mA
R4
10k
C
T
SHDN
SHUTDOWN
C5
10nF
VOFF
10V/DIV
C1: TAIYO YUDEN LMK316BJ225MD
C2: TAIYO YUDEN LMK325BJ335MD ×2
C3: AVX 0.22µF 25V X7R
D1: MBRM120LT3
D2: CMDSH-3
D3, D4: BAT54S DUAL DIODE
L1: SUMIDA CLQ4D103R3
L2: TAIYO YUDEN LB2012B4R7M
2ms/DIV
1947 TA01.tif
1947 F01
C4, C6: TAIYO YUDEN LMK107BJ684MA
Figure 1. 3.3V Powered TFT-LCD Bias Generator
1947fa
1
LT1947
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
FB1, FB2 .................................................................... 3V
SHDN......................................................................... 8V
Operating Temperature Range (Note 2) .. –40°C to 85°C
Lead Temperature (Soldering, 10 sec).................. 300°C
VIN Voltage ................................................................ 8V
CT Voltage.................................................................. 6V
SW1, SW2 Voltage .................................................. 36V
VON, VO2 Voltage ..................................................... 30V
U W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
11
FB1
FB2
T
SW1
GND
1
2
3
4
5
10
9
V
V
FB1
FB2
T
SW1
GND
1
2
3
4
5
10
9
V
V
ON
O2
ON
02
LT1947EMSE
LT1947EMS
C
8
SHDN
SW2
C
8
SHDN
7
6
7
6
SW2
V
IN
V
IN
MS PACKAGE
10-LEAD PLASTIC MSOP
MSE PACKAGE
10-LEAD PLASTIC MSOP
MSE PART MARKING
LTBQW
MS PART MARKING
LTUE
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 120°C/W
TJMAX = 125°C, θJA = 40°C/W
Order Options Tape and Reel: Add #TR, Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
= 3.3V unless otherwise specified.
temperature range, otherwise specifications are at T = 25°C. V = 3.3V, V
SHDN
A
IN
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range
Supply Current
2.7
8
V
SHDN = 2.4V
SHDN = 0V
9.5
12.5
1
mA
µA
FB1 Voltage
1.240
1.225
1.26
1.26
0.01
1.280
1.295
V
V
●
●
FB2 Voltage
1.225
1.210
1.295
1.310
V
V
Reference Line Regulation
V
= 2.7V to 8V
0.05
%/V
IN
1947fa
2
LT1947
ELECTRICAL CHARACTERISTICS
The
temperature range, otherwise specifications are at T = 25°C. V = 3.3V, V
SHDN
●
denotes the specifications which apply over the full operating
= 3.3V unless otherwise specified.
A
IN
SYMBOL
CONDITIONS
MIN
TYP
100
5.5
MAX
UNITS
V/V
µA
V
Error Amplifier Voltage Gain
EA1 and EA2
C Current Source
T
V
= 1.3V
FB1
4
6.5
1.30
1.23
2
C Threshold to Turn On Q3
T
1.25
1.17
1.1
1.28
1.2
FB1 Voltage to Begin C Charge
V
T
SW1 Current Limit
(Note 3)
(Note 3)
1.4
A
SW2 Current Limit
0.35
0.6
1
A
SW1 Saturation Voltage
SW2 Saturation Voltage
SW1 Maximum Duty Cycle
SW2 Maximum Duty Cycle
Oscillator Frequency
I
I
= 800mA
= 300mA
0.230
0.3
0.280
0.36
V
SW1
SW2
V
82
%
85
3
%
●
2.3
3.5
200
5
MHz
mV
µA
µA
µA
V
V
Switch Drop
I
= 7mA
Q3
160
0.01
0.01
10
ON
SW1 Leakage Current
SW2 Leakage Current
SHDN Pin Bias Current
SHDN Pin High
Switch Off, SW1 = 3.3V
Switch Off, SW2 = 3.3V
5
V
= 2.4V
25
SHDN
Active Mode
2.4
SHDN Pin Low
Shutdown Mode
0.4
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 2: The LT1947 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
Note 3: Switch current limit guaranteed by design and/or correlation to
static tests.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
3.3V TFT-LCD Converter Efficiency
Supply Current
C Current Source
T
12
10
8
–2
–4
85
80
75
70
65
60
55
50
45
40
35
SHDN = 2.4V
V
= 3.3V
IN
V
= 3V
V
= 2.7V
IN
IN
–6
6
–8
4
–10
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
25 50 75
125 200
150 175
0
100
TEMPERATURE (°C)
TEMPERATURE (°C)
AV LOAD CURRENT (mA)
DD
1947 G02
1947 G03
1947 G01
1947fa
3
LT1947
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SW1 Current Limit
SW2 Current Limit
1.8
1.0
0.8
0.6
0.4
0.2
0
1.6
1.4
1.2
1.0
0.8
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
1947 G04
1947 G05
Switch 2 Saturation Voltage
Switch 1 Saturation Voltage
500
800
600
400
200
0
25°C
400
300
200
100
0
25°C
90°C
90°C
–45°C
–45°C
0
0.2 0.4 0.6 0.8
1
1.2 1.4
0
0.1
0.2
0.3
0.4
0.5
0.6
SWITCH CURRENT (A)
SWITCH CURRENT (A)
1947 G06
1947 G07
SW1 Maximum Duty Cycle
Oscillator Frequency
100
90
80
70
60
50
3.2
3.0
2.8
2.6
2.4
2.2
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
1947 G08
1947 G09
1947fa
4
LT1947
U
U
U
PI FU CTIO S
FB1 (Pin 1): Feedback Pin for First Switcher. Connect
resistor divider tap here. Set AVDD according to:
AVDD = 1.26V(1 + R1/R2).
VIN (Pin 6): Input Supply Pin. Must be bypassed with a
ceramic capacitor close to the pin.
SW2 (Pin 7): VO2 Switch Node. Connect L2 and D2 here.
Minimize trace area at this pin to keep EMI down.
FB2 (Pin 2): Feedback Pin for Second Switcher. Connect
resistor divider 2 here and set VON using:
VON = 1.26V (1 + R3/R4) – 160mV.
SHDN (Pin 8): Pull this pin low for shutdown mode. For
normal operation, tie to a voltage between 2.4V and 8V.
CT (Pin3):TimingCapacitorPin.Connecta10nFcapacitor
from CT to ground to program a 2.3ms delay from FB1
reaching 1.26V to VON turning on.
VO2 (Pin 9): SW2 Output. This node is also internally
connected to the emitter of Q3 (see Block Diagram), the
high side switch between VO2 and VON.
SW1 (Pin 4): AVDD Switch Node. Connect L1 and D1 here
(see Figure 1). Minimize trace area at this pin to keep EMI
down.
VON (Pin 10): This is the delayed output for second
Switcher. VON reaches its programmed voltage after the
internal timer times out.
GND (Pin 5): Ground. Connect directly to local ground
plane.
Exposed Pad (Pin 11): Ground (MSE package only). The
exposed pad must be soldered to the PCB and electrically
connected to ground.
1947fa
5
LT1947
W
BLOCK DIAGRA
V
GND
SHDN
IN
V
IN
SHUTDOWN
SW1
OSC
S
FB1
–
+
5.5µA
–
+
28mV
+ –
Q1
R
Q
C
T
–
+
Q4
V
ON
REF
REF
–
+
+
Q3
0.01Ω
∑
REF
+
V
O2
SLOPE 1
OSC
S
SW2
Q2
FB2
–
+
–
R
Q
+
OSC
1.26V REFERENCE
AND
UNDERVOLTAGE
LOCKOUT
3MHz
OSCILLATOR
SLOPE 1
SLOPE 2
REF
REF
+
0.03Ω
∑
+
1947BD
SLOPE 2
1947fa
6
LT1947
U
OPERATIO
To best understand operation of the LT1947, please refer
to the LT1947 Block Diagram. The device contains two
switchingregulators, atimerandahighsideswitch. Three
outputs can be generated: an adjustable AVDD output, a
C = (5.5µA • tDELAY)/1.28V
A 10nF capacitor results in approximately 2.3ms of delay.
Layout Hints
charge-pumped inversion of the AVDD output called VOFF
,
The high speed operation of the LT1947 mandates careful
attentiontolayoutforproperperformance.Besuretokeep
input capacitor C1 as close as possible to the IC and
minimize trace area and length at the SW and FB pins.
Always use a ground plane under the switching regulator
to minimize interplane coupling. Figure 2 shows the rec-
ommended component placement.
and a time delayed adjustable output called VON. Q3 keeps
VON offforanexternallysettimeinterval,setbyacapacitor
connected to the CT pin.
The switching frequency of both switchers is 3MHz, set
internally. The switchers are current mode and are inter-
nally compensated. The main AVDD switcher is current
limited at 1.1A, while the second VON switcher is limited to
350mA. They share the same 1.26V reference voltage.
When the input voltage is below approximately 2.7V, an
undervoltage lockout circuit disables switching.
The exposed pad of the MSE package must be soldered to
the PCB and electrically connected to ground. Thermal
vias to a large ground plane will lower the thermal resis-
tance.
When AVDD is less than its final voltage, Q4 is turned on,
holding the CT pin at ground. When AVDD reaches final
value, Q4 lets go of the CT pin, allowing the 5.5µA current
source to charge the external capacitor, CT. When the
voltage on the CT pin reaches 1.28V, Q3 turns on,
connecting VO2 to VON. Capacitor value can be calculated
using the following formula:
Soft-Start
Forapplicationsrequiringsoft-start, acircuitconsistingof
RSS and CSS tied to the SHDN pin can be used, as shown
in Figure 3. For a combination of 33.2k/33nF, AVDD rises
to its final value in approximately 3ms.
R3
GND
R4
R2
V
ON
R1
1
2
3
4
5
10
9
LT1947
C5
8
SHDN
7
L1
6
C1
L2
D2
V
IN
C6
V
IN
C3
D1
D3
D4
GND
C4
C2
AV
DD
V
OFF
1947 F02
Figure 2. Recommended Component Placement
1947fa
7
LT1947
U
OPERATIO
D3
D4
V
OFF
–8V
10mA
C4
0.68µF
CERAMIC
AV
8V
200mA
C6
L1
0.68µF
3.3µH
DD
V
IN
D1
L2
R1
53.6k
4.7µH
V
SW1
FB1
C2
IN
SW2
3.3µF
CERAMIC
×2
C1
D2
2.2µF
R2
10k
CERAMIC
V
O2
LT1947
R3
182k
V
ON
C3
220nF
FB2
SHDN
V
24V
ON
GND
10mA
R4
10k
C
T
R
SS
33.2k
V
SS
C5
10nF
C
SS
33nF
V
OFF
1947 F03
C1: TAIYO YUDEN LMK316BJ225MD
C2: TAIYO YUDEN LMK325BJ335MD ×2
C3: AVX 0.22µF 25V X7R
D1: MBRM120LT3
D2: CMDSH-3
D3, D4: BAT54S DUAL DIODE
L1: SUMIDA CLQ4D103R3
L2: TAIYO YUDEN LB2012B4R7M
C4, C6: TAIYO YUDEN LMK107BJ684MA
Figure 3. R and C at SHDN Pin Provide Soft-Start
SS
SS
VSS
5V/DIV
VON
20V/DIV
AVDD
10V/DIV
VOFF
10V/DIV
5ms/DIV
1947 F04.tif
Figure 4. Start-Up Waveforms
with Soft-Start Circuit Added
1947fa
8
LT1947
U
TYPICAL APPLICATIO S
TFT-LCD Bias Generator: 12V, 20V, –6V Output
34k
V
OFF
–6V
Q1
20mA
BAT54S
Q2
D3
D4
34k
C4
L1
4.7µH
C6
AV
12V
120mA
DD
V
IN
3.3V
D1
L2
R1
4.7µH
V
SW1
FB1
C2
IN
86.6k
3.3µF
CERAMIC
×2
SW2
C1
4.7µF
D2
R2
10k
V
LT1947
O2
R3
147k
V
ON
C3
0.22µF
FB2
SHDN
V
ON
20V
10mA
R4
10k
C
GND
T
SHUTDOWN
C5
10nF
C1: TAIYO YUDEN JMK316BJ475MD
4.7µF 6.3V X7R
D1: MBRM120
D2: CMDSH-3
1947 TA02
C2: TAIYO YUDEN LMK325BJ335MD
3.3µF 10V X7R ×2
L1: SUMIDA CLQ4DI04R7
L2: TAIYO YUDEN LB2012B4R7M
Q1: MMBT3904 NPN
C3: AVX 0.22µF 25V X7R
C4, C6: TAIYO YUDEN LMK107BJ684MA
0.68µF 10V X7R
Q2: MMBT3906 PNP
TFT-LCD Bias Generator: 10V, 24V, –6V Output
BAT54S
D3
D4
V
OFF
–6V
10mA
C4
C6
0.68µF
L1
220nF
3.3µH
AV
10V
150mA
DD
V
IN
3.3V
D1
L2
R1
69.8k
4.7µH
V
SW1
FB1
C2
IN
SW2
3.3µF
CERAMIC
×2
C1
D2
2.2µF
R2
10k
CERAMIC
V
O2
LT1947
R3
182k
V
ON
C3
220nF
FB2
SHDN
V
24V
ON
GND
10mA
R4
10k
C
T
SHUTDOWN
C5
10nF
1947 TA04
C1: TAIYO YUDEN LMK316BJ225MD 2.2µF X7R
C2: TAIYO YUDEN LMK325BJ335MD 3.3µF X5R
C3, C6: AVX 0.22µF CERAMIC X7R
D1: MBRM120
D2: CMDSH-3
L1: SUMIDA CLQ4DI03R3
L2: TAIYO YUDEN LB2012B-4R7M
C4: TAIYO YUDEN EMK212BJ684MD
1947fa
9
LT1947
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1947fa
10
LT1947
U
PACKAGE DESCRIPTIO
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1663)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 ± 0.102
(.081 ± .004)
1.83 ± 0.102
(.072 ± .004)
2.794 ± 0.102
(.110 ± .004)
0.889 ± 0.127
(.035 ± .005)
1
5.23
(.206)
MIN
2.083 ± 0.102 3.20 – 3.45
(.082 ± .004) (.126 – .136)
10
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
2
3
4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MSE) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1947fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LT1947
U
TYPICAL APPLICATIO
TFT-LCD Bias Generator: 7.5V, 15V, –10V Output
L1
3.3µH
AV
DD
V
IN
3.3V
7.5V
34k
V
C7
0.68µF
C6
0.68µF
200mA
OFF
D7
L2
D1
–10V
R1
4.7µH
20mA
V
SW1
FB1
C2
IN
SW2
49.9k
C8
Q1
3.3µF
CERAMIC
×2
C1
34k
D3
D4
D5
D6
1µF
CERAMIC
×2
D2
R2
10k
V
LT1947
O2
C4
0.68µF
R3
BAT54S
BAT54S
105k
V
ON
C3
0.68µF
FB2
SHDN
V
15V
ON
GND
10mA
R4
10k
C
T
SHUTDOWN
C5
10nF
C1: TAIYO YUDEN JMK107BJ105MA
1 µF 6.3V X7R ×2
D1: MBRM120
D2: CMDSH-3
D7: MMBZ5240 10V ZENER
L1: SUMIDA CLQ4D103R3
1947 TA03
C2: TAIYO YUDEN LMK325BJ335MD
3.3µF 10V X7R×2
C3, C7, C8: TAIYO YUDEN EMK212BJ684MD L2: TAIYO YUDEN LB2012B-4R7M
0.68µF 16V X7R
C4, C6: TAIYO YUDEN LMK107BJ684MA
0.68µF 10V X5R
Q1: MMBT3906 PNP
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
= 2.75V to 18V, V
LT1310
1.5A I , 4.5MHz, High Efficiency
V
V
V
V
V
V
V
V
V
V
Max = 35V, I = 12mA, I
= <1µA, MS10E
SW
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
Q
SHDN
Step-Up DC/DC Converter
LT1613
550mA I , 1.4MHz, High Efficiency
= 0.9V to 10V, V
= 1.2V to 15V, V
Max = 34V, I = 3mA, I
SHDN
= <1µA, ThinSOT
= <1µA, ThinSOT
= <1µA, TSSOP-16E
= <1µA, MS10
SW
OUT
OUT
Q
Step-Up DC/DC Converter
LT1615/LT1615-1 300mA/80mA I , Constant Off-Time,
Max = 34V, I = 20µA, I
Q
SW
SHDN
SHDN
High Efficiency Step-Up DC/DC Converter
LT1940
Dual Output 1.4A I , Constant 1.1MHz,
= 3V to 25V, V
Min = 1.2V, I = 2.5mA, I
OUT Q
OUT
High Efficiency Step-Down DC/DC Converter
LT1944
Dual Output 350mA I , Constant Off-Time,
= 1.2V to 15V, V
= 1.2V to 15V, V
= 1.2V to 15V, V
Max = 34V, I = 20µA, I
Q
SW
OUT
OUT
OUT
SHDN
SHDN
High Efficiency Step-Up DC/DC Converter
LT1944-1
LT1945
Dual Output 150mA I , Constant Off-Time,
Max = 34V, I = 20µA, I
= <1µA, MS10
SW
Q
High Efficiency Step-Up DC/DC Converter
Dual Output, Pos/Neg 350mA I , Constant Off-Time,
High Efficiency Step-Up DC/DC Converter
Max = ±34V, I = 20µA, I
= <1µA, MS10
SW
Q
SHDN
LT1946/LT1946A
1.5A I , 1.2MHz/2.7MHz, High Efficiency
= 2.45V to 16V, V
Max = 34V, I = 3.2mA, I
= <1µA, MS8
SHDN
SW
OUT
Q
Step-Up DC/DC Converter
LT1949/LT1949-1 550mA I , 600kHz/1.1MHz, High Efficiency
= 1.5V to 12V, V
Max = 28V, I = 4.5mA, I
= <25µA, MS8, S8
SHDN
SW
OUT
OUT
Q
Step-Up DC/DC Converter
LTC3400/LTC3400B 600mA I , 1.2MHz, Synchronous
= 0.85V to 5V, V
Max = 5V, I = 19µA/300µA, I
= <1µA, ThinSOT
SW
Q
SHDN
Step-Up DC/DC Converter
LTC3401
LTC3402
LTC3423
1A I , 3MHz, Synchronous Step-Up DC/DC Converter V = 0.5V to 5V, V
Max = 6V, I = 38µA, I
= <1µA, MS10
= <1µA, MS10
= <1µA, MS10
SW
IN
OUT
OUT
OUT
Q
SHDN
SHDN
SHDN
2A I , 3MHz, Synchronous Step-Up DC/DC Converter V = 0.5V to 5V, V
Max = 6V, I = 38µA, I
Q
SW
IN
IN
1A I , 3MHz, Low V , Synchronous Step-Up
V
= 0.5V to 5V, V
Max = 6V, I = 38µA, I
Q
SW
OUT
DC/DC Converter
LTC3424
2A I , 3MHz, Low V , Synchronous Step-Up
DC/DC Converter
V
= 0.5V to 5V, V
Max = 6V, I = 38µA, I
= <1µA, MS10
SW
OUT
IN
OUT
Q
SHDN
1947fa
LT/LT 0605 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
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