LT1619ES8#TR [Linear]
LT1619 - Low Voltage Current Mode PWM Controller; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LT1619ES8#TR |
| 厂家： | 
Linear |
| 描述： | LT1619 - Low Voltage Current Mode PWM Controller; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 控制器 |
| 文件： | 总20页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1619
Low Voltage Current Mode
PWM Controller
U
FEATURES
DESCRIPTIO
■
Wide VIN Range: 1.9V to 18V
The LT®1619 is a fixed frequency PWM controller for
implementing current mode DC/DC converters with mini-
mum external parts. The LT1619 operates with input
voltages ranging from 1.9V to 18V and is suitable for a
variety of battery-powered and distributed DC/DC con-
verters. The internal rail-to-rail N-channel MOSFET driver
operates either from the input in the nonbootstrapped
mode or from the output in bootstrapped operation. The
driver is designed to drive a low side power transistor in
boost, SEPIC, flyback and other topologies.
■
300kHz Fixed Frequency Current Mode Control
■
1A Rail-to-Rail N-Channel MOSFET Driver
■
Low 53mV Current Limit Threshold Voltage
Improves Efficiency
■
Implements Boost, SEPIC and Flyback Converters
Requiring Low Side Power Transistors
■
Internal Current Sense Amplifier
with Leading Edge Blanking
■
Up to 500kHz External Synchronization
Burst Mode® Operation for High Efficiency
■
Converter efficiency is improved at heavy loads with a
53mV current sense voltage and at light load with Burst
Mode operation. The operating frequency is internally set
at 300kHz. The oscillator can also be synchronized exter-
nallyupto500kHz.Noloadquiescentcurrentis140µAand
shutdown current is 15µA.
at Light Load
■
140µA Quiescent Current
■
15µA Shutdown Current
■
8-Lead MSOP and SO Packages
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APPLICATIO S
The LT1619 is available in 8-lead MSOP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
■
3.3V to 5V DC/DC Converters
■
Distributed Power Supplies
■
Isolated Power Supplies
U
TYPICAL APPLICATIO
Efficiency
V
IN
3.3V
95
90
1
2
3
4
8
7
6
5
L1
37.4k
S/S
FB
V
IN
+
5.6µH
C1
0.1µF
5A
22µF
12.4k
85
80
75
70
DRV
LT1619
GATE
V
OUT
5V
0.1µF
2.2A
M1
Si9804
D1
V
C
+
75k
15nF
C
OUT
440µF
GND SENSE
220pF
R
SENSE
0.01Ω
1619 F01
C1: PANASONIC EEFCDOK220R
1
10
100
1000
C
: KEMET T495X227K010AS (×2)
OUT
LOAD CURRENT (mA)
D1: MBRD835L
1619 F01a
L1: COILCRAFT DO5022P-562
Figure 1. High Efficiency 3.3V to 5V DC/DC Converter
1619fa
1
LT1619
ABSOLUTE AXI U RATI GS
W W
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(Note 1)
Current Sense Voltage (SENSE) ................. –0.5V to VIN
Operating Temperature Range (Note 2) .. –40°C to 85°C
Junction Temperature (Note 3)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Input Voltage (VIN) ................................... –0.3V to 20V
Gate Drive Supply Voltage (DRV) ............. –0.3V to 20V
Shutdown/Synch Voltage (S/S) ................ –0.3V to 20V
Feedback Voltage (FB) .............................................. VIN
Compensation Voltage (VC) ...................................... 3V
Gate Drive Output Current (GATE) ........................ ±1.5A
U W
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
S/S
FB
1
2
3
4
8
7
6
5
V
IN
LT1619EMS8
LT1619ES8
S/S
FB
1
2
3
4
8 V
IN
DRV
7 DRV
6 GATE
5 SENSE
V
C
V
C
GATE
SENSE
GND
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTHC
S8 PART MARKING
1619
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 200°C/ W
TJMAX = 125°C, θJA = 120°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
1.24
0.004
10
MAX
1.26
0.05
25
UNITS
V
Reference Voltage
Measured at the FB Pin
●
1.22
Reference Line Regulation
FB Input Bias Current
1.9V ≤ V ≤ 18V
%/V
IN
V
= V
REF
nA
FB
–1
Error Amplifier Transconductance
Error Amplifier Output Source Current
Error Amplifier Output Sink Current
Error Amplifier Clamp Voltage
Undervoltage Lockout Threshold
Input Voltage Range
80
4
170
8.7
260
14
µΩ
V
V
V
= 1V, V
= 1V
µA
µA
V
FB
FB
FB
COMP
= 1.5V, V
= 1V
= 1V
4
8.7
14
COMP
1.6
1.65
1.9
220
370
88
2.2
1.85
18
V
●
●
V
Switching Frequency
1.9V ≤ V ≤ 18V
300
360
500
kHz
kHz
%
IN
Synchronization Frequency Range
Maximum Duty Cycle
●
●
92
53
10
Current Limit Threshold
40
66
mV
mV
Burst Mode Operation Current Limit
1619fa
2
LT1619
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = VDRV = 2.5V, VS/S = VIN, COMP open, VSENSE = 0V unless otherwise noted.
PARAMETER
CONDITIONS
= 0V
MIN
TYP
–120
150
30
MAX
UNITS
µA
Current Sense Input Current
Current Limit Delay
V
●
–90
–150
SENSE
ns
Driver Output Rise Time
Driver Output Fall Time
Driver Output High Level
C = 3300pF
L
ns
C = 3300pF
L
35
ns
I
I
= –20mA
= –200mA
V
V
– 0.6
– 1.6
V – 0.35
DRV
V
V
OUT
OUT
DRV
DRV
V
– 1.2
DRV
Driver Output Low Level
I
I
= 20mA
= 200mA
100
200
0.7
mV
V
OUT
OUT
0.5
100
100
Shutdown Driver Output Level
Idle Mode Driver Output Level
S/S Pin Current
V
V
= 0V, I
= 20mA
200
200
mV
mV
S/S
S/S
OUT
= V , V = 1.5V, I
= 20mA
IN FB
OUT
V
V
= V
4
–2
µA
µA
S/S
S/S
IN
= 0V
Operating Supply Current
Quiescent Supply Current
Shutdown Supply Current
V
V
= 1V
9
mA
FB
= V , V = 1.5V
●
140
220
19
µA
S/S
IN FB
V
V
= 0V
15
40
µA
µA
S/S
S/S
= 0V, V = 18V, T = 85°C
IN
A
Shutdown Threshold
Shutdown Delay
0.45
12
1.2
33
V
17
µs
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 3: T is calculated from the ambient temperature T , the power
J A
dissipation P and the thermal resistance θ of the package according to
D
JA
the formula:
T = T + P • θ
JA
Note 2: The LT1619E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
J
A
D
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TYPICAL PERFOR A CE CHARACTERISTICS
S/S Pin Current vs Temperature
Bandgap Voltage vs Temperature
IS/S vs VS/S
1.245
1.243
1.241
1.239
1.237
5
4
5
4
V
IN
= 2.5V
T
= –40°C
A
V
S/S
= 2.5V
T
= 25°C
= 85°C
A
3
3
T
A
2
2
1
1.235
1.233
1.231
1.229
1.227
1.225
1
0
0
–1
–2
–3
V
S/S
= 0V
–1
–2
–3
–20
0
20 40 60
120
80 100
–40
40 60
20
TEMPERATURE (°C)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
–40 –20
0
80 100 120
TEMPERATURE (°C)
V
S/S
1619 G01
1619 G02
1619 G03
1619fa
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LT1619
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Frequency Deviation from
Nominal vs Temperature
Shutdown Supply Current
vs Input Voltage
Idle Mode Supply Current
vs Temperature
10
8
45
40
35
30
25
20
15
10
5
200
190
180
170
160
150
140
V
= 2.5V
V
= 2.5V
IN
IN
NOMINAL FREQUENCY = 300kHz
6
4
2
T
= –40°C
A
T
= 25°C
A
0
T
= 85°C
A
–2
–4
–6
–8
–10
60 80
20 40
TEMPERATURE (°C)
–40 –20
0
20
40
60
80 100
–40 –20
0
100 120
0
2
4
6
8
10 12 14 16 18 20
TEMPERATURE (°C)
INPUT VOLTAGE (V)
1619 G05
1619 G06
1619 G04
Maximum Duty Ratio
vs Temperature
Deviation from Nominal
Current Limit Threshold
vs Temperature
Frequency vs Input Voltage
95
94
93
92
91
90
8
6
58
57
56
55
54
53
52
51
50
V = 2.5V
IN
V
IN
= 2.5V
T
= 25°C
A
NOMINAL FREQUENCY = 300kHZ
4
2
0
–2
–4
–40 –20
0
20
40
60
80 100
2
4
6
8
10 12 14 16 18 20
INPUT VOLTAGE (V)
–40
–20
0
20
40
60
80 100
0
TEMPERATURE (°C)
TEMPERATURE (°C)
1619 G07
1619 G08
1619 G09
SENSE Pin Input Bias Current
vs Sense Voltage
Burst Mode Operation Current
Limit Threshold vs Temperature
SENSE Pin Input Bias Current
vs Temperature
–115
–117
–119
–121
–123
–125
–127
–129
–131
–133
–135
14
12
–90
–95
V
= 0V
T
= 25°C
SENSE
V
= 2.5V
A
IN
DUTY CYCLE = 0
–100
–105
–110
–115
–120
–125
–130
10
8
6
4
2
0
–40
0
20
40
60
80 100
40
TEMPERATURE (°C)
80 100
–20
20
30
–40 –20
0
20
60
–10
0
10
40
50
60
TEMPERATURE (°C)
V
(mV)
SENSE
1619 G11
1619 G10
1619 G12
1619fa
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LT1619
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PI FU CTIO S
S/S (Pin 1): Shutdown and Synchronization. Shutdown is
active low with a typical threshold voltage of 0.9V. For
normal operation, the S/S pin is tied to VIN. To externally
synchronize the controller, drive the S/S pin with pulses.
SENSE (Pin 5): The Input of the Current Sense Amplifier.
TheSENSEpinisconnectedtothesourceoftheN-channel
MOSFETandtoasenseresistortotheground. Thecurrent
limitthresholdisinternallysetat53mV,givingamaximum
switch current of 53mV/RSENSE
.
FB (Pin 2): The inverting Input of the Error Amplifier.
Connect the resistor divider tap here. Set VOUT according
to VOUT = 1.24(1 + R1/R2). See Figure 1.
GATE (Pin 6): The Output of the MOSFET Driver.
DRV(Pin7):ThePull-UpSupplyoftheMOSFETDriver.Tie
this pin to VIN (Pin 8) for nonbootstrapped operation or to
the converter output for bootstrapped operation.
VC (Pin 3): Compensation Pin for the Error Amplifier. VC is
the output of the transconductance amplifier. Overall loop
is compensated with an RC network from this pin to the
ground.
VIN (Pin 8): Supply or Battery Input. Must be closely
bypassed to the ground plane.
GND (Pin 4): Ground. Connect to local ground plane.
W
BLOCK DIAGRA
V
V
IN
C
3
8
–
+
UVLO
A2
1.8V
ERROR
AMPLIFIER
1.24V
+
–
g
m
–
+
IDLE
FB
A1
2
V
B
V
IN
DRV
7
–
+
C1
S
R
GATE
SENSE
GND
DRIVER
6
5
4
Q
LOAD
+
+
Σ
R
SENSE
–
CLK
RAMP COMP
300kHz
OSCILLATOR
CURRENT
280ns
S/S
SYNC
1
SENSE
AMP
LEADING
EDGE
BLANKING
+
+
–
SHUTDOWN
DELAY
I
REF/BIAS
CURRENT
LIM
LIMIT
1619 F02
COMPARATOR
Figure 2. LT1619 Block Diagram
1619fa
5
LT1619
U
OPERATIO
The LT1619 is a fixed frequency current mode switching
regulatorPWMcontrollerthatcanbeusedinboost, SEPIC
or flyback modes. The device operates from an input
supply range of 1.9V to 18V, and has a separate supply pin
(DRV)forthegatedriver.TheDRVpincanbebootstrapped
to VOUT for additional gate enhancement in low voltage
applications like 3.3V to 5V boost converters, or con-
nected to the input supply for higher voltage inputs.
discharges the output capacitor, causing the output volt-
age to decrease. As VOUT decreases, VC increases. As VC
increases above VB, switching action begins, delivering
power to the output. The switch current sense threshold is
about 10mV in this VC region. If the output load remains
light, the output voltage will rise and VC will fall, causing
the converter to idle again. This is known as Burst Mode
operation. The burst frequency depends on input voltage,
output voltage, inductance and output capacitance. Out-
put voltage ripple during Burst Mode operation is usually
higher than when the converter is switching continuously.
Burst Mode operation increases light load efficiency be-
causeitdeliversmoreenergyperclockcyclethanpossible
with discontinuous mode operation and extremely low
peak switch current, allowing fewer switching cycles to
maintain a given output. IC supply current therefore be-
comes a small fraction of the total input current.
To best understand operation of the LT1619, please refer
to Figure 2, the Block Diagram. The gate drive circuit turns
on the external MOSFET at the trailing edge of oscillator
output signal CLK. MOSFET current is sensed with an
external resistor (RSENSE of Figure 1). A leading edge
blanking circuit disables the current sense amplifier for
280ns immediately following switch turn-on, preventing
gate charging current from prematurely tripping the PWM
comparator. A slope compensating ramp, derived from
the oscillator, is added to the current sense output. The
driver turns off the MOSFET when this sum exceeds the
error amplifier output VC. The switch current is limited
with a separate comparator. The compensating ramp is a
progressive nonlinear function of the operating duty ratio
whereas the current limit does not vary with the duty ratio.
Setting Output Voltage
The output voltage of the LT1619 is set with resistive
divider R1 and R2 connected from the output to ground as
detailed in Figure 3. The divider tap is tied to the device FB
pin. Current through R2 should be significantly higher
than the FB pin bias current of 25nA. With R2 = 10k, the
input bias current of the error amplifier is 0.02% of the
current in R2.
Error amplifier output VC determines the peak switch cur-
rent required to regulate the output voltage. VC can be
considered a measure of output current. At heavy loads,
VC is in its upper range. Average and peak inductor cur-
rents are high. In this range, the inductor tends to run in
continuous conduction mode (CCM), where current is al-
ways flowing in the inductor. As load current decreases,
average and peak inductor current decreases. When the
averageinductorcurrentfallsbelow1/2ofthepeak-to-peak
inductor current ripple, the converter enters discontinu-
ous conduction mode (DCM), where current in the induc-
tor reaches zero sometime during the discharge phase.
V
O
R1
R2
R1
R2
V
= 1.24V 1 +
LT1619
FB
O
(
)
V
O
– 1
R1 = R2
(
)
1.24
1619 F03
Figure 3. Feedback Resistive Divider
Synchronization and Shutdown
Further reduction in output current moves VC towards its
lower operating range, decreasing inductor current. Hys-
teretic comparator A1 determines if VC is too low for the
LT1619 to operate efficiently. As VC falls below the trip
voltage VB, A1’s output goes high, turning off all blocks
except the error amplifier, A1 and A2. The LT1619 enters
the idle state and switching stops. The device draws just
140µA from the input in the idle state. Output load current
The S/S pin (Pin 1) can be used to synchronize the
oscillator to an external source. The S/S pin is tied to the
input (VIN > 1.9V) for normal operation. The oscillator in
the LT1619 can be externally synchronized by driving the
S/S pin with a pulse train with an amplitude of at least 1V.
The maximum allowable rise time is a function of the
pulse amplitude, as shown in Table 1. Rise times equal to
1619fa
6
LT1619
U
OPERATIO
or less than the number specified in Table 1 are accept-
able.Themaximumdutycycleisessentiallyunaffectedby
synchronization.
more than 33µs. This shutdown delay is reset whenever
the S/S pin voltage rises above the shutdown threshold.
Applying a logic low signal at the S/S pin causes the gate
drive output to go low. Although all circuits in the LT1619
are disabled, the pull-down circuit in the MOSFET buffer is
still biased on. It is capable of shunting any leakage or
transient current at the GATE pin to ground, eliminating
the need for an external bleed resistor. The LT1619 con-
sumes 15µA in shutdown.
The device will go into shutdown mode if the S/S pin
voltage stays below the shutdown threshold of 0.45V for
Table 1. Maximum Allowable Rise Time of Synchronization
Pulse. Rise Time Can Be Slower if Clock Amplitude is Higher
SYNCHRONIZATION
AMPLITUDE (V)
MAXIMUM ALLOWABLE
RISE TIME (ns)
The LT1619 is guaranteed to start with a minimum VIN of
1.85V. Comparator A2 senses the input voltage and gen-
erates an undervoltage lockout (UVLO) signal if VIN falls
below this minimum. While in undervoltage lockout, VC is
pulled low and the LT1619 stops switching. The supply
current drawn by the device falls to 140µA.
1.2
1.5
2.0
2.5
3.0
120
220
350
470
530
W U U
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APPLICATIO S I FOR ATIO
Inductor
pin (DRV) for design flexibility. In a boost converter
design, the DRV pin can be tied to the converter output if
the minimum input voltage is insufficient to fully enhance
thepowerMOSFET.Duringstart-up,theMOSFETisdriven
with a gate voltage starting from VIN – VD (VD is the
forward voltage of the rectifying diode). As the output
voltage rises, the gate drive also increases until steady
state is reached. If the steady-state converter output
voltage exceeds the maximum allowable gate source
voltage and the input voltage is sufficient to enhance the
MOSFET, the DRV pin is tied to the input supply. For a
SEPIC converter, the DRV pin can be tied to the input or
diode OR’ed from the input and the output (Figure 4).
The value of the inductor is usually selected so that the
peak-to-peak ripple current is less than 30% of the maxi-
mum inductor current. The inductor should be able to
handle the maximum inductor current at full load without
saturation. Powder iron cores are not suitable for high
frequency switch mode power supply applications be-
cause of their high core losses. Ferrite cores have very low
core losses and are the material of choice for high fre-
quency DC/DC converters.
Power MOSFET Driver
The LT1619 is capable of driving a low side N-channel
power MOSFET with up to 60nC of total gate charge (Qg).
An external driver is recommended for MOSFETs with
greater than 80nC of total gate charge. The peak gate drive
current varies from 0.5A with VDRV = 2.5V to 1.2A with
VDRV = 10V. The MOSFET driver is capable of charging the
gate of the power MOSFET to within 350mV of the upper
gate drive supply rail (DRV). It can also pull the gate of the
MOSFET to within 100mV of ground during turnoff. The
uppersupplyrailofthegatedriveisbroughtoutasadevice
V
OUT
•
V
IN
DRV
+
LT1619
GND
•
R
S
1619 F03
Figure 4. SEPIC Converter with Diode OR’ed Gate Drive Supply
1619fa
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LT1619
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APPLICATIO S I FOR ATIO
Power MOSFET
the output capacitor and the peak-to-peak capacitor
current. Depending on topology, current feeding the out-
putcapacitorcanbecontinuousordiscontinuous.Theinput
currentcanalsobecontinuousordiscontinuousevenifthe
inductorcurrentitselfiscontinuous.Inboosttopology,the
inductor is in series with the input source so the input
currentiscontinuousandtheoutputcurrentisdiscontinu-
ous. In buck-boost or flyback converters, the inductor is
not in series with the input source nor the output, so nei-
ther the input current nor output current is continuous.
MOSFET power dissipation can be separated into fre-
quency independent and frequency dependent compo-
nents. The RDS(ON) loss in the switch is the product of the
mean square switch current and switch RDS(ON) and it
does not vary with the operating frequency.
The frequency-dependent switching losses consist of 1)
switchtransitionlossduetofiniteriseandfalltimesofthe
drainsourcevoltageandthedraincurrent2)gateswitch-
ing loss, i.e., a packet of charge Qg (the total gate charge)
which is moved from the gate drive power supply to
ground in every switch cycle, and 3) the drain switching
loss, charge stored on the parasitic drain capacitance,
COSS isdumpedtogroundastheswitchisturnedon. The
transistor loss can be expressed as:
Whenever a terminal current is discontinuous, the capaci-
tor at that terminal should be chosen to handle the ripple
current. Capacitor reliability will be adversely affected if
the ripple current exceeds the maximum allowable rat-
ings. This maximum rating is specified as the RMS ripple
current. Several capacitors may be mounted in parallel to
meet the size and ripple current requirements.
2
PLOSS = IDRMS RDS(ON) + transition loss + QgVGfS
+ 1/2COSS DS(OFF)
V
2fS
Besides the ripple voltage requirements, the output ca-
pacitor also needs to be sized for acceptable output
voltage variation under load transients.
where the transition loss can be estimated with:
CRSS DS(OFF) S
V
2f
TransitionLoss = ID
Current Sensing Resistor RSENSE
IG(AVG)
The LT1619 drives a low side N-channel MOSFET switch.
The switch current is sensed with an external resistor
RSENSE connected between the source of the MOSFET and
ground. The internal blanking circuit blocks the voltage
spike developed across RSENSE for 280ns at switch turn-
on. The switch is turned off when the instantaneous
voltageacrossRSENSE exceedsthecurrentlimitthreshold,
Qg = The total gate charge
VG = Gate drive voltage ≈ VDRV
IG(AVG) = The average MOSFET buffer output current
fS = Operating frequency
CRSS = The average CGD between VDS = 0V
and VDS = VDS(OFF)
V
SENSE. Allowing variations in VSENSE yields:
VSENSE(MIN)
IL(MAX)
At low VDS(OFF) (≤12V) and operating frequencies below
500kHz,theohmiclossesoftendominate.Forhighvoltage
converters, the transition loss and COSS charge dumping
loss can dramatically impact the converter efficiency.
MOSFETs with lower parasitic capacitances but higher
RDS(ON) may actually provide better efficiency in these
situations.
RSENSE
=
The current limit threshold is constant and does not vary
with duty ratio.
Duetolowsignallevelofthesensevoltage,lowinductance
sense resistors are required to reduce switching noise.
Low TC resistors maintain constant current limit over
temperature. Dale WSL and IRC series sense resistors
meet these criteria.
Capacitors
In a switch mode DC/DC converter, output ripple voltage
is the product of the equivalent series resistance (ESR) of
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8
LT1619
W U U
APPLICATIO S I FOR ATIO
U
Diode
toleranceof±25%andistemperaturestable, developsan
offsetvoltageatthesenseinput.ThevalueofROS required
for non-Burst Mode operation can be obtained with the
expression:
Schottky diodes are recommended for low output voltage
applications because of their low forward voltage. Since
Schottky diodes have negligible stored charge, charge
dumping loss is also reduced. The reverse breakdown
voltage of the diode should exceed the maximum reverse
voltage stress of the topology used. The diode should also
be able to carry the peak diode current with acceptable
foward voltage. For the boost converter in Figure 1, the
peak inductor current is approximately 5A. A Motorola
MBRD835 is used due to its low forward voltage.
I
R
BIAS OS ≥ VSENSE(BURST)
where
VSENSE(BURST) = (Burst Mode operation peak switch
current, ID(BURST)) • RSENSE
For example, if IBIAS = 120µA and VSENSE(BURST) = 10mV:
10mV
120µA
ROS
≥
= 83Ω
Lowering Burst Mode Operation Current Limit
The LT1619 automatically enters Burst Mode operation as
VC voltage falls below VB. The corresponding switch
currentistheBurstModeoperationswitchcurrentthresh-
Allowing for 25% and 30% variations in IBAIS and
VSENSE(BURST) respectively:
old, ID(BURST)
.
ROS = (1.25)(1.3)(83Ω)
The effective Burst Mode operation current threshold can
be lowered by adding an offset to the input of the current
sense amplifier so that the switch current appears higher
to the PWM comparator. This has the effect of shifting the
VC operatingrangeaboveVB. AlthoughBurstModeopera-
tionisnotentirelydisabled, thepeakswitchcurrentbefore
entering Burst Mode operation is greatly reduced due to
the offset of the current sense amplifier. The peak switch
current is also determined by the current sense amplifier
blanking.
Choose ROS = 137Ω to completely disable Burst Mode
operation. Lower values of ROS (for example, 50Ω to
100Ω) can be used to lower the effective Burst Mode
current limit.
Thevalueofthesenseresistoristhenadjustedtocompen-
sate for the reduced full-scale sense voltage.
IBIAS OS
Filtering Current Sense Signal
n a current mode converter, the current sense circuit
R
+ IL(MAX)RSENSE = 40mV
To lower the Burst Mode operation current sense thresh-
old, a resistor ROS is added between the SENSE pin and
the sense resistor RSENSE (Figure 5). The input bias
current IBIAS of the current sense amplifier, which has a
I
senses the switch current and terminates the switch
conduction. In the LT1619, the current sense amplifier
hasafull-scaleinputvoltagerangefromthegroundtothe
currentlimitthreshold(53mV).Duetohighspeedswitch-
ingtransientsandparasitictraceinductances, thecurrent
sense signal VSENSE tends to be noisy. If the VSENSE
switching transient is excessive, the current sense ampli-
fierwillamplifythespurioustransientinstead,resultingin
jittery operation. In situations where the internal leading
edge blanking is inadequate, a lowpass filter (Figure 6)
with corner frequency about 5 times the switching
frequency can be used to further attenuate high speed
switchingtransients. InFigure6thelowpassfilterROS and
CS has a corner frequency of:
CURRENT
I
D
SENSE
AMPLIFIER
–
+
I
= 120µA
I
= 120µA
BIAS
BIAS
5
R
OS
SENSE
R
SENSE
4
1619 F05
GND
Figure 5. Lowering Burst Mode Operation Current Limit
1619fa
9
LT1619
W U U
U
APPLICATIO S I FOR ATIO
V
IN
1
V
fCORNER
=
≈ 5fS
Z
1
2
3
4
8
7
6
5
2πROSCS
S/S
FB
V
IN
I
I
S/S
S/S
R3 < SHUTDOWN THRESHOLD
(
)
V
= 0
S/S
(The input impedance of the sense amplifier at the SENSE
pin is 2500Ω and ROS is typically less than 137Ω.) Typical
values for ROS and CS are 100Ω and 1nF. The 100Ω value
for ROS reduces Burst Mode threshold; use 10Ω and 10nF
when this is not desireable.
DRV
LT1619
GATE
UVLO THRESHOLD = V + SHUTDOWN
THRESHOLD ≈ V + V
R3
Z
Z
BE
V
C
I
S/S
≈ –2µA
V
= 0
S/S
GND SENSE
1619 F07
Figure 7. Implementing Undervoltage Lockout
I
LT1619
D
PWM
COMPARATOR
CURRENT
SENSE
AMPLIFIER
I
R
OS
ZENER
DIODE
AVALANCHE
DIODE
SENSE
GND
+
–
5
4
+
+
–
C
S
R
V
SENSE
SENSE
I
V
–
1619 F06
V
Figure 6. Current Sense Filter for Improving Jitter Performance
0
BV < 5V
Figure 8. I-V Characteristics of Zener
and Avalanche Breakdown Diodes
Use of Shutdown Function to
Modify Undervoltage Lockout
V
IN
The LT1619 is designed to operate from an input supply
with voltage as low as 1.85V. Shutdown is activated when
theS/Spinispulledbelow0.45V. Theshutdownthreshold
is slightly greater than one junction diode forward voltage
and has the temperature characteristics of a junction
diode. The S/S pin is normally tied to the input when
operating from a low voltage input source.
R4
R3
1
2
3
4
8
7
6
5
S/S
FB
V
IN
DRV
LT1619
GATE
C1
V
C
GND SENSE
Consider the 12V to –65V isolated flyback converter (see
Typical Applications). The converter draws 3A at low line
while delivering 0.4A to the output. If the S/S pin is tied to
the input, then the LT1619 will start switching as soon as
VIN exceeds the internal UVLO threshold. With full load,
the converter can draw much higher than the steady-state
3A from the input source during start-up. If the input
source is current limited, the input voltage will collapse
and latch low.
1619 F09
Figure 9. Filtering Input Voltage Ripple in UVLO Circuit
resistor R3. The voltage developed across R3 due to IS/S
should be less than the shutdown threshold. The LT1619
remains off until VIN exceeds the sum of VZ and the
shutdown threshold. True zener diodes (BV < 5V) and
higher voltage avalanche diodes have different I-V charac-
teristics (Figure 8). They need to be biased appropriately
(value of R3) in order to obtain correct UVLO threshold.
The start-up problem can be prevented by adding a zener
diode and a resistor to the S/S pin (Figure 7). This is
equivalent to increasing undervoltage lockout voltage of
thecontroller. BeforeVIN exceedsthezenervoltageVZ, the
S/S pin current is shunted to the ground through the
WhenimplementingUVLOwithconverterswithhighinput
ripple voltages (such as flyback and forward), the circuit
in Figure 7 is modified and shown in Figure 9.
1619fa
10
LT1619
W U U
APPLICATIO S I FOR ATIO
U
Here the input voltage ripple is filtered with R3, R4 and C1
so as to prevent the input ripple from falsely tripping the
LT1619 synchronization circuit. It is recommended that:
The collector votage of Q2 is made about 1.4V at the VIN
lower trip voltage. This is necessary to prevent the UVLO
circuit from interfering with the feedback amplifier in the
LT1619.
1
R4 ≈ R3
Trickle Current Start from High Voltage Supplies
5
1
The low shutdown and idle mode quiescent supply cur-
rents of the LT1619 can be utilized to implement trickle
current start from high voltage input sources (such as a
36V to 72V telecom bus). The trickle current start-up
circuit in Figure 11 is modified from the UVLO circuit of
Figure 10. R10 is a high value resistor that charges the
storage capacitor C2 during start-up. Before VCC reaches
the upper UVLO trip point, Q2 holds the S/S pin low. The
LT1619drawsshutdownmodecurrent(≈15µA)fromVCC.
Q2 collector can also be tied to the VC pin through a diode
as in Figure 10. The LT1619 will then draw idle mode
quiescent current (≈140µA) from VCC. R10 should be able
to charge C2 while supplying current to the UVLO circuit
and the LT1619. Maximizing R5 to R9 values reduces
power dissipation in R10.
and
<< fOSC
2π R3||R4 C1
(
)
Implementation of Hysteretic UVLO
with External Synchronization
The UVLO circuit shown in Figure 10 operates down to
0.9V supply voltage. Algebraically the UVLO trip points
are:
R5
R6||R7
VINH = VZ + VBE 1+
and
R5|| R7 +R9
R5|| R7 +R9
(
)
(
)
V
INL
=
VZ + VBE
R5
R5||R6|| R7 +R9
(
)
When VCC crosses the upper UVLO threshold, the LT1619
starts switching and its current consumption increases.
Before the bootstrap takes over, the LT1619 draws its
current from C2. VCC ramps towards the lower UVLO
threshold. Increasing the value of C2 allows more time for
thebootstrapcircuittoestablishitselfbeforetheconverter
enters undervoltage lockout.
R5
UVLOHysteresis = VINH – V
=
VZ +
INL
R5 +R7 +R9
R5|| R7 +R9
(
)
R5
R6||R7
VBE
–
R6
V
IN
HV V
IN
1
2
3
4
8
7
6
5
R8
30k
R9
BOOTSTRAP
WINDING
R10
CLK
S/S
FB
V
IN
510k
V
CC
+
–
8.2V
R7
51k
DRV
LT1619
GATE
D1
BAT85
D2
1
8
7
6
5
C2
R8
R9
R7
S/S
FB
V
IN
V
C
2
3
4
DRV
LT1619
GATE
Q2
R5
51k
2N2222
T1
GND SENSE
Q1
2N2222
1619 F10
V
R5
R6
C
Q2
R6
51k
Q1
V
V
UPPER TRIP POINT = 10V
LOWER TRIP POINT = 8.4V
GND SENSE
IN
IN
1619 F11
Figure 10. Addition of Hysteresis UVLO While Synchronizing the
LT1619. Component Values Shown are for the Upper and the
Lower VIN Trip Points of 10V and 8.4V. In UVLO, the Gate Drive
is Disabled by Pulling the VC Pin Low. Disabling the Clock Shuts
Down the LT1619. If Not Synchronized, the Collector of Q2 Can
Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated
Figure 11. Trickle Current Start-Up with Bootstrapped VCC
1619fa
11
LT1619
W U U
U
APPLICATIO S I FOR ATIO
Increasing Ramp Compensation While Synchronizing
whosepeakamplitudesaremadebetween1/4to1/3ofthe
current limit threshold, are developed across R13. As a
result, the effective current limit threshold is reduced by
the sum of the compensating ramp and the offset voltage
developed across R13 due to the SENSE pin input bias
current (see Figure 5). Moreover, the current limit thresh-
old becomes duty cycle dependent.
The LT1619 is synchronized by forced discharge of the
internal timing ramp. The timing ramp amplitude de-
creasesasthesynchronizationfrequencyincreases.Since
theinternalcompensationrampisderivedfromthetiming
ramp, reduced timing ramp results in diminished com-
pensating ramp. If the LT1619 is synchronized at frequen-
cies 20% to 30% higher than the free-running frequency,
external ramp compensation will be required. Figures 12
and 13 show two such schemes.
PC Board Layout and Other Practical Considerations
The following is recommended for PC board layout:
1. Trace lengths of the branches carrying switched cur-
rent should be kept short. For example, in the boost
converter of Figure 1, the circuit loop formed by M1,
In both figures the compensating ramps are kept linear by
makingR11-C1andR14-C2productssubstantiallyhigher
than the synchronizing period. The compensation ramps,
RSENSE, D1 and COUT carries switched current. The size
of this loop must be minimized. RSENSE and COUT
should be grounded to a single point on a large ground
plane. This reduces switching noise and overall con-
verter jitter. It is also preferable to ground the input
capacitor C1 close to the common point between COUT
and RSENSE although this is less important.
1
2
3
4
8
7
6
5
MAIN POWER
TRANSISTOR
CLK
S/S
FB
V
IN
R11
100k
DRV
LT1619
GATE
Q1
D2
1N4148
2N2222
V
C
R12
2200Ω
GND SENSE
R13
51Ω
C1
220pF
R
2. Keep the trace between the sense resistor and the
SENSE pin short. When sensing high switch current,
Kelvin connection to RSENSE is necessary.
SENSE
1619 F12
Figure 12. Increasing Ramp Compensation. Q1 Buffers the C1
Ramp. D2 Discharges C1. Values Shown are for 10V Gate Drive
and 15mV Ramp Across R13 at 90% Duty Cycle and 500kHz
3. Bypass both the VIN and DRV pins with ceramic capaci-
tors next to the IC and the ground plane.
4. Keep high voltage switching nodes, such as the drain
and gate of the MOSFET, away from the FB and VC pins.
1
2
3
4
8
7
6
5
CLK
S/S
FB
V
IN
R14
5. Use inductor so that its ripple current is between 1/4
and 1/3 of its peak current. Steeper inductor current
ramp results in sharper PWM comparator switching,
hence less jitter.
8200Ω
DRV
LT1619
GATE
D2
D3
1N4148
1N4148
V
C
R15
2400Ω
GND SENSE
6. In most cases, filtering the current sense signal is not
necessary for jitter-free operation.
R13
51Ω
C2
2.2nF
R
SENSE
1619 F13
Figure 14 is the PC board layout for the 5V/8A and 12V/5A
boost converters shown in Figures 15a and 16a.
Figure 13. Externally Increasing Ramp Compensation. Similar
to Figure 12 Except That C2 is Not Buffered with Transistor
1619fa
12
LT1619
W U U
APPLICATIO S I FOR ATIO
U
C
DRV
C
IN2
R1
R2
R
C
1
2
3
4
8
7
6
5
S
S
LT1619
G
M1
M1
G
C
Z
C
P
D
D
R
SENSE
C
OUT1, 2
GND
C
IN1
D1
L1
V
OUT
V
IN
1619 F14
Figure 14. Recommended Component Placement for the Boost Converters in Figures 15a and 16a
1619fa
13
LT1619
APPLICATIO S I FOR ATIO
W U U
U
V
IN
3.3V
1
2
3
4
8
7
6
5
C
L1
S/S
FB
V
IN
IN2
1µF
1µH
CERAMIC
DRV
LT1619
GATE
C
+
DRV
C
5V
8A
IN1
0.1µF
300µF
CERAMIC
V
C
M1
D1
R1
FDS6680A
R
C
OUT2
C
37400Ω
×2
C
P
75k
10µF
+
GND SENSE
C
OUT1
220µF
×4
150pF
CERAMIC
C
15nF
Z
R
SENSE
R2
12400Ω
1619 F15a
C
C
: SANYO POSCAP 6TPB150M ×2
OUT1
IN1
: SANYO POSCAP 10TPB220M ×4
D1: MOTOROLA MBRB1545CT
L1: SUMIDA CEPH149-1R0
R
: PANASONIC 0.002Ω 1W
SENSE
Figure 15a. 3.3V to 5V/8A Boost Converter
89
V
= 3.3V
IN
88
87
86
85
84
83
0.01
0.1
1
10
LOAD CURRENT (A)
1619 F15b
Figure 15b. Efficiency of the 5V/8A Boost Converter
1619fa
14
LT1619
W U U
APPLICATIO S I FOR ATIO
U
V
IN
5V
1
2
3
4
8
7
6
5
C
L1
S/S
FB
V
IN
IN2
1µF
1.8µH
CERAMIC
DRV
LT1619
GATE
C
+
DRV
C
12V
5A
IN1
0.1µF
100µF
CERAMIC
V
C
M1
D1
R1
FDS6690A
R
C
OUT2
C
107k
×2
C
P
68.1k
10µF
+
GND SENSE
47pF
C
CERAMIC
OUT1
600µF
C
Z
R
SENSE
R2
2200pF
12400Ω
1619 F15a
C
C
: SANYO OS-CON 10SA100M
OUT1
IN1
: SANYO OS-CON 16SA150M ×4
D1: MOTOROLA MBRB1545CT
L1: SUMIDA CDEP149-1R8
R
: PANASONIC 0.002Ω 1W
SENSE
Figure 16a. 5V to 12V/5A Boost Converter
95
V
= 5V
IN
94
93
92
91
90
89
88
87
86
85
0.01
0.1
1
10
LOAD CURRENT (A)
1619 F16b
Figure 16b. Efficiency of the 12V/5A Boost Converter
1619fa
15
LT1619
TYPICAL APPLICATIO S
U
V
IN
T1
4.75V TO
5.25V
–48V/0.5A
•
•
•
•
•
•
470µF
35V
+
MBRS340T3
SANYO MV-GX
1µF
+
1500µF
470µF
1N749
4.3V
4.7µF
FILM
15Ω
6.3V
35V
+
SANYO MV-GX
SANYO MV-GX
1
8
7
6
5
S/S
V
IN
4.7µF
FILM
MBRS340T3
1.1k
2
FB
DRV
LT1619
GATE
1M
12k
10µF
SUD45N05-20L
50V, 0.018Ω
43nC
3
V
C
30Ω
220pF
2.2nF
36k
22nF
4
2N5210
GND SENSE
10.5k
1%
0.007Ω
2N5210
432k
1%
1619 F17a
T1: COILTRONICS CTX02-14261, EFD20-3F3, 6 WINDINGS EACH, 12µH
Figure 17a. 5V to –48V Cuk Converter
90
89
88
87
86
85
84
83
82
81
80
79
V
= 5.25V
IN
V
= 5V
IN
V
= 4.75V
IN
10
100
LOAD CURRENT (mA)
1000
1619 F17b
Figure 17b. Efficiency of the 5V to –48V Cuk
1619fa
16
LT1619
U
TYPICAL APPLICATIO S
10k
CNY17-3
6.2V
V
IN
10.5V TO
13.7V
220pF
330pF
100V
470Ω
T1
2.2µF
100Ω
43Ω
•
40V
1/4W
62k
0.22µF
50V
1k
W1
W3
8.1V
43Ω
470pF
121Ω
1W
LT1431
•
1
2
3
4
8
7
6
5
COLL
NC
REF
NC
–32.5V
MBRS1100T3
V+
NC
FGND
SGND
20k
•
W4
W2
MBRS1100T3
2.49k
1µF
50V
2.2µF
40V
330pF
50V
–65V
•
MBRS1100T3
1
2
3
4
8
7
6
5
S/S
FB
V
IN
0.1µF
82k
DRV
T1
PHILIPS EFD20-3F3-A100-S
CORE SET (0.013" GAP, AI = 100nH/T
LT1619
10µF
IRLR024N
10k
2
150µF
20V
55V, 0.065Ω
V
C
GATE
Q
= 15nC
G
2mil
POLYESTER
FILM
W4 6T TRIFILAR 28AWG
W3 24T 28AWG
100Ω
1µF
SANYO
GND SENSE
20SV150M
(OS-CON)
W2 24T 28AWG
0.008Ω
W1 6T TRIFILAR 28AWG
1619 F18a
Figure 18a. Isolated Local SLIC Power Supply (Flyback) 20W Total Output Power (65V/0.3A or 32.5V/0.6A)
90
85
80
75
70
65
60
V
V
V
= 13.7V
= 12V
IN
IN
IN
55
50
= 10.5V
10
100
LOAD CURRENT (mA)
1000
1619 F18b
Figure 18b. Efficiency of the Isolated Local SLIC (Flyback)
1619fa
17
LT1619
U
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.206)
REF
0.65
(.0256)
BSC
0.42 ± 0.04
(.0165 ± .0015)
TYP
8
7 6
5
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.077)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.13 ± 0.076
(.005 ± .003)
0.65
(.0256)
BSC
MSOP (MS8) 0802
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1619fa
18
LT1619
U
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 ±.005
NOTE 3
.050 BSC
N
7
5
8
6
N
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
2
3
N/2
N/2
4
.030 ±.005
TYP
RECOMMENDED SOLDER PAD LAYOUT
1
3
2
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0502
1619fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT1619
U
TYPICAL APPLICATIO
V
IN
T1
4V TO 28V
7
9
C4
1.5µF
100V
•
•
•
•
•
•
R3
5.6k
10
2
12
1
5
3
4
8
6
11
C5
D2
1.5µF
MBRS340T3
100V
V
OUT
Q1
D3
5V
FMMT3904
MBRS0530T1
0.5A
D4
Q3
1N4687
4.3V
MMFT3055VL
8
7
6
R5
LOW LEVEL
R7
30Ω
C6
10µF
10V
R6
3.74k
1%
100Ω
V
IN
DRV GATE
(I = 50µA)
ZT
5
2
SENSE
LT1619
FB
C1
0.022µF
S/S GND
V
C
R10
1.24k
1%
1
4
3
R9
2.2k
C9
R8
0.015Ω
C7
220pF
C8
1µF
16V
2.2nF
C4, C5: VITRAMON VJ1825Y155MXB (1825/X7R)
C6: TAIYO YUDEN LMK325BJ106MN (1210/X7R)
1619 TA01
C8: TAIYO YUDEN EMK316BJ105ML (1206/X7R)
T1: COILTRONICS VP1-0190 (ER11/5, 6 WINDINGS EACH 12.2µH)
Figure 19. 2.5W, 4VIN-28VIN to 5V/0.5A Nonisolated Supply
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
Boost, Buck, Flyback, Forward, Inverting; 42V Switch Voltage
SO-8, 2.7V ≤ V ≤ 30V, 42V Switch Voltage
LT1370
LT1372
LT1613
LTC1624
LT1680
LT1698
500kHz, 6A Switching Regulator
500kHz, 1.5A Switching Regulator
1.4MHz, SOT-23 DC/DC Converter
Switching Regulator Controller
Synchronous Boost Controller
IN
Fixed Frequency, 0.9V ≤ V ≤ 10V, 36V Switch Voltage
IN
SO-8, Drives N-Ch MOSFET, 3.5V ≤ V ≤ 36V
IN
Synchronous Operation for High Current/High Efficiency
Isolated or Nonisolated 10W to 100W
Power Supply Solution with Multiple Outputs
50% Lower Cost than Quarter Brick and Half Brick Modules
Fits the Foot Print
LTC1871
No R
Boost, Flyback, SEPIC Controller
2.5V ≤ V ≤ 36V, Current Mode Control, 50kHz to 1MHz
SENSE
IN
Adjustabe Frequency, MSOP-10
550kHz Fixed Frequency, Current Mode
MSOP-8, 5V to 12V/400mA
LTC1872
LT1946
SOT-23 Boost Controller
1.2MHz, 65A DC/DC Converter
LT3710/LT3781 Isolated or Nonisolated 10W to 100W
Power Supply Solution with Multiple Outputs
50% Lower Cost than Quarter Brick and Half Brick Modules
Fits the Foot Print
1619fa
LT/TP 1002 1K REV A • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2000
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