LT1394CMS8 [Linear]
7ns, Low Power, Single Supply, Ground-Sensing Comparator; 为7ns ，低功耗，单电源，接地检测比较
| 型号： | LT1394CMS8 |
| 厂家： | 
Linear |
| 描述： | 7ns, Low Power, Single Supply, Ground-Sensing Comparator |
| 文件： | 总16页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1394
7ns, Low Power,
Single Supply, Ground-Sensing
Comparator
U
FEATURES
DESCRIPTIO
UltraFastTM: 7ns
The LT®1394 is an UltraFast(7ns) comparator with comple-
mentary outputs and latch. The input common mode range
extends from 1.5V below the positive supply down to the
negative supply rail. Like the LT1016, LT1116 and LT1671,
this comparator has complementary outputs designed to
interface directly to TTL or CMOS logic. The LT1394 may
operate from either a single 5V supply or dual ±5V supplies.
Low offset voltage specifications and high gain allow the
LT1394 to be used in precision applications.
■
■
Low Power: 6mA
■
Low Offset Voltage: 0.8mV
■
Operates Off Single 5V or Dual ±5V Supplies
■
Input Common Mode Extends to Negative Supply
■
No Minimum Input Slew Rate Requirement
■
Complementary TTL Outputs
■
Inputs Can Exceed Supplies without Phase Reversal
■
Pin Compatible with LT1016, LT1116 and LT1671
■
Output Latch Capability
Available in 8-Lead MSOP and SO Packages
The LT1394 is designed for improved speed and stability for
a wide range of operating conditions. The output stage
provides active drive in both directions for maximum speed
intoTTL,CMOSorpassiveloadswithminimalcross-conduc-
tion current. Unlike other fast comparators, the LT1394
remains stable even for slow transitions through the active
region,whicheliminatestheneedtospecifyaminimuminput
slew rate.
■
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APPLICATIO S
■
High Speed A/D Converters
■
Zero-Crossing Detectors
■
Current Sense for Switching Regulators
■
Extended Range V/F Coverters
■
Fast Pulse Height/Width Discriminators
The LT1394 has an internal, TTL/CMOS compatible latch for
retaining data at the outputs. The latch holds data as long as
the LATCH pin is held high. Device parameters such as gain,
offsetandnegativepowersupplycurrentarenotsignificantly
affected by variations in negative supply voltage.
■
High Speed Triggers
Line Receivers
High Speed Sampling Circuits
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
45MHz Single Supply Adaptive Trigger
Propagation Delay vs
Input Overdrive
5V
2k
12
10
8
T
V
V
= 25°C
STEP
= ±5V
6
A
3
1
5
= 100mV
Q1
Q2
S
5V
3M
4
2
5V
500pF
+
–
0.005µF
t
+
–
A1
LT1227
PDLH
6
t
A2
LT1006
PDHL
0.005µF
3M
Q1, Q2, Q3, Q4 = CA3096 ARRAY:
4
TIE SUBSTRATE (PIN 16) TO GROUND
13
15
10
11
= 1N4148
2k
750Ω
0.1µF
510Ω
12
14
Q4
5V
Q3
2
36Ω
470Ω
0
+
+
0
10
20
30
40
50
2k
0.1µF
10µF
100µF
OVERDRIVE (mV)
+
TRIGGER
OUT
0.1µF
LT1394
1394 TA02
470Ω
–
INPUT
1394 F18
1
LT1394
ABSOLUTE MAXIMUM RATINGS
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(Note 1)
Total Supply Voltage (V+ to V–) ............................... 12V
Positive Supply Voltage ............................................. 7V
Negative Supply Voltage .......................................... –7V
Differential Input Voltage ....................................... ±12V
Input and Latch Current (Note 2)........................ ±10mA
Output Current (Continuous)(Note 2) ................. ±20mA
Operating Temperature Range ................ –40°C to 85°C
Specified Temperature Range (Note 3)... –40°C to 85°C
Junction Temperature........................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
NUMBER
+
V
1
2
3
4
8
7
6
5
Q OUT
Q OUT
GND
+
V
1
2
3
4
8 Q OUT
7 Q OUT
6 GND
5 LATCH
ENABLE
+
–
+IN
–IN
+IN
–IN
LT1394CS8
LT1394IS8
LT1394CMS8
–
V
–
LATCH
ENABLE
V
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTBH
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 250°C/ W
1394
1394I
TJMAX = 150°C, θJA = 190°C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V+ = 5V, V– = –5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
R ≤ 100Ω (Note 4)
0.8
2.5
4.0
mV
mV
OS
S
●
●
∆V
∆T
Input Offset Voltage Drift
Input Offset Current
4
0.1
2
µV/°C
OS
I
I
0.5
0.8
µA
µA
OS
●
●
Input Bias Current
(Note 5)
4.5
7.0
µA
µA
B
V
Input Voltage Range (Note 6)
Common Mode Rejection Ratio
●
●
–5
0
3.5
3.5
V
V
CMR
Single 5V Supply
CMRR
PSRR
–5V ≤ V ≤ 3.5V, T > 0°C
55
55
100
100
dB
dB
CM
A
–5V ≤ V ≤ 3.3V, T ≤ 0°C
CM
A
Single 5V Supply
0V ≤ V ≤ 3.5V, T > 0°C
55
55
dB
dB
CM
A
0V ≤ V ≤ 3.3V, T ≤ 0°C
CM
A
+
Power Supply Rejection Ratio
4.6V ≤ V ≤ 5.4V
●
●
50
65
65
100
dB
dB
–
–7V ≤ V ≤ –2V
A
V
Small Signal Voltage Gain
Output Voltage Swing High
1V ≤ V
≤ 2V
OUT
750
1600
V/V
V
+
V
V
≥ 4.6V, I
≥ 4.6V, I
= 1mA
= 4mA
●
●
2.7
2.4
3.1
3.0
V
V
OH
OUT
OUT
+
2
LT1394
ELECTRICAL CHARACTERISTICS
V+ = 5V, V– = –5V, VOUT(Q) = 1.4V, VLATCH = VCM = 0V unless otherwise noted.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Output Voltage Swing Low
I
I
= –4mA
= –10mA
●
●
0.3
0.4
0.5
V
V
OL
OUT
OUT
+
I
I
Positive Supply Current
Negative Supply Current
6
8.5
10.0
mA
mA
–
1.2
2.2
2.5
mA
mA
●
●
●
●
V
V
LATCH Pin High Input Voltage
LATCH Pin Low Input Voltage
LATCH Pin Current
2
V
V
IH
IL
0.8
I
t
V
= 0V
LATCH
–4
7
–10
µA
IL
PD
Propagation Delay (Note 7)
∆V = 100mV, V = 5mV
9
14
ns
ns
IN
OD
●
∆t
Differential Propagation Delay (Note 7)
Latch Propagation Delay (Note 8)
Latch Setup Time (Note 8)
∆V = 100mV, V = 5mV
0.5
6
2.2
ns
ns
ns
ns
ns
PD
LPD
SU
IN
OD
t
t
t
t
–0.4
2
Latch Hold Time (Note 8)
H
Minimum Disable Pulse Width
3
PW(D)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 7: t and ∆t cannot be measured in automatic handling
equipment with low values of overdrive. The LT1394 is 100% tested with a
PD
PD
100mV step and 20mV overdrive. Correlation tests have shown that t
Note 2: This parameter is guaranteed to meet specified perforamnce
through design and characterization. It has not been tested.
Note 3: The LT1394CMS8 and LT1394CS8 are guaranteed to meet
specified performance from 0°C to 70°C and are designed, characterized
and expected to meet these extended temperature limits, but are not tested
at –40°C and 85°C. The LT1394IS8 is guaranteed to meet the extended
temperature limits.
PD
and ∆t limits can be guaranteed with this test, if additional DC tests are
PD
performed to guarantee that all internal bias conditions are correct.
Propagation delay (t ) is measured with the overdrive added to the actual
PD
V
. Differential propagation delay is defined as:
OS
∆t = t
PD
– t
PDHL
PDLH
Note 8: Latch propagation delay (t ) is the delay time for the output to
LPD
respond when the LATCH pin is deasserted. Latch setup time (t ) is the
interval in which the input signal must remain stable prior to asserting the
Note 4: Input offset voltage (V ) is defined as the average of the two
voltages measured by forcing first one output, then the other to 1.4V.
SU
OS
latch signal. Latch hold time (t ) is the interval after the latch is asserted in
H
Note 5: Input bias current (I ) is defined as the average of the two input
B
which the input signal must remain stable.
currents.
Note 6: Input voltage range is guaranteed in part by CMRR testing and in
part by design and characterization.
3
LT1394
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TYPICAL PERFORMANCE CHARACTERISTICS
Propagation Delay vs
Load Capacitance
Propagation Delay vs
Positive Supply Voltage
Gain Characteristics
12
10
8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
10
8
V
OUT
= ±5V
S
I
= 0
T
= 125°C
A
t
PDLH
T
= 25°C
A
t
PDHL
t
PDHL
t
PDLH
6
6
T
= –55°C
A
4
4
I
= 0
= ±5V
= 25°C
OUT
S
A
–
V
V
= –5V
T
V
T
= 25°C
A
STEP
2
2
= 100mV
V
= 100mV
STEP
OVERDRIVE = 5mV
OVERDRIVE = 5mV
0
0
0
10
20
30
40
50
4.4
4.6
4.8
5.0
5.2
5.4
5.6
–3
–2
0
1
2
3
–1
OUTPUT LOAD CAPACITANCE (pF)
POSITIVE SUPPLY VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (mV)
1394 G02
1394 G03
1394 G01
Propagation Delay vs
Input Overdrive
Propagation Delay vs
Source Resistance
Propagation Delay vs
Temperature
12
10
8
12
10
8
80
70
60
50
40
30
20
10
0
V
V
T
= ±5V
OD
= 25°C
V
V
V
= ±5V
T
V
V
= 25°C
STEP
= ±5V
S
S
A
= 20mV
= 100mV
STEP
= 100mV
= 5mV
OD
A
S
t
PDLH
t
PDHL
t
PDLH
6
6
400mV
t
PDHL
STEP SIZE = 800mV
4
4
2
200mV
2.5
2
100mV
0
0
0
0.5
1.0
1.5
2.0
3.0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
10
20
30
40
50
SOURCE RESISTANCE (kΩ)
OVERDRIVE (mV)
1394 G04
1394 G05
1394 TA02
Input Bias Current vs
Temperature
Positive Common Mode Limit vs
Temperature
Input Offset Voltage vs
Temperature
6
5
4
3
2
1
0
4
3
2
1
0
2
V = ±5V
S
V
= ±5V
V
= ±5V
S
S
1
0
–1
–2
–3
–4
–5
V
= –5V
= 0V
CM
V
CM
V
= 3.5V
CM
50
TEMPERATURE (°C)
100 125
50
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
1394 G08
LT1394 G07
LT1394 G06
4
LT1394
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TYPICAL PERFORMANCE CHARACTERISTICS
Negative Common Mode Limit vs
Temperature
Output High Voltage (VOH) vs
Output Source Current
Output Low Voltage (VOL) vs
Output Sink Current
1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
= ±5V
V = ±5V
S
∆V = –30mV
IN
S
∆V = 30mV
IN
V
= SINGLE 5V
S
–1
–2
–3
–4
–5
–6
T
= 125°C
A
T
= 125°C
T
= 25°C
A
A
T
= –55°C
A
T
= 25°C
A
T
= –55°C
A
V
= ±5V
S
50
100 125
0
2
4
6
8
10 12 14 16
8
–50 –25
0
25
75
0
2
6
10
14 16
4
12
TEMPERATURE (°C)
OUTPUT SINK CURRENT (mA)
OUTPUT SOURCE CURRENT (mA)
LT1394 G09
1394 G10
1394 G11
Positive Supply Current vs
V+ Supply Voltage
Negative Supply Current vs
V– Supply Voltage
Positive Supply Current vs
Switching Frequency
16
14
12
10
8
10
9
8
7
6
5
4
3
2
1
0
4
3
2
1
0
–
V
= ±5V
+
V
V
= 0V
S
V = 5V
T
= 25°C
A
= –60mV
∆V = –60mV
IN
OUT
IN
I
= 0
T
= 125°C
= –55°C
A
T
= 125°C
A
T
= 125°C
T = 25°C
A
A
6
T
= 25°C
A
T
A
4
T
4
= –55°C
T
= –55°C
A
A
2
0
1
10
SWITCHING FREQUENCY (MHz)
100
0
6
7
1
2
3
5
8
–8
–7
–5 –4 –3 –2
0
–6
–1
SUPPLY VOLTAGE (V)
NEGATIVE SUPPLY VOLTAGE (V)
1394 G13
1394 G12
1394 G14
Latch Pin Current vs Temperature
Response to 100MHz ±10mV
8
7
6
5
4
3
2
1
0
Sine Wave
V
V
= ±5V
LATCH
S
= 0V
+IN
10mV/DIV
1V/DIV
20mVP-P
3V
Q
OUT
0V
FET PROBES
5ns/DIV
1394 G16
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
LT1394 G15
5
LT1394
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TYPICAL PERFORMANCE CHARACTERISTICS
tPD– Response Time to
5mV Overdrive
tPD+ Response Time to
5mV Overdrive
1.4V
1.4V
5mV
Q OUT
5mV
+IN
–95mV
+IN
Q OUT
0V
–95mV
0V
V
S = ±5V
fIN = 2MHz
OD = 5mV
2ns/DIV
VS = ±5V
2ns/DIV
fIN = 2MHz
V
1394 G17
V
OD = 5mV
1394 G18
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PIN FUNCTIONS
V+ (Pin 1): Positive Supply Voltage. Normally 5V.
+IN (Pin 2): Noninverting Input.
GND (Pin 6): Ground.
Q OUT (Pin 7): Noninverting Logic Output. This pin is high
when +IN is above –IN and LATCH ENABLE is low.
–IN (Pin 3): Inverting Input.
V– (Pin4):NegativeSupplyVoltage. Normallyeither0Vor
–5V.
Q OUT (Pin 8): Inverting Logic Output. This pin is low
when +IN is above –IN and LATCH ENABLE is low.
LATCHENABLE(Pin5):LatchControlPin. Whenhigh, the
outputs remain in a latched condition, independent of the
current state of the inputs.
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TI I G DIAGRA S
V
OD
LATCH
ENABLE
t
t
H
SU
∆V
IN
V
IN
V
IN
t
PD
t
L
PD
V
OUT
V
OUT
1394 TD01
1394 TD02
6
LT1394
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APPLICATIONS INFORMATION
Common Mode Considerations
Input Bias Current
The LT1394 is specified for a common mode range of –5V
to 3.5V on a ±5V supply or a common mode range of 0V
to 3.5V on a single 5V supply. A more general consider-
ation is that the common mode range is 0V below the
negative supply and 1.5V below the positive supply, inde-
pendent of the actual supply voltage. The criterion for
common mode limit is that the output still responds
correctly to a small differential input signal.
Input bias current is measured with the output held at
1.4V. As with any PNP differential input stage, the LT1394
bias current flows out of the device. It will go to zero on an
input which is high and double on an input which is low.
LATCH Pin Dynamics
The LATCH pin is intended to retain input data (output
latched) when the LATCH pin goes high. The pin will float
to a high state when disconnected, so a flow-through
condition requires that the LATCH pin be grounded. The
LATCH pin is designed to be driven with either a TTL or
CMOS output. It has no built-in hysteresis.
When either input signal falls below the negative common
mode limit, the internal PN diode formed with the sub-
strate can turn on, resulting in significant current flow
through the die. An external Schottky clamp diode
between the input and the negative rail can speed up
recovery from negative overdrive by preventing the sub-
strate diode from turning on. The zero-crossing detector
in Figure 1 demonstrates the use of a fast clamp diode.
To guarantee data retention, the input signal must remain
valid at least 2ns after the latch goes high (hold time), and
must be valid at least –0.4ns before the latch goes high
(setup time). The negative setup time simply means that
the data arriving 0.4ns after (rather than before) the latch
signal is valid. When the latch signal goes low, new data
will appear at the output in approximately 6ns (latch
propagation delay).
The zero-crossing detector terminates the transmission
line at its 50Ω characteristic impedance. Negative inputs
should not fall below –2V to keep the signal current within
the clamp diode’s maximum forward rating. Positive
inputs should not exceed the device’s absolute maximum
ratings or the power rating on the terminating resistor.
Measuring Response Time
To properly measure the response of the LT1394 requires
an input signal source with very fast rise times and
exceptionally clean settling characteristics. The last
requirementcomesaboutbecausethestandardcompara-
tor test calls for an input step size that is large compared
to the overdrive amplitude. Typical test conditions are
100mV step size with 5mV overdrive. This requires an
input signal that settles to within 1% (1mV) of final value
in only a few nanoseconds with no ringing or settling tail.
Ordinary high speed pulse generators are not capable of
generating such a signal, and in any case, no ordinary
oscilloscope is capable of displaying the waveform to
check its fidelity. Some means must be used to inherently
generate a fast, clean edge with known final value. The
circuit shown in Figure 2 is the best electronic means of
generating a fast, clean step to test comparators. It uses
a very fast transistor in a common base configuration. The
transistor is switched off with a fast edge from the genera-
tor and the collector voltage settles to exactly 0V in just a
few nanoseconds. The most important feature of this
Either input may go above the positive common mode
limitwithoutdamagingthecomparator. Theuppervoltage
limit is determined by an internal diode from each input to
the positive supply. The input may go above the positive
supply as long as it does not go far enough above it to
conductmorethan10mA. Functionalitywillcontinueifthe
remaining input stays within the allowed common mode
range. There will, however, be an increase in propagation
delay as the input signal switches back into the common
mode range.
5V
R
S
CABLE
50Ω
V
+
IN
Q
Q
R
T
LT1394
1N5712
50Ω
–
1394 F01
Figure 1. Fast Zero-Crossing Detector
7
LT1394
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APPLICATIONS INFORMATION
0.01µF*
5V
0V
25Ω
10k
–100mV
Q
+
FET PROBE
FET PROBE
25Ω
LT1394
–
Q
0.1µF
130Ω
* TOTAL LEAD LENGTH INCLUDING DEVICE PIN.
SOCKET AND CAPACITOR LEADS SHOULD BE
LESS THAN 0.5 IN. USE GROUND PLANE
PULSE
IN
V1**
2N3866
50Ω
0.01µF
0V
** (V + OVERDRIVE)/200
OS
–3V
50Ω
400Ω
750Ω
–5V
1394 F02
–5V
Figure 2. Response Time Test Circuit
circuit is the lack of feedthrough from the generator to the
comparator input. This prevents overshoot on the com-
parator input, which would give a false fast reading on
comparator response time.
ceramic is recommended, in parallel with a larger capaci-
tor such as a 4.7µF tantalum.
Poor trace routes and high source impedances are also
common sources of problems. Be sure to keep trace
lengthsasshortaspossible, andavoidrunninganyoutput
trace adjacent to an input trace to prevent unnecessary
coupling. If output traces are longer than a few inches, be
sure to terminate them with a resistor to eliminate any
reflections that may occur. Resistor values are typically
250Ω to 400Ω. Also, be sure to keep source impedances
as low as possible, preferably 1kΩ or less.
To adjust the circuit for exactly 5mV overdrive, V1 is
adjusted so that the LT1394 output under test settles to
1.4V (in the linear region). Then V1 is changed by –1V to
set overdrive to 5mV.
High Speed Design Techniques
AsubstantialamountofdesignefforthasmadetheLT1394
relatively easy to use. It is much less prone to oscillation
than some slower comparators, even with slow input
signals. However, as with any high speed comparator,
there are a number of pitfalls which may arise because of
PC board layout and design. The most common problems
involve power supply bypassing. Bypassing is necessary
to maintain low supply impedance. DC resistance and
inductanceinsupplywiresandPCtracescanquicklybuild
up to unacceptable levels. This allows the supply line to
move with changing internal current levels of the con-
nected devices. This will almost always result in improper
operation.Inaddition,adjacentdevicesconnectedthrough
anunbypassedsupplycaninteractwitheachotherthrough
the finite supply impedances. Bypass capacitors furnish a
simple solution to this problem by providing a local
reservoir of energy at the device, keeping supply imped-
ances low.
Crystal Oscillators
Figure 3’s circuits are crystal oscillators. In the circuit (a)
the resistors at the LT1394’s positive input set a DC bias
point. The2k-0.068µFpathsetsupphaseshiftedfeedback
and the circuit looks like a wideband unity-gain follower at
DC. The crystal’s path provides resonant positive feed-
back and stable oscillation occurs. The circuit (b) is
similar, but supports oscillation frequencies to 30MHz.
Above 10MHz, AT-cut crystals operate in overtone mode.
Because of this, oscillation can occur at multiples of the
desired frequency. The damper network rolls off gain at
high frequency, ensuring proper operation.
Switchable Output Crystal Oscillator
Figure 4 permits crystals to be electronically switched by
logic commands. This circuit is similar to the previous
examples, except that oscillation is only possible when
one of the logic inputs is biased high.
Bypass capacitors should be as close as possible to the
LT1394. A good high frequency capacitor such as a 0.1µF
8
LT1394
U
W U U
APPLICATIONS INFORMATION
5V
Temperature-Compensated Crystal Oscillator (TXCO)
1MHz TO 10MHz
CRYSTAL (AT-CUT)
2k
Figure 5 is a temperature-compensated crystal oscillator
(TXCO). This circuit reduces oscillator temperature drift
by inserting a temperature-dependent compensatory cor-
rection into the crystal’s frequency trimming network.
Thisopen-loopcorrectiontechniquereliesoncancellation
of the temperature characteristics of the oscillator, which
are quite repeatable.
+
OUTPUT
(a)
LT1394
2k
–
2k
0.068µF
The LT1394 and associated components form the crystal
oscillator, operating similarly to Figure 3’s examples. The
LM134, a temperature-dependent current source, biases
A1. A1 takes gain referred to the LM134’s output and the
negative offset supplied via the 470kΩ-LT1004 reference
path. Note that the LT1004’s negative voltage bias is
bootstrapped from the oscillator’s output, maintaining
single supply operation. This arrangement delivers tem-
perature-dependent bias to the varactor diode, causing a
scaled variation in the crystal’s resonance versus ambient
temperature. The varactor’s bias-dependent capacitance
shift pulls crystal frequency to complement the circuit’s
temperature drift. The simple first order fit provided by the
compensation is very effective. Figure 6 shows results.
The –70ppm frequency shift over 0°C to 70°C is corrected
within a few ppm. The “FREQ SET” trim also biases the
varactor, allowing accurate output frequency setting. It is
worth noting that better compensation is possible by
including higher order terms in the temperature-to-volt-
age conversion.
10MHz TO 25MHz
CRYSTAL (AT-CUT)
5V
2k
2k
22Ω
+
(b)
OUTPUT
LT1394
820pF
–
2k
200pF
1394 F03
Figure 3. Crystal Oscillators for Outputs to 30MHz. Circuit (b)’s
Damper Network Supresses Overtone Crystal’s Harmonic Modes
XTAL X
R
X
LOGIC INPUTS
AS MANY STAGES
AS DESIRED
XTAL B
XTAL A
D
X
1k
1k
B
5V
A
18ns, 500µV Sensitivity Comparator
1k
1k
D1
D2
The ultimate limitation on comparator sensitivity is avail-
able gain. Unfortunately, increasing gain invariably
involves giving up speed. The gain vs. speed trade-off in a
fast comparator is usually a practical compromise
designed to satisfy most applications. Some situations,
however, require more sensitivity (e.g., higher gain) with
minimal impact on speed. Figure 7’s circuit adds a differ-
ential preamplifier ahead of the LT1394, increasing gain.
This permits 500µV comparisons in 18ns. A parallel path
DC stabilization approach eliminates preamplifier drift as
an error source. A1 is the differential preamplifier, operat-
ingatagainof100. ItsoutputisAC-coupledtotheLT1394.
+
–
OUTPUT
LT1394
2k
75pF
= 1N4148
1394 F04
GROUND XTAL CASES
Figure 4. Switchable Output Crystal Oscillator. Biasing A or B
High Places Associated Crystal in Feedback Path. Additional
Crystal Branches Are Permissible
9
LT1394
U
W U U
APPLICATIONS INFORMATION
5.8M*
5V
1M*
1M*
–
+
LM134
2M
A1
LT1077
226Ω*
MV-209
VARACTOR
DIODE
1µF
10mV/°C
2M
10k*
470k*
0.01µF
10M
10MHz
2k
10MHz
0.05ppm/°C
5V
+
–
LT1394
0.01µF
BAT-85
390Ω
50k
100k
1M
2k
1µF
4.7k
LT1004-1.2
+
0.068µF
FREQ SET
1394 F05
XTAL AT-CUT, 35° 25′ ANGLE
* 1% FILM RESISTOR
Figure 5. Temperature-Compensated 10MHz Crystal Oscillator.
Temperature-Dependent Varactor Bias Reduces Drift by 20:1
5V
+
0
–10
A2
200pF
COMPENSATED
≈ 0.05ppm/°C
1/2 LT1126
2k
–
10k
–20
–30
–40
–50
–60
–70
200Ω
10k
UNCOMPENSATED
–
(VARACTOR CORRECTION
A3
DISABLED) –1ppm/°C
1/2 LT1126
+
40
TEMPERATURE (°C)
60
70
0
10
20
30
50
2k
–5V
200pF
5V
1394 F06
1k
1µF
+
–
+
+
–
Figure 6. Figure 5’s Compensated vs Uncompensated
Temperature Dependence. First Order Compensation
Reduces Oscillator Drift to 0.05ppm/°C
+INPUT
–INPUT
A1
LM733
OUTPUT
LT1394
A = 100
–
1µF
1k
–5V
1394 F07
Figure 7. Parallel Preamplified Paths Allow 18ns Comparator
Response to 500µV Overdrive
10
LT1394
U
W U U
APPLICATIONS INFORMATION
A1 has poorly defined DC characteristics, necessitating
some form of DC correction. A2 and A3, operating at a
differential gain of 100, provide this function. They differ-
entiallysenseabandlimitedversionofA1’sinputsandfeed
DC and low frequency amplified information to the com-
parator. The low frequency roll-off of A1’s signal path
complements A2-A3’s high frequency roll-off. The sum-
mation of these two signal channels at the LT1394 inputs
results in flat response from DC to high frequency.
correct, amplified composite signal at the LT1394’s posi-
tiveinputinTraceD. TheLT1394’soutputisTraceE. Figure
9 details circuit propagation delay. The output responds in
18ns to a 500µV overdrive on a 1mV step. Figure 10 plots
response time versus overdrive. As might be expected,
propagation delay decreases at higher overdrives. A1’s
noise limits usable sensitivity.
1100
1000
900
800
700
600
500
Figure 8 shows waveforms for the high gain comparator.
Trace A is a 500µV overdrive on a 1mV step applied to the
circuit’s positive input (negative input grounded). Trace B
shows the resulting amplified step at A1’s positive output.
Trace C is A2’s band limited output. A1’s wideband output
combines with A2’s DC corrected information to yield the
15
16
17
18
A = 1mV/DIV
RESPONSE TIME (ns)
1394 F10
B = 0.1V/DIV
(AC-COUPLED)
Figure 10. Response Time vs Overdrive for the
Composite Comparator
C = 0.1V/DIV
D = 0.1V/DIV
E = 5V/DIV
Voltage-Controlled Delay
The ability to set a precise, predictable delay has broad
application in pulse circuitry. Figure 11’s configuration
sets a 0 to 300ns delay from a corresponding 0V to 3V
control voltage. It takes advantage of the LT1394’s speed
and the clean dynamics of an emitter switched current
source.
5µs/DIV
1394 F08
Figure 8. 500µV Input (Trace A) Is Split into Wideband
and Low Frequency Gain Paths (Traces B and C) and
Recombined (Trace D). Comparator Output Is Trace E
Q1 and Q2 form a current source that charges the 1000pF
capacitor. When the trigger input is high (Trace A, Figure
12) both Q3 and Q4 are on. The current source is off and
Q2’s collector (Trace B) is at ground. The latch input at the
LT1394preventsitfromrespondinganditsoutputremains
high. When the trigger input goes low, the LT1394’s latch
input is disabled and its output drops low. Q4’s collector
(Trace C) lifts and Q2 comes on, delivering constant
current to the 1000pF capacitor (Trace B). The resulting
linear ramp at the LT1394’s positive input is compared to
the delay programming voltage input. When a crossing
occurs, the comparator goes high (Trace D). The length of
time the comparator was low is directly proportional to the
A = 1mV/DIV
B = 1V/DIV
10ns/DIV
1394 F09
Figure 9. Parallel Path Comparator Shows 18ns
Response (Trace B) to 500µV Overdrive (Trace A)
11
LT1394
APPLICATIONS INFORMATION
U
W U U
5V
DELAY PROGRAMMING
A = 5V/DIV
B = 2V/DIV
VOLTAGE INPUT
0V TO 3V = 0 TO 300ns DELAY
0.1µF
100Ω
100Ω
LT1634
1k
(DELAY
CALIB)
C = 5V/DIV
D = 5V/DIV
51pF
0.1µF
330Ω
330Ω
100ns/DIV
1394 F12
Q2 Q4
Q1
–
+
LT1394
Q OUTPUT
Q OUTPUT
Figure 12. Voltage-Controlled Delay’s Waveforms.
Programming Voltage Determines Delay Between Input
(Trace A) Falling Edge and Output (Trace D) Rising Edge.
High Linearity Timing Ramp (Trace B) Permits 1ns
Accuracy and 100ps Repeatability
1000pF
Q3
220Ω
TRIGGER INPUT
200ns MINIMUM
1394 F11
PNP = 2N5087
NPN = 2N2369
A = 2V/DIV
Figure 11. Fast, Precise, Voltage-Controlled Delay.
Emitter Switched Current Source Has Clean,
Predictable Dynamics
B = 0.1V/DIV
C = 2V/DIV
D = 2V/DIV
delay programming voltage. The fast switching and ramp
linearity permits 1ns accuracy and 100ps repeatability.
Figure 13, a high speed expansion of the current source
turn-on, details the clean switching. Q4 goes off within 2ns
of the trigger input (Trace A) dropping low, enabling the
current source (Q2’s emitter is Trace C). Concurrently, the
1000pF capacitor’s ramp (Trace B) begins. The LT1394’s
output (Trace D) drops low about 7ns later, returning high
after crossing (in this case) a relatively low programming
voltage. Figure 14 juxtaposes the waveforms differently,
permitting enhanced study of circuit timing. Switching
beginswiththeinputtriggerfallinglow(TraceA).Theramp
(Trace C) begins 3ns after the current source turns on (Q2
emitter is Trace D). The output pulse (Trace B) begins
about 4ns later.
10ns/DIV
1394 F13
Figure 13. High Speed Expansion of Figure 12. Ramp
(Trace B) Begins When Trigger (Trace A) Falls and
Current Source Turns On (Trace C). Trace D is Output
A = 1V/DIV
B = 1V/DIV
C = 0.1V/DIV
D = 1V/DIV
10ns/DIV
1394 F14
Figure 14. Delay’s Output Switching Begins with
Trigger Falling Low (Trace A). Ramp (Trace C) Starts
3ns After Current Source Turn-On (Trace D). Output
(Trace B) Begins 4ns Later
To calibrate this circuit apply a trigger input and 3V to the
programming input. Adjust the 100Ω trim for a 300ns
width at the LT1394’s output.
12
LT1394
U
W U U
APPLICATIONS INFORMATION
Fast, High Impedance, Variable Threshold Trigger
Q1 should contribute negligible timing error to minimize
overall delay. Figure 16’s photo verifies Q1’s wideband
operation. Trace B, Q1’s source, lags the input (Trace A) by
only 300ps. Input, FET buffer output and C1 output appear
as Traces A, B and C, respectively in Figure 17. As before,
the FET buffer is seen to contribute small timing error, and
C1’s output is about 8ns delayed from the input.
A frequent requirement in instrumentation is a fast trigger
with a variable threshold. Often, a high impedance input is
also required. Figure 15 meets these requirements. Com-
parator C1 is the basic trigger, with threshold voltage set at
its negative input. Source follower Q1 provides high
impedancewithabout2pFinputcapacitanceand50pAbias
current. Normally, Q1’s source bias point would be uncer-
tain and drifty, but stabilization techniques eliminate this
concern. A1 measures filtered versions of Q1’s gate and
source voltages. A1’s output biases Q2, forcing Q1’s
channel current to whatever value is required to equalize
A1’s inputs, and hence Q1’s gate and source voltages. A1’s
inputfilteringandroll-offarefarslowerthaninputfrequen-
cies of interest; its action does not interfere with the
circuit’s main signal path. The 330pF capacitor prevents
fast edges coupled through Q2’s collector base junction
from influencing A1’s operation.
A = 1V/DIV
B = 1V/DIV
200ps/DIV
1394 F16
Figure 16. Trigger Buffer’s 300ps Delay Minimizes
Timing Error. 4GHz Sampling Oscilloscope’s Output Is
a Series of Dots
V
TRIG
±3V
5V
–
+
C1
LT1394
Q1
2N5486
INPUT
±3V
OUTPUT
10M
10M
0.01µF
10k
C = 2V/DIV
–
+
1.5k
A1
LT1097
Q2
2N3904
A = 1V/DIV
B = 1V/DIV
330pF
100Ω
0.1µF
0.1µF
10ns/DIV
1394 F17
–5V
1394 F15
Figure 17. Input (Trace A), FET Source (Trace B)
and Output (Trace C) Waveforms for the Trigger.
Total Delay Is 8ns
Figure 15. Buffer Provides 2pF, 50pA Input Characteristics for
Fast Trigger. Amplifier-Stabilized Biasing Eliminates FET Offset
13
LT1394
U
W U U
APPLICATIONS INFORMATION
High Speed Adaptive Trigger Circuit
Figure19showsoperatingwaveformsat45MHz. TraceA’s
input produces Trace B’s amplified output at A1. The
comparator’s output is Trace C.
Line and fibre-optic receivers often require an adaptive
trigger to compensate for variations in signal amplitude
and DC offsets. The circuit in Figure 18 triggers on 2mV to
175mVsignalsfrom100Hzto45MHzwhileoperatingfrom
a single 5V rail. A1, operating at a gain of 15, provides
wideband AC gain. The output of this stage biases a 2-way
peak detector (Q1 through Q4). The maximum peak is
storedinQ2’semittercapacitor, whiletheminimumexcur-
sion is retained in Q4’s emitter capacitor. The DC value of
the midpoint of A1’s output signal appears at the junction
of the 500pF capacitor and the 3MΩ units. This point
always sits midway between the signal’s excursions,
egardless of absolute amplitude. This signal-adaptive volt-
age is buffered by A2 to set the trigger voltage at the
LT1394’s positive input. The LT1394’s negative input is
biased directly from A1’s output. The LT1394’s output, the
circuit’s output, is unaffected by >85:1 signal amplitude
variations. BandwidthlimitinginA1doesnotaffecttrigger-
ing because the adaptive trigger threshold varies
ratiometrically to maintain circuit output.
Split supply versions of this circuit can achieve band-
widths to 50MHz with wider input operating range.
A = 0.1V/DIV
B = 0.1V/DIV
C = 5V/DIV
50ns/DIV
AN72 F64
Figure 19. Adaptive Trigger Responding to a 40MHz,
5mV Input. Input Amplitude Variations from 2mV to
175mV Are Accommodated
5V
2k
6
4
3
2
1
5
Q1
Q2
5V
3M
5V
500pF
+
–
0.005µF
+
A1
LT1227
A2
LT1006
0.005µF
3M
Q1, Q2, Q3, Q4 = CA3096 ARRAY:
TIE SUBSTRATE (PIN 16) TO GROUND
–
13
15
10
11
= 1N4148
2k
750Ω
0.1µF
510Ω
12
14
Q4
5V
Q3
36Ω
470Ω
+
+
2k
0.1µF
10µF
100µF
+
TRIGGER
OUT
0.1µF
LT1394
470Ω
–
INPUT
1394 F18
Figure 18. 45MHz Single Supply Adaptive Trigger. Output Comparator’s
Threshold Varies Ratiometrically with Input Amplitude, Maintaining Data
Integrity over >85:1 Input Amplitude Range
14
LT1394
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.192 ± 0.004
(4.88 ± 0.10)
1
2
3
4
0.040 ± 0.006
(1.02 ± 0.15)
0.034 ± 0.004
(0.86 ± 0.102)
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.012
(0.30)
REF
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1197
0.0256
(0.65)
TYP
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT1394
U
TYPICAL APPLICATION
9
8
7
6
5
4
3
2
1
0
Voltage-Controlled Crystal Oscillator (VCXO)
14.3217MHz
Figure 20, a variant of the basic crystal oscillator, permits
voltage tuning the output frequency. Such voltage-con-
trolled crystal oscillators (VCXO) are often employed
where slight variation of a stable carrier is required. This
example is specifically intended to provide a 4× NTSC
sub-carrier tunable oscillator suitable for phase locking.
14.31818MHz
The LT1394 is set up as a crystal oscillator, operating
similarly to Figure 3 (a). The varactor diode is biased from
the tuning input. The tuning network is arranged so a 0V
to5Vdriveprovidesareasonablysymmetric,broadtuning
range around the 14.31818MHz center frequency. The
indicated selected capacitor sets tuning bandwidth. It
should be picked to complement loop response in phase
locking applications. Figure 21 is a plot of tuning input
voltageversusfrequencydeviation.Tuningdeviationfrom
the 4× NTSC 14.31818MHz center frequency exceeds
±240ppm for a 0V to 5V input.
14.314.0MHz
1
0
4
5
2
3
INPUT VOLTAGE (V)
1394 F21
Figure 21. Control Voltage vs Output Frequency for Figure 15.
Tuning Deviation from Center Frequency Exceeds ±240ppm
5V
47k*
1N4148
1M*
3.9k*
V
IN
0V TO 5V
C SELECT***
1M
1M
LT1004-2.5
1k*
0.047µF
†
MV-209
5V
1M
100pF
2k
390Ω
Y1**
15pF 100pF
+
LT1394
–
FREQUENCY
OUTPUT
* 1% FILM RESISTOR
2k
** NORTHERN ENGINEERING LABS C-2350N-14.31818MHz
*** C SELECT SETS TUNING BANDWIDTH. SET TO COMPLEMENT
200pF
LOOP RESPONSE IN PHASE LOCKING APPLICATIONS
†
VARACTOR DIODE
1394 F20
Figure 20. A 4× NTSC Sub-Carrier Voltage-Tunable Crystal Oscillator. Tuning Range
and Bandwidth Accommodate Variety of Phase Locked Loops
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1016
UltraFast Precision Comparator
12ns Single Supply Ground-Sensing Comparator
Fast Single Supply Comparator
UltraFast Dual Single Supply Comparator
Industry Standard 10ns Comparator
Single Supply Version of LT1016
60ns, 450µA Single Supply Comparator
Dual 4.5ns, 4mA Single Supply Comparator
LT1116
LT1671
LT1720
1394f LT/TP 0499 4K • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1998
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