LSISAS1068E_技术文档

LSISAS1068E PCI Express to 8-Port

Serial Attached SCSI Controller

Datasheet

Version 2.1

The LSISAS1068E is an eight-port, 3.0 Gbit/s SAS/SATA controller that

is compliant with the Fusion-MPT™ (Message Passing Technology)

architecture, provides an eight-lane PCI Express interface, and supports

Integrated RAID™ technology. The PCI Express software is backward

compatible with previous revisions of the PCI bus and PCI-X bus. The

LSISAS1068E supports the PCI Express Base Specification, Revision

1.0a, the SAS protocol as described in the Serial Attached SCSI

Standard, version 1.1, and the Serial ATA Specification, revision 2.5.

Figure 1 and Figure 2 provide examples of LSISAS1068E applications.

The point-to-point interconnect feature of the PCI Express bus limits the

electrical load on links, allowing increased transmission and reception

frequencies. The PCI Express transmission and reception data rates for

each full-duplex interconnect is 2.5 Gbits/s. The LSISAS1068E has eight

PCI Express phys, which provide host-side possible maximum transmission

and reception rates of 4.0 Gbytes/s. The LSISAS1068E supports x8, x4,

and x1 PCI Express link widths, and automatically downshifts if plugged

into either a x4 connector or into a x8 connector that is wired as a x4

connector. The serial PCI Express interconnect between devices lowers the

number of pins per device, which reduces both the PCI Express board

design costs and the overall board design complexity. The serial connection

also makes the PCI Express performance highly scalable.

Figure 1

LSISAS1068E Direct-Connect Example

PCI Express Interface

32-Bit Memory

Address/Data

Bus

8

Flash ROM/

PBSRAM/

NVSRAM

LSISAS1068E

PCI Express to SAS Controller

Serial

Interface

2

I C

SAS/SATA

Drives

SAS/SATA

Drives

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Version 2.1

October 2006

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Figure 2

LSISAS1068E Controller and LSISASx12 Expander Example

PCI Express Interface

8

32-Bit Memory

Address/Data

Flash ROM/

PBSRAM/

NVSRAM

Bus

LSISAS1068E

Serial

Interface

2

I C

SAS/SATA

Drives

LSISASx12

SAS/SATA

Drives

SAS/SATA

Drives

SAS/SATA

Drives

SAS/SATA

Drives

PCI Express implements a switch-based technology to interconnect a

large number of devices. Communication over the serial interconnect is

accomplished using packet-based communication protocol. Quality of

Service (QOS) features provide differentiated transmission performance

for different applications. Hot Plug/Hot Swap support enables “always-on”

systems. Enhanced error handling features, such as end-to-end CRC

(ECRC) and Advanced Error Reporting, make PCI Express suitable for

robust, high-end server applications. Hot Plug, power management, error

handling, and interrupt signaling are accomplished using packet-based

messaging rather than sideband signals. This keeps the device pin count

low and reduces the system cost.

Each of the eight SAS phys on the LSISAS1068E is capable of

SAS/SATA link rates of 3.0 Gbits/s and 1.5 Gbits/s. The user can

configure ports as wide or narrow. Narrow ports have one phy per port.

Wide ports have two, three, or four phys per port. Each port supports the

SSP, SMP, STP, and SATA protocols.

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The SAS interface uses the proven SCSI command set to ensure reliable

data transfers, while providing the connectivity and flexibility of

point-to-point serial data transfers. The SAS interface provides improved

performance, simplified cabling, smaller connectors, lower pin count, and

lower power requirements when compared to parallel SCSI. SAS

controllers leverage an electrical and physical connection interface that

is compatible with SATA technology.

The LSISAS1068E supports the Integrated RAID solution, which is a

highly integrated, low-cost RAID implementation. It is designed for

systems requiring redundancy and high availability, but not needing a full-

featured RAID implementation. Integrated RAID technology supports up

to two volumes and ten drives. Each volume can contain up to eight

drives. The Integrated RAID solution includes Integrated Mirroring™ (IM)

technology, Integrated Mirroring Enhanced (IME), and Integrated

Striping™ (IS) technology. IM technology provides physical mirroring of

two physical drives, plus a hot spare drive. IME supports three to eight

drives plus a hot spare drive. IM technology and IME require an

NVSRAM to support write journaling. IS technology enables data striping

across up to eight physical drives. The Integrated RAID solution is OS

independent, easy to install and configure, supports up to eight drives at

RAID Level 0, and does not require a special driver. The runtime

operation of the Integrated RAID solution is transparent to the operating

system. A single firmware build supports all Integrated RAID capabilities.

The LSISAS1068E uses the Fusion-MPT architecture, which features a

performance based message passing protocol that offloads the host

CPU by completely managing all I/Os and minimizes system bus

overhead by coalescing interrupts. The proven Fusion-MPT architecture

requires only thin, easy-to-develop device drivers that are independent of

the I/O bus. LSI Logic provides these device drivers.

To meet its flexibility and data transfer requirements, the LSISAS1068E

uses an ARM966 processor that operates at 225 MHz. LSI manufactures

the LSISAS1068E using Gflx™ technology.

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Features

This section lists the features of the LSISAS1068E.

SSP and SAS Features

This section describes the SSP and SAS features.

•

Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SAS data transfers

Provides a serial, point-to-point, enterprise-level storage interface

Supports wide transfers consisting of two, three, or four phys from a

single Quad Port

•

Supports narrow ports consisting of a single phy

Transfers data using SCSI information units

Is compatible with SATA target devices

SATA and STP Features

This section describes the SATA and STP features.

•

Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SATA data transfers

Each phy supports 3.0 Gbit/s and 1.5 Gbit/s STP data transfers

Allows addressing of multiple SATA targets through an expander

Allows multiple initiators to address a single target (in a fail-over

configuration) through an expander

PCI Express Features

The LSISAS1068E supports these PCI Express features.

•

Provides eight PCI Express phys

Supports a single-phy (1 lane) link transfer rate up to 2.5 Gbits/s in

each direction

•

Supports x8, x4, and x1 link widths

Automatically downshifts to a x4 link width if plugged into a x4

connector or into a x8 connector that is wired as a x4 connector

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LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

•

Provides a scalable interface

–

Single-lane aggregate bandwidth of up to 0.5 Gbytes/s

(500 Mbytes/s)

Quad-lane aggregate bandwidth of up to 2.0 Gbytes/s

(2000 Mbytes/s)

8-lane aggregate bandwidth of up to 4.0 Gbytes/s

(4000 Mbytes/s)

•

Offers a maximum payload of 2 Kbytes

Supports serial, point-to-point interconnections between devices

–

Reduces the electrical load of the connection

Enables higher transmission and reception frequencies

•

Supports lane reversal and polarity inversion

Supports PCI Express Hot Plug

Supports Power Management

–

Supports the PCI Power Management 1.2 specification

Supports Active State Power Management, including the L0, L0s,

and L1 states, by placing links in a power-savings mode during

times of no link activity

•

Uses a packetized and layered architecture

Achieves a high bandwidth per pin with low overhead and low latency

PCI Express is software compatible with PCI and PCI-X software

–

Leverages existing PCI device drivers

Supports the Memory, I/O, and Configuration address spaces

Supports memory read/write transactions, I/O read/write

transactions, and configuration read/write transactions

•

Provides 4 Kbytes of PCI Configuration address space per device

Supports posted and nonposted transactions

Provides quality of service (QOS) link configuration and

arbitration policies

•

Supports Traffic Class 0 and one virtual channel

Supports Message Signaled Interrupts (both MSI and MSI-X) as well

as INTx interrupt signaling for legacy PCI support

•

Supports end-to-end CRC (ECRC) and Advanced Error Reporting

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Integration

These features make the LSISAS1068E easy to integrate:

•

Leverages the proven Fusion-MPT technology

PCI Express device can use PCI-based device drivers, which

reduces integration challenges and risks

•

Provides unequaled performance through the Fusion-MPT

architecture

Reduces time to market with the Fusion-MPT architecture

–

Single driver binary for SAS/SATA, Ultra320 SCSI, and

Fibre Channel products

–

One firmware build supports all Integrated RAID capabilities

Thin, easy to develop drivers

Reduced integration and certification effort

Usability

These usability features are incorporated into the design:

•

Simplifies cabling with point-to-point, serial architecture

Provides drive spin-up sequencing control

Provides up to two LED signals for each SAS/SATA phy to indicate

drive activity and faults

•

Provides a serialized general purpose I/O (SGPIO) interface

Flexibility

These features increase the flexibility of the LSISAS1068E:

•

Supports an 8-bit flash ROM interface, an 8-bit nonvolatile RAM

(NVSRAM) interface, and a 32-bit pipelined synchronous burst

SRAM (PBSRAM) interface

•

Offers a flexible programming interface to tune I/O performance

Allows mixed connections to SAS or SATA targets

Allows a grouping of up to four phys from a Quad Port module into

a wide port

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LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

•

Leverages compatible connectors for SAS and SATA connections

Supports Integrated RAID technology, which provides for

Integrated Mirroring technology and/or Integrated Striping technology

•

Provides 17 LED signals

Provides four independent GPIO signals

Reliability

These features enhance the reliability of the LSISAS1068E:

®

•

Uses proven GigaBlaze transceivers on both the SAS/SATA phys

and the PCI Express phys

•

Isolates the power and ground of I/O pads and internal chip logic

Provides ESD protection

Provides latch-up protection

Has a high proportion of power and ground pins

Integrated Mirroring technology provides physical mirroring of the

boot volume

Testability

These features enhance the testability of the LSISAS1068E:

•

Offers JTAG boundary scan

®

Offers ARM Multi-ICE technology for debugging the ARM966

processor

Block Diagram Description

Figure 3 provides the block diagram for the LSISAS1068E. The following

subsections discuss the block diagram. There is a single Host Interface

module and two Quad Port modules. The Host Interface module supports

the 8-lane PCI Express interface. Each Quad Port module supports four

SAS phys.

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Figure 3

LSISAS1068E Block Diagram

Quad Port 0 Module

Queue

Manager

AHB Bridge

SATA Engine

Host Interface Module

AHB Interface

SECONDARY

PCI

TimerConfig

PCI Express

PCI

Express

Interface

AHB Interface

CONTEXT

DMA Arbiter

Transport Modules

Quad Port

DMA Arbiter

System Interface

Port Layer Connection

Manager and Switch

ICE I/F

SAS Link SAS Link SAS Link SAS Link

SAS Phy SAS Phy SAS Phy SAS Phy

IOP

(ARM966)

Processor

AHB Arbiter

IRQ Controller

GPIO/LED

SIO A

TimerConfig

Quad Port 1 Module

Queue

AHB Bridge

SATA Engine

Manager

SIO A

SIO B

UART

AHB Interface

SECONDARY

UART

AHB Interface

CONTEXT

Context RAM

XMEM Bus

Transport Module

External

Memory

Quad Port

DMA Arbiter

2

I C

2

I C

Port Layer Connection

Manager and Switch

SAS Link SAS Link SAS Link SAS Link

SAS Phy SAS Phy SAS Phy SAS Phy

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Host Interface Module

The LSISAS1068E interfaces with the host through the host interface

module. The host interface module contains the PCI Express interface,

system interface, IOP (ARM966) processor, timer and configuration,

DMA arbiter, PCI timer and configuration, SIO A, SIO B, UART, external

2

memory, I C, and UART blocks.

PCI Express Interface

The PCI Express interface block supports an 8-lane PCI Express

interface. This is a high bandwidth, serial interface that features

point-to-point interconnects between devices and an advanced packetized

and layered protocol architecture. The PCI Express software is backward

compatible with previous implementations of the PCI specification.

System Interface

In combination with the IOP, the system interface supports the Fusion-MPT

architecture. The system interface efficiently passes messages between

the LSISAS1068E and the host interface using a high-performance,

packetized mailbox architecture. The LSISAS1068E system interface takes

advantage of PCI Express point-to-point connections, thereby allowing a

dedicated connection to each device with no sharing.

IOP (ARM966) Processor

The LSISAS1068E I/O processor (IOP) controls the system interface and

manages the host side of the Fusion-MPT architecture without host

processor intervention, which frees the host processor for other tasks.

Timer and Configuration

This block supports the LSISAS1068E LED and GPIO interfaces. There

are 17 LED signals. The GPIO interface contains four independent GPIO

signals. This block also supports internal timing adjustments and

power-on sense configuration options.

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DMA Arbiter

The LSISAS1068E provides the ability to transfer system memory blocks

to and from local memory through the descriptor-based DMA arbiter and

router. The DMA channel includes a system DMA FIFO and the internal

bus interface logic.

PCI Timer and Configuration

This PCI timer and configuration module supports the PCI configuration

register space and a power-on reset (POR).

SIO A and SIO B

The LSISAS1068E provides two SGPIO interfaces that are compliant

with the SFF-8485 specification. A typical use of the serial I/O (SIO)

modules is to control LEDs. The SIO A signals are associated with

Quad Port Module 0. The SIO B signals are associated with Quad Port

Module 1. The SIO modules are SFF-8485 compliant.

External Memory

The external memory controller block provides an interface for flash ROM,

NVSRAM, and PBSRAM devices. The external memory bus provides a

32-bit memory bus, parity checking, and chip select signals for PBSRAM,

NVSRAM, and flash ROM. The flash ROM and NVSRAM are capable of

8-bit accesses, while the PBSRAM is capable of 32-bit accesses.

Most configurations use a flash ROM to store firmware, configuration

information, and persistent data information. The LSISAS1068E uses a

PBSRAM to support super large drive count (SLDC) applications, or to

support firmware download boot procedures. In SLDC applications, each

LSISAS1068E controller can support up to 1023 drives.

2

I C

2

The LSISAS1068E contains an Inter-IC (I C) block that communicates

2

with peripherals. The I C block operates as either a master or a slave on

2

the bus and sustains data rates up to 400 Kbits/s. The I C block

accomplishes byte-wise bidirectional data transfers by using either an

2

interrupt or a polling handshake at the completion of each byte. The I C

block controls all bus timing and performs bus-specific sequences.

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LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

UART

The UART provides test and debug access to the LSISAS1068E.

Quad Port Modules

The Quad Port modules in the LSISAS1068E implement the SSP, SMP, and

STP/SATA protocols, and manage the SAS/SATA phys. There are two Quad

Port modules in the LSISAS1068E. Each Quad Port module supports four

phys. The following subsections describe the Quad Port modules.

Transport Modules

Queue Manager

SATA Engine

The transport modules transmit frames to and from the port layer and

implement the STP, SSP, and SMP protocols. Each Quad Port module has

four instances of the transport module, one for each SAS/SATA phy on the

LSISAS1068E. The transport modules also manage DMA transfers.

The queue manager is responsible for managing various queue

structures that support the SSP, SMP, and SATA/STP protocols. The

queue structures are the primary means for the IOP to initiate I/Os to the

hardware, and for the hardware to notify the IOP of I/O status.

The SATA engine provides information to the transport modules to enable

handling of SATA commands. The SATA engine tracks queued commands

per device and provides these tags to the SATA transport layer blocks.

Port Layer Connection Manager and Switch

The port layer connection manager and switch handles transmission

requests from the transport modules and originates connection requests

to the SAS links. It is also responsible for handling SAS wide port

configurations.

SAS Link

The SAS link layer manages SAS connections between initiator and

target ports, data clocking, and CRC checking on transmitted data. The

SAS link is also responsible for starting a link reset sequence.

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SAS Phys

The SAS phys interface to the physical layer, perform serial-to-parallel

conversion of received data and parallel-to-serial conversion of transmit

data, manage phy reset sequences, and perform 8b/10b encoding.

Quad Port DMA Arbiter

Each quad port module contains a quad port arbiter that interfaces with

the host interface DMA arbiter and determines bus priority between the

four phys in the quad port for DMA transfers.

Context RAM

The context RAM is a memory that is shared between the host interface

module and the quad port modules. The context RAM holds a portion of

the firmware.

Signal Descriptions

The following subsections provide the signal descriptions for the

LSISAS1068E. A “/” following the signal indicates an active LOW signal.

PCI Express Signals

This section describes the PCI Express signals. Refer to the PCI Express

specification for detailed signal descriptions.

PCI Express System Signals

This section describes the PCI Express system signals.

P_REFCLK_P PCI Express Differential Clock

Input

This signal provides half of the PCI Express differential

clock input signal.

P_REFCLK_N PCI Express Differential Clock

This signal provides half of the PCI Express differential

clock input signal.

RST/

Reset

Asserting the RST/ signal causes a reset.

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PCI Express Data Signals

This section describes the PCI Express transmit and receive signals.

P_RX[7:0]+

PCI Express Receive Differential Data

Input

P_RX[x]+ provides the positive differential data receiver

for PCI Express phy[x].

P_RX[7:0]−

P_TX[7:0]+

P_TX[7:0]−

PCI Express Receive Differential Data

P_RX[x]− provides the negative differential data receiver

for PCI Express phy[x].

Input

PCI Express Transmit Differential Data

P_TX[x]+ provides the positive differential data

transmitter for PCI Express phy[x].

Output

PCI Express Transmit Differential Data

P_TX[x]− provides the negative differential data

transmitter for PCI Express phy[x].

SAS Signals

This section describes the SAS interface signals.

REFCLK_P, REFCLK_N

Input

These pins provide the serial differential clock. Connect a

75 MHz oscillator with an accuracy of at least 50 ppm to

these pins. To use a single-ended crystal, tie the crystal to

REFCLK_P and tie REFCLK_N to a resistor termination.

RTRIM

Resistor Reference

Analog

This pin provides the analog resistor reference for the

GigaBlaze transceivers. The resistor provides a reference

to calibrate the 50 Ω termination.

RX[7:0]−

RX[7:0]+

TX[7:0]−

Receive Negative Differential Data

RX[x]− provides the negative differential data receiver for

SAS/SATA phy[x].

Input

Receive Positive Differential Data

RX[x]+ provides the positive differential data receiver for

SAS/SATA phy[x].

Input

Transmit Negative Differential Data

TX[x]− provides the negative differential data transmit

Output

signal for SAS/SATA phy[x].

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TX[7:0]+

Transmit Positive Differential Data

Output

TX[x]+ provides the positive differential data transmit

signal for SAS/SATA phy[x].

2

I C and UART Signals

2

This section describes the I C and UART signals.

2

ISTWI_CLK

I C Clock

Input/Output

2

This signal provides the I C clock signal.

2

ISTWI_DATA I C Data

Input/Output

Input

2

This signal provides the I C data signal.

UART_RX

UART_TX

UART Receive

This signal provides the UART receive signal.

UART Transmit

Output

This signal provides the UART transmit signal.

Memory Interface Signals

This section describes the memory interface signals.

MCLK

Memory Clock

Output

All synchronous RAM control/data signals reference the

rising edge of this clock.

ADSC/

ADV/

Address-Strobe-Controller

Asserting this active LOW signal initiates read, write, or

chip deselect cycles.

Output

Advance

Output

Asserting this active LOW signal increments the burst

address counter of the selected synchronous SRAM.

MAD[31:0]

Multiplexed Address/Data

Input/Output

These signals provide the address and data bus for the

PBSRAM, flash ROM, and NVSRAM. These signals also

provide Power-On Sense configuration functions to the

LSISAS1068E. These signals are internally pulled LOW.

MADP[3:0]

Memory Parity

Input/Output

These signals provide parity checking for MAD[31:0].

These signals are internally pulled HIGH.

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MOE[1:0]/

Memory Output Enables

Output

Asserting these active LOW signals enable the selected

PBSRAM, flash ROM, or NVSRAM device to drive data.

MOE1/ enables PBSRAM and flash ROM devices.

MOE0/ enables NVSRAM devices. MOE[1:0]/ allow

interleaved PBSRAM configurations.

MWE[1:0]/

BWE[3:0]/

Memory Write Enables

The LSISAS1068E uses these active LOW bank write

signals for interleaved PBSRAM configurations.

Output

Memory Byte Write Enables

Output

Asserting these active LOW, byte-lane write signals

enable partial word writes to the PBSRAM. BWE[3]/

and BWE[2]/ enable partial word writes to the flash ROM

and the NVSRAM if FLASH_CS/ or NVSRAM_CS/

is asserted.

NVSRAM_CS/

PBSRAM_CS/

NVSRAM Chip Select

Asserting this active LOW signal selects the NVSRAM

device.

Output

RAM Chip Select

Output

Asserting this active LOW signal selects the PBSRAM

devices. The LSISAS1068E uses the PBSRAM to sup-

port firmware download boot and SLDC applications.

FLASH_CS/ Flash Chip Select

Output

Asserting this active LOW signal selects the flash ROM.

The LSISAS1068E maps flash ROM address space into

system memory space.

SIO Signals

This section describes the SIO A and SIO B signals. SIO A is associated

with Quad Port 0. SIO B is associated with Quad Port 1.

SIO_CLK_A SIO Clock

Input/Output

This signal provides the clock signal for SIO A.

SIO_CLK_B SIO Clock

Input/Output

This signal provides the clock signal for SIO B.

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SIO_DIN_A

SIO_DIN_B

SIO Data In A

This signal provides the data input signal to the SIO

interface for Quad Port 0.

Input

SIO Data In B

Input

This signal provides the data input signal to the SIO

interface for Quad Port 1.

SIO_DOUT_A SIO Data Out A

Output

This signal provides the data output signal to the SIO bus

from Quad Port 0. This signal controls the Quad Port 0

LED drives.

SIO_DOUT_B SIO Data Out B

Output

This signal provides the data output signal to the SIO bus

from Quad Port 1. This signal controls the Quad Port 1

LED drives.

SIO_END_A SIO End Control

Input/Output

The SIO module drives this output to end control of the

SIO bus.

SIO_END_B SIO End Control

Input/Output

The SIO module drives this output to end control of the

SIO bus.

Configuration and General Purpose Signals

This section describes the configuration and general purpose pins.

TST_RST/

Test Reset

Input

Asserting this signal forces the chip into a Power-On-Reset

(POR) state. This signal has an internal pull-up. The

LSISAS1068E does not have an internal POR.

REFCLK_B

MODE[7:0]

ARM Reference Clock

This pin provides the ARM reference clock.

Input

Mode Select

Input

This 8-bit bus defines operational and test modes for the

chip. These pins have internal pull-downs.

FAULT_LED[7:0]/

Fault LED

Input/Output

These output signals indicate a SAS link fault.

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ACTIVE_LED[7:0]/

Activity LED

These output signals indicate SAS link activity.

Input/Output

GPIO[3:0]

General Purpose I/O

Input/Output

These signals provide general purpose input/output

signals. These signals have internal pull-ups.

HB_LED/

Heartbeat LED

Output

Firmware intermittently asserts this signal to indicate that

the IOP is operational.

JTAG and Test Signals

This section describes the JTAG and test signals.

FSELA

Clock Select

Input

This is a test signal. Pull this signal LOW.

SCAN_ENABLE

Scan Enable

Input

Output

Input

Output

Input

Output

Input

SCAN_MODE Scan Mode

TCK

JTAG Debug Clock

TRST/

JTAG Debug Reset

TDI

JTAG Debug Test Data In

JTAG Debug Test Data Out

JTAG Debug Test Mode Select

Multi-ICE Debug Clock

TDO

TMS

TCK_ICE

RTCK_ICE

TRST_ICE/

TDI_ICE

TDO_ICE

TMS_ICE

IDDT

Multi-ICE Debug Return Clock

Multi-ICE Debug Reset

Multi-ICE Debug Test Data In

Multi-ICE Debug Test Data Out

Multi-ICE Debug Test Mode Select

IDDQ Test Mode Enable

This signal is active HIGH.

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TN/

3-State Output Enable Control

Input

This signal is active LOW.

PROCMON

TDIODE_P

Process Monitor Test Output Driver

Output

Input

Anode Connection of the Thermal Diode

TDIODE_VSS Cathode Connection of the Thermal Diode

Output

Power and Ground Signals

This section describes the power and ground signals.

REFPLL_VDD

Power

Ground

Power

These signals provide 1.2 V power.

REFPLL_VSS

These signals provide ground.

VDD2

These signals provide 1.2 V core power.

VDDIO33

Power

These signals provide 3.3 V I/O power.

VSS

Ground

These signals provide ground.

RX_VSS[7:0], RXB_VSS[7:0], TX_VSS[7:0], TXB_VSS[7:0] Ground

These signals provide ground for the SAS GigaBlaze core.

RX_VDD[7:0], RXB_VDD[7:0], TX_VDD[7:0], TXB_VDD[7:0]

These signals provide 1.2 V power for the SAS

GigaBlaze core.

Power

P_RX_VDD[7:0], P_RXB_VDD[7:0], P_TX_VDD[7:0],

P_TXB_VDD[7:0]

Power

These signals provide 1.2 V power for the PCI Express

GigaBlaze core.

P_RX_VSS[7:0], P_RXB_VSS[7:0], P_TX_VSS[7:0],

P_TXB_VSS[7:0]

Ground

These signals provide ground for the PCI Express

GigaBlaze core.

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Pin Listing

Table 1 provides the signal listing by signal name. Table 2 provides the

signal listing by pin name. Figure 4 provides a BGA pinout diagram.

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1

Table 1

Signal

LSISAS1068E Pin Assignments Listed by Signal Name

Signal

ACTIVE_LED[0] /H1

ACTIVE_LED[1]/ H2

ACTIVE_LED[2]/ G1

ACTIVE_LED[3]/ H3

ACTIVE_LED[4]/ K4

ACTIVE_LED[5]/ K3

ACTIVE_LED[6]/ K2

ACTIVE_LED[7]/ M4

MOE1/

MWE0/

MWE1/

N/C

N24

T23

P24

B14

C24

C25

D3

N/C

Y22

P_TX_VSS4

P_TX_VSS5

P_TX_VSS6

P_TX_VSS7

P_TX0-

AB14

AC16

Y18

AB19

AE2

AF2

AE5

AE4

AF5

AF6

AE9

AF9

AF15

AF16

AF18

AE18

AF21

AF22

AE23

AE22

Y7

AD8

AB10

AA12

AF14

AA16

AB18

AA20

AC4

AB8

AA10

AC11

AA14

AB16

AE19

AB20

R21

AA4

B13

D12

C13

D13

A13

H24

K22

P3

RX5+

B8

N/C

AA1

RX6-

B7

N/C

AA5

AA6

RX6+

B6

N/C

RX7-

C3

N/C

AB13

AB26

AC12

AC13

AC24

AD1

RX7+

B3

N/C

P_TX0+

RXB_VDD0

RXB_VDD1

RXB_VDD2

RXB_VDD3

RXB_VDD4

RXB_VDD5

RXB_VDD6

RXB_VDD7

RXB_VSS0

RXB_VSS1

RXB_VSS2

RXB_VSS3

RXB_VSS4

RXB_VSS5

RXB_VSS6

RXB_VSS7

C23

C19

F17

E15

A12

C10

E9

N/C

P_TX1-

D23

E1

N/C

P_TX1+

ADSC/

ADV/

V22

V23

T21

U24

R23

W25

N/C

P_TX2-

E3

E

N/C

P_TX2+

BWE[0]/

BWE[1]/

BWE[2]/

BWE[3]/

13

N/C

AD3

AD13

AE3

AE13

AF13

N26

P_TX3-

E22

E23

E24

F1

N/C

P_TX3+

N/C

P_TX4-

G8

N/C

P_TX4+

F21

F19

E17

G16

F13

F11

G10

C7

FAULT_LED[0]/ N1

FAULT_LED[1]/ N3

FAULT_LED[2]/ M1

FAULT_LED[3]/ L1

FAULT_LED[4]/ N4

FAULT_LED[5]/ N2

FAULT_LED[6]/ P1

FAULT_LED[7]/ N5

N/C

P_TX5-

F6

NVSRAM_CS/

P_REFCLK_N

P_REFCLK_P

P_RX_VDD0

P_RX_VDD1

P_RX_VDD

P_RX_VDD3

P_RX_VDD4

P_RX_VDD5

P_RX_VDD6

P_RX_VDD7

P_RX_VSS0

P_RX_VSS1

P_RX_VSS2

P_RX_VSS3

P_RX_VSS4

P_RX_VSS5

P_RX_VSS6

P_RX_VSS7

P_RX0-

P_TX5+

F22

F23

G20

G21

H5

AD14

AE14

AB6

P_TX6-

P_TX6+

P_TX7-

AC7

P_TX7+

2

AC9

P_TXB_VDD0

P_TXB_VDD1

P_TXB_VDD2

P_TXB_VDD3

P_TXB_VDD4

P_TXB_VDD5

P_TXB_VDD6

P_TXB_VDD7

P_TXB_VSS0

P_TXB_VSS1

P_TXB_VSS2

P_TXB_VSS3

P_TXB_VSS4

P_TXB_VSS5

P_TXB_VSS6

P_TXB_VSS7

PBSRAM_CS/

PROCMON

REFCLK_B

REFCLK_N

REFCLK_P

REFPLL_VDD

REFPLL_VSS

RESERVED

RST/

H6

AE10

AC15

AD18

AC19

AB21

AB7

SCAN_ENABLE E4

FSELA

E2

H21

H23

H25

J1

SCAN_MODE

SIO_CLK_A

SIO_CLK_B

SIO_DIN_A

SIO_DIN_B

SIO_DOUT_A

SIO_DOUT_B

SIO_END_A

SIO_END_B

TCK

F5

FLASH_CS/

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

HB_LED/

IDDT

P25

V4

H22

G22

J21

G23

D25

D24

E25

D26

AB2

U3

Y1

W3

J2

AB1

P4

J3

AA9

AD9

J4

AB4

G26

K21

J26

J5

AB12

AA15

AC17

AA18

AC22

AF4

ISTWI_CLK

ISTWI_DATA

MAD[0]

J22

K1

K5

TCK_ICE

TDI

MAD[1]

H26

K24

J24

K6

AC1

T5

MAD[2]

L4

TDI_ICE

TDIODE_P

TDIODE_VSS

TDO

MAD[3]

L5

P_RX0+

AF3

V26

T22

AC2

V3

MAD[4]

J23

L6

P_RX1-

AE7

MAD[5]

M26

M23

J25

L22

M5

M6

M21

M22

N6

P_RX1+

AE6

MAD[6]

P_RX2-

AF8

TDO_ICE

TMS

MAD[7]

P_RX2+

AE8

AC3

U4

MAD[8]

K25

L26

L23

K23

K26

N23

R26

P23

V21

Y26

W24

U21

AA26

W23

AA23

Y23

AB25

AB23

AB24

Y21

AC25

AC26

AB22

AD25

L21

U26

W26

AA22

U23

J6

P_RX3-

AF11

AF10

AE17

AF17

AF20

AF19

AE21

AE20

AE25

AE24

Y8

TMS_ICE

TN/

MAD[9]

P_RX3+

AD2

Y4

MAD[10]

MAD[11]

MAD[12]

MAD[13]

MAD[14]

MAD[15]

MAD[16]

MAD[17]

MAD[18]

MAD[19]

MAD[20]

MAD[21]

MAD[22]

MAD[23]

MAD[24]

MAD[25]

MAD[26]

MAD[27]

MAD[28]

MAD[29]

MAD[30]

MAD[31]

MADP[0]

MADP[1]

MADP[2]

MADP[3]

MCLK

P_RX4-

TRST/

N21

N22

N25

P2

P_RX4+

TRST_ICE/

TST_RST/

TX_VDD0

TX_VDD1

TX_VDD2

TX_VDD3

TX_VDD4

TX_VDD5

TX_VDD6

TX_VDD7

TX_VSS0

TX_VSS1

TX_VSS2

TX_VSS3

TX_VSS4

TX_VSS5

TX_VSS6

TX_VSS7

TX0-

W1

C2

P_RX5-

P_RX5+

A23

D18

C17

D14

D10

D8

P_RX6-

P5

T1

AB3

T4

P6

P_RX6+

P21

P22

P26

R1

P_RX7-

P_RX7+

RTCK_ICE

RTRIM

P_RXB_VDD0

P_RXB_VDD1

P_RXB_VDD2

P_RXB_VDD3

P_RXB_VDD4

P_RXB_VDD5

P_RXB_VDD6

P_RXB_VDD7

P_RXB_VSS0

P_RXB_VSS1

P_RXB_VSS2

P_RXB_VSS3

P_RXB_VSS4

P_RXB_VSS5

P_RXB_VSS6

P_RXB_VSS7

P_TX_VDD0

P_TX_VDD1

P_TX_VDD2

P_TX_VDD3

P_TX_VDD4

P_TX_VDD5

P_TX_VDD6

P_TX_VDD7

P_TX_VSS0

P_TX_VSS1

P_TX_VSS2

P_TX_VSS3

C14

E21

D19

C18

D15

B10

D9

AB9

RX_VDD0

RX_VDD1

RX_VDD2

RX_VDD3

RX_VDD4

RX_VDD5

RX_VDD6

RX_VDD7

RX_VSS0

RX_VSS1

RX_VSS2

RX_VSS3

RX_VSS4

RX_VSS5

RX_VSS6

RX_VSS7

RX0-

C4

E5

R4

AD10

AF12

AB15

AA17

AD19

AD23

AD7

R5

E19

G18

D16

E14

E11

A7

R6

R22

T6

T26

U1

D7

E6

U2

Y10

D22

F18

F8

F7

U5

AA11

AA13

Y16

U6

D17

F15

B23

B22

A21

A22

A18

B18

A15

A16

B9

U22

V1

TX0+

AB17

AA19

AA21

AB5

AD4

AC8

E12

C9

TX1-

V2

TX1+

V5

F9

E7

TX2-

V6

TX2+

V24

V25

W2

W4

W5

W6

W7

W21

W22

Y5

B25

B24

B21

B20

A20

A19

B17

A17

A11

A10

A8

TX3-

RX0+

TX3+

MODE[0]

MODE[1]

MODE[2]

MODE[3]

MODE[4]

MODE[5]

MODE[6]

MODE[7]

MOE0/

AC10

AC14

AD17

AC18

AF23

AA7

RX1-

TX4-

H4

RX1+

TX4+

A9

D1

RX2-

TX5-

A5

G4

RX2+

TX5+

A6

G5

RX3-

TX6-

B5

D2

RX3+

TX6+

B4

F4

AA8

RX4-

TX7-

A3

G6

AF7

RX4+

TX7+

A4

U25

Y6

AB11

RX5-

TXB_VDD0

F20

1. N/C pins are not connected.

20 of 30

DB08-000274-03

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

1

Table 1

Signal

LSISAS1068E Pin Assignments Listed by Signal Name (Cont.)

Signal

TXB_VDD1

TXB_VDD2

TXB_VDD3

TXB_VDD4

TXB_VDD5

TXB_VDD6

TXB_VDD7

TXB_VSS0

TXB_VSS1

TXB_VSS2

TXB_VSS3

TXB_VSS4

TXB_VSS5

TXB_VSS6

TXB_VSS7

UART_RX

UART_TX

VDD2

E18

F16

A14

F12

E10

C8

VDDIO33

A24

B2

B11

B12

B15

B16

C1

C5

C6

C20

C21

C26

F2

F25

G2

G9

VDDIO33

VSS

T25

U7

VSS

H9

VSS

R11

R13

R15

R17

R19

R24

T3

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

J8

U20

V7

V20

W20

Y2

G7

T8

E20

B19

E16

F14

D11

F10

E8

Y9

T10

Y11

Y12

Y13

Y14

Y15

Y17

Y19

Y20

Y25

AA2

AA25

AC23

AD5

AD6

AD20

AD21

AD24

AD26

AE11

AE12

AE15

AE16

AF24

A2

T12

T14

T16

T19

J19

K8

T24

U8

D4

K10

K12

K14

K16

K19

L3

U11

U13

U15

U17

U19

V8

E26

F26

K11

K13

K15

K17

L10

L12

L14

L16

M11

M13

M15

M17

N10

N12

N14

N16

P11

P13

P15

P17

R10

R12

R14

R16

T11

T13

T15

T17

U10

U12

U14

U16

G11

G12

G13

G14

G15

G17

G19

G25

H7

VDD2

L8

V19

W8

W9

VDD2

L11

L13

L15

L17

L19

L24

M3

VDD2

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

Y3

Y24

AA3

AA24

AC5

AC6

AC20

AC21

AD11

AD12

AD15

AD16

AD22

AE1

AE26

AF25

VDD2

H20

J7

VDD2

J20

K7

VDD2

M8

VDD2

K20

L2

M10

M12

M14

M16

M19

M24

N8

VDD2

L7

VDD2

L20

L25

M2

VSS

A25

B1

VDD2

VSS

VDD2

VSS

B26

C11

C12

C15

C16

C22

D5

VDD2

M7

VSS

VDD2

M20

M25

N7

VSS

N11

N13

N15

N17

N19

P8

VDD2

VSS

VDD2

VSS

VDD2

N20

P7

VSS

VDD2

VSS

VDD2

P20

R2

VSS

D6

VDD2

VSS

D20

D21

F3

P10

P12

P14

P16

P19

R3

VDD2

R7

VSS

VDD2

R20

R25

T2

VSS

VDD2

VSS

F24

G3

G24

H8

VDD2

VSS

VDD2

T7

T20

VSS

VDD2

VSS

R8

1. N/C pins are not connected.

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller 21 of 30

DB08-000274-03

1

Table 2

LSISAS1068E Pin Assignments Listed by Pin Number

Signal

A2

VSS

D3

N/C

G3

VSS

K14

K15

K16

K17

K19

K20

K21

K22

K23

K24

K25

K26

L1

VSS

VDD2

N21

N22

N23

N24

N25

N26

P1

N/C

A3

TX7-

TX7+

D4

TXB_VSS7

VSS

G4

MODE[3]

MODE[4]

MODE[7]

TXB_VDD7

RXB_VDD7

VDDIO33

RXB_VSS6

VDDIO33

RXB_VSS3

VDDIO33

TX_VSS1

VDDIO33

N/C

MAD[13]

MOE1/

N/C

A4

D5

G5

VSS

A5

TX5-

TX5+

D6

VSS

G6

VDD2

VSS

A6

D7

RX_VDD6

TX_VDD5

RX_VDD5

TX_VDD4

TXB_VSS4

REFCLK_N

REFPLL_VDD

TX_VDD3

RX_VDD3

TX_VSS2

RX_VSS2

TX_VDD1

RX_VDD1

VSS

G7

A7

TX_VSS5

RX5-

D8

G8

VDDIO33

ISTWI_DATA

RESERVED

MAD[11]

MAD[2]

MAD[8]

MAD[12]

FAULT_LED[3]/

VDDIO33

VSS

NVSRAM_CS/

FAULT_LED[6]/

N/C

A8

D9

G9

A9

TX4+

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

H1

P2

A10

A11

A12

RX4+

P3

RESERVED

HB_LED/

RESERVED

N/C

RX4-

P4

RXB_VDD4

P5

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

B1

REFPLL_VSS

TXB_VDD3

TX3-

P6

P7

VDDIO33

VSS

L2

P8

TX3+

L3

P10

P11

P12

P13

P14

P15

P16

P17

P19

P20

P21

P22

P23

P24

P25

P26

R1

VSS

RX3+

L4

N/C

VDD2

TX2-

L5

N/C

VSS

RX2+

L6

N/C

VDD2

RX2-

VSS

RX_VSS0

N/C

L7

VDDIO33

VSS

TX1-

SIO_CLK_B

SIO_DIN_B

VSS

L8

VDD2

TX1+

L10

L11

L12

L13

L14

L15

L16

L17

L19

L20

L21

L22

L23

L24

L25

L26

M1

VDD2

VSS

TX_VDD0

VDDIO33

VSS

SIO_DOUT_B

SIO_DOUT_A

SIO_END_B

N/C

VSS

VDD2

VDDIO33

ISTWI_CLK

ACTIVE_LED[0]/

ACTIVE_LED[1]/

ACTIVE_LED[3]/

MODE[1]

N/C

VDD2

VSS

VDDIO33

N/C

VSS

VDD2

B2

VDDIO33

RX7+

E2

FSELA

N/C

H2

VSS

N/C

B3

E3

H3

VDD2

MAD[15]

MWE1/

FLASH_CS/

N/C

B4

TX6+

E4

SCAN_ENABLE

TX_VDD7

RX_VDD7

RX_VSS7

TXB_VSS6

RXB_VDD6

TXB_VDD5

TX_VSS4

RX_VSS4

N/C

H4

VSS

B5

TX6-

E5

H5

VSS

B6

RX6+

E6

H6

N/C

VDDIO33

MADP[0]

N/C

B7

RX6-

E7

H7

VDDIO33

VSS

N/C

B8

RX5+

E8

H8

R2

VDDIO33

VSS

B9

TX4-

E9

H9

VSS

MAD[10]

VSS

R3

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

C1

RX_VDD4

VDDIO33

REFCLK_B

N/C

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

J1

VSS

R4

N/C

VSS

VDDIO33

MAD[9]

FAULT_LED[2]/

VDDIO33

VSS

R5

N/C

VSS

R6

N/C

VSS

R7

VDDIO33

VSS

TX_VSS3

RXB_VDD3

TXB_VSS2

RXB_VSS2

TXB_VDD1

TX_VSS0

TXB_VSS0

RX_VDD0

N/C

SIO_END_A

UART_RX

N/C

VSS

M2

R8

VDDIO33

RX3-

VSS

M3

R10

R11

R12

R13

R14

R15

R16

R17

R19

R20

R21

R22

R23

R24

R25

R26

T1

VDD2

VSS

M4

ACTIVE_LED[7]/

N/C

VSS

M5

VDD2

TX2+

VSS

M6

N/C

VSS

TXB_VSS1

RX1+

VSS

M7

VDDIO33

VSS

VDD2

VDDIO33

N/C

M8

VSS

RX1-

M10

M11

M12

M13

M14

M15

M16

M17

M19

M20

M21

M22

M23

M24

M25

M26

N1

VSS

VDD2

TX0+

SIO_CLK_A

N/C

VDD2

VSS

TX0-

VSS

RX0+

RESERVED

N/C

VDD2

VDDIO33

PBSRAM_CS/

N/C

RX0-

VSS

MAD[1]

N/C

VDD2

VDDIO33

TST_RST/

RX7-

VSS

BWE[2]/

VSS

VDDIO33

MAD[14]

RESERVED

VDDIO33

VSS

C2

F2

VDDIO33

VSS

MODE[6]

SCAN_MODE

N/C

J2

N/C

VDD2

C3

F3

J3

N/C

VSS

C4

TX_VDD6

VDDIO33

RXB_VSS7

TXB_VDD6

RX_VSS5

RXB_VDD5

VSS

F4

J4

N/C

VDDIO33

N/C

C5

F5

J5

N/C

C6

F6

J6

MODE[0]

VDDIO33

VSS

N/C

T2

C7

F7

TX_VSS7

TX_VSS6

RX_VSS6

TXB_VSS5

RXB_VSS5

TXB_VDD4

RXB_VSS4

TXB_VSS3

RX_VSS3

TXB_VDD2

RXB_VDD2

RX_VSS1

RXB_VSS1

TXB_VDD0

RXB_VSS0

N/C

J7

MAD[6]

VSS

T3

C8

F8

J8

T4

RTCK_ICE

TDI_ICE

N/C

C9

F9

J19

J20

J21

J22

J23

J24

J25

J26

K1

VSS

VDDIO33

MAD[5]

FAULT_LED[0]/

FAULT_LED[5]/

FAULT_LED[1]/

FAULT_LED[4]/

FAULT_LED[7]/

N/C

T5

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

VDDIO33

SIO_DIN_A

N/C

T6

T7

VDDIO33

VSS

N2

T8

REFCLK_P

RTRIM

VSS

MAD[4]

MAD[3]

MAD[7]

MAD[0]

N/C

N3

T10

T11

T12

T13

T14

T15

T16

T17

T19

T20

T21

T22

T23

T24

T25

T26

VSS

N4

VDD2

N5

VSS

N6

VDD2

TX_VDD2

RX_VDD2

RXB_VDD1

VDDIO33

VSS

N7

VDDIO33

VSS

K2

ACTIVE_LED[6]/

ACTIVE_LED[5]/

ACTIVE_LED[4]/

N/C

N8

VDD2

K3

N10

N11

N12

N13

N14

N15

N16

N17

N19

N20

VDD2

VSS

K4

VSS

VDD2

K5

VDD2

VSS

K6

N/C

VSS

VDDIO33

BWE[0]/

TDIODE_VSS

MWE0/

VSS

RXB_VDD0

N/C

VSS

VDDIO33

UART_TX

ACTIVE_LED[2]/

VDDIO33

K7

VDDIO33

VSS

VDD2

K8

VSS

N/C

K10

K11

K12

K13

VSS

VDD2

VDDIO33

MODE[2]

MODE[5]

VDD2

VSS

VDDIO33

N/C

D2

G2

VDD2

VDDIO33

1. N/C pins are not connected.

22 of 30

DB08-000274-03

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

1

Table 2

LSISAS1068E Pin Assignments Listed by Pin Number (Cont.)

Signal

U1

N/C

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

Y1

VSS

AA7

P_TX_VSS0

P_TX_VSS1

P_RX_VSS1

P_TXB_VSS2

P_RXB_VSS2

P_TXB_VDD3

P_RXB_VSS3

P_TXB_VSS4

P_RX_VSS4

P_TXB_VDD5

P_RXB_VDD5

P_RX_VSS6

P_RXB_VSS6

P_TXB_VDD7

P_RXB_VSS7

MADP[3]

AC4

P_TXB_VSS0

VSS

AE1

VSS

U2

N/C

TCK_ICE

TMS_ICE

N/C

VSS

AA8

AC5

AE2

P_TX0-

N/C

AE3

U3

AA9

AC6

VSS

AE4

P_TX1+

P_TX1-

U4

VSS

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

AC7

P_RX_VDD1

P_TX_VDD2

P_RX_VDD2

P_TX_VDD3

P_TXB_VSS3

N/C

AE5

U5

VSS

AC8

AE6

P_RX1+

P_RX1-

U6

N/C

VSS

AC9

AE7

U7

VDDIO33

VSS

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

AE8

P_RX2+

P_TX3-

U8

VSS

AE9

U10

U11

U12

U13

U14

U15

U16

U17

U19

U20

U21

U22

U23

U24

U25

U26

V1

VDD2

VSS

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AF2

P_RX_VDD3

VDDIO33

N/C

VSS

N/C

VDD2

VSS

VDDIO33

N/C

P_TX_VDD4

P_RX_VDD4

P_TX_VSS5

P_RX_VSS5

P_TX_VDD6

P_RX_VDD6

VSS

VDD2

VSS

N/C

P_REFCLK_P

VDDIO33

P_RX4-

MAD[21]

MAD[18]

BWE[3]/

MADP[2]

GPIO[1]

VDDIO33

VSS

VDD2

VSS

MAD[22]

P_TX5+

P_TXB_VSS6

P_RX6+

P_RX6-

VDDIO33

MAD[19]

N/C

VSS

Y2

VDDIO33

P_RX_VSS7

VDDIO33

N/C

Y3

MAD[20]

MCLK

BWE[1]/

MOE0/

MADP[1]

N/C

Y4

TRST/

GPIO[3]

P_TX7+

P_TX7-

Y5

N/C

AB2

TCK

MAD[28]

MAD[29]

N/C

Y6

N/C

AB3

RST/

P_RX7+

P_RX7-

Y7

P_TXB_VDD0

P_RXB_VDD0

VDDIO33

P_RXB_VSS1

VDDIO33

P_RXB_VSS4

VDDIO33

P_TX_VSS6

VDDIO33

MAD[27]

N/C

AB4

IDDT

Y8

AB5

P_TX_VDD0

P_RX_VDD0

P_RX_VSS0

P_TXB_VSS1

P_RXB_VDD1

P_TXB_VDD2

P_TX_VSS3

P_RX_VSS3

N/C

AD2

TN/

N/C

VSS

V2

N/C

Y9

AB6

AD3

P_TX0+

P_RX0+

P_RX0-

V3

TDO_ICE

GPIO[0]

N/C

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

AA1

AA2

AA3

AA4

AA5

AA6

AB7

AD4

P_TX_VDD1

VDDIO33

P_RXB_VSS0

P_TXB_VDD1

P_RX_VSS2

P_RXB_VDD2

VSS

AF3

V4

AB8

AD5

AF4

V5

AB9

AD6

AF5

P_TX2-

V6

N/C

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AC1

AD7

AF6

P_TX2+

P_TX_VSS2

P_RX2-

V7

VDDIO33

VSS

AD8

AF7

V8

AD9

AF8

V19

V20

V21

V22

V23

V24

V25

V26

W1

W2

W3

W4

W5

W6

W7

W8

W9

VSS

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AF9

P_TX3+

P_RX3+

P_RX3-

VDDIO33

MAD[16]

ADSC/

ADV/

P_TX_VSS4

P_RXB_VDD4

P_TXB_VSS5

P_RXB_VSS5

P_TXB_VDD6

P_TX_VSS7

P_TXB_VSS7

P_RX_VDD7

MAD[30]

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

VSS

N/C

P_RXB_VDD3

N/C

P_TXB_VDD4

P_TX4-

P_REFCLK_N

VSS

N/C

VSS

TDIODE_P

TRST_ICE/

N/C

MAD[23]

VSS

P_TX_VDD5

P_RX_VDD5

P_RXB_VDD6

VDDIO33

VSS

P_TX4+

P_RX4+

P_TX5-

P_RX5+

P_RX5-

P_TX6-

VDDIO33

MAD[17]

N/C

GPIO[2]

N/C

MAD[25]

MAD[26]

N/C

VDDIO33

VSS

MAD[24]

N/C

P_RXB_VDD7

VDDIO33

MAD[31]

VDDIO33

P_TX6+

P_TX_VDD7

VDDIO33

VSS

N/C

PROCMON

N/C

TDI

VSS

AC2

AC3

TDO

VSS

N/C

TMS

1. N/C pins are not connected.

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller 23 of 30

DB08-000274-03

Figure 4

LSISAS1068E 636 EPBGA-T Diagram – Top View (Sheet 1 of 2)

24 of 30

DB08-000274-03

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

Figure 4

LSISAS1068E 636 EPBGA-T Diagram – Top View (Sheet 2 of 2)

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller 25 of 30

DB08-000274-03

Package Drawing

The LSISAS1068E uses a 636 EPBGA-T package. The package code

is 8C. Figure 5 provides the package drawing.

26 of 30

DB08-000274-03

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

Figure 5

636-Ball EPBGA-T (8C) Mechanical Drawing (Sheet 1 of 3)

Important:

This drawing may not be the latest version. For board layout and manufacturing,

obtain the most recent engineering drawings from your LSI marketing

representative by requesting the outline drawing for package code 8C.

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller 27 of 30

DB08-000274-03

Figure 5

636-Ball EPBGA-T (8C) Mechanical (Sheet 2 of 3); Bottom View (Cont.)

Important:

This drawing may not be the latest version. For board layout and manufacturing,

obtain the most recent engineering drawings from your LSI marketing

representative by requesting the outline drawing for package code 8C.

28 of 30

DB08-000274-03

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller

Figure 5

636-Ball EPBGA-T (8C) Mechanical (Sheet 3 of 3); Bottom View (Cont.)

Important:

This drawing may not be the latest version. For board layout and manufacturing,

obtain the most recent engineering drawings from your LSI marketing

representative by requesting the outline drawing for package code 8C.

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller 29 of 30

DB08-000274-03

To receive product literature, visit us at http://www.lsi.com.

For a current list of our distributors, sales offices, and design resource centers, view our web page located at

http://www.lsilogic.com/contacts/index.html.

Headquarters

LSI Logic Corporation

North American Headquarters

Milpitas CA

Tel: 408.433.8000

ISO 9000 Certified

LSI Logic Europe Ltd.

European Headquarters

Bracknell England

Tel: 44.1344.413200

Fax: 44.1344.413254

2

This document contains proprietary information of LSI Logic

Corporation. The information contained herein is not to be

used by or disclosed to third parties without the express writ-

ten permission of an officer of LSI Logic Corporation.

Purchase of I C components of LSI Logic Corporation, or

one of its sublicensed Associated Companies, conveys a

license under the Philips I C Patent Rights to use these

2

components in an I C system, provided that the system

2

conforms to the I C standard Specification as defined by

Philips.

LSI Logic K.K.

Headquarters

Tokyo Japan

Tel: 81.3.5463.7821

LSI Logic, the LSI Logic logo design, Fusion-MPT, Gflx,

GigaBlaze, Integrated Mirroring, Integrated RAID, and

Integrated Striping are trademarks or registered trademarks

of LSI Logic Corporation. ARM and Multi-ICE are registered

trademarks of ARM Ltd., used under license. PCI-X is a

registered trademark of PCI SIG. All other brand and prod-

uct names may be trademarks of their respective compa-

nies.

LSI Logic Corporation reserves the right to make changes

to any products and services herein at any time without

notice. LSI Logic does not assume any responsibility or

liability arising out of the application or use of any product

or service described herein, except as expressly agreed to

in writing by LSI Logic; nor does the purchase, lease, or use

of a product or service from LSI Logic convey a license

under any patent rights, copyrights, trademark rights, or any

other of the intellectual property rights of LSI Logic or of

third parties.

Fax: 81.3.5463.7820

LSI Logic products are not intended for use in life-support

appliances, devices, or systems. Use of any LSI Logic

product in such applications without written consent of the

appropriate LSI Logic officer is prohibited.

AP

Doc. No. DB08-000274-03

30 of 30

October 2006

LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller


型号：	LSISAS1068E
厂家：	Linear
描述：	SCSI BUS CONTROLLER, PBGA636, EPBGA-636 PC 外围集成电路
文件：	总30页 (文件大小：743K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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