LF3324BGC [LOGIC]
Memory Circuit, 1MX24, CMOS, PBGA172, LBGA-172;
| 型号： | LF3324BGC |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Memory Circuit, 1MX24, CMOS, PBGA172, LBGA-172 内存集成电路 |
| 文件： | 总29页 (文件大小：853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Features
LF3324s may be Cascaded for depth and
width, supporting HDTV, Multiframe SDTV,
and other high resolution formats
24,883,200-bit Frame Memory
54 Mhz Max Data Rate
May be Organized Into the Following Configurations:
• 3,110,400 x 8-bit
• Seamless address space is maintained
with up to 8 cascaded devices
• 2,488,320 x 10-bit
Built-in ITU-R BT.656 TRS detection and
Synchronization
• 2,073,600 x 12-bit
Operating Modes:
Set & Clear Read/Write Pointer Control Pins
Choice of Control Interfaces:
• Random Access with Burst Control
• FIFO
• Two-wire Serial Microprocessor Interface
• Parallel Microprocessor Interface
Near-Full/Empty Flags With Programmable
Thresholds
Input Enable Control (Write Mask) for freeze-
frame applications
Flexible Pointer Manipulation
• Write and Read Pointers may be independently
jumped to arbitrary address locations
Output Enable Control (Data Skipping)
JTAG Boundary Scan - IEEE 1149.1
172 ball LBGA package
• Write or Read Pointers can be manipulated in real-
time based on external 24bit address
1.8V Internal Core Power Supply
3.3V I/O Supply
NOTE: This Preliminary Datasheet references LF3324BGC Engineering Samples
with an E marking under the part designation.
Applications
SD/HDTV Video Stream Buffer
RGB Graphics Buffer
Frame Synchronization
CCTV Security Camera Systems
Time Base Correction (TBC)
Freeze-Frame Buffer
Regional Read/Write for Picture-in-Picture (PIP)
Field-Based or Frame-Based Comb Filtering
Video Capture & Editing Systems
Deep Data Buffering
Video Special Effects (Rotation, Zoom)
Test Pattern Generation
Motion Detection or Frame-to-Frame Correlation
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
LF3324 Overview
The LF3324 is a 24 Mbit memory device that handles 8, 10, or 12bit data. The input data port may be
clocked asynchronously to the output ports. Since reads are non-destructive, a given data value, once
written into the memory core, may be read as many times as desired. A user requiring more storage can
cascade up to eight LF3324s into a larger array.
A great deal of memory addressing flexibility is offered with the LF3324. Both Burst Mode and Random
Access addressing is possible. In addition to simple clearing of the Write and Read pointers, either pointer
may be set/jumped to any location within the entire address space. Real-time random-access Writing or
Reading is also supported through an external address port.
The device is controlled by sixteen instruction words of eight bits each, which may be programmed or
verified via standard I2C 2-wire serial or parallel microprocessor interfaces.
The OPMODE configuration register selects one of the chip’s operating modes, each of which has versatile
submode options:
- FIFO With Asynchronous I/O
- Synchronous Shift Register (Single Clock; User-set Latency)
- Random Access With Burst Address
Figure 1. LF3324 Functional Block Diagram
SDA SCL
LOAD
PROGRAM
PCE0
PCE1
PWE
PRE
TDI
TWO-WIRE SERIAL
INTERFACE
TDO
TRST
TMS
TCLK
PARALLEL
INTERFACE
JTAG
6
PADDR
8
PDATA
MEMORY
24Mbit
OE
OUTPUT
DATA
PORT
INPUT
DATA
PORT
D[11:0]
Q[11:0]
3,110,400 x
2,488,320 x 10
2,073,600 x 12
8
(x8, x10, x12)
(x8, x10, x12)
PE
PF
FLAGS
WCLK
WEN
COLLIDE
WRITE
POINTER
READ
RCLK
REN
RSET
RCLR
WRITE
CONTROL
WSET
IEN
POINTER
OUTPUT
CONTROL
WCLR
MARK
RANDOM ACCESS
ADDRESS CONTROL
24
RADDRSEL
WADDRSEL
ADDR[23:0]
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Figure 2. Single Channel FIFO Mode Functional Block Diagram
MARK
WCLK
RCLK
WEN
WIEN
WRITE
READ
WRITE ADDRESS
READ ADDRESS
REN
RSET
RCLR
CONTROL A
CONTROLA
WCLR
WSET
OE
MEMORY CELL ARRAY
12
12
2,073,600 x 12-bit
2,488,320 x 10-bit
3,110,400 x 8-bit
D[11:0]
Q[11:0]
7
CHIP_ADDR6-0
PROGRAM
PDATA
8
6
PF
FLAG
PADDR
COLLIDE
PE
MASTER
CONTROL
GENERATOR
PCE0
PCE1
PRE
PWE
SDA
SCL
I2C
Figure 3. Random Access Mode Functional Block Diagram
WCLK
WEN
WIEN
RCLK
WRITE
READ
REN
WRITE ADDRESS
READ ADDRESS
CONTROL A
WCLR
WSET
MARK
RSET
RCLR
CONTROL
OE
MEMORY CELL ARRAY
12
12
2,073,600 x 12-bit
2,488,320 x 10-bit
3,110,400 x 8-bit
D[11:0]
7
Q[11:0]
CHIP_ADDR6-0
PROGRAM
PDATA
8
6
PADDR
PCE0
MASTER
CONTROL
PCE1
24
PRE
PWE
SDA
SCL
ADDRESS
CONTROL
RADDRSEL
WADDRSEL
I2C
24
ADDR[23:0]
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June 8, 2007 LDS.3324 G
LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Operating Modes
Asynchronous FIFO mode (OPMODE = 3)
In OPMODE 3, the LF3324 is configured as asynchronous First-In-First-Out 24Mbit memory, with indepen-
dent read and write clocks to allow for asynchronous operation. This mode is ideal for buffering or burst
data applications. Arbitrary write/read pointer jumping is supported in all FIFO modes. In this mode the
device can re-time a data stream according to a read sync signal (RSET or RCLR) and either ITU-R656
Timing Reference Signals (TRS) embedded within the incoming (video) data or the falling edge of a write
sync signal applied to WCLR, WSET, or MARK.
The input (write) and output (read) clocks need not be synchronous with one another, although the memory
core may fill or empty if they differ in average frequency. After it “fills,” the LF3324 continues writing and
the oldest data gets written over. If the memory core “empties” (and neither the read nor write pointer
have been set or cleared during run-time) the read pointer stops incrementing, and the device re-reads the
last written sample until more data is written. In either case, when the read and write addresses are the
same, the COLLIDE flag will go high, to alert the host. The almost-full (PF) and almost-empty (PE) flags
provide advance warning of these conditions whenever user-selected “fullness” or “emptiness” thresholds,
expressed in approximate eightieths of the memory core size, are exceeded. For example, if the 1/80 and
79/80 thresholds are enabled, flag PE will go HIGH whenever the read pointer lags behind the write pointer
by less than 1/80 of the memory space, and flag PF will go HIGH whenever the read pointer leads the
write pointer by this amount. (Calculations are performed modulo the total address space.) The data input
and output are sequential and the timing between write and read sync signals dynamically determines the
effective delay (depth) of the FIFO.
The “stop reading when empty” FIFO-mode behavior can be avoided by making sure LOAD is HIGH and
issuing any write or read pointer SET or CLEAR command at any time. This effectively gets the device out
of this “read-pointer-halting” mode from that point onwards, but invalidates the flags. Random Access Mode
allows free manipulation of the r/w pointers, and never halts the read pointer without being commanded
to do so using REN. Since Random Access mode naturally increments the r/w pointers sequentially, like
in FIFO mode, it may be a better mode to use if complex pointer manipulation of a single-channel of
memory is desired.
Synchronous shift register mode (OPMODE = 0)
In OPMODE 0, the LF3324 becomes a shift register with programmable total latency up to 224-8 clock
cycles. Writes and reads occur simultaneously, hence synchronous operation.
In OPMODE 0, the user provides a single clock for both the input and output clocks and specifies a desired
input-to-output data path latency, configuration register “WADDR” via the control interface. WCLK and RCLK
must be tied together, as should WEN and REN. When activated, WADDR will begin to countdown, and
once expired, will allow the inputs to begin to appear on the outputs. In OPMODE 0, WADDR countdown
can be activated in two ways. The first occurs when the first enable is brought LOW after the LOAD
signal has been set HIGH after MPU programming. The second is by bringing LOAD HIGH once MPU
programming complete, after the enables have been brought LOW.
Random Access Mode (OPMODE = 1)
Random Access mode is a FIFO mode, with the capability of either full-time write or read pointer Random
Accessability. This mode also supports write and read pointer jumps to arbitrary locations throughout
the address space. Unlike Asynchronous FIFO mode, Random Access mode does not disable memory
reads when the read pointer catches up to the write pointer. Write pointer manipulation can be done
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June 8, 2007 LDS.3324 G
LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Operating Modes
through setting (jumping) the write pointer to the 24bit address via the ADDR[23:0] port or to the WADDR
configuration register. Read pointer manipulation can be done through setting (jumping) the write pointer
to the 24bit address via the ADDR[23:0] port or to the RADDR configuration register. Periodic write and
read pointer jumping can be accomplished by supplying an address through either the ADDR[23:0] external
address or the WADDR/RADDR instruction registers. Continuous random access can only be accomplished
through the use of the ADDR[23:0] ports. When the write/read pointers are not being set to an address,
they increment sequentially in burst mode.
In Random Access Mode, when WADRSEL = 1 and RADRSEL = 0 the write pointer is set to the address
supplied by the ADDR[23:0] ports when WSET is brought LOW. In other words, on each active write clock
cycle (rising edge of WCLK for which WEN was LOW two rising edges of WCLK previously), the user
directs the write pointer to any desired memory location, using what are otherwise the second channel
data input and output ports. In this application, ADDR[23:12] denotes the vertical (row) component,
and ADDR[11:0], the horizontal (column) component, of a Cartesian set. Setting the configuration
register ROW_LENGTH to the frame’s line (row) length internally defines the Cartesian coordinates. Also,
ADDR[23:0] can also represent a single 24-bit linear address. The user governs the mapping of (ADDR)
to the internal memory space by setting the parameter ROW_LENGTH such that the internal ADDRESS
= ADDR[23-12] * ROW_LENGTH + ADDR[11-0]. A ROW_LENGTH setting of 0 is interpreted as 4096,
such that ADDRESS = a 24-bit concatenation of {ADDR} for this particular value. For a standard D1 video
application with 1716 samples per line, the user would set ROW_LENGTH to 1716 decimal = 6B4 hex.
Offset circuitry within the LF3324 permits the user to cascade several chips in parallel and to use them
collectively as a single large memory with a seamless address space. Data are read out sequentially by
rising edges of RCLK, under the control of REN (read enable), RSET (read pointer force to constant), and
RCLR (read pointer clear to 0). Holding WSET LOW keeps the device continuously in random access
write mode. Releasing WSET to its HIGH state causes the chip to continue to write sequentially from
the last-loaded address.
In Random Access Mode, when RADRSEL = 1, WADRSEL = 0, MARK_SEL = 1, the read pointer is set
to the address supplied by the ADDR[23:0] ports when RSET is brought LOW. As mentioned above,
ADDR[23:12] represents the upper bits or the vertical (row) address, whereas ADDR[11:0] represents the
lower bits or the horizontal (column) address. Releasing RSET HIGH causes the read address pointer to
increment from its last assigned location to the next sequential address.
It is important to note that WSET and RSET can be programmed to be level or negative-edge triggered.
An edge sensitive “SET” command is useful for using SYNC signals to reset FIFO pointers. Level sensitive
“SET” commands allow full-time Random Access capability.
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Depth Expansion
Cascading Devices
Multiple devices can be cascaded to deepen the address space. For every device cascaded more of the
24bit address space is used.
Internally, the LF3324 has a 24bit address space. The LF3324 was designed to be cascaded in parallel.
That is, the inputs of each device are tied together. The input data word (the data word placed on the D
input port) is to be common for all devices. Similarly, the outputs of all devices are tied together. Each
device’s write and read pointers behave identically. Only one device drives the shared output bus at one
time, controlled automatically through internal bus enables.
Each device in a cascade of N devices is responsible for 1/N of the address space. That is, each device
writes and/or reads based on the common W/R pointer locations and where that particular device sits in
the cascade. Configuration Register C[3:0] (BASE_ADDR) is used to define each device’s place in the
cascade.
When cascading LF3324s, all write enables WEN and WIEN must be tied together, as must read enables
REN (see the device connection diagram below).
The configuration registers of each device must be programmed identically, depending on mode/function,
except for Register C. Register C defines which region of the 24bit address space the particular device is
responsible for. Within Register C, there is a 4bit BASE_ADDR and 4bit CASCADE word. BASE_ADDR
determines the region of address space each device controls, and CASCADE defines how many devices
are in cascade. Register C effectively is programmed as “Chip n of N”.
Figure 4. Depth Expansion Example: 48Mbit Memory
LF3324_1
WCLK
WCLK
RCLK
AREN
RCLK
REN
SET
WADRSEL
CLR
SET
WADRSEL
CLR
RSET
RCLR
RSET
RCLR
RADRSEL
WEN
RADRSEL
WEN
IEN
IEN
12
12
24
D
D
Q
Q
ADDR23-0
ADDR
LF3324_2
WCLK
RCLK
AREN
SET
WADRSEL
CLR
RSET
RCLR
RADRSEL
WEN
IEN
D
Q
ADDR
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Device Configuration
The LF3324 has two MPU interfaces. The first is a standard two wire serial interface following the I2C
protocol. The second is a parallel interface allowing the user to write a byte of data at a time to the
configuration registers. When the user wishes to use the serial interface, the PROGRAM pin must be set
LOW, while a HIGH selects the parallel interface. To provide users with more flexibility, the control registers
have been combined with a “working latch” . Ultimately, the register-latch combination allows users to
update the configuration registers during chip operation, and then to transfer the register contents to all
working latches simultaneously using the LOAD signal. When high, the LOAD signal allows the LF3324
to be pre-programmed during operation, and once brought low after programming updates the working
latches allowing the new changes to take effect. LOAD can also be maintained low to allow changes to the
configuration registers to be immediately reflected in the working latches.
Programming
the LF3324
When the PROGRAM pin is LOW, the serial interface is active. Up to 8 LF3324 devices can be connected
to and programmed by the serial interface. The two wire interface is composed of an SCL clock pin and a
bi-directional SDA data pin. When inactive, SDA and SCL are forced HIGH by external pull up resistors.
Serial MPU
Interface
Data transmission is achieved over the SDA pin and must remain constant during the logical HIGH portion
of the SCL clock pulse. The level of SDA, while SCL is HIGH, is interpreted as the appropriate bit value as
will be shown later. Changing the data on SDA must only occur when SCL is low, because any changes
to SDA while SCL is HIGH is interpreted as a start or stop request, which are shown in Figure 7 with an
example data transfer in Figure 8.
The first operation to begin programming the LF3324 through the serial interface, is to send a start signal.
When the interface is inactive, a HIGH to LOW transition must be sent on SDA while SCL is HIGH, notifying
all connected devices (slaves) to expect a data transmission. When transferring data, the MSB of the eight
bit sequence is the first bit to be transmitted to or from the master or slave. The first byte of data to be
transmitted on SDA must consist of the 7-bit base address of the slave, along with an 8th READ/WRITE bit
as the LSB, which describes the direction of the data transmission. The slave whose 7-bit CHIP_ADDR6-0,
matches the 7-bit base address sent on SDA, will send an acknowledgement back to the master by bringing
SDA LOW on the 9th SCL pulse. NOTE: In order to differentiate the two internal die, die 0’s CHIP_ADDR(0)
is tied LOW and die 1’s CHIP_ADDR(0) is tied HIGH.
During a write operation, if the slave does not send an acknowledgment back to the master device, SDA is
left high which forces the master to generate a stop signal. In contrast, during a read operation, if there is no
acknowledgement back from the master device, the LF3324 interprets this as if it were the end of the data
transmission, and leaves SDA high, allowing the master to generate its stop signal.
Figure 5. I2C Start and Stop Signals
Start Signal
Stop Signal
SDA
SCL
SDA
SCL
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Device Configuration
There are four operations that can be performed between the master and the slave. They are: Write
to consecutive registers, write to a single configuration register, read from consecutive registers and read
from a single register. To write to consecutive control registers, a start signal and base address must be
sent with the R/W bit as described above. After the acknowledgment back from the appropriate slave, the
8-bit address of the target configuration register must be written to the slave with the R/W bit LOW. The
slave then acknowledges by setting SDA LOW. The data byte to be written into the register can now be
transferred on SDA. The slave then acknowledges by pulling SDA LOW on the next positive going pulse of
SCL. The first configuration register address loaded into the LF3324 is considered as the beginning address
for consecutive writes, and automatically increments to the next higher address space. Therefore after the
acknowledgement, the data byte to configure register (first address + 1) can now be transferred from master
to slave. At any point a stop signal can be given to end the data transfer. To write to a single configuration
register, the same technique can be applied adding a stop signal after the first data write.
To read from consecutive control registers, the master must again give the start signal followed by a
base address with the R/W bit = 0, as if the master wants to write to the slave. The appropriate slave
then acknowledges. The master will then transfer the target register address to the slave and wait for
an acknowledge. The master will then give a repeated start signal to the slave, along with the base
address and R/W bit this time HIGH signifying a read and wait for an acknowledge. The user must write
to the LF3324 to select the appropriate initial target register. Otherwise the starting position of the read is
uncertain. Once the LF3324 acknowledges, the next byte of data on SDA is the contents of the addressed
register sent from the device. If the master acknowledges, the LF3324 will send the next higher register’s
contents on the following byte of data. To read from only one register is the same procedure as for
consecutive reading with a stop signal following the transfer of the register’s contents.
Figure 6. I2C Example of transferring 11001101 on SDA
1
2
3
4
5
6
7
8
SCL
SDA
The parallel MPU interface can be used to write instructions to the control registers or to read them back
for verification. When the PROGRAM pin is HIGH, the parallel interface is selected. An external processor
can write into an internal register by setting PADDR to the desired register address, selecting the chip using
the PCEx pin, setting PDATA to the desired value and then pulsing PWE LOW. The data will be written into
the selected register when both PWE and PCEx are LOW, and will be held when either signal goes HIGH.
To read from a configuration register the processor must set PADDR to the desired address, select the chip
with the PCEx pin, and then set PRE LOW. The chip will then drive PDATA with the contents of the selected
register. After the processor has read the value from PDATA, PRE and PCEx should be set HIGH. The
PDATA pins are turned off (High Impedance) whenever PCEx or PRE are HIGH or when PWE is LOW. The
chip will only drive these pins when both PCEx and PRE are LOW and PWE is HIGH. One can also ground
the PRE pin and use the PWE pin as a read/write direction control and use the PCEx pin as a control I/O
strobe. NOTE: PCE0 addresses die 0, while PCE1 addresses die 1.
Parallel MPU
Interface
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Device Configuration
Parallel
Interface
Cont’d
Figure 7. Normal Reading and Writing From a Configuration Register
Read Cycle - Normal Mode
PCEx
tCSU
PWE
tCSPW
tCSU
PRE
tCSU
PADDR[5:0]
PDATA[7:0]
tCDLY
tCZ
Write Cycle - Normal Mode
PCEx
tCSU
tCSPW
PWE
PRE
tCSU
tCSU
PADDR[5:0]
PDATA[7:0]
tCHD
tCSU
Figure 8. Reading and Writing From a Configuration Register with PRE Held Low
Read Cycle - PRE held low
tCSPW
PCEx
PWE
tCSU
PADDR[5:0]
tCDLY
tCZ
PDATA[7:0]
Write Cycle - PRE held low
tCSPW
PCEx
PWE
tCSU
PADDR[5:0]
PDATA[7:0]
tCSU
tCHD
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Detailed Signal Definitions
VCCINT - Internal Core Power Supply
+1.8V power supply. All pins must be connected.
Power
VCCO - Output Driver Power Supply
+3.3V power supply. All pins must be connected.
Clocks
WCLK - Write Clock
Data present on D11-0 is written into the LF3324 on the rising edge of WCLK when WEN was LOW for
the previous rising edge of WCLK.
RCLK - Read Clock
In data is read from the LF3324 and presented on the output port (Q11-0) after a rising edge of RCLK
while REN and OE are LOW. When using the ADDR[23:0] external address port for read-address setting,
ADDR[23:0] is latched on the rising edge or RCLK.
Inputs
D11-0 - Data Input
D11-0 is the 12-bit registered data input port. Bit 11 is the MSB in all modes. D1-0 are ignored in 10-bit
mode and D3-0 are ignored in 8-bit mode. Any such unused inputs should either be tied to ground or
driven to proper logic levels by external logic.
ADDR23-0 - Random Access Address Port
ADDR[23:0] is the 24-bit external address port. The 24bit address is a purely linear address when the
configuration register ROW_LENGTH is equal to 0(default). When ROW_LENGTH is a non-zero value,
the memory is set to have a row (line) length of ROW_LENGTH. ADDR11-0 specifies the X/Column-
coordinate and ADDR23-12 specifies the Y/Row-coordinate.
CHIP_ADDR6-1 - Serial Interface Chip Address
CHIP_ADDR6- determines the LF3324’s address on the two-wire microprocessor bus. Each LF3324
chip’s 7-bit two-wire serial microprocessor interface address is equal to its CHIP_ADDR6-0. NOTE:
CHIP_ADDR0 is internally tied LOW on die 0 and HIGH on die 1.
SCL - Serial Clock Input
SCL is a standard two-wire serial microprocessor interface clock pin. With this chip, it functions as a
dedicated input, since this part cannot be the master on an two-wire serial microprocessor interface.
PADDR5-0 - Parallel Microprocessor Interface Address Port
PADDR5-0 is the 6-bit address port for the parallel microprocessor interface.
PDATA7-0 - Parallel Microprocessor Interface Data Port
PDATA7-0 is the 8-bit data port for the parallel microprocessor interface. When inactive becomes high
impedance.
Input/Output
SDA - Serial Data I/O
SDA is the standard bidirectional data pin of a two-wire serial microprocessor interface. External pullup
is required on SDA.
WCLR - Write Pointer Clear
Controls
When WCLR is brought LOW, the next rising edge of WCLK will bring the current value on D[11:0] into
memory address 0. Whenever WCLR is HIGH, the destination for D[11:0] will be controlled by WSET.
The user may program WCLR such that either its falling edge or its LOW state is active. If its LOW state
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Detailed Signal Definitions
is active, holding this pin LOW will hold the write address in its zero position continuously. This control
takes effect only when WEN is LOW.
RADDRSEL - Read Address Select
RADDRSEL selects the source of the read address. This pin and control MARKSEL select whether
RSET forces the read address to the RADDR configuration register (RADDRSEL = 0) or to ADDR[23:0]
(RADDRSEL = 1). This control takes effect only when REN is LOW.
WSET - Write Pointer Set
This control is active only when WCLR is HIGH. Bringing WSET LOW will cause the next rising edge
of WCLK to bring the current value on D[11:0] into memory at the address specified by WADDR, or at
the address present on ADDR[23:0]. Whenever WSET and WCLR are HIGH, the next rising edge of
WCLK will bring the current D[11:0] data value into the next-higher address in sequence. WSET may be
programmed to be either edge-triggered, in which case it affects the write pointer for only one clock cycle
following a falling edge, after which incrementing resumes, or level-triggered, in which case it affects the
write pointer until it is brought HIGH. For continuous random access write operation, holding WSET LOW
and programming it to be level-triggered will provide the needed continuous write pointer override. This
control takes effect only when WEN is LOW.
WADDRSEL - Write Pointer Set
WADDRSEL selects the source of the write address. WADDRSEL determines whether WSET forces
the write address pointer to the WADDR configuration register (WADDRSEL = 0) or to ADDR[23:0]
(WADDRSEL = 1). This control takes effect only when WEN is LOW.
MARK - Write Address Pointer Mark
Bringing this bit LOW will cause an internal register to store a copy the current value of the write address
pointer, for subsequent use in synchronizing the corresponding read address pointer to the same location.
Unlike WCLR and WSET, this control does not affect the write pointer value itself. The system must use
MARK instead of WCLR if the entire memory core can be filled between sequential falling edges of the
sync reference signal. In contrast, the system must use WCLR or WSET to establish a definite relationship
between the internal address and the data stream, as in random access read mode.
RSET - Read Address Pointer Set
If REN is LOW, bringing RSET LOW will force the read address to the most recently marked value
(MARK_SEL LOW), to RADDR (MARKSEL HIGH and RADRSEL LOW), or to ADDR[23:0] (MARK_SEL
is HIGH and RADRSEL is HIGH). This pin may be programmed to be either falling edge or level sensitive
active.
RCLR - Read Address Pointer Clear
Bringing RCLR LOW causes the next rising edge of RCLK to force the read address pointer to zero.
This pin may be programmed to be active on its falling edge or in its LOW state. It can reset the read
pointer only when REN is LOW.
WEN - Write Enable
If WEN is LOW, data on D11-0 is written to the device on the rising edge of WCLK. When WEN is HIGH,
the device ignores data on D and holds the write pointer. The user must anticipate the use of WEN by one
cycle. Therefore when desiring not to write a sample, WEN must be brought high the cycle before.
WIEN - Memory Write Enable (Write Masking)
WIEN is used to enable/disable writing into the memory core. A LOW on WIEN enables writing, while a
HIGH on WIEN disables writing. The internal write address pointer is incremented by WEN regardless of
the WIEN level. If disabling of WIEN is never desired, tie WIEN LOW.
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Detailed Signal Definitions
REN - Read Enable
If REN is LOW and the output port is enabled, data is read and presented on Q[11:0] after tD has elapsed
from the rising edge of RCLK. If REN goes HIGH, the last value loaded into output register will remain
unchanged and the read pointer will be held. The user must anticipate the use of REN by one cycle.
Therefore when desiring not to read a sample, REN must be brought high the cycle before.
PROGRAM - Serial/Parallel Interface Selector
When the user wishes to use the serial microprocessor to configure the LF3324, the PROGRAM pin must
be set LOW. If the user wishes to use the parallel interface, PROGRAM must be set HIGH.
LOAD – Instruction Load
Bringing asynchronous control LOAD LOW updates the working instruction latches to match the current
contents of the instruction preload latches. Holding it LOW causes the working latches to reflect all ongoing
instruction preloads. Holding it HIGH permits the user to preset the instruction preload latches to any
desired configuration without disturbing the work in progress. After any write to the configuration registers,
LOAD must be brought high for one cycle, and can then be brought and left low if so desired.
RESET - Global Reset
Bringing synchronous control RESET LOW forces all state machines and read and write pointers to 0 and
holds them there until it is released HIGH. It also forces the configuration registers to their default states,
if and only if LOAD is also LOW. The user may then modify the control registers as necessary. Bringing
RESET LOW while holding LOAD HIGH will reset the state machines and pointers, but will not change
either the preload or the working latches.
OE - Output Enable
When OE is LOW, Q[11:0] is enabled for output. When OE is HIGH, Q[11:0] is placed in a high-impedance
state. In 10-bit modes, Q1-0 are unconditionally tristated. In 8-bit modes, Q3-0 are tristated. The flag
outputs are not affected by OE.
PCE0/PCE1 - Parallel Interface Chip Enable
When LOW, PCE0 enables writing to die 0 with the parallel micrprocessor interface. When LOW, PCE1
enables writing to die 1 with the parallel micrprocessor interface.
PWE - Parallel Interface Write Enable
When LOW, PWE enables writing to the LF3324’s Instruction Registers with the parallel micrprocessor
interface.
PRE - Parallel Interface Read Enable
When LOW, PRE enables reading from the LF3324’s Instruction Registers with the parallel micrprocessor
interface.
Data Outputs
Q11-0 - Data Output
Q[11:0] is the 12-bit registered data output port. Q[11:0] is always the MSB. In 10-bit mode, bits
1 and 0 are tristated. In 8-bit mode, bits 3-0 are tristated. All active bits are updated on each
rising edge of RCLK when REN is LOW.
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Detailed Signal Definitions
PF - Programmable Almost Full
Flag Outputs
PF goes HIGH (active) when the write pointer is more than (MAX_depth - (MAX_depth x TH)) locations
ahead of the read pointer. TH is a threshold value stored in Register 9 [2:0]. PF is updated on the
rising edge of WCLK. TRS bits either entering of emerging to/from the device can be mapped to PF
(Register B[3:0]).
PE - Programmable Almost Empty Flag
PE goes HIGH (active) when the write pointer is less than or equal to (MAX_depth - (MAX_depth x TL))
locations ahead of the read pointer. TL is a threshold value stored in Register 9 [2:0]. PE is updated
on the rising edge of RCLK. TRS bits either entering of emerging to/from the device can be mapped
to PE (Register B[7:4]).
COLLIDE - Memory Read/Write Pointer Collision Flag
This flag goes high whenever the read and write addresses to the memory core coincide.
By monitoring the partial full/empty flags, the user can ascertain the direction of approach,
i.e., read pointer catching up with write (FIFO empty) or write pointer catching up with read
(FIFO full). TRS bits from D and Q can be mapped to COLLIDE (Register B[3:0]).
TDI - JTAG input data
TDI is the input data pin when using JTAG.
JTAG
TDO - JTAG output data
TDO is the output data pin when using JTAG.
TRSTB - JTAG reset
TRSTB is used to reset all the registers and state machine fount the the JTAG module.
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Detailed Signal Definitions
TMS - JTAG Tap controller input
TMS controls the state of the tap controller.
TCK - JTAG clock
TCK is the used supplied clock of JTAG. It controls the flow of data and latches input data on the
rising edge.
Configuration Register Map
The various 8-bit control registers may be pre-programmed with either the parallel microprocessor port
(PROGRAM=1), or through the serial microprocessor interface bus(PROGRAM=0). Changes in pre-
programming begin to affect the data path when LOAD is brought LOW. In each instance, the value in
parens () is the default state following assertion of RESET while LOAD = 0.
Configuration Register 0 (default = 00000000)
3:0 = ROW_LENGTH[11:8]
(0000: 24-bit linear map; see reg 7)
Configuration Register 1 (default = 00000000)
7:0 = ROW_LENGTH[7:0]
(00000000: 24-bit linear map; see reg 6)
Configuration Register 2 (default = 00000000)
7:0 = WADDR[23:16]
(00000000: default = 0; see reg 9, a)
Configuration Register 3 (default = 00000000)
7:0 = WADDR[15:8]
(00000000: default = 0; see reg 8, a)
Configuration Register 4 (default = 00000000)
7:0 = WADDR[7:0]
(00000000: default = 0; see reg 8, 9)
Configuration Register 5 (default = 00000000)
7:0 = RADDR[23:16]
(00000000)
Configuration Register 6 (default = 00000000)
7:0 = RADDR[15:8] (00000000)
Configuration Register 7 (default = 00000000)
7:0 = RADDR[7:0]
(00000000)
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Configuration Register Map
Configuration Register 8 (default = 10_00_0_111)
7:6 = WIDTH[1:0]
5:4 = Reserved
(10: 10 bits)
(Make equal to 00)
(Make equal to 0)
(111)
3
= MARK_ACTIVE_RSET
2:0 = OPMODE
Configuration Register 9 (default = 00_000_000)
7:6 = TRS_SYNC[1:0] (00: ignore embedded TRS)
Reserved - set to 0
5
4
3
= -------
= A_FLD
(0: frame sync - use falling F-bit from TRS)
(0: use marked address - not user defined address)
(000: trigger empty, full on 1/80, 79/80)
= MARK_SEL
2:0 = FLAG_SET
Configuration Register A (default = 00000000)
7
6
5
4
3
2
1
0
= -------
Reserved - set to 0
= WSET_catch
= RSET_b_sel
= RCLR_b_sel
= -------
(0: setting pointer does not MARK its new value)
(0: RSET is falling edge triggered)
(0: RCLR is falling edge triggered)
Reserved - set to 0
= -------
Reserved - set to 0
= WSET_b_sel
= WCLR_b_sel
(0: WSET is falling edge triggered)
(0: WCLR is falling edge triggered)
Configuration Register B (default = 00_00_00_00)
7:4 = -------
RESERVED
3:0 = FLAG_CTL
(00: PE, PF are part-empty, -full)
Configuration Register C (default = 0000_0000)
7:4 = BASE_ADDR
3:0 = CASCADE
(0000: lowest-address chip in cascade sequence)
(0000: single chip - no cascade of multiple chips)
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Configuration Register Definitions
Register 0[3:0], Register 1[7:0] = ROW_LENGTH[11:0] - for Cartesian-to-linear address map
This control governs the remapping of Cartesian coordinates arriving on ADDR[11-0] (horizontal/column
component) and ADDR[23-12] (vertical/row component) into a linear address, for use by the chip’s internal
address generator. Setting ROW_LENGTH to 0 causes the incoming address to be interpreted directly as a
linear address, with the 24bits ADDR[23:0] address.
Register 2[7:0], Register 3[7:0], Register 4[7:0] = WADDR[23:0] - 24bit ‘Jump’ Address
Configuration register WADDR defines a static 24bit address (image pixel or memory location) that
the Write pointer can be ‘jumped’ to. Bringing WSET LOW forces/jumps the memory write pointer to
the address defined by WADDR (when WADRSEL is LOW). When used in this way, WADDR is an
override address. For 2-D applications, where ROW_LENGTH defines a frame’s Horizontal dimension,
, WADDR[11:0] is equal to the 12-bit X-coordinate (Horizontal) and WADDR[23:12] is considered the
Y-coordinate (Vertical) in a Cartesian Coordinate system. When ROW_LENGTH is 0, WADDR[23:0]
is considered to be a linear address in the memory space. By changing the ROW_LENGTH, the
X-coordinate can be from 0 to (ROW_LENGTH-1) to make up the Cartesian plane. For example, if
ROW_LENGTH = 16, the X-coordinate or WADDR[11:0] can be from 0 to 15 in the Cartesian space.
Register 5[7:0], Register 6[7:0], Register 7[7:0] = RADDR[23:0] - 24bit ‘Jump’ Address
Bringing RSET LOW forces/jumps the read pointer to the address defined by RADDR.
Register 8[7:6] = WIDTH[1:0] - data word size at input/output ports
Input Port
D[11:4]
Output Port
0x
10
11
8 bits
Q[11:4] (Q[3:0] tristated)
Q[11:2] (Q[1:0] tristated)
Q[11:0]
10 bits
12 bits
D[11:2] (default)
D[11:0]
Register 8[5:4] = Reserved
Register 8[3] = MARK_ACTIVE_RSET
0
1
ignores the internal RSET that occurs following the MARK
obeys the internal RSET according to the MARK
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Configuration Register Definitions
Register 8[2:0] = OPMODE[2:0] - operating mode
000
001
010
011
1XX
RESERVED
Random Access
RESERVED
FIFO
RESERVED
Register 9[7:6] = TRS_SYNC[1:0] - response to embedded TRS EAV
00
01
10
disable TRS sync detection (default)
F-bit of embedded TRS EAV marks current write pointer.
F-bit of embedded TRS EAV sets current write pointer to value
set by ADDR[23:0] or WADDR
11
RESERVED
Register 9[4] = FLD frame/field sync select
0
1
use only falling F-bit in EAV (frame-based sync); ignore rising F-bit (default)
use both rising and falling F-bit in EAV (field-based sync)
Register 9[3] MARK_SEL - This signal is used in combination with pin RADRSEL to determine to
effect of bringing RSET low on the read pointer(s). When RSET goes to 0:
0
1
force read pointer(s) to marked address(es) (default)
force read pointer(s) as shown in following table:
RADRSEL
Read Pointer Equals:
ADDR[23:0] address
RADDR address
1
0
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Configuration Register Definitions
Register 9[2:0] = FLAG_SET[2:0] - sets fractional “fullness” and “emptiness” thresholds in
memory core.
Partially Full flag goes HIGH when the memory is more than “TH” full. Partially Empty flag goes
HIGH when the memory is less than or equal to “TL” full.
000
001
010
011
100
101
110
111
TH = 79/81 (default)
TH = 78/81
TL = 1/81 (default)
TL = 2/81
TH = 77/81
TL = 3/81
TH = 76/81
TL = 4/81
TH = 75/81
TL = 5/81
TH = 74/81
TL = 6/81
TH = 73/81
TL = 7/81
TH = 72/81
TL = 8/81
Register A[6] = WSET_catch
0
1
Setting Write Pointer does not “MARK” its new value (default)
Setting Write Pointer auto-MARKS its new value
Register A[5:0] Control action.
Rb[5]
Rb[4]
Rb[3]
Rb[2]
Rb[1]
RSET_b_sel
RCLR_b_sel
WADDRSEL_b_sel
RADDRSEL_b_sel
WSET_b_sel
Rb[0]
if 0:
WCLR_b_sel
Each falling edge on the corresponding control pin overrides a
memory address counter for exactly one clock cycle, after which
normal memory address incrementing immediately resumes. (default)
The corresponding pin continuously overrides the memory address
counter as long as it is held LOW. Memory address incrementing
resumes when the pin is returned HIGH.
if 1:
Register B[7:4]=
-------
Reserved
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June 8, 2007 LDS.3324 G
LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Configuration Register Definitions
Register B[3:0] FLAG_CTL[3:0] for pins PE and PF *
FLAG_CTL
0000
0001
0010
PE
Empty (Emerging)
------
PF
COLLIDE
Full (Incoming)
COLLIDE (Emerging)
RA=MA (Emerging)
D v (Incoming)
Q v (Emerging)
D v (Incoming)
Q v (Emerging)
D h (Incoming)
Q h (Emerging)
D h (Incoming)
Q h (Emerging)
COLLIDE (Emerging)
D h (Incoming)
D f (Incoming)
Q f (Emerging)
D f (Incoming)
Q f (Emerging)
D f (Incoming)
Q f (Emerging)
D v (Incoming)
Q v (Emerging)
0011
Q h (Emerging)
0100
COLLIDE (Emerging)
COLLIDE (Emerging)
COLLIDE (Emerging)
COLLIDE (Emerging)
COLLIDE (Emerging)
COLLIDE (Emerging)
0101
0110
0111
1000
1001
*Each flag is updated on the rising edge of its associated clock: WCLK (Incoming) or RCLK (Emerging)
D f, v, h are the TRS bits embedded in the incoming TRS signals.
Q f, v, h are the TRS bits embedded in the emerging TRS signals.
RA is the read address pointer value.
MA is the ‘marked’ address pointer value.
Register C[7:4] = BASE_ADDR[3:0] - position of chip in cascade series; 0000 = lowest;
BASE_ADDR[3:0] must not exceed CASCADE[3:0]**
0000:
0001:
....
chip one of N (N is number of chips in system)
chip two of N (N is number of chips in system)
....
0111:
chip eight of N (N is number of chips in system)
** Note: There are two cascaded die per LF3324. Die 0 is chip 1 of 2, die 2 is chip 2 of 2.
Register C[3:0] = CASCADE[3:0] - number of chips in a system with concatenated address
spaces*.
0001:
0011:
....
single chip operation (two die)
two chip cascade (four die)
....
1111:
eight chip cascade (sixteen die)
* Note limits regarding the number of possible chips, related to WIDTH control:
8bit data: 5 or less LF3324s (WIDTH = 0x)
10bit data: 6 or less LF3324s (WIDTH = 10)
12bit data: 8 or less LF3324s (WIDTH = 11)
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June 8, 2007 LDS.3324 G
LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Reserved Configuration Registers
Instruction registers D hex and above are reserved for test purposes only.
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature
–65°C to +150°C
VCCINT , Internal supply voltage with respect to ground
VCCO, Output drivers supply voltage with respect to ground
Signal applied to high impedance output
Output current into low outputs
–0.5V to + 2.0V
–0.5V to + 4.0V
–0.5V to + 3.3V
25 mA
Latchup current
> 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Characteristic
VCCINT
Mode
Temperature Range
0°C to +70°C
Supply Voltage
1.71V < Vcc < 1.89V
3.00V < Vcc < 3.60V
Commerical
Commerical
VCCO
0°C to +70°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
Typ Max Unit
2.4
V
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
V
CC = Min., IOH MAX = -4 mA
CC = Min., IOL MAX = 4 mA
VOH
VOL
VIH
VIL
V
V
0.4
2.0
V
V
(Note 3)
0.8
µA
With Internal Pull-up - JTAG
All other pins
IIx
+20
µA
Input Current
IIx
±10
µA
Ground < VOUT < VCC (Note 12)
(Note 5,6)
Output Leakage Current
IOZ
±10
mA
V
CC Current, Dynamic
CC Current, Quiescent
ICC1
ICC2
CIN
COUT
400
mA
10
(Note 7)
V
pF
7
TA = 25°C, f = 1 MHz
TA = 25°C, f = 1 MHz
Input Capacitance
Output Capacitance
pF
7
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Switching Characteristics
Commercial Operating Range (0°C to +70°C) Notes 9, 10 (ns)
LF3324BGC
-
Max
Min
Max
Min
18
18
5
Symbol
tCYC1
tCYC2
tPWH
tPWL
tDS
Parameter
Cycle Time 1 (WCLK, RCLK) - FIFO Mode
Cycle Time 2 (WCLK, RCLK) - Full-time Random Access
Clock Pulse Width High (WCLK, RCLK)
Clock Pulse Width Low (WCLK, RCLK)
Setup Time, Data Inputs (D)
5
5
Hold Time, Data Inputs (D)
1
tDH
Write Enable Setup Time (WEN)
Write Enable Hold Time (WEN)
5
tWES
tWEH
tRES
tREH
tLDS
tLDH
tRWS
tRWH
tD
1
Read Enable Setup Time (REN)
Read Enable Hold Time (REN)
5
1
Load Setup Time
5
Load Hold Time
1
R/W Set/Clr Setup Time
5
(WCLR,RADDRSEL,WSET,WADDRSEL,RSET,RCLR)
R/W Set/Clr Hold Time
1
7
7
(WCLR,RADDRSEL,WSET,WADDRSEL,RSET,RCLR)
Access Time
tF
10
10
tDIS
Write Clock to Programmable Flags (PE, PF, COLLIDE)
Tri-state Output Disable Delay
tENA
tCSU
tCHD
tCSPW
tCDLY
tCZ
5
1
Tri-state Output Enable Delay
Parallel Interface Control Setup Time for Reads/Writes
Parallel Interface Control Hold Time for Reads/Writes
Parallel Interface Control Strobe Pulse Width
Parallel Interface Control Output Delay
Parallel Interface Control Tristate Delay
20
8
10
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LF3324
24Mbit Frame Buffer / FIFO
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Write Cycle Timing - Write Enable
WCLK
Preliminary Datasheet
tWES
tWEH
tPWH
tPWL
tCYC1
tCYC2
WEN
tDS tDH
(n)
(n+1)
(n+3)
(n+4)
(n+5)
D[11:0]
IEN = LOW
NOTE: WEN must be brought LOW 2 rising edges of WCLK prior to latching valid data on D
Write Cycle Timing - Write Masking
WCLK
tWES
tWEH
tPWH
tCYC1
tCYC2
tPWL
WIEN
tDS tDH
data not
written
(n+5)
data not
D[11:0]
(n)
(n+1)
(n+3)
(n+4)
written
(n+7)
(n+6)
WEN = LOW
NOTE: Bringing WIEN HIGH disables data on D from being written into memory, yet it does not disable the Write pointer from incrementing
NOTE: WIEN must be brought HIGH 2 rising edges of WCLK prior to masking input data on D
Read Cycle Timing
RCLK
tRES
tPWH
tCYC1
tCYC2
tPWL
tREH
tD
REN
tD
Q[11:0]
(n–2)
(n–1)
(n)
(n+1)
(n+2)
(n+3)
tF
tF
PE
COLLIDE
OE = LOW
NOTE: REN should be brought LOW 2 rising edges of RCLK prior to expecting valid data on Q
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LF3324
24Mbit Frame Buffer / FIFO
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Write Reset Timing
WCLK
Preliminary Datasheet
1
2
3
4
5
tRWH
tRWS
WCLR
WSET
tRWH
tRWS
tDS tDH
(0)
(n)
(n+1)
(1)
(2)
(A)
(A+1)
D[11:0]
WEN = LOW
CLR and SET both programmed to be falling edge sensitive
*
Rising Edge 1: Clears Write Pointer and latches data on D to be written in address 0
*
Rising Edge 4: Sets Write Pointer to Address A (based on WADDR) and latches data on D to be written in Address A
Read Reset Timing
1
2
8
9
10
RCLK
CLR
tRWS
tD
....
Q[11:0]
(1)
(n)
(n+1)
(n+2)
(n+8)
(0)
REN = LOW
NOTE: CLR programmed as being falling edge sensitive
It takes 9 REN-enabled rising edges of RCLK (including the edge that latches a LOW on CLR) to pass the contents of address 0 to the Q port.
Random Access Read Pointer ‘Jump’Timing
1
13
14
RCLK
tDS tDH
A23–0
ADDR23-0
RSET
tD
tD
Q[11:0]
(n–2)
(n-1)
(n)
(n+13)
(A)
(A+1)
OE = LOW
REN = LOW WADDRSEL= LOW RADDRSEL= HIGH OPMODE[2:0]=001 MARK_SEL (Register 9[3]) =1
NOTE: RSET programmed to be falling edge sensitive
NOTE: It takes 14 rising edges of RCLK upon setting/jumping the Read pointer
(to the 24bit Address "A" on ADDR) for the contents of location A to be dumped onto Q
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LF3324
24Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Random Access Write Pointer ‘Jump’Timing
1
WCLK
tDS tDH
ADDR23–0
WSET
A23-0
tRWS
(n+1)
(A)
(A+1)
(A+2)
(A+3)
D[11:0]
(n)
(A+4)
WEN= LOW WADDRSEL= HIGH
OPMODE[2:0]=001
NOTE: SET programmed to be falling edge sensitive
NOTE: Rising edge of WCLK labeled "1" writes data on D to 24bit Address "A"
Output Enable and Disable
OE
tDIS
tENA
HIGH IMPEDANCE
Q[11:0]
Jumping/Setting Pointers based on Configuration Register Address after Remapping Process
1
2
3
4
5
6
7
WCLK
WEN
tRWH
tRWH
1
2
LOAD
WSET
tRWS
tRWH
3
tRWS
tRWH
4
RSET
SET and RSET programmed to be level sensitive
1WEN is LOW for 3 rising edges of WCLK prior to LOAD transition. It stays LOW for the minimum required 5 rising edges after the LOAD transition.
2The configuration registers are programmed while LOAD is LOW. The LOAD transition triggers the address remap process.
3WSET can be brought LOW (edge "3") 3 rising edges of WCLK after the LOAD transition, jumping the write pointer to the address programmed into the WADR register.
4RSET can be brought LOW (edge "7") 7 rising edges of RCLK after the LOAD transition, jumping the read pointer to the address programmed into the RADDR register.
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LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Notes
1. Maximum Ratings indicate stress specifications only. Functional operation of these products
at values beyond those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designedtoprotect the chip
from damaging substrate injection currents and accumulations of static charge. Nevertheless,
conventional precautions should be observed during storage, handling, and use of these circuits
in order to avoid exposure to excessive electrical stress values.
3. This device provides hard clamping of transient undershoot. Input levels below ground will be
clamped beginning at –0.6V. The device can withstand operation with inputs or outputs in the
range of –0.5 V to +5.5 V. Device operation will not be adversely affected, however, input current
levels may be in excess of 100 mA.
4. Actual test conditions may vary from those designated but operation is guaranteed as speci-
fied.
5. Supply current for a given application can be approximated by:
2
NCV F
where
2
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with outputs changing every cycle and no load, at a 50 MHz clock rate.
7. Tested with all inputs within 0.1V of VCC or Ground, and no load.
8. These parameters are guaranteed but not 100% tested.
9. AC specifications are tested with input transition times less than 3 ns, output reference levels
of 1.5 V (except t
test), and input levels of nominally 0to 3.0V. Output loading may be a
dis
resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and
VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH
and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30
pF minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current change pulses and
fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The
following measures are recommended:
a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to
the device as possible. Similar capacitors should be installed between device VCC and the tester
common, and device ground and tester common.
b. Ground and VCC supply planes must be brought directly to the device leads.
c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC
noise to maintain required input levels relative to the device ground pin.
Video Imaging Product
LOGIC Devices Incorporated
26
June 8, 2007 LDS.3324 G
LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Notes
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified
from the point of view of the external system driving the chip. Setup time, for example, is specified
as a minimum since the external system must supply at least that much time to meet the worst-
case requirements of all parts. Responses from the internal circuitry are specified from the point of
view of the device. Output delay, for example, is specified as a maximum since worst-case opera-
tion of any device always provides data within that time.
11. For the t
For the t
dis
test, the transition is measured to the 1.5 V crossing point with datasheet loads.
test, the transition is measured to the ±200mV level from the measured steady-state
ena
output voltage with ±10mA loads. The balancing voltage, V , is set at 3.0 V for Z-to-0 and 0-to-Z
th
tests, and set at 0 V for Z-to-1 and 1-to-Z tests.
12. These parameters are only tested at the high temperature extreme, which is the worst case
for leakage current.
FIGURE B.THRESHOLD LEVELS
FIGURE A. OUTPUT LOADING CIRCUIT
tENA
tDIS
OE
0
1.5 V
1.5 V
S1
Z
Z
3.0V Vth
DUT
1.5 V
1.5 V
VOL*
0.2 V
0.2 V
I
OL
0
1
Z
Z
V
TH
C
L
VOH*
I
OH
1
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Video Imaging Product
LOGIC Devices Incorporated
27
June 8, 2007 LDS.3324 G
LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Package and Ordering Information
BALL PAD CORNER
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
OE_b
Q11
REN_b
VCCI
VCCINT
PADDR5
RCLR_b
PADDR3
PADDR4
PADDR0 PROGRAM
PWEB
PREB
CHIP_ID5 CHIP_ID2
CHIP_ID4 CHIP_ID1
VCCINT
WIEN_b
VCCINT
WEN_b
RESET_b
VCCINT
GNDINT
RSET_b
PADDR1
LOAD_b
VCCINT
GNDINT
PCE0
D11
Q10
VCCO
Q9
GNDO
VCCO
Q7
VCCINT
GNDO
GNDO
GNDO
GNDO
GNDO
GNDO
ADDR19
VCCO
VCCI
PADDR2
GNDINT
Q6
VCCINT
GNDINT
CHIP_ID6 CHIP_ID3
VCCINT
PCE1
GNDINT
D6
VCCINT
GNDINT
GNDINT
D3
D8
D9
D10
Q8
VCCINT
GNDINT
GNDINT
VCCINT
VCCI
VCCI
D1
D7
Q5
VCCO
Q4
D4
D5
Q3
VCCO
Q1
Q2
VCCINT
D2
G
H
J
Q0
RCLK
VCCO
ADDR14
ADDR16
ADDR21
ADDR22
VCCI
GNDINT
GNDINT
GNDINT
ADDR3
ADDR6
TCK
D0
VCCI
ADDR0
VCCI
ADDR5
VCCI
ADDR9
GNDO
VCCO
WCLK
VCCINT
ADDR2
ADDR4
ADDR7
ADDR10
VCCINT
GNDINT
ADDR12
ADDR15
ADDR17
ADDR20
ADDR23
VCCI
PE
ADDR13
VCCO
ADDR18
VCCO
VCCO
VCCINT
ADDR1
GNDINT
ADDR8
ADDR11
TDI
GNDO
GNDO
WCLR_b
VCCI
GNDINT
GNDINT
PDATA2
VCCO
K
L
GNDO
GNDO
VCCO
VCCO
GNDO
GNDO
PDATA4
VCCO
GNDO
PDATA7
SDA
GNDO
VCCO
M
N
P
COLLIDE WADRSEL
VCCO
PDATA6
PDATA5
PDATA0
PDATA1
TMS
PF
VCCI
WSET_b WMARK_b RADRSEL
SCL
PDATA3
TRST_b
TDO
Notes:
VCCINT = 1.8V
VCCO = 3.3V
VCCI = 3.3V
Ground
1.00 REF
1.00 REF
172 Ball - Low Profile Ball Grid Array (LBGA)
0°C to 70°C--Commercial Screening
Speed
_
LF3324BGC
The information contained herein is subject to change without notice. LOGIC Devices reserves the right to make changes to or discontinue any semiconductor product or service
without notice. LOGIC Devices assumes no responsibility for the use of any circuitry other than circuitry embodied in a LOGIC Devices product. Nor does it convey or imply any license
under patent or other rights. LOGIC Devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless
pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of LOGIC Devices’ products in life-support system applications implies
that the manufacturer assumes all risk of such use and in doing so indemnifies LOGIC Devices against all charges.
Video Imaging Product
LOGIC Devices Incorporated
28
June 8, 2007 LDS.3324 G
LF3324
24Mbit Frame Buffer / FIFO
DEVICES INCORPORATED
Preliminary Datasheet
Document History Page
DOCUMENT TITLE: LF3324 24MBIT FRAME BUFFER / FIFO
Rev.
A
ECN NO. Issue Date Description of Change
03/08/05
03/28/05
04/07/05
Initiate
B
Downgraded part speed from 12ns to 13.5ns
Upgraded Speed from 13.5ns to 13.4ns
C
Fixed incorrect description of the program pin on page 14
Added data rate
D
E
F
08/18/05
09/14/05
07/7/06
Clarified Programmable FLAG operation text
Clarified FIFO operation text
Downgraded speed in full-time Random Access to 54MHz
Downgraded speed in FIFO Mode to 54MHz
G
06/08/07
LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and
to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current
and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed
the purchase price of LOGIC Devices products. LOGIC Devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety
applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user.
Video Imaging Product
LOGIC Devices Incorporated
29
June 8, 2007 LDS.3324 G
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