LF3330QC12G [LOGIC]
Digital Filter, 12-Bit, CMOS, PQFP100, GREEN, PLASTIC, QFP-100;
| 型号： | LF3330QC12G |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Digital Filter, 12-Bit, CMOS, PQFP100, GREEN, PLASTIC, QFP-100 时钟 LTE 外围集成电路 |
| 文件： | 总15页 (文件大小：741K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DEVICES INCORPORATED
LF3330
Vertical Digital Image Filter
FEATURES
DESCRIPTION
ꢀ 83 MHz Data Rate
The LF3330 filters digital images in the data streams. The number of inter-
vertical dimension at real-time video
rates. The input and coefficient data
are both 12 bits and in two’s comple-
ment format. The output is also in
two’s complement format and may be or less, the filter can handle it.
rounded to 16 bits.
leaved data sets that the device can
handle is limited only by the length
of the on-chip line buffers. If the inter-
leaved video line has 3076 data values
ꢀ 12-bit Data and Coefficients
ꢀ On-board Memory for 256
Coefficient Sets
ꢀ LF InterfaceTM Allows All 256 Coef-
ficient Sets to be Updated Within
Vertical Blanking
ꢀ Selectable 16-bit Data Output with
User-Defined Rounding and Limit-
ing
The LF3330 contains enough on-board
memory to store 256 coefficient sets.
The filter is an 8-tap FIR filter with
all required line buffers contained on- The LF InterfaceTM allows all 256 coef-
chip. The line buffers can store video
lines with lengths from 4 to 3076
pixels.
ficient sets to be updated within verti-
cal blanking.
ꢀ Seven 3K x 12-bit, Programmable
Two-Mode Line Buffers
ꢀ Separate Input Port for Odd and
Selectable 16-bit data output with
user-defined rounding and limiting
Multiple LF3330s can be cascaded
Even Field Filtering
ꢀ 8 Filter Taps
ꢀ Cascadable for More Filter Taps
ꢀ Supports Interleaved Data Streams
ꢀ 3.3 Volt Power Supply
ꢀ 5 Volt Tolerant I/O
together to create larger vertical filters. minimizes the constraints put on coef-
ficient sets for various filter imple-
Due to the length of the line buffers,
mentations.
interleaved data can be fed directly
into the device and filtered without
separating the data into individual
SIGNAL DEFINITIONS
ꢀ 100 Lead PQFP
LF3330 BLOCK DIAGRAM
12
DIN11-0
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
ROUND
SELECT
LIMIT
32
16
DOUT15-0
12
3K LINE BUFFER
VB11-0
CIRCUITRY
OED
3K LINE BUFFER
3K LINE BUFFER
3K LINE BUFFER
12
COUT11-0
OEC
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
FIGURE 1. LF3330 FUNCTIONAL BLOCK DIAGRAM
T I M I L
S E L E C T
R O U N D
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
Power
FIGURE 2. INPUT FORMATS
VCC and GND
Input Data
Coefficient Data
+3.3 V power supply. All pins must
be connected.
11 10
9
2
1
0
11 10
9
2
1
0
211 210 29
22 21 20
20 21 22
29 210 211
(Sign)
(Sign)
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
TABLE 1. OUTPUT FORMATS
SLCT4-0
00000
S15 S14 S13
F15 F14 F13
F16 F15 F14
· · ·
· · ·
· · ·
· · ·
S8
F8
F9
S7
F7
F8
F9
· · ·
· · ·
· · ·
· · ·
S2
F2
F3
F4
S1
F1
F2
F3
S0
F0
F1
F2
Inputs
00001
DIN11-0 — Data Input
00010
·
F·17 · ·
F16 F15
F·10 ·
· ·
· · ·
DIN11-0 is the 12-bit registered data
input port. Data is latched on the
rising edge of CLK.
·
· · ·
· · ·
·
· · ·
F29 F28 F27
F30 F29 F28
F31 F30 F29
· ·
· · ·
F16 F15 F14
F17 F16 F15
F18 F17 F16
VB11-0 — Field Filtering Data Input
01110
01111
10000
· · ·
· · ·
· · ·
F22 F21
F23 F22
F24 F23
· · ·
· · ·
· · ·
VB11-0 is the 12-bit registered data
input port used only when imple-
menting Odd and Even Field Filtering
(see Functional Description section for
a full discussion). Data is latched on
the rising edge of CLK.
COUT11-0 — Cascade Data Output
FIGURE 3. ACCUMULATOR FORMAT
COUT11-0 is a 12-bit cascade output
port. COUT11-0 on one device should
be connected to DIN11-0 of another
LF3330.
Accumulator Output
CF11-0 — Coefficient Input
CF11-0 is used to load data into the
coefficient banks and configuration/
control registers. Data present on
CF11-0 is latched into the LF Inter-
faceTM on the rising edge of CLK when
LD is LOW (see the LF InterfaceTM sec-
tion for a full discussion).
31 30 29
2
1
0
220 219 218
29 210 211
(Sign)
Controls
LD — Coefficient Load
When PAUSE is HIGH, the LF Inter-
faceTM loading sequence is halted
until PAUSE is returned to a LOW
state. This effectively allows the user
to load coefficients and control regis-
ters at a slower rate than the master
clock (see the LF InterfaceTM section
for a full discussion).
When LD is LOW, data on CF11-0 is
latched into the LF InterfaceTM on the
rising edge of CLK. When LD is
CA7-0 — Coefficient Address
HIGH, data can not be latched into the
LF InterfaceTM. When enabling the LF
InterfaceTM for data input, a HIGH to
LOW transition of LD is required in
order for the input circuitry to func-
tion properly. Therefore, LD must
be set HIGH immediately after power
up to ensure proper operation of the
input circuitry (see the LF InterfaceTM
section for a full discussion).
CA7-0 determines which row of data
in the coefficient banks is fed to the
multipliers. CA7-0 is latched into the
Coefficient Address Register on the
rising edge of CLK when CEN is
LOW.
CEN — Coefficient Address Enable
When CEN is LOW, data on CA7-0 is
latched into the Coefficient Address
Register on the rising edge of CLK.
When CEN is HIGH, data on CA7-0 is
not latched and the register’s contents
will not be changed.
Outputs
DOUT15-0 — Data Output
PAUSE — LF InterfaceTM Pause
DOUT15-0 is the 16-bit registered data
output port.
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
TABLE 2. CONFIGURATION REGISTER 0 – ADDRESS 200H
FIGURE 4. RSL CIRCUITRY
BITS
FUNCTION
DESCRIPTION
RSL3-0
4
DATA IN
32
11-0
Line Buffer Length
See Line Buffer Description Section
TABLE 3. CONFIGURATION REGISTER 1 – ADDRESS 201H
BITS
FUNCTION
DESCRIPTION
0
Line Buffer Mode
0 : Delay Mode
32
RND
1 : Recirculate Mode
0 : Normal Load
1
2
Line Buffer Load
1 : Parallel Load
Odd and Even Field
Filtering Port Enable
Odd and Even Field
0 : VB Port Disabled
1 : VB Port Enabled
0 : VB Line Buffer Disabled
32
3
5
SELECT
Filtering Line Buffer Enable 1 : VB Line Buffer Enabled
Reserved Must be set to “0”
11-4
TABLE 4. CONFIGURATION REGISTER 2 – ADDRESS 202H
16
BITS
FUNCTION
DESCRIPTION
0
Limit Enable
0 : Limiting Disabled
32
LIMIT
1 : Limiting Enabled
Must be set to “0”
11-1
Reserved
TABLE 5. CONFIGURATION REGISTER 3 – ADDRESS 203H
BITS
0
FUNCTION
Cascade Mode
DESCRIPTION
0 : First Device
RSL CIRCUITRY
16
DATA OUT
1 : Cascaded Device
Must be set to “0”
11-1
Reserved
the line buffers on the rising edge of
CLK. When SHEN is HIGH, data can cussion).
not be loaded into the input/cascade
registers or shifted through the line
buffers and their contents will not be
changed.
and limit sections for a complete dis-
ACC — Accumulator Control
When ACC is HIGH, the accumulator
is enabled for accumulation and the
accumulator output register is dis-
abled for loading. When ACC is
LOW, no accumulation is performed
and the accumulator output register is
enabled for loading. ACC is latched
on the rising edge of CLK.
OED — DOUT Output Enable
When OED is LOW, DOUT15-0 is
enabled for output. When OED is
HIGH, DOUT15-0 is placed in a high-
impedance state.
RSL3-0 — Round/Select/Limit Control
RSL3-0 determines which of the
sixteen user-programmable round/
select/limit registers are used in the
round/select/limit circuitry. A value
of 0 on RSL3-0 selects round/select/
limit register 0. A value of 1 selects
round/select/limit register 1 and so
on. RSL3-0 is latched on the rising
edge of CLK (see the round, select,
OEC — COUT Output Enable
SHEN — Shift Enable
When OEC is LOW, COUT15-0 is
enabled for output. When OEC is
HIGH, COUT15-0 is placed in a high-
impedance state.
SHEN enables or disables the loading
of data into the input/cascade regis-
ters and the line buffers. When SHEN
is LOW, data is loaded into the input/
cascade registers and shifted through
FUNCTIONAL DESCRIPTION
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
Line Buffers
the line buffers to be preloaded with
data in the amount of time it normally
takes to load a single line buffer.
Cascading
The maximum delay length of each
line buffer is 3076 cycles and the mini-
mum is 4 cycles. Configuration Reg-
ister 0 (CR0) determines the delay
length of the line buffers. The line
buffer length is equal to the value of
CR0 plus 4. A value of 0 for CR0 sets
the line buffer length to 4. A value of
3072 for CR0 sets the line buffer length
to 3076. Any values for CR0 greater
than 3072 are not valid.
A cascade port is provided to allow
cascading of multiple devices for more
filter taps (see Figure 5). COUT11-0
of one device should be connected to
DIN11-0 of another device. As many
LF3330s as desired may be cascaded
together. However, the outputs of the
LF3330s must be added together with
external adders.
Odd and Even Field Filtering
The LF3330 is capable of odd and even
field filtering. Bit 2 of Configuration
Register 1 enables the VB Data Input
port required for odd and even field
filtering. Bit 3 of the same configura-
tion register enables the line buffer in
the VB Data path. Line buffer length
is set to the length written to Configu-
ration Register 0. If line buffer parallel
load is enabled and odd and even field
filtering is enabled, the data for the VB
line buffer comes from the VB Data
Input port.
The first line buffer on a cascaded
device must have its length shortened
by two delays. This is to account for
the added delays of the input register
on the device and the cascade output
register from the previous LF3330. If
Bit 0 of Configuration Register 3 is
set to “1”, the length of the first line
buffer will be reduced by two. This
will make its effective length the same
as the other line buffers on the device.
If Bit 0 of Configuration Register 3 is
set to “0”, the length of the first line
buffer will be the same as the other
line buffers. When cascading devices,
the first LF3330 should have Bit 0 of
Configuration Register 3 set to “0”.
Any LF3330s cascaded after the first
LF3330 should have Bit 0 of Configu-
The line buffers have two modes of
operation: delay mode and recirculate
mode. Bit 0 of Configuration Register
1 determines which mode the line buf-
fers are in. In delay mode, the data
input to the line buffer is delayed by
an amount determined by CR0. In
recirculate mode, the output of the
line buffer is routed back to the input
of the line buffer allowing the line
buffer contents to be read multiple
times.
Interleaved Data
The LF3330 is capable of handling
interleaved data. The number of data
sets it can handle is determined by the
number of data values contained in a
video line. If the interleaved video
line has 3076 data values or less,
the LF3330 can handle it no matter
how many data sets are interleaved
together.
Bit 1 of Configuration Register 1
allows the line buffers to be loaded in
parallel. When Bit 1 is “1”, the input
register (DIN11-0) loads all seven line
buffers in parallel. This allows all
FIGURE 5.
MULTIPLE LF3330S CASCADED TOGETHER
LF3330
LF3330
LF3330
LF3330
12
COUT
DIN
COUT
DIN
COUT
DIN
DIN
LINE BUFFERS
LINE BUFFERS
LINE BUFFERS
LINE BUFFERS
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
RSL
RSL
RSL
RSL
CIRCUIT
CIRCUIT
CIRCUIT
CIRCUIT
LF3347
25
25
RSL
CIRCUIT
16
DATA OUT
29 TAP RESULT
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
ration Register 3 set to “1”. When
not cascading, Bit 0 of Configuration
Register 3 should be set to “0”.
ters, the device can support complex
rounding algorithms as well as stan-
dard half-LSB rounding. RSL3-0 deter- (see Table 1). There are sixteen select
mines which of the sixteen round reg- registers which control the select cir-
isters are used in the rounding opera- cuitry. Each select register is 5 bits
tion. A value of 0 on RSL3-0 selects
round register 0. A value of 1 selects
round register 1 and so on. RSL3-0
may be changed every clock cycle if
desired. This allows the rounding
algorithm to be changed every clock
cycle. This is useful when filtering
interleaved data. If rounding is not
desired, a round register should be
sent to DOUT15-0. The select circuitry
determines which 16 bits are passed
It is important to note that the first
multiplier on all cascaded devices
should not be used. This is because
the first multiplier does not have a line
buffer in front of it. The coefficient
value sent to the first multiplier on a
cascaded device should be “0”.
wide and user-programmable. RSL3-0
determines which of the sixteen select
registers are used in the select cir-
cuitry. Select register 0 is chosen by
loading a 0 on RSL3-0. Select register 1
is chosen by loading a 1 on RSL3-0 and
so on. RSL3-0 may be changed every
clock cycle if desired. This allows the
16-bit window to be changed every
Rounding
The filter output may be rounded by
adding the contents of one of the
sixteen round registers to the filter
output (see Figure 4). Each round
register is 32 bits wide and user-pro-
grammable. This allows the filter’s
output to be rounded to any precision
required. Since any 32-bit value may
be programmed into the round regis-
loaded with 0 and selected as the reg- clock cycle. This is useful when filter-
ister used for rounding. Round reg-
ister loading is discussed in the LF
InterfaceTM section.
ing interleaved data. Select register
loading is discussed in the LF Inter-
faceTM section.
Output Select
Limiting
The word width of the filter output is
32 bits. However, only 16 bits may be vided for the output of the filter.
An output limiting function is pro-
FIGURE 6. COEFFICIENT BANK LOADING SEQUENCE
COEFFICIENT SET 1
COEFFICIENT SET 2
COEFFICIENT SET 3
CLK
LD
W1
W2
W3
CF11-0
ADDR1 COEF0
COEF7 ADDR2 COEF0
COEF7 ADDR3 COEF0
COEF7
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
FIGURE 7. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE
CONFIG REG
SELECT REG
ROUND REGISTER
LIMIT REGISTER
CLK
LD
W1
W2
W3
W4
CF11-0
ADDR1 DATA1 ADDR2 DATA1 ADDR3 DATA1 DATA2 DATA3 DATA4 ADDR4 DATA1 DATA2 DATA3 DATA4
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
The limit registers determine the valid values into the device, the upper limit select, and limit. There are sixteen
range of output values when limiting
is enabled (Bit 0 in Configuration Reg- Limit register loading is discussed in
must be greater than the lower limit.
round registers. Each round register
is 32 bits wide. RSL3-0 determines
which round register is used for
rounding.
ister 2). There are sixteen 32-bit limit
registers. RSL3-0 determines which
limit register is used during the limit
operation. A value of 0 on RSL3-0
selects limit register 0. A value of 1
selects limit register 1 and so on. Each
limit register contains both an upper
and lower limit value. If the value
fed to the limiting circuitry is less than
the lower limit, the lower limit value
is passed as the filter output. If
the value fed to the limiting circuitry
is greater than the upper limit, the
upper limit value is passed as the filter
output. RSL3-0 may be changed every
clock cycle if desired. This allows the
limit range to be changed every clock
cycle. This is useful when filtering
interleaved data. When loading limit
the LF InterfaceTM section.
Coefficient Banks
There are sixteen select registers. Each
select register is 5 bits wide. RSL3-0
determines which select register is
used for the select circuitry.
The coefficient banks store the coef-
ficients which feed into the multipliers
in the filter. There is a separate bank
for each multiplier. Each bank can
hold 256 12-bit coefficients. The banks
There are sixteen limit registers. Each
limit register is 32 bits wide and stores
both an upper and lower limit value.
The lower limit is stored in bits 15-0
and the upper limit is stored in bits
31-16. RSL3-0 determines which limit
register is used for limiting when lim-
iting is enabled. Configuration and
control register loading is discussed in
the LF InterfaceTM section.
are loaded using the LF InterfaceTM
.
Coefficient bank loading is discussed
in the LF InterfaceTM section.
Configuration and Control Registers
The configuration registers determine
how the LF3330 operates. Tables 2
through 5 show the formats of the
four configuration registers. There are
three types of control registers: round,
LF InterfaceTM
The LF InterfaceTM is used to load
FIGURE 8. COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
COEFFICIENT SET 1
CLK
W1
PAUSE
LD
CF11-0
ADDR1
COEF0
COEF1
COEF7
W1: Configuration Register loaded with new data on this rising clock edge.
FIGURE 9. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
CONFIGURATION REGISTER
SELECT REGISTER
CLK
W1
W2
PAUSE
LD
CF11-0
ADDR1
DATA1
ADDR2
DATA1
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
data into the coefficient banks and
interface on CF11-0 is an address which or configuration/control registers (see
configuration/control registers. LD is determines what the interface is going Table 6). The nine least significant bits
used to enable and disable the LF
InterfaceTM. When LD goes LOW,
the LF InterfaceTM is enabled for data
input. The first value fed into the
to load. The three most significant
bits (CF11-9) determine if the LF
(CF8-0) are the address for whatever is
to be loaded (see Tables 7 through
InterfaceTM will load coefficient banks 9). For example, to load address 15
of the coefficient banks, the first data
FIGURE 10. ROUND REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
ROUND REGISTER
CLK
W1
PAUSE
LD
CF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Round Register loaded with new data on this rising clock edge.
FIGURE 11. LIMIT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
LIMIT REGISTER
CLK
W1
PAUSE
LD
CF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Limit Register loaded with new data on this rising clock edge.
TABLE 10. COEFFICIENT BANK LOADING FORMAT
CF11
CF10
CF9
0
CF8
0
CF7
CF6
0
CF5
0
CF4
CF3
1
CF2
CF1
1
CF0
0
1st Word - Address
2nd Word - Bank 0
3rd Word - Bank 1
4th Word - Bank 2
5th Word - Bank 3
6th Word - Bank 4
7th Word - Bank 5
8th Word - Bank 6
9th Word - Bank 7
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
1
0
1
1
1
1
0
0
0
0
1
0
0
0
1
0
1
0
1
1
0
1
0
0
0
0
1
1
0
0
1
1
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
value into the LF InterfaceTM should be
00FH. To load limit register 10, the
first data value should be E0AH. The
first address value should be loaded
into the interface on the same clock
cycle that latches the HIGH to LOW
transition of LD (see Figures 6 and 7).
TABLE 6. CF11-9 DECODE
11 10 9 DESCRIPTION
TABLE 7. ROUND REGISTERS
REGISTER
ADDRESS (HEX)
0
0
0
1
0
0
1
0
0
1
1
1
Coefficient Banks
Configuration Registers
Select Registers
0
1
A00
A01
Round Registers
14
15
A0E
A0F
1
1
1
Limit Registers
The next value(s) loaded into the
interface are the data value(s) which
will be stored in the bank or register
defined by the address value. When
loading coefficient banks, the interface
will expect eight values to be loaded
PAUSE is returned to a LOW. Figures
8 through 11 display the effects of
PAUSE while leading coefficient and
control data.
TABLE 8. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
0
1
600
601
into the device after the address value. Table 10 shows an example of loading
The eight values are coefficients 0
through 7. When loading configura-
tion or select registers, the interface
will expect one value after the address through 7: 210H, 543H, C76H, 9E3H,
value. When loading round or limit 701H, 832H, F20H, 143H. Table 11
registers, the interface will expect four shows an example of loading data
data into the coefficient banks. The
following data values are written into
address 10 of coefficient banks 0
14
15
60E
60F
values after the address value. Fig-
ures 6 and 7 show the data loading
sequences for the coefficient banks
and configuration/control registers.
into a configuration register. Data
value 003H is written into Configura-
tion Register 2. Table 12 shows an
example of loading data into a round
register. Data value 7683F4A2H is
written into round register 12. Table
13 shows an example of loading data
into a select register. Data value 00FH
is loaded into select register 2. Table
14 shows an example of loading data
TABLE 9. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
0
1
E00
E01
PAUSE allows the user to effectively
slow the rate of data loading through
the LF InterfaceTM. When PAUSE is
HIGH, the LF InterfaceTM is held until
14
15
E0E
E0F
TABLE 11. CONFIGURATION REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
CF6
0
CF5
0
CF4
CF3
0
CF2
0
CF1
1
CF0
0
1st Word - Address
2nd Word - Data
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
TABLE 12. ROUND REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
0
CF6
0
CF5
0
CF4
0
CF3
1
CF2
1
CF1
0
CF0
0
1st Word - Address
2nd Word - Data
3rd Word - Data
4th Word - Data
5th Word - Data
1
0
1
0
R
R
R
R
1
0
1
0
0
0
1
0*
0
R
R
R
R
1
1
1
1
0
1
0
R
R
R
R
1
0
0
0
0
0
1
1
R
R
R
R
0**
1
1
1
0
1
1
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
into limit register 7. Data value
3B60H is loaded as the lower limit and
72A4H is loaded as the upper limit.
is done by setting LD HIGH on the
clock cycle after the clock cycle which
latches the last data value. It is impor-
tant that the LF InterfaceTM remain dis-
abled when not loading data into it.
loaded with data until all data values
for the specified address are loaded
into the LF InterfaceTM. In other
words, the coefficient banks are not
written to until all eight coefficients
have been loaded into the LF Inter-
faceTM. A round register is not written
to until all four data values are loaded.
It takes 9S clock cycles to load S coef-
ficient sets into the device. Therefore,
it takes 2304 clock cycles to load all
256 coefficient sets. Assuming an 83
MHz clock rate, all 256 coefficient sets
can be updated in less than 27.7 µs,
which is well within vertical blanking
time. It takes 5S clock cycles to load
S round or limit registers. Therefore,
it takes 160 clock cycles to update all
round and limit registers. Assuming
an 83 MHz clock rate, all round/limit
registers can be updated in 1.92 µs.
After the last data value is loaded, the
interface will expect a new address
value on the next clock cycle. After
the next address value is loaded, data
loading will begin again as previously
discussed. As long as data is loaded
into the interface, LD must remain
LOW. After all desired coefficient
banks and configuration/control reg-
isters are loaded with data, the LF
InterfaceTM must be disabled. This
The coefficient banks and
configuration/control registers are not
TABLE 13. SELECT REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
0
CF6
0
CF5
0
CF4
0
CF3
0
CF2
0
CF1
1
CF0
0
1st Word - Address
2nd Word - Data
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
TABLE 14. LIMIT REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
0
CF6
0
CF5
0
CF4
0
CF3
0
CF2
1
CF1
1
CF0
1
1st Word - Address
2nd Word - Data
3rd Word - Data
4th Word - Data
5th Word - Data
1
1
1
0
R
R
R
R
0
1
1
0
0
0
0
0
R
R
R
R
0*
1
0
1
1
1
0
1
1
R
R
R
R
0
1
0
0
1
0
0
R
R
R
R
0**
1
1
1
0
0
1
0
R = Reserved. Must be set to “0”.
* This bit represents the MSB of the Lower Limit.
** This bit represents the MSB of the Upper Limit.
Video Imaging Products
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ............................................................................................................ –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5V to +4.5V
Input signal with respect to ground .......................................................................................... –0.5V to 5.5 V
Signal applied to high impedance output ................................................................................. –0.5V to 5.5 V
Output current into low outputs ............................................................................................................ 25 mA
Latchup current ............................................................................................................................... > 400 mA
ESD Classification (MIL-STD-883E METHOD 3015.7) ....................................................................... Class 3
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
3.00V ≤ VCC ≤ 3.60V
3.00V ≤ VCC ≤ 3.60V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
Min
Typ
Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = Min., IOH = –4 mA
VCC = Min., IOL = 8.0 mA
2.4
V
Output Low Voltage
Input High Voltage
Input Low Voltage
0.4
5.5
V
V
2.0
0.0
VIL
(Note 3)
0.8
V
IIX
Input Current
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±10
±10
µA
µA
IOZ
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
Input Capacitance
Output Capacitance
ICC1
ICC2
CIN
COUT
240 mA
(Note 7)
1
10
10
mA
pF
pF
TA = 25°C, f = 1 MHz
TA = 25°C, f = 1 MHz
Video Imaging Products
9/19/2005–LDS.3330-N
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LF3330–
*
*
25
18
15
12
Symbol Parameter
Min
Max
Min
Max
Min
Max
Min
Max
tCYC
tPW
tS
Clock Cycle Time
25
18
15
12
Clock Pulse Width
10
8
8
6
7
5
5
4
Input Setup Time
tH
Input Hold Time
0.5
0.5
0.5
0.5
tDD
tDC
tDIS
tENA
Data Output Delay
13
13
15
15
9
9
10
10
12
12
8
9
Cascade Data Output Delay
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
11
11
10
10
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LF3330–
*
*
*
15
25
18
Symbol Parameter
Min
Max
Min
Max
Min
Max
tCYC
tPW
tS
Clock Cycle Time
25
18
15
Clock Pulse Width
10
8
8
6
7
5
Input Setup Time
tH
Input Hold Time
0.5
0.5
0.5
tDD
tDC
tDIS
tENA
Data Output Delay
13
13
15
15
9
9
10
10
12
12
Cascade Data Output Delay
Three-State Output Disable Delay (Note 11)
Three-State Output Enable Delay (Note 11)
11
11
SWITCHING WAVEFORMS:
DATA I/O
1
2
3
4
5
6
7
CLK
tH
tPW
tS
tPW
DIN11-0
CA7-0
DINN
CAN
VBN
DINN+1
CAN+1
VBN+1
tCYC
VB11-0
CONTROLS
(Except OE)
OE
DOUT15-0
COUT11-0
tENA
tDIS
tDD
tDC
HIGH IMPEDANCE
DOUTN-1
COUTN-1
DOUTN
HIGH IMPEDANCE
COUTN
*DISCONTINUED SPEED GRADE
Video Imaging Products
9/19/2005–LDS.3330-N
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
COMMERCIAL OPERATING RANGE (0°C to +70°C)
LF3330–
*
*
25
18
15
12
Symbol Parameter
Min
Max
Min
Max
Min
Max
Min
Max
tCFS
tCFH
tLS
Coefficient Input Setup Time
Coefficient Input Hold Time
Load Setup Time
8
6
5
5
0
8
0
7
0
6
0
4
tLH
Load Hold Time
0
0
0
0
tPS
PAUSE Setup Time
PAUSE Hold Time
8
6
5
4
tPH
0.5
0.5
0.5
0.5
MILITARY OPERATING RANGE (–55°C to +125°C)
LF3330–
*
*
*
25
18
15
Symbol Parameter
Min
Max
Min
Max
Min
Max
tCFS
tCFH
tLS
Coefficient Input Setup Time
Coefficient Input Hold Time
Load Setup Time
8
6
5
0
8
0
7
0
6
tLH
Load Hold Time
0
0
0
tPS
PAUSE Setup Time
PAUSE Hold Time
8
6
5
tPH
0.5
0.5
0.5
TM
SWITCHING WAVEFORMS:
LF INTERFACE
1
2
3
4
5
6
CLK
tLS
tPW
tPW
tLH
tCYC
LD
tPS
tPH
PAUSE
tCFH
tCFS
CF11–0
ADDRESS
CF0
CF1
CF2
*DISCONTINUED SPEED GRADE
Video Imaging Products
9/19/2005–LDS.3330-N
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
NOTES
1. Maximum Ratings indicate stress but not 100% tested.
specifications only. Functional oper-
case operation of any device always
provides data within that time.
9. AC specifications are tested with
ation of these products at values
beyond those indicated in the Operat-
ing Conditions table is not implied.
Exposure to maximum rating condi-
tions for extended periods may affect
reliability.
input transition times less than 3 ns, 11. For the tENA test, the transition is
output reference levels of 1.5 V (except measured to the 1.5 V crossing point
tDIS test), and input levels of nominally with datasheet loads.
0to 3.0 V. Output loading may be a tDIS test, the transition is measured
resistive divider which provides for to the ±200mV level from the mea-
specified IOH and IOL at an output sured steady-state output voltage with
For
the
2. The products described by this spec- voltage of VOH min and VOL max ±10mA loads. The balancing voltage,
ification include internal circuitry respectively. Alternatively, a diode VTH, is set at 3.0 V for Z-to-0 and 0-to-Z
designed to protect the chip from bridge with upper and lower current tests, and set at 0 V for Z-to-1 and
damaging substrate injection currents sources of IOH and IOL respectively, 1-to-Z tests.
and accumulations of static charge. and a balancing voltage of 1.5 V may
Nevertheless, conventional precau- be used. Parasitic capacitance is 30 pF
tions should be observed during stor- minimum, and may be distributed.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
age, handling, and use of these circuits
This device has high-speed outputs
in order to avoid exposure to excessive
capable of large instantaneous current
electrical stress values.
pulses and fast turn-on/turn-off times.
3. This device provides hard clamping As a result, care must be exercised in
of transient undershoot. Input levels the testing of this device. The following
below ground will be clamped begin- measures are recommended:
ning at –0.6V. The device can with-
a. A 0.1 µF ceramic capacitor should
stand indefinite operation with inputs
S1
be installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device
VCC and the tester common, and device
ground and tester common.
DUT
or outputs in the range of –0.5 V to
+5.5 V. Device operation will not be
adversely affected, however, input
current levels will be well in excess
of 100 mA.
IOL
VTH
CL
IOH
4. Actual test conditions may vary
from those designated but operation is
guaranteed as specified.
FIGURE B.THRESHOLD LEVELS
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
tENA
tDIS
OE
0
1.5 V
1.5 V
5. Supply current for a given applica-
tion can be accurately approximated
Z
Z
3.0V Vth
c. Input voltages on a test fixture
should be adjusted to compensate for
inductive ground and VCC noise to
maintain required DUT input levels
relative to the DUT ground pin.
1.5 V
1.5 V
V
OL
*
*
0.2 V
0.2 V
0
1
Z
Z
by:
2
NCV F
V
OH
1
0V Vth
4
V
OL
*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH
* Measured VOH with IOH = –10mA and IOL = 10mA
where
10. Each parameter is shown as a
minimum or maximum value. Input
requirements are specified from the
point of view of the external system
driving the chip. Setup time, for
example, is specified as a minimum
since the external system must supply
at least that much time to meet the
worst-case requirements of all parts.
Responses from the internal circuitry
are specified from the point of view of
the device. Output delay, for example,
is specified as a maximum since worst-
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with outputs changing every
cycle and no load, at a 40 MHz clock
rate.
7. Tested with all inputs within 0.1V of
VCC or Ground, no load.
8. These parameters are guaranteed
Video Imaging Products
9/19/2005–LDS.3330-N
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LF3330
DEVICES INCORPORATED
Vertical Digital Image Filter
ORDERING INFORMATION
100-pin
GND
ACC
RSL0
RSL1
RSL2
RSL3
CA0
CA1
CA2
CA3
CA4
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OED
VCC
CF0
CF1
CF2
CF3
CF4
CF5
CF6
CF7
CF8
CF9
CF10
CF11
LD
PAUSE
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CA5
CA6
CA7
Top
View
CEN
VCC
GND
SHEN
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
DIN10
DIN11
GND
COUT0
COUT1
COUT2
COUT3
COUT4
COUT5
COUT6
COUT7
COUT8
COUT9
COUT10
COUT11
Plastic Quad Flatpack
(Q2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
LF3330QC15
15 ns
12 ns
12 ns
LF3330QC12
LF3330QC12G (GREEN)
LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and
to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current
and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed
the purchase price of LOGIC Devices products. LOGIC Devices products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety
applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in
life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user.
Video Imaging Products
9/19/2005–LDS.3330-N
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