LTC6406CUD-TRPBF [Linear]
3GHz, Low Noise, Rail-to-Rail Input Differential Amplifi er/Driver; 3GHz的，低噪声，轨至轨输入差分功率放大器器/驱动器
| 型号： | LTC6406CUD-TRPBF |
| 厂家： | 
Linear |
| 描述： | 3GHz, Low Noise, Rail-to-Rail Input Differential Amplifi er/Driver |
| 文件： | 总24页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6406
3GHz, Low Noise,
Rail-to-Rail Input Differential
Amplifier/Driver
FEATURES
DESCRIPTION
The LTC®6406 is a very low noise, low distortion, fully
differential input/output amplifier optimized for 3V, single
supplyoperation.TheLTC6406inputcommonmoderange
is rail-to-rail, while the output common mode voltage is
independently adjustable by applying a voltage on the
n
Low Noise: 1.6nV/√Hz RTI
n
Low Power: 18mA at 3V
n
Low Distortion (HD2/HD3):
–80dBc/–69dBc at 50MHz, 2V
P-P
P-P
–104dBc/–90dBc at 20MHz, 2V
n
n
n
n
n
n
n
n
Rail-to-Rail Differential Input
V
pin. This makes the LTC6406 ideal for level-shifting
OCM
2.7V to 3.5V Supply Voltage Range
Fully Differential Input and Output
Adjustable Output Common Mode Voltage
800MHz –3dB Bandwidth with A = 1
Gain-Bandwidth Product: 3GHz
Low Power Shutdown
signalswithawidecommonmoderangefordriving12-bit
to 16-bit single supply, differential input ADCs.
A3GHzgain-bandwidthproductresultsin70dBlinearityfor
50MHzinputsignals.TheLTC6406isunity-gainstableand
the closed-loop bandwidth extends from DC to 800MHz.
The output voltage swing extends from near ground to
2V, to be compatible with a wide range of ADC converter
input requirements. The LTC6406 draws only 18mA, and
has a hardware shutdown feature which reduces current
consumption to 300μA.
V
Available in 8-Lead MSOP and Tiny 16-Lead
3mm × 3mm × 0.75mm QFN Packages
APPLICATIONS
n
Differential Input ADC Driver
TheLTC6406isavailableinacompact3mm×3mm16-pin
leadless QFN package as well as an 8-lead MSOP package,
and operates over a –40°C to 85°C temperature range.
n
Single-Ended to Differential Conversion
n
Level-Shifting Ground-Referenced Signals
n
Level-Shifting V -Referenced Signals
CC
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
High Linearity Direct Conversion Receivers
TYPICAL APPLICATION
ADC Driver: Single-Ended Input to Differential Output with
Common Mode Level Shifting
Harmonic Distortion vs Frequency
–30
1.8pF
V
V
R
V
= 3V
S
= V
= 1.25V
ICM
OCM
LOAD
OUTDIFF
–40
–50
= 800Ω
= 2V
V
IN
150Ω
150Ω
3V
P-P
DIFFERENTIAL INPUTS
3V
–60
2ND, R = R = 150Ω
I
F
V
DD
2ND, R = R = 500Ω
I
F
–70
+INA
LTC22xx ADC
–INA
– +
LTC6406
3RD, R = R = 150Ω
I
F
V
OCM
3RD, R = R = 500Ω
I
F
–80
1.25V
+ –
–90
GND
–100
–110
150Ω
150Ω
1.8pF
1
10
FREQUENCY (MHz)
100
6406 TA01
6406 TA01b
6406fb
1
LTC6406
ABSOLUTE MAXIMUM RATINGS (Note 1)
+
–
Total Supply Voltage (V to V )................................3.5V
Specified Temperature Range (Note 5)
Input Current
LTC6406C ................................................ 0°C to 70°C
LTC6406I.............................................. –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
+IN, –IN, V
, SHDN, V (Note 2)............... 10mA
TIP
OCM
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range
(Note 4) ............................................... –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
16 15 14 13
–
TOP VIEW
SHDN
1
2
3
4
12
11
10
9
V
V
V
V
–IN 1
8 +IN
+
+
+
–
9
V
V
2
3
4
7 SHDN
OCM
17
+
–
–
V
6 V
V
+OUT
5 –OUT
V
OCM
MS8E PACKAGE
8-LEAD PLASTIC MSOP
5
6
7
8
T
= 150°C, θ = 40°C/W, θ = 10°C/W
JA JC
JMAX
–
EXPOSED PAD (PIN 9) IS V , MUST BE SOLDERED TO PCB
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
T
= 150°C, θ = 68°C/W, θ = 4.2°C/W
JA JC
JMAX
–
EXPOSED PAD (PIN 17) IS V , MUST BE SOLDERED TO PCB
ORDER INFORMATION
SPECIFIED
TEMPERATURE RANGE
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
LTC6406CUD#PBF
LTC6406IUD#PBF
LTC6406CMS8E#PBF
LTC6406IMS8E#PBF
LTC6406CUD#TRPBF
LTC6406IUD#TRPBF
LTC6406CMS8E#TRPBF
LTC6406IMS8E#TRPBF
LCTC
LCTC
LTCTB
LTCTB
0°C to 70°C
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
8-Lead Plastic MSOP
–40°C to 85°C
0°C to 70°C
8-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6406fb
2
LTC6406
DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = 1.25V, VSHDN = open,
RBAL = 100kΩ, RI = 150Ω, RF = 150Ω (0.1% Resistors), CF = 1.8pF (See Figure 1) unless otherwise noted. VS is defined as (V+ – V–).
VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
Differential Offset Voltage (Input Referred)
V
ICM
V
ICM
V
ICM
= 3V (Note 12)
= 1.25V
= 0V (Note 12)
1
0.25
1
5
3.5
5
mV
mV
mV
OSDIFF
l
l
l
Differential Offset Voltage Drift (Input Referred)
Input Bias Current (Note 6)
V
V
V
= 3V (Note 12)
= 1.25V
12
1
μV/°C
μV/°C
μV/°C
ΔV
/ΔT
OSDIFF
ICM
ICM
ICM
= 0V (Note 12)
7
I
I
V
ICM
V
ICM
V
ICM
= 3V
= 1.25V
= 0V
6
μA
μA
μA
B
l
l
–24
–9
–1
3
–17
Input Offset Current (Note 6)
Input Resistance
V
ICM
V
ICM
V
ICM
= 3V
= 1.25V
= 0V
1
1
1
μA
μA
μA
OS
R
IN
Common Mode
Differential Mode
130
3
kΩ
kΩ
C
IN
Input Capacitance
Differential
1
pF
e
n
Differential Input Referred Noise Voltage Density
f = 1MHz, Not Including
1.6
nV/√Hz
R /R Noise
I
F
i
Input Noise Current Density
f = 1MHz, Not Including
R /R Noise
2.5
9
pA/√Hz
n
I
F
e
Input Referred Common Mode Output Noise Voltage Density f = 1MHz
(Note 7) Input Signal Common Mode Range Op-Amp Inputs
nV/√Hz
nVOCM
–
+
l
l
V
V
V
V
ICMR
CMRRI
(Note 8)
Input Common Mode Rejection Ratio
(Input Referred) ΔV /ΔV
V
from 0V to 3V
50
50
55
55
65
70
75
65
dB
ICM
ICM
OSDIFF
l
l
l
CMRRIO
(Note 8)
Output Common Mode Rejection Ratio (Input Referred)
ΔV /ΔV
V
from 0.5V to 2V
dB
dB
dB
OCM
OCM
OSDIFF
PSRR
(Note 9)
Differential Power Supply Rejection
(ΔV /ΔV
V = 2.7V to 3.5V
S
)
OSDIFF
S
PSRRCM
(Note 9)
Output Common Mode Power Supply Rejection
(ΔV /ΔV
V = 2.7V to 3.5V
S
)
OSCM
S
l
l
G
V
V
from 0.5V to 2V
1
V/V
%
Common Mode Gain (ΔV
/ΔV
)
OCM
CM
OCM
OUTCM
Common Mode Gain Error 100 • (G – 1)
from 0.5V to 2V
0.4
0.8
ΔG
CM
OCM
CM
BAL
Output Balance (ΔV
/ΔV
)
ΔV
OUTDIFF
= 2V
OUTCM
OUTDIFF
l
l
–57
–65
–45
–45
dB
dB
Single-Ended Input
Differential Input
l
l
l
V
Common Mode Offset Voltage (V
– V )
OCM
6
15
mV
μV/°C
V
OSCM
OUTCM
Common Mode Offset Voltage Drift
15
ΔV
/ΔT
OSCM
V
Output Signal Common Mode Range
0.5
2
OUTCMR
(Note 7)
(Voltage Range for the V
Pin)
OCM
l
l
R
Input Resistance, V
Pin
12
18
24
kΩ
INVOCM
OCM
V
V
Self-Biased Voltage at the V
Pin
V = Open
OCM
1.15
1.25
1.35
V
OCM
OUT
OCM
l
l
Output Voltage, High, +OUT/–OUT Pins
V = 3.3V, I = 0
2.2
2
2.35
2.15
V
V
S
L
V = 3.3V, I = –20mA
S
L
l
l
l
V = 3V, I = 0
2
1.95
1.7
2.05
2
1.85
V
V
V
S
L
V = 3V, I = –5mA
S
L
V = 3V, I = –20mA
S
L
l
l
l
Output Voltage, Low, +OUT/–OUT Pins
V = 3V, I = 0
0.23
0.34
0.75
0.33
0.4
0.85
V
V
V
S
L
V = 3V, I = 5mA
S
L
V = 3V, I = 20mA
S
L
6406fb
3
LTC6406
DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = 1.25V, VSHDN = open,
RBAL = 100kΩ, RI = 150Ω, RF = 150Ω (0.1% Resistors), CF = 1.8pF (See Figure 1) unless otherwise noted. VS is defined as (V+ – V–).
VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
55
MAX
UNITS
mA
dB
l
I
Output Short-Circuit Current, +OUT/–OUT Pins (Note 10)
Large-Signal Open Loop Voltage Gain
Supply Voltage Range
35
SC
A
VOL
90
l
l
l
l
l
l
V
S
2.7
3.5
22
V
I
I
Supply Current
18
300
100
0.7
mA
μA
S
Supply Current in Shutdown
SHDN Pull-Up Resistor
SHDN Input Logic Low
SHDN Input Logic High
Turn-On Time
V
V
= 0V
500
140
SHDN
SHDN
R
= 0V to 0.5V
60
kΩ
V
SHDN
IL
SHDN
V
V
0.4
2.25
200
50
2.55
V
IH
t
t
ns
ns
ON
OFF
Turn-Off Time
AC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = 1.25V, VSHDN = open,
RI = 150Ω, RF = 150Ω (0.1% Resistors), CF = 1.8pF, RLOAD = 400Ω (See Figure 2) unless otherwise noted. VS is defined as (V+ – V–).
VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
SR
PARAMETER
CONDITIONS
MIN
TYP
630
3
MAX
UNITS
V/μS
GHz
Slew Rate
Differential Output
GBW
Gain-Bandwidth Product
–3dB Frequency (See Figure 2)
50MHz Distortion
Differential Input, V
(Note 13)
f
= 30MHz
TEST
f
l
l
500
800
MHz
–3dB
V
V
V
= 1.25V, V = 3V
S
OCM
2nd Harmonic
3rd Harmonic
= 2V
–77
–65
dBc
dBc
OUTDIFF
P-P
–55
= 1.25V, V = 3V, R
2nd Harmonic
3rd Harmonic
= 800Ω
= 800Ω,
OCM
S
LOAD
LOAD
–85
–72
dBc
dBc
= 1.25V, V = 3V, R
OCM
I
S
R = R = 500Ω
F
–80
–69
dBc
dBc
2nd Harmonic
3rd Harmonic
50MHz Distortion
Single-Ended Input, V
(Note 13)
V
= 1.25V, V = 3V, R
= 800Ω,
OCM
I
S
LOAD
= 2V
P-P
R = R = 500Ω
OUTDIFF
F
–69
–73
dBc
dBc
2nd Harmonic
3rd Harmonic
3rd-Order IMD at 49.5MHz, 50.5MHz
V
= 2V Envelope,
–65
dBc
OUTDIFF
LOAD
P-P
R
= 800Ω
OIP3 at 50MHz (Note 11)
Settling Time
36.5
dBm
R
= 800Ω
= 2V Step
LOAD
t
V
OUTDIFF
S
1% Settling
7
11
ns
ns
0.1% Settling
NF
Noise Figure at 50MHz
14.1
7.5
dB
dB
Shunt-Terminated to 50Ω, R = 50Ω
IN
S
Z
= 200Ω (R = 100Ω, R = 300Ω)
I F
6406fb
4
LTC6406
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
both V
= 1.25V and at the Electrical Characteristics table limits to verify
OCM
that the common mode offset (V
10mV from the V
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of
) has not deviated by more than
OSCM
= 1.25V case.
OCM
Note 2: Input pins (+IN, –IN, V
, SHDN and V ) are protected by
OCM
TIP
steering diodes to either supply. If the inputs should exceed either supply
voltage, the input current should be limited to less than 10mA. In addition,
the inputs +IN, –IN are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1.4V, the input current should be limited
to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely. Long-term application of output currents in excess of the
absolute maximum ratings may impair the life of the device.
the change in the voltage at the V
pin to the change in differential
OCM
input referred voltage offset. This specification is strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is difficult to measure actual amplifier performance (see the
“Effects of Resistor Pair Mismatch” in the Applications Information section
of this data sheet). For a better indicator of actual amplifier performance
independent of feedback component matching, refer to the PSRR
specification.
Note 9: Differential power supply rejection (PSRR) is defined as the ratio
of the change in supply voltage to the change in differential input referred
voltage offset. Common mode power supply rejection (PSRRCM) is
defined as the ratio of the change in supply voltage to the change in the
Note 4: The LTC6406C/LTC6406I are guaranteed functional over the
operating temperature range –40°C to 85°C.
Note 5: The LTC6406C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6406C is designed, characterized, and expected
to meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6406I is guaranteed to meet
specified performance from –40°C to 85°C.
common mode offset, V
– V
.
OUTCM
OCM
Note 10: Extended operation with the output shorted may cause the
junction temperature to exceed the 150°C limit.
Note 6: Input bias current is defined as the average of the input currents
Note 11: Because the LTC6406 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power can be very small in many applications. In
order to compare the LTC6406 with “RF style” amplifiers that require 50Ω
load, the output voltage swing is converted to dBm as if the outputs were
flowing into the inputs (–IN, and +IN). Input offset current is defined as the
+
–
difference between the input currents (I = I – I ).
OS
B
B
Note 7: Input common mode range is tested using the test circuit of
Figure 1 by taking three measurements of differential gain with a 1V DC
driving a 50Ω load. For example, 2V output swing is equal to 10dBm
differential output with V
the differential gain has not deviated from the V
than 0.5%, and that the common mode offset (V
= 0V; V
= 1.25V; V
= 3V, verifying that
= 1.25V case by more
) has not deviated
P-P
ICM
ICM
ICM
using this convention.
ICM
Note 12: Includes offset/drift induced by feedback resistors mismatch. See
the Applications Information section for more details.
OSCM
from the common mode offset at V
= 1.25V by more than 20mV.
ICM
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the V pin and testing at
Note 13: QFN package only. Refer to data sheet curves for MSOP package
numbers.
OCM
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Input Referred
Offset Voltage vs Input Common
Mode Voltage
Differential Input Referred Offset
Voltage vs Temperature
Common Mode Offset Voltage
vs Temperature
1.2
1.0
0.8
0.6
0.4
0.2
0
7
6
5
4
3
2
1
0
2.0
1.5
T
T
T
T
T
= –40°C
= 0°C
= 25°C
= 70°C
= 85°C
A
A
A
A
A
1.0
V
V
V
= 3V
S
= 1.25V
= 1.25V
F
OCM
ICM
0.5
R = R = 150Ω
I
0
FIVE TYPICAL UNITS
–0.5
–1.0
–1.5
–2.0
V
V
= 3V
OCM
S
V
V
V
= 3V
= 1.25V
S
= 1.25V
= 1.25V
R = R = 150Ω
OCM
ICM
I
F
0.1% FEEDBACK NETWORK RESISTORS
TYPICAL UNIT
FIVE TYPICAL UNITS
–0.2
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
0
0.5
1.0
1.5
2.0
2.5
3.0
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT COMMON MODE VOLTAGE (V)
6406 G01
6406 G03
6406 G02
6406fb
5
LTC6406
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Supply Current
vs Supply Voltage
Supply Current vs Supply Voltage
Supply Current vs SHDN Voltage
20
15
10
5
500
450
400
350
300
250
200
150
100
50
20
15
10
5
T
A
T
A
T
A
T
A
T
A
= –40°C
= 0°C
= 25°C
= 70°C
= 85°C
T
A
T
A
T
A
T
A
T
A
= –40°C
= 0°C
= 25°C
= 70°C
= 85°C
T
A
T
A
T
A
T
A
T
A
= –40°C
= 0°C
= 25°C
= 70°C
= 85°C
–
V
= 3V
V
= V
V
= OPEN
S
SHDN
SHDN
0
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
SHDN VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6406 G05
6406 G06
6406 G04
Input Noise Density vs Input
Common Mode Voltage
Differential Slew Rate
vs Temperature
Input Noise Density vs Frequency
100
10
1
100
10
1
4
3
2
1
0
4
3
2
1
0
650
630
610
590
570
550
V
= 3V
V
V
= 3V
ICM
S
S
= 1.25V
i
n
e
n
i
n
V
= 3V
S
e
n
NOISE MEASURED AT f = 1MHz
0.5 1.0 1.5 2.0
INPUT COMMON MODE VOLTAGE (V)
0
2.5
3.0
–50
–25
0
25
50
75
100
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
6406 G09
6406 G08
6406 G07
Differential Output Impedance
vs Frequency
CMRR vs Frequency
Differential PSRR vs Frequency
80
70
60
5O
40
30
20
10
1000
100
10
80
70
60
5O
40
30
20
10
V
= 3V
F
S
I
R = R = 150Ω
1
V
V
= 3V
OCM
S
0.1
0.01
= 1.25V
R = R = 150Ω, C = 1.8pF
I
F
F
0.1% FEEDBACK NETWORK RESISTORS
V = 3V
S
1
10
100
1000 2000
1
10
100
1000 2000
1
10
100
1000 2000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6406 G11
6406 G10
6406 G12
6406fb
6
LTC6406
TYPICAL PERFORMANCE CHARACTERISTICS (QFN Package)
Small-Signal Step Response
Large-Signal Step Response
Output Overdrive Response
2.5
2.0
1.5
1.0
0.5
0
–OUT
+OUT
–OUT
20mV/DIV
0.2V/DIV
–OUT
+OUT
+OUT
6406 G15
6406 G13
6406 G14
100ns/DIV
10ns/DIV
10ns/DIV
V
V
= 3V
V
V
= 3V
V
= 3V
S
S
S
= 1.25V
= V
ICM
= 1.25V
R
V
= 400Ω
LOAD
OCM
OCM
LOAD
R
= 200Ω TO GROUND PER OUTPUT
R
I
= 400Ω
= 2V , DIFFERENTIAL
IN P-P
LOAD
R = R = 150Ω, C = 1.8pF
F
F
C
V
= 0pF
L
IN
= 200mV , DIFFERENTIAL
P-P
Frequency Response
vs Closed-Loop Gain
Frequency Response
vs Load Capacitance
Frequency Response vs Input
Common Mode Voltage
50
40
30
10
5
C
C
C
= 0pF
= 2pF
= 3pF
L
L
L
L
L
20
10
30
C = 4.7pF
0
C
= 10pF
20
V
ICM
V
ICM
V
ICM
V
ICM
V
ICM
= 0V
0
–5
= 0.5V
= 1.25V
= 2V
10
–10
–20
–30
–40
–50
–60
–10
–15
–20
–25
–30
–35
0
= 3V
V
V
= 3V
–10
–20
–30
–40
S
A
A
A
A
A
A
= 1
= V
= 1.25V
ICM
V
V
V
V
V
V
OCM
LOAD
= 2
R
= 400Ω
= 5
R = R = 150Ω, C = 1.8pF
V
V
= 3V
I
F
F
S
= 10
= 20
= 100
V
V
= 3V
CAPACITOR VALUES ARE FROM EACH
OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
= 1.25V
= 400Ω
S
OCM
LOAD
= V
= 1.25V
ICM
R
OCM
R
= 400Ω
R = R = 150Ω, C = 1.8pF
I F F
LOAD
–50
1
10
100
1000 2000
1
10
100
1000 2000
1
10
100
1000 2000
FREQUENCY (MHz)
(V/V) R (Ω) (Ω) C (pF)
F
FREQUENCY (MHz)
FREQUENCY (MHz)
6406 G17
6406 G18
A
R
V
I
F
1
2
5
10
20
100
150
150
150
150
150
150
150
300
750
1.5k
3k
1.8
1.8
0.7
0.3
0.2
0
15k
6406 G16
6406fb
7
LTC6406
TYPICAL PERFORMANCE CHARACTERISTICS (QFN Package)
Harmonic Distortion
vs Input Common Mode Voltage
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
–30
–40
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
2ND, R = R = 150Ω
V
V
R
V
= 3V
V
V
f
= 3V
S
OCM
I
F
S
2ND, R = R = 500Ω
= V
= 1.25V
= V
= 1.25V
ICM
I
F
OCM
LOAD
OUTDIFF
ICM
3RD, R = R = 150Ω
= 800Ω
= 2V
= 50MHz
I
F
IN
3RD, R = R = 500Ω
R = 800Ω
LOAD
I
F
P-P
–50
DIFFERENTIAL INPUTS
R = R = 150Ω
I F
DIFFERENTIAL INPUTS
–60
2ND, R = R = 150Ω
I
F
2ND, R = R = 500Ω
I
F
–70
3RD, R = R = 150Ω
I
F
3RD
3RD, R = R = 500Ω
I
F
–80
–90
V
V
IN
R
= 3V
S
OCM
= 1.25V
2ND
8
–100
–110
f
= 50MHz
V
= 2V
OUTDIFF P-P
= 800Ω DIFFERENTIAL INPUTS
LOAD
1
10
FREQUENCY (MHz)
100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.0
3.0
–4
(0.4V
–2
0
2
4
6
10
(2V
)
)
)
)
INPUT COMMON MODE VOLTAGE (V)
P-P
INPUT AMPLITUDE (dBm)
P-P
6406 G19
6406 G20
6406 G21
Harmonic Distortion
vs Input Common Mode Voltage
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
–30
–40
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
V
V
= 3V
V
= 2V
V
V
f
= 3V
S
OCM
S
OUTDIFF
P-P
=V
=1.25V SINGLE-ENDED INPUT
= V
= 1.25V
ICM
OCM
LOAD
ICM
R
= 800Ω
= 50MHz
LOAD
IN
R
= 800Ω
–50
R = R = 500Ω
SINGLE-ENDED INPUT
I
F
2ND, R = R = 150Ω
2ND
I
F
–60
2ND, R = R = 500Ω
I
F
3RD, R = R = 150Ω
I
F
–70
3RD, R = R = 500Ω
I
F
2ND
V
V
IN
R
= 3V
S
3RD
–80
= 1.25V
OCM
f
= 50MHz
–90
3RD
= 800Ω
LOAD
R = R = 500Ω
V
I
F
–100
–110
= 2V
OUTDIFF
P-P
SINGLE-ENDED INPUT
0.5 1.0 1.5
INPUT COMMON MODE VOLTAGE (V)
1
10
FREQUENCY (MHz)
100
0
2.0
2.5
–4
(0.4V
–2
0
2
4
6
8
10
(2V
)
P-P
INPUT AMPLITUDE (dBm)
P-P
6406 G22
6406 G23
6406 G24
Intermodulation Distortion
vs Frequency
Intermodulation Distortion
Intermodulation Distortion
vs Input Amplitude
vs Input Common Mode Voltage
–30
–40
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
V
V
= 3V
V
V
f
= 3V
S
S
= V
= 1.25V
ICM
= V
= 1.25V
ICM
OCM
LOAD
OCM
R
= 800Ω
= 50MHz
IN
R
I
R = R = 150Ω
= 800Ω
I
F
LOAD
–50
2 TONES, 1MHz TONE
R = R = 150Ω
F
SPACING, 2V COMPOSITE
2 TONES, 1MHz TONE
SPACING
P-P
–60
DIFFERENTIAL INPUTS
DIFFERENTIAL INPUTS
–70
V
V
IN
R
= 3V
S
= 1.25V
OCM
–80
f
= 50MHz
= 800Ω
LOAD
–90
R = R = 150Ω
I
F
2 TONES, 1MHz TONE
–100
–110
SPACING, 2V COMPOSITE
P-P
DIFFERENTIAL INPUTS
1
10
100
0
0.5
1.0
1.5
2.0
2.5
–4
(0.4V
–2
0
2
4
6
8
10
(2V
)
P-P
FREQUENCY (MHz)
INPUT COMMON MODE VOLTAGE (V)
INPUT AMPLITUDE (dBm)
P-P
6406 G25
6406 G26
6406 G27
6406fb
8
LTC6406
TYPICAL PERFORMANCE CHARACTERISTICS (MSOP Package)
Frequency Response
vs Closed-Loop Gain
Frequency Response
vs Load Capacitance
Frequency Response vs Input
Common Mode Voltage
50
40
10
5
30
20
C
C
C
= 0pF
= 2pF
= 3pF
L
L
L
L
L
30
C = 4.7pF
0
10
C
= 10pF
V
ICM
V
ICM
V
ICM
V
ICM
V
ICM
= 0V
20
–5
0
= 0.5V
= 1.25V
= 2V
10
–10
–15
–20
–25
–30
–35
–10
–20
–30
–40
–50
–60
0
= 3V
–10
–20
–30
–40
–50
V
V
= 3V
S
A
A
A
A
A
A
= 1
V
V
V
V
V
V
= V
= 1.25V
ICM
OCM
LOAD
= 2
R
= 400Ω
V
V
= 3V
= 5
S
R = R = 150Ω, C = 2.2pF
I
F
F
= 1.25V
= 400Ω
V
V
= 3V
= 10
= 20
= 100
OCM
LOAD
S
CAPACITOR VALUES ARE FROM
EACH OUTPUT TO GROUND.
R
I
= V
= 1.25V
OCM
ICM
R = R = 150Ω, C = 2.2pF
R
= 400Ω
F
F
LOAD
NO SERIES RESISTORS ARE USED.
1
10
100
1000 2000
1
10
100
1000 2000
1
10
100
1000 2000
FREQUENCY (MHz)
(V/V) R (Ω) (Ω) C (pF)
F
FREQUENCY (MHz)
FREQUENCY (MHz)
6406 G30
6406 G29
A
R
V
I
F
1
2
5
10
20
100
150
150
150
150
150
150
150
300
750
1.5k
3k
2.2
2.2
0.9
0.4
0.2
0
15k
6406 G28
Harmonic Distortion
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
vs Input Common Mode Voltage
–30
–40
–40
–50
–60
–70
–80
–90
–100
–40
V
V
= 3V
S
V
V
R
V
= 3V
2ND, R = R = 150Ω
S
I
F
= V = 1.25V
ICM
= V
= 1.25V
ICM
OCM
2ND, R = R = 500Ω
OCM
I
F
f = 50MHz
= 800Ω
= 2V
–50 IN
3RD, R = R = 150Ω
LOAD
I
F
R
= 800Ω
LOAD
3RD, R = R = 500Ω
OUTDIFF
P-P
–50
I
F
R = R = 150Ω
I
F
DIFFERENTIAL INPUTS
–60
–70
DIFFERENTIAL INPUTS
–60
2ND
3RD
2ND, R = R = 150Ω
I
F
2ND, R = R = 500Ω
I
F
–70
3RD, R = R = 150Ω
I
F
3RD, R = R = 500Ω
I
F
–80
V
V
= 3V
S
–80
= 1.25V
OCM
–90
f
= 50MHz
IN
R
= 800Ω
LOAD
–90
–100
–110
V
= 2V
OUTDIFF
P-P
DIFFERENTIAL INPUTS
0.5 1.0 1.5
INPUT COMMON MODE VOLTAGE (V)
–100
10
10
FREQUENCY (MHz)
100
0
2.0
2.5
3.0
–4
P-P
–2
0
2
4
6
8
10
(2V
(0.4V
)
)
P-P
INPUT AMPLITUDE (dBm)
6406 G32
6406 G31
6406 G33
6406fb
9
LTC6406
TYPICAL PERFORMANCE CHARACTERISTICS
(MSOP Package)
Harmonic Distortion
vs Input Common Mode Voltage
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
–30
–40
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
V
V
R
V
= 3V
V
V
f
= 3V
S
OCM
S
= V
=1.25V
ICM
= V
= 1.25V
ICM
OCM
= 50MHz
LOAD
= 800Ω
= 2V
IN
LOAD
R
= 800Ω
OUTDIFF
P-P
–50
2ND
3RD
R = R = 500Ω
SINGLE-ENDED INPUT
I
F
SINGLE-ENDED INPUT
–60
2ND
–70
V
V
IN
R
= 3V
S
3RD
–80
= 1.25V
OCM
f
= 50MHz
–90
= 800Ω
2ND, R = R = 150Ω
LOAD
I
F
R = R = 500Ω
V
SINGLE-ENDED INPUT
2ND, R = R = 500Ω
I
F
I
F
–100
–110
= 2V
3RD, R = R = 150Ω
OUTDIFF
P-P
I
F
3RD, R = R = 500Ω
I
F
10
10
FREQUENCY (MHz)
100
0
0.5 1.0 1.5
2.0
2.5
3.0
–4
(0.4V
–2
0
2
4
6
8
10
(2V
)
)
P-P
P-P
INPUT COMMON MODE VOLTAGE (V)
INPUT AMPLITUDE (dBm)
6406 G35
6406 G36
6406 G34
PIN FUNCTIONS
(QFN/MSOP)
SHDN (Pin 1/Pin 7): When SHDN is floating or directly
voltages on the +OUT and –OUT pins). The V
voltage
OCM
+
tied to V , the LTC6406 is in the normal (active) operat-
isinternallysetbyaresistivedividerbetweenthesupplies,
developing a default voltage potential of 1.25V with a 3V
–
ing mode. When the SHDN pin is connected to V , the
LTC6406 enters into a low power shutdown state with
Hi-Z outputs.
supply. The V
pin can be overdriven by an external
OCM
voltage capable of driving the 18kΩ Thevenin equivalent
impedance presented by the pin. The V pin should be
+
–
OCM
V , V (Pins 2, 10, 11 and Pins 3, 9, 12/Pins 3, 6): Power
Supply Pins. It is critical that close attention be paid to
supply bypassing. For single supply applications it is
recommended that a high quality 0.1μF surface mount
bypassedwithahighqualityceramicbypasscapacitorofat
least 0.01μF, to minimize common mode noise from being
converted to differential noise by impedance mismatches
both externally and internally to the IC.
+
–
ceramicbypasscapacitorbeplacedbetweenV andV with
–
direct short connections. In addition, V should be tied
V
(Pin 5/NA): This pin can normally be left floating.
TIP
directly to a low impedance ground plane with minimal
routing.Fordual(split)powersupplies,itisrecommended
that additional high quality, 0.1μF ceramic capacitors are
It determines which pair of input transistors (NPN or
PNP or both) is sensing the input signal. The V pin is
TIP
set by an internal resistive divider between the supplies,
+
–
used to bypass V to ground and V to ground, again
with minimal routing. For driving large loads (<200Ω),
additional bypass capacitance may be needed for optimal
performance.Keepinmindthatsmallgeometry(e.g.0603
orsmaller)surfacemountceramiccapacitorshaveamuch
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
developing a default 1.55V voltage with a 3V supply. V
TIP
has a Thevenin equivalent resistance of approximately
15k and can be overdriven by an external voltage. The
V
pin should be bypassed with a high quality ceramic
TIP
bypass capacitor of at least 0.01μF. See the Applications
Information section for more details.
+OUT, –OUT (Pins 7, 14/Pins 4, 5): Unfiltered Output
Pins. Besides driving the feedback network, each pin
can drive an additional 50Ω to ground with typical short-
circuit current limiting of 55mA. Each amplifier output
V
(Pin 4/Pin 2): Output Common Mode Reference
OCM
Voltage. The voltage on V
sets the output common
OCM
mode voltage level (which is defined as the average of the
6406fb
10
LTC6406
PIN FUNCTIONS
is designed to drive a load capacitance of 5pF. Larger
capacitive loads should be decoupled with at least 15Ω
resistors from each output.
(QFN/MSOP)
mance, it is highly recommended that stray capacitance
be kept to an absolute minimum by keeping printed circuit
connections as short as possible.
+OUTF,–OUTF(Pins8,13/NA):FilteredOutputPins.These
pins have a series RC network (R = 50Ω, C = 3.75pF) con-
nectedbetweenthefilteredandunfilteredoutputs. Seethe
Applications Information section for more details.
NC (Pin 16/NA): No Connection. This pin is not connected
internally.
–
Exposed Pad (Pin 17/Pin 9): Tie the bottom pad to V . If
split supplies are used, DO NOT tie the pad to ground.
+IN,–IN(Pins15,6/Pins8,1):NoninvertingandInverting
Input Pins of the amplifier, respectively. For best perfor-
BLOCK DIAGRAMS
LTC6406 Block Diagram/Pinout in MSOP Package
8
7
6
5
–
+IN
SHDN
V
–OUT
–
V
100k
+
V
+
+
V
V
V
43k
30k
+
–
–
–
V
+
V
+
–IN
V
V
+OUT
6406 BD01
OCM
1
2
3
4
LTC6406 Block Diagram/Pinout in QFN Package
16
15
14
13
NC
+IN
–OUT
–OUTF
1.25pF
–
SHDN
V
V
100k
+
1
2
12
V
+
+
V
V
V
–
–
50Ω
+
+
V
+
V
+
–
11
V
V
43k
+
–
1.25pF
–
+
+
–
V
V
V
V
+
30k
50Ω
3
4
10
V
V
30k
32k
V
–
1.25pF
–
–
V
OCM
V
9
V
–IN
+OUT
+OUTF
TIP
V
5
6
7
8
6406 BD02
6406fb
11
LTC6406
APPLICATIONS INFORMATION
Functional Description
single-ended output amplifiers. The balanced differential
nature of the amplifier also provides even-order harmonic
distortion cancellation, and less susceptibility to common
modenoise(likepowersupplynoise).TheLTC6406canbe
usedasasingle-endedinputtodifferentialoutputamplifier,
or as a differential input to differential output amplifier.
The LTC6406 is a small outline, wideband, low noise, and
low distortion fully-differential amplifier with accurate
output phase balancing. The LTC6406 is optimized to
drive low voltage, single-supply, differential input analog-
to-digital converters (ADCs). The LTC6406 input common
mode range is rail-to-rail, while the output common mode
voltage is independently adjustable by applying a voltage
TheLTC6406outputcommonmodevoltage,definedasthe
average of the two output voltages, is independent of the
input common mode voltage, and is adjusted by applying
on the V
pin. The output voltage swing extends from
OCM
near ground to 2V, to be compatible with a wide range of
ADCconverterinputrequirements.ThismakestheLTC6406
ideal for level-shifting signals with a wide common mode
range for driving 12-bit to 16-bit single supply, differential
input ADCs. The differential output allows for twice the
signal swing in low voltage systems when compared to
a voltage on the V
pin. If the pin is left open, there
OCM
is an internal resistive voltage divider, which develops a
potential of 1.25V (if the supply is 3V). It is recommended
that a high quality ceramic capacitor is used to bypass the
V
pintoalowimpedancegroundplane.TheLTC6406’s
OCM
internal common mode feedback path forces accurate
C
F
R
R
I
F
V
+IN
V
–OUT
+
–
V
–OUTF
V
INP
16
15
14
13
NC
+IN
–OUT
50Ω
–OUTF
1.25pF
LTC6406
R
BAL
100k
–
–
SHDN
V
V
12
SHDN
0.1μF
V
–
1
2
SHDN
V
V
–
+
+
100k
V
V
V
+
+
11
V
V
+
0.1μF
V
OUTCM
+
+
1.25pF
V
V
0.1μF
V
OCM
–
+
V
V
V
V
CM
–
–
–
50Ω
3
4
10
V
V
–
0.1μF
0.1μF
–
1.25pF
–
V
V
OCM
–
V
9
V
R
BAL
100k
VOCM
0.1μF
0.01μF
V
–IN
+OUT
+OUTF
TIP
5
6
7
8
6406 F01
0.01μF
–
+
V
+OUTF
V
INM
R
R
I
F
V
–IN
V
+OUT
C
F
Figure 1. DC Test Circuit
6406fb
12
LTC6406
APPLICATIONS INFORMATION
C
F
0.1μF
0.1μF
R
I
R
F
100Ω
V
+IN
V
–OUT
V
–OUTF
R
T
16
15
14
13
NC
SHDN
SHDN
+IN
–OUT
–OUTF
LTC6406
1.25pF
–
–
V
V
MINI-CIRCUITS
TCM4-19
MINI-CIRCUITS
TCM4-19
12
50Ω
V
1
2
0.1μF
SHDN
–
V
V
50Ω
–
+
+
100k
V
V
V
+
–
+
+
V
11
V
+
0.1μF
50Ω
V
IN
+
+
1.25pF
V
OCM
V
V
0.1μF
–
+
V
V
V
V
–
–
–
50Ω
3
4
10
V
V
–
0.1μF
0.1μF
–
1.25pF
–
V
OCM
–
V
9
V
VOCM
0.01μF
0.1μF
–IN
+OUT
+OUTF
V
TIP
R
CHOSEN SO
T
5
6
7
8
6406 F02
THAT R ||R = 100Ω
T
I
0.01μF
V
+OUTF
R
T
0.1μF
0.1μF
R
I
R
F
V
+OUT
100Ω
V
–IN
C
F
Figure 2. AC Test Circuit (–3dB BW Testing)
output phase balancing to reduce even order harmonics,
and centers each individual output about the potential set
addition, the input pins have clamping diodes to either
power supply. If the input pins are over-driven, the current
should be limited to under 10mA to prevent damage to the
IC. The LTC6406 also has clamping diodes to either power
by the V
pin.
OCM
V+OUT + V–OUT
VOUTCM = VOCM
=
supply on the V , V and SHDN pins and if driven to
OCM TIP
2
voltages which exceed either supply, they too, should be
current limited to under 10mA.
The outputs (+OUT and –OUT) of the LTC6406 are capable
of swinging from close to ground to typically 1V below
+
SHDN Pin
V . They can source or sink up to approximately 55mA of
current. Each output is designed to directly drive up to 5pF
to ground. Higher load capacitances should be decoupled
with at least 15Ω of series resistance from each output.
The SHDN pin is a CMOS logic input with a 100k internal
pull-upresistor.Ifthepinisdrivenlow,theLTC6406powers
down with Hi-Z outputs. If the pin is left unconnected or
driven high, the part is in normal active operation. Some
care should be taken to control leakage currents at this pin
topreventinadvertentlyputtingtheLTC6406intoshutdown.
The turn-on and turn-off time between the shutdown and
active states are typically less than 1μs.
Input Pin Protection
The LTC6406 input stage is protected against differential
input voltages which exceed 1.4V by two pairs of series
diodes connected back to back between +IN and –IN. In
6406fb
13
LTC6406
APPLICATIONS INFORMATION
General Amplifier Applications
Δβ is defined as the difference in feedback factors:
RI2 RI1
RI2 +RF2 RI1 +RF1
is defined as the average of the two input voltages
As levels of integration have increased and correspond-
ingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal to noise ratios. These ADCs are
typically supplied from a single supply voltage which can
be as low as 3V, and will have an optimal common mode
input range of 1.25V or 1.5V. The LTC6406 makes interfac-
ing to these ADCs easy, by providing both single-ended
to differential conversion as well as common mode level
shifting. The front page of this data sheet shows a typical
Δβ =
–
V
V
ICM
, and V
(also called the input common mode
INP
INM
voltage):
1
2
V
= • VINP + V
(
)
ICM
INM
and V
is defined as the difference of the input voltages:
INDIFF
application. The gain to V
from V
and V is:
OUTDIFF
INM INP
V
= V – V
INP INM
INDIFF
RF
RI
VOUTDIFF = V+OUT – V–OUT
≈
• VINP – V
(
)
V
V
is defined as the average of the two output voltages
INM
OCM
and V
:
+OUT
–OUT
Note from the above equation, the differential output volt-
age (V – V ) is completely independent of input
and output common mode voltages, or the voltage at
the common mode pin. This makes the LTC6406 ideally
suited for preamplification, level shifting and conversion
of single-ended signals to differential output signals in
preparation for driving differential input ADCs.
V+OUT + V–OUT
VOCM
=
+OUT
–OUT
2
When the feedback ratios mismatch (Δβ), common mode
to differential conversion occurs.
Setting the differential input to zero (V
gree of common mode to differential conversion is given
by the equation:
= 0), the de-
INDIFF
Effects of Resistor Pair Mismatch
Δβ
βAVG
Figure 3 shows a circuit diagram which takes into consid-
eration that real world resistors will not match perfectly.
Assuming infinite open-loop gain, the differential output
relationship is given by the equation:
VOUTDIFF = V+OUT – V–OUT ≈ VICM – VOCM
•
(
)
R
I2
R
F2
V
+IN
V
–OUT
+
–
RF
RI
V
INP
VOUTDIFF = V+OUT – V–OUT
≅
• V
+
INDIFF
Δβ
βAVG
Δβ
βAVG
+
• V
–
• VOCM
ICM
V
V
VOCM
OCM
–
where:
–
+
V
INM
R is the average of R , and R , and R is the average
F
F1
F2
I
R
I1
R
F1
V
–IN
V
+OUT
of R , and R .
6406 F03
I1
I2
β
is defined as the average feedback factor from the
Figure 3. Real-World Application with Feedback Resistor
Pair Mismatch
AVG
outputs to their respective inputs:
⎛
⎞
RI1
RI2
RI2 +RF2
1
βAVG = •
2
+
⎜
⎟
R +R
⎝
⎠
I1
F1
6406fb
14
LTC6406
APPLICATIONS INFORMATION
In general, the degree of feedback pair mismatch is a
sourceofcommonmodetodifferentialconversionofboth
signalsandnoise.Using1%resistorsorbetterwillmitigate
most problems, and will provide about 34dB worst case of
commonmoderejection.Using0.1%resistorswillprovide
about 54dB of common mode rejection. A low impedance
ground plane should be used as a reference for both the
thebalanceddifferentialcase.Theinputimpedancelooking
into either input is:
RI
RINP =RINM
=
⎛
⎞
⎛
⎞
RF
1
1– •
2
⎜
⎟
⎜
⎟
R +R
⎝
⎠
⎝
⎠
I
F
input signal source and the V
pin. Bypassing the V
Input signal sources with non-zero output impedances
can also cause feedback imbalance between the pair of
feedback networks. For the best performance, it is rec-
ommended that the input source output impedance be
compensated for. If input impedance matching is required
by the source, a termination resistor R1 should be chosen
(see Figure 4):
OCM
OCM
with a high quality 0.1μF ceramic capacitor to this ground
planewillfurtherhelppreventcommonmodesignalsfrom
being converted to differential signals.
There may be concern on how feedback factor mismatch
affects distortion. Feedback factor mismatch from using
1%resistorsorbetter, hasanegligibleeffectondistortion.
However,insinglesupplylevel-shiftingapplicationswhere
there is a voltage difference between the input common
mode voltage and the output common mode voltage,
resistor mismatch can make the apparent voltage offset
of the amplifier appear worse than specified.
RINM •RS
R1=
RINM –RS
R
INM
R
S
R
R
F
I
The apparent input referred offset induced by feedback
factor mismatch is derived from the above equation:
R1
V
S
–
+
–
V
≈ (V
– V
) • Δβ
OCM
OSDIFF(APPARENT)
ICM
R1 CHOSEN SO THAT R1||R
R2 CHOSEN TO BALANCE R1||R
= R
S
+
INM
S
Using the LTC6406 in a single supply application on a
single 3V supply with 1% resistors, and the input com-
R
R
F
I
6406 F04
mon mode grounded, with the V
pin biased at 1.25V,
R2
S
OCM
R ||R1
the worst case DC offset can induce 12.5mV of apparent
offset voltage. With 0.1% resistors, the worst-case ap-
parent offset reduces to 1.25mV.
Figure 4. Optimal Compensation for Signal Source Impedance
According to Figure 4, the input impedance looking into
Input Impedance and Loading Effects
thedifferentialamp(R )reflectsthesingle-endedsource
INM
The input impedance looking into the V or V
of Figure 1 depends on whether or not the sources V
input
INM
INP
case, thus:
INP
and V
are fully differential or not. For balanced input
RI
INM
RINM
=
sources(V =–V ),theinputimpedanceseenateither
INP
INM
⎛
⎞
⎛
⎞
RF
1
1– •
2
input is simply:
⎜
⎟
⎜
⎟
R +R
⎝
⎠
⎝
⎠
I
F
R
= R = R
INM I
INP
R2 is chosen to equal R1||R :
S
For single-ended inputs, because of the signal imbalance
at the input, the input impedance actually increases over
R1•RS
R2=
R1+RS
6406fb
15
LTC6406
APPLICATIONS INFORMATION
Input Common Mode Voltage Range
Manipulating the Rail-to-Rail Input Stage with V
TIP
The LTC6406’s input common mode voltage (V ) is
Toachieverail-to-railinputoperation,theLTC6406features
anNPNinputstageinparallelwithaPNPinputstage.When
ICM
defined as the average of the two input voltages, V , and
+IN
+
V
. At the inputs to the actual op amp, the range extends
the input common mode voltage is near V , the NPNs are
–IN
–
+
from V to V . This makes it easy to interface to a wide
rangeofcommonmodesignals,fromgroundreferencedto
active while the PNPs are off. When the input common
–
mode is near V , the PNPs are active while the NPNs are
V
CC
referenced signals. Moreover, due to external resistive
off. At some range in the middle, both input stages are
active. This ‘hand-off’ operation happens automatically.
divideractionofthegainandfeedbackresistors,theeffective
range of signals that can be processed is even wider. The
input common mode range at the op amp inputs depends
In the QFN package, a special pin, V , is made available
TIP
that can be used to manipulate the ‘hand-off’ operation
on the circuit configuration (gain), V
and V (refer to
OCM
CM
between the NPN and PNP input stages. By default, the
Figure 5). For fully differential input applications, where
V
pin is internally biased by an internal resistive divider
TIP
V
INP
= –V , the common mode input is approximately:
INM
between the supplies, developing a default 1.55V voltage
⎛
⎞
V+IN + V–IN
RI
R +R
with a 3V supply. If desired, V can be overdriven by an
TIP
V
=
≈ VOCM
•
+
ICM
⎜
⎟
external voltage (the Thevenin equivalent resistance is
2
⎝
⎠
I
F
approximately 15k).
⎛
⎞
RF
–
VCM
•
If V is pulled closer to V , the range over which the NPN
⎜
⎟
TIP
R +R
⎝
⎠
F
I
inputpairremainsactiveisincreased, whiletherangeover
which the PNP input pair is active is reduced. In applica-
tions where the input common mode does not come close
With single-ended inputs, there is an input signal compo-
nent to the input common mode voltage. Applying only
–
to V , this mode can be used to further improve linearity
V
(setting V
to zero), the input common voltage is
INP
INM
beyond the specified performance.
approximately:
+
If V is pulled closer to V , the range over which the PNP
TIP
⎛
⎞
V+IN + V–IN
RI
R +R
inputpairremainsactiveisincreased, whiletherangeover
which the NPN input pair is active is reduced. In applica-
tions where the input common mode does not come close
V
=
≈ VOCM
•
+
ICM
⎜
⎟
2
⎝
⎠
I
F
⎛
⎞
⎛
⎞
RF
V
RF
R +R
INP
2
+
VCM
•
+
•
to V , this mode can be used to further improve linearity
⎜
⎟
⎜
⎟
R +R
⎝
⎠
⎝
⎠
F
I
F
I
beyond the specified performance.
Use the equations above to check that the V
at the op
ICM
–
+
amp inputs is within range (V to V ).
R
I
R
F
V
+IN
V
–OUT
+
V
INP
–
+
V
V
VOCM
OCM
+
–
–
V
CM
–
V
INM
R
I
R
F
V
+
–IN
V
+OUT
6406 F05
Figure 5. Circuit for Common Mode Range
6406fb
16
LTC6406
APPLICATIONS INFORMATION
Output Common Mode Voltage Range
–OUTF
14
13
–OUT
50Ω
–OUTF
1.25pF
LTC6406
The output common mode voltage is defined as the aver-
age of the two outputs:
–
V
12
V+OUT + V–OUT
–
–
V
VOUTCM = VOCM
The V
=
2
+
–
FILTERED OUTPUT
1.25pF
V
pin sets this average by an internal common
OCM
50Ω
mode feedback loop which internally forces V
=
OUTCM
–
1.25pF
V
V
OCM
.Theoutputcommonmoderangeextendsfrom0.5V
9
–
+
above V to 1V below V . The V
voltage is internally
OCM
+OUT
+OUTF
set by a resistive divider between the supplies, develop-
ing a default voltage potential of 1.25V with a 3V supply.
7
8
6406 F06
+OUTF
Figure 6. LTC6406 Internal Filter Topology
In single supply applications, where the LTC6406 is used
to interface to an ADC, the optimal common mode input
range to the ADC is often determined by the ADC’s refer-
ence. If the ADC makes a reference available for setting
the input common mode voltage, it can be directly tied
1.25pF(tolerance 15%)capacitorconnectedbetweenthe
two filtered outputs. This resistor/capacitor combination
creates filtered outputs that look like a series 50Ω resistor
with a 3.75pF capacitor shunting each filtered output to
AC ground, providing a –3dB bandwidth of 850MHz, and
a noise bandwidth of 1335MHz. The filter cutoff frequency
is easily modified with just a few external components. To
increase the cutoff frequency, simply add two equal value
resistors, one between +OUT and +OUTF and the other
between –OUT and –OUTF (Figure 7). These resistors, in
parallel with the internal 50Ω resistors, lower the overall
resistance and therefore increase filter bandwidth. For
example, to double the filter bandwidth, add two external
50Ω resistors to lower the series filter resistance to 25Ω.
The 3.75pF of capacitance remains unchanged, so filter
bandwidth doubles. Keep in mind, the series resistance
alsoservestodecoupletheoutputsfromloadcapacitance.
The outputs of the LTC6406 are designed to drive 5pF to
ground, so care should be taken to not lower the effec-
tive impedance between +OUT and +OUTF or –OUT and
–OUTF below 15Ω.
to the V
pin (as long as it is able to drive the 18kΩ
OCM
Thevenin equivalent input impedance presented by the
V
pin).
OCM
The V
pin should be bypassed with a high quality
OCM
ceramic bypass capacitor of at least 0.01μF to filter any
common mode noise rather than being converted to dif-
ferential noise and to prevent common mode signals on
this pin from being inadvertently converted to differential
signals by impedance mismatches both externally and
internally to the IC.
Output Filter Considerations and Use
Filtering at the output of the LTC6406 is often desired to
provide antialiasing or to improve signal to noise ratio.
To simplify this filtering, the LTC6406 in the QFN package
includes an additional pair of differential outputs (+OUTF
and –OUTF) which incorporate an internal lowpass RC
network with a –3dB bandwidth of 850MHz (Figure 6).
To decrease filter bandwidth, add two external capacitors,
one from +OUTF to ground, and the other from –OUTF to
ground. A single differential capacitor connected between
+OUTF and –OUTF can also be used, but since it is being
These pins each have an output resistance of 50Ω (toler-
ance 12%). Internal capacitances are 1.25pF (tolerance
–
15%) to V on each filtered output, plus an additional
6406fb
17
LTC6406
APPLICATIONS INFORMATION
thefilteredoutputs, whichalsohalvesthefilterbandwidth.
Combinations of capacitors could be used as well; a three
capacitor solution of 1.2pF from each filtered output to
groundplusa1.2pFcapacitorbetweenthefilteredoutputs
would also halve the filter bandwidth (Figure 8).
driven differentially it will appear at each filtered output
as a single-ended capacitance of twice the value. To halve
the filter bandwidth, for example, two 3.9pF capacitors
could be added (one from each filtered output to ground).
Alternatively, one 1.8pF capacitor could be added between
49.9Ω
–OUTF
14
13
–OUT
50Ω
–OUTF
LTC6406
–
1.25pF
V
12
–
V
+
–
FILTERED OUTPUT
(1.7GHz)
1.25pF
V
50Ω
–
–
1.25pF
V
9
+OUT
+OUTF
7
8
6406 F07
49.9Ω
+OUTF
Figure 7. LTC6406 Filter Topology Modified for 2x Filter
Bandwidth (Two External Resistors)
–OUTF
14
13
–OUT
50Ω
–OUTF
1.25pF
LTC6406
1.2pF
–
V
12
–
–
V
+
–
FILTERED OUTPUT
(425MHz)
1.2pF
1.25pF
V
50Ω
–
1.2pF
1.25pF
V
9
+OUT
+OUTF
7
8
6406 F08
+OUTF
Figure 8. LTC6406 Filter Topology Modified for 1/2x Filter
Bandwidth (Three External Capacitors)
6406fb
18
LTC6406
APPLICATIONS INFORMATION
Noise Considerations
100
10
1
TOTAL (AMPLIFIER AND
FEEDBACK NETWORK)
OUTPUT NOISE
The LTC6406’s input referred voltage noise is 1.6nV/√Hz.
Its input referred current noise is 2.5pA/√Hz. In addition
to the noise generated by the amplifier, the surrounding
feedback resistors also contribute noise. A noise model
is shown in Figure 9. The output noise generated by both
the amplifier and the feedback components is governed
by the equation:
FEEDBACK NETWORK
NOISE ALONE
2
0.1
⎛
⎞
⎛
⎞
RF
RI
2
10
100
1k
10k
eni • 1+
+ 2• I •R
+
(
)
n
F
⎜
⎟
⎜
⎝
⎟
R = R (Ω)
I
F
⎠
6406 F10
⎝
⎠
eno =
Figure 10. LTC6406 Output Spot Noise vs Spot Noise
Contributed by Feedback Network Alone
2
⎛
⎞
⎛
⎞
RF
2
2• enRI
•
+ 2•enRF
⎜
⎟
⎜
⎟
R
⎝
⎠
⎝
⎠
I
TheLTC6406’sinputreferredvoltagenoisecontributesthe
equivalent noise of a 155Ω resistor. When the feedback
network is comprised of resistors whose values are less
than this, the LTC6406’s output noise is voltage noise
dominant (see Figure 10):
A plot of this equation, and a plot of the noise generated
by the feedback components for the LTC6406 is shown
in Figure 10.
⎛
⎞
RF
RI
eno ≈eni • 1+
⎜
⎝
⎟
2
2
e
e
nRF
⎠
nRI
R
R
F
I
Feedback networks consisting of resistors with values
greater than about 200Ω will result in output noise which
is resistor noise and amplifier current noise dominant.
+2
i
n
2
e
ncm
+
⎛
⎞
⎟
RF
RI
eno ≈ 2 • I •R 2 + 1+
• 4•k • T •RF
2
V
OCM
e
no
(
)
n
F
⎜
⎝
⎠
–
–2
i
n
Lowerresistorvalues(<100Ω)alwaysresultinlowernoise
atthepenaltyofincreaseddistortionduetoincreasedload-
ing of the feedback network on the output. Higher resistor
values (but still less than <500Ω) will result in higher
output noise, but typically improved distortion due to less
loadingontheoutput. Theoptimalfeedbackresistancefor
the LTC6406 runs in between 100Ω to 500Ω.
2
e
ni
2
2
e
e
nRF
nRI
R
R
I
F
6406 F09
Figure 9. Noise Model of the LTC6406
The differential filtered outputs +OUTF and –OUTF will
have a little higher noise than the unfiltered outputs (due
to the two 50Ω resistors which contribute 0.9nV/√Hz
each), but can provide superior signal-to-noise due to the
output noise filtering.
6406fb
19
LTC6406
APPLICATIONS INFORMATION
Layout Considerations
output common mode rejection. This will also prevent
input referred common mode noise of the common
mode amplifier path (which cannot be filtered) from being
converted to differential noise, degrading the differential
noise performance.
V
OCM
Because the LTC6406 is a very high speed amplifier, it is
sensitive to both stray capacitance and stray inductance.
In the QFN package, three pairs of power supply pins are
provided to keep the power supply inductance as low
as possible to prevent any degradation of amplifier 2nd
harmonic performance. It is critical that close attention be
paid to supply bypassing. For single supply applications
it is recommended that high quality 0.1μF surface mount
ceramic bypass capacitor be placed directly between each
Feedback factor mismatch has a weak effect on distortion.
Using 1% or better resistors will limit any mismatch from
impacting amplifier linearity. However, in single supply
level-shifting applications where there is a voltage differ-
ence between the input common mode voltage and the
output common mode voltage, resistor mismatch can
make the apparent voltage offset of the amplifier appear
worse than specified.
+
–
–
V and V pin with direct short connections. The V pins
should be tied directly to a low impedance ground plane
with minimal routing. For dual (split) power supplies, it is
recommended that additional high quality, 0.1μF ceramic
+
–
capacitors are used to bypass V to ground and V to
ground,againwithminimalrouting.Fordrivinglargeloads
(<200Ω),additionalbypasscapacitancemaybeneededfor
optimal performance. Keep in mind that small geometry
(e.g.0603)surfacemountceramiccapacitorshaveamuch
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
Interfacing the LTC6406 to A/D Converters
Rail-to-rail input and fast settling time make the LTC6406
ideal for interfacing to low voltage, single supply, differ-
ential input ADCs. The sampling process of ADCs create
a sampling glitch caused by switching in the sampling
capacitorontheADCfrontendwhichmomentarily“shorts”
theoutputoftheamplifieraschargeistransferredbetween
the amplifier and the sampling capacitor. The amplifier
mustrecoverandsettlefromthisloadtransientbeforethis
acquisition period ends for a valid representation of the
inputsignal. Ingeneral, theLTC6406willsettlemuchmore
quickly from these periodic load impulses than from a 2V
input step, but it is a good idea to either use the filtered
outputs to drive the ADC (Figure 11 shows an example
of this), or to place a discrete R-C filter network between
the differential unfiltered outputs of the LTC6406 and the
input of the ADC to help absorb the charge injection that
comes out of the ADC from the sampling process. The
capacitanceofthefilternetworkservesasachargereservoir
to provide high frequency charging during the sampling
process, while the two resistors of the filter network are
used to dampen and attenuate any charge kickback from
the ADC. The selection of the R-C time constant is trial
and error for a given ADC, but the following guidelines
are recommended: Choosing too large of a resistor in the
decoupling network leaving insufficient settling time will
createavoltagedividerbetweenthedynamicinputimped-
ance of the ADC and the decoupling resistors. Choosing
too small of a resistor will possibly prevent the resistor
Anystrayparasiticcapacitancestogroundatthesumming
junctions,+INand–IN,shouldbeminimized.Thisbecomes
especially true when the feedback resistor network uses
resistor values >500Ω in circuits with R = R . Excessive
F
I
peaking in the frequency response can be mitigated by
addingsmallamountsoffeedbackcapacitancearoundR .
F
AlwayskeepinmindthedifferentialnatureoftheLTC6406,
and that it is critical that the load impedances seen by both
outputs (stray or intended), should be as balanced and
symmetric as possible. This will help preserve the natural
balance of the LTC6406, which minimizes the generation
of even order harmonics, and improves the rejection of
common mode signals and noise.
It is highly recommended that the V
pin be bypassed
OCM
to ground with a high quality ceramic capacitor whose
value exceeds 0.01μF. This will help stabilize the common
mode feedback loop as well as prevent thermal noise from
the internal voltage divider and other external sources of
noise from being converted to differential noise due to
divider mismatches in the feedback networks. It is also
recommended that the resistive feedback networks be
comprised of 1% resistors (or better) to enhance the
6406fb
20
LTC6406
APPLICATIONS INFORMATION
from properly dampening the load transient caused by
the sampling process, prolonging the time required for
settling. In 16-bit applications, this will typically require
a minimum of 11 R-C time constants. It is recommended
that the capacitor chosen have a high quality dielectric
(such as C0G multilayer ceramic).
1.8pF
V
, 2V
IN P-P
150Ω
150Ω
16
15
14
13
NC
SHDN
+IN
–OUT
50Ω
–OUTF
1.25pF
LTC6406
CONTROL
–
V
V
CM
SHDN
12
2.2μF
1
2
–
–
+
+
V
V
100k
V
V
D15
•
0.1μF
3.3V
0.1μF
+
+INA
–INA
3.3V
V
11
+
•
+
1.25pF
0.1μF
V
LTC2208
GND
V
D0
OCM
–
+
V
V
V
–
–
50Ω
3
4
V
10
3.3V
1μF
V
DD
–
1.25pF
+OUTF
1μF
V
OCM
9
0.1μF
V
–IN
+OUT
TIP
5
6
7
8
0.1μF
150Ω
6406 F11
150Ω
1.8pF
Figure 11. Interfacing the LTC6406 to an ADC
TYPICAL APPLICATION
DC-Coupled Level Shifting of Demodulator Output
C5
1.8pF
5V
DC LEVEL
3.3V
DC LEVEL
1.25V
DIFF OUTPUT Z
130Ω\ \2.5pF
LT5575
R5
475Ω
5V
5V
3.3V
DC LEVEL
3.9V
C8
22pF
5pF
5pF
3.3V
R1
R3
R7
R9
65Ω
65Ω
I
75Ω
75Ω
49.9Ω
10Ω
0dBm
10dBm
+
–
C3
12pF
C6
LTC2249
R2
75Ω
R4
75Ω
R8
49.9Ω
R10
10Ω
LTC6406
22pF
14-BIT ADC
RF IN
900MHz
–3dBm
+
–
C1
10pF
C2
10pF
C7
22pF
5V
5V
6406 TA02
V
OCM
1.25V
5pF
65Ω
5pF
80MHz
SAMPLE
CLOCK
65Ω
R6
475Ω
Q
IDENTICAL
Q CHANNEL
C4
1.8pF
GAIN: 3dB
INPUT NF: 13dB
OIP3: 31dBm
GAIN: 10dB
INPUT NF: 18dB
OIP3: 44dBm
SEE DN418 FOR MORE INFORMATION
6406fb
21
LTC6406
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05
3.50 0.05
2.10 0.05
1.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 0.05
3.00 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
1.45 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6406fb
22
LTC6406
PACKAGE DESCRIPTION
MS8E Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1662)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 0.102
(.081 .004)
1
1.83 0.102
(.072 .004)
0.889 0.127
(.035 .005)
2.794 0.102
(.110 .004)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
2.083 0.102
(.082 .004)
8
3.00 0.102
(.118 .004)
(NOTE 3)
0.52
(.0205)
REF
0.65
(.0256)
BSC
0.42 0.038
(.0165 .0015)
TYP
8
7 6 5
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 0.152
(.021 .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 0.0508
(.004 .002)
0.65
(.0256)
BSC
MSOP (MS8E) 0307 REV D
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6406fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6406
TYPICAL APPLICATIONS
Attenuating and Level Shifting a Single-Ended 5V Signal to a Differential 2VP-P Signal at a 1.25V Common Mode
C1, 2.7pF
2V DIFF OUTPUT
P-P
LEVEL-SHIFTED TO 1.25V
R3, 100Ω
3.3V
3.3V
R5
511Ω
R1
51.1Ω
– +
LTC6406
p5V SINE WAVE
(10V
R6
511Ω
R2
51.1Ω
LTC2207
)
V
P-P
IN
CENTERED AT 0V
+ –
6406 TA03
V
CM
= 1.25V
R4, 100Ω
C2, 2.7pF
Second Order 30MHz 0.5dB Chebyshev Differential Input/Output Lowpass Filter
R1, 150Ω
3.3V
C1, 8.2pF
C7
4.7pF
R7
51.1Ω
R9
4.99Ω
R3
150Ω
R2
232Ω
C6
4.7pF
R8
51.1Ω
R10
4.99Ω
+
–
LTC2207
C3
68pF
LTC6406
DIFFERENTIAL
+
C5
4.7pF
+
–
–
V
IN
6406 TA04
R5
R4
150Ω
232Ω
C2
8.2pF
105MHz
CLOCK
V
CM
R6
150Ω
C4
68pF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1809/LT1810
Single/Dual 180MHz, 350V/μs Rail-to-Rail Input and Output
Low Distortion Op Amps
180MHz, 350V/μs Slew Rate, Shutdown
LT1993-2/LT1993-4/
LT1993-10
800MHz/900MHz/700MHz Low Distortion, Low Noise
Differential Amplifier/ADC Driver
A = 2V/V / A = 4V/V / A = 10V/V, NF = 12.3dB/14.5dB/12.7dB,
V
V
V
OIP3 = 38dBm/40dBm/40dBm at 70MHz
LT1994
Low Noise, Low Distortion Fully differential Input/Output
Amplifier/Driver
Low Distortion, 2V , 1MHz: –94dBc, 13mA, Low Noise: 3nV/√Hz
P-P
LTC6400-20
LTC6401-20
1.8GHz Low Noise, Low Distortion, Differential ADC Driver
1.3GHz Low Noise, Low Distortion, Differential ADC Driver
300MHz IF Amplifier, A = 20dB
V
140MHz IF Amplifier, A = 20dB
V
LT6402-6/LT6402-12/ 300MHz/300MHz/300MHz Low Distortion, Low Noise
A = 6dB/A = 12dB/A = 20dB, NF = 18.6dB/15dB/12.4dB,
V V V
OIP3 = 49dBm/43dBm/51dBm at 20MHz
LT6402-20
Differential Amplifier/ADC Driver
LTC6404-1
600MHz Low Noise, Low Distortion, Differential ADC Driver
1.5nV/√Hz Noise, –90dBc Distortion at 10MHz
LT6600-2.5/LT6600-5/ Very Low Noise, Fully Differential Amplifier and 4th
LT6600-10/LT6600-20 Order Filter
2.5MHz/5MHz/10MHz/20MHz Integrated Filter, 3V Supply,
SO-8 Package
6406fb
LT 0208 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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