LTC1760_1 [Linear]
Dual Smart Battery System Manager; 双智能电池系统管理器
| 型号： | LTC1760_1 |
| 厂家： | 
Linear |
| 描述： | Dual Smart Battery System Manager |
| 文件： | 总44页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1760
Dual Smart Battery
System Manager
U
FEATURES
DESCRIPTIO
The LTC®1760 Smart Battery System Manager is a highly
integratedlevel3batterychargerandselectorintendedfor
products using dual smart batteries. Three SMBus inter-
faces allow the LTC1760 to servo to the internal voltage
and currents measured by the batteries while allowing an
SMBus Host to monitor either battery’s status. Charging
accuracy is determined by the battery’s internal voltage
and current measurement, typically better than ±0.2%.
A proprietary PowerPathTM architecture supports simulta-
neous charging or discharging of both batteries. Typical
battery run times are extended by up to 10%, while
charging times are reduced by up to 50%. The LTC1760
automatically switches between power sources in less
than 10µs to prevent power interruption upon battery or
wall adapter removal.
■
SMBus Charger/Selector for Two Smart Batteries*
Voltage and Current Accuracy within 0.2% of Value
Reported by Battery
Simplifies Construction of “Smart Battery System
Manager”
Includes All SMBus Charger V1.1 Safety Features
Supports Autonomous Operation without a Host
Allows Both Batteries to Discharge Simultaneously
into Single Load with Low Loss (Ideal Diode)
SMBus Switching for Dual Batteries with Alarm
Monitoring for Charging Battery at All Times
Pin Programmable Limits for Maximum Charge
Current and Voltage Improve Safety
■
■
■
■
■
■
■
■
■
■
■
■
■
Fast Autonomous Power Path Switching (<10µs)
Low Loss Simultaneous Charging of Two Batteries
>95% Efficient Synchronous Buck Charger
AC Adapter Current Limiting* Maximizes Charge Rate
SMBus Accelerator Improves SMBus Timing**
Available in 48-LUead TSSOP Package
The LTC1760 implements all elements of a version 1.1
“Smart Battery System Manager” except for the genera-
tion of composite battery information. An internal multi-
plexer cleanly switches the SMBus Host to either of the
two attached Smart Batteries without generating partial
messages to batteries or SMBus Host. Thermistors on
both batteries are automatically monitored for tempera-
ture and disconnection information (SafetySignal).
APPLICATIO S
■
Portable Computers and Instruments
■
Standalone Dual Smart Battery Chargers
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
PowerPath is a trademark of Linear Technology Corporation.
Battery Backup Systems
Protected by U.S. Patents, including *5723970 **6650174
U
TYPICAL APPLICATIO
Dual Battery Charger/Selector System Architecture
Dual vs Sequential Charging
DC
IN
3500
BAT2
CURRENT
BAT1
CURRENT
3000
2500
2000
1500
1000
500
SYSTEM
POWER
SEQUENTIAL
0
LTC1760
3500
3000
2500
2000
1500
1000
500
BAT1
CURRENT
SMBus (HOST)
BAT2
DUAL
CURRENT
SafetySignal 1
SMBus 1
100
MINUTES
0
0
100
150
200 250
300
50
TIME (MINUTES)
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
REQUESTED CURRENT = 3A
SafetySignal 2
SMBus 2
REQUESTED VOLTAGE = 12.3V
1760 TA01
MAX CHARGER CURRENT = 4.1A
1760 TA03
1760f
1
LTC1760
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
Voltage from DCIN, SCP, SCN, CLP,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 SCH2
47 GCH2
46 GCH1
45 SCH1
44 TGATE
43 BOOST
42 SW
V
PLUS
NUMBER
BAT2
BAT1
SCN
VPLUS, SW to GND...................................32V/–0.3 V
Voltage from SCH1, SCH2 to GND................28V/–0.3 V
Voltage from BOOST to GND ........................37V/ –0.3V
CSP, CSN, BAT1, BAT2 to GND .....................28V/–0.3V
LOPWR, DCDIV to GND ................................10V/ –0.3V
Voltage from VCC2, VDDS to GND ....................7V/–0.3 V
SDA1, SDA2, SDA, SCL1, SCL2, SCL, SMBALERT
to GND ........................................................7V/–0.3V
MODE to GND.....................................VCC2 +0.3V/–0.3V
COMP1 to GND...............................................5V/ –0.3V
Maximum DC Current Into Pin
LTC1760CFW
SCP
GDCO
GDCI
GB1O
GB1I
GB2O
GB2I
41 DCIN
40 V
CC
39 BGATE
38 PGND
37 COMP1
36 CLP
35 CSP
34 CSN
LOPWR
V
SET
I
TH
I
SET
33 V
DCDIV
SCL2
SCL
SCL1
V
LIMIT
32 I
LIMIT
31 TH1B
30 TH1A
29 SMBALERT
28 TH2A
27 TH2B
DDS
SDA1, SDA2, SDA, SCL1, SCL2, SCL .............. ±3mA
TH1A, TH2A..................................................... –5mA
TH1B, TH2B.................................................. –102µA
Operating Ambient Temperature (Note 6).... 0°C to 70°C
Operating Junction Temperature ...........–40°C to 125°C
Storage Temperature .............................–65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
SDA2
SDA
26 MODE
SDA1
GND
25 V
CC2
FW PACKAGE
48-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 110°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V
unless otherwise noted.
SYMBOL
Supply and Reference
DCIN Operating Range
DCIN Operating Current
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DCIN Selected
6
28
V
I
I
Not Charging (DCIN Selected) (Note 10)
Charging (DCIN Selected) (Note 10)
1
1.3
1.5
2
mA
mA
CH0
CH1
I
I
V
CC2
Operating Current
AC Present (Note 11)
AC Not Present (Note 11)
0.75
75
1
100
mA
µA
VCC2_AC1
VCC2_AC0
Battery Operating Voltage Range Battery Selected, PowerPath Function
Battery Selected, Charging Function (Note 2)
6
0
28
28
V
V
I
Battery Drain Current
Diodes Forward Voltage:
Battery Selected, Not Charging, V
= 0V (Note 10)
175
µA
BAT
DCIN
V
PLUS
V
V
V
V
DCIN to V
BAT1 to V
BAT2 to V
I
I
I
I
= 10mA
= 0mA
= 0mA
= 0mA
0.8
0.7
0.7
0.7
V
V
V
V
FDC
FB1
PLUS
PLUS
PLUS
PLUS
VCC
VCC
VCC
VCC
FB2
SCN to V
FSCN
UVLO
Undervoltage Lockout Threshold
V
Ramping Down, Measured at V
to GND
●
●
●
3
5
5.5
1
V
V
PLUS
PLUS
V
VCC
V
LDR
V
CC
V
CC
Regulator Output Voltage
Load Regulation
4.9
5.2
0.2
I
= 0mA to 10mA
%
VCC
Switching Regulator
Voltage Accuracy
V
With Respect to Voltage Reported by Battery
< Requested Voltage < V
●
–32
32
mV
TOL
V
CHMIN
LIMIT
1760f
2
LTC1760
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Current Accuracy
With Respect to Current Reported by Battery
TOL
4mV/R
< Requested Current < I
(Min)
SENSE
LIMIT
(Note 12)
R
ILIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
= 0 (Short to GND)
●
●
●
●
–2
–4
–8
–8
2
4
8
8
mA
mA
mA
mA
= 10k ±1%
= 33k ±1%
= Open (or Short I
to V
)
CC2
LIMIT
f
f
Regulator Switching Frequency
255
20
300
25
345
kHz
kHz
0SC
DO
Regulator Switching Frequency in Low
Dropout Mode
Duty Cycle ≥99%
DC
Regulator Maximum Duty Cycle
Maximum Current Sense Threshold
CA1 Input Bias Current
99
99.5
155
150
%
mV
µA
V
MAX
I
I
V
V
= 2.2V
140
190
MAX
SNS
ITH
= V
> 5V
CSN
CSP
CMSL
CMSH
CA1/I Input Common Mode Low
0
1
CA1/I Input Common Mode High
V
– 0.2
DCIN
V
1
V
CL1 Turn-On Threshold
95
94
100
100
105
108
mV
mV
CL1
●
TGATE Transition Time:
TGATE Rise Time
TGATE Fall Time
TG t
TG t
C
C
= 3300pF, 10% to 90%
= 3300pF, 10% to 90%
50
50
90
90
ns
ns
r
f
LOAD
LOAD
BGATE Transition Time:
BGATE Rise Time
BGATE Fall Time
BG t
BG t
C
C
= 3300pF, 10% to 90%
= 3300pF, 10% to 90%
50
40
90
80
ns
ns
r
f
LOAD
LOAD
Trip Points
V
V
DCDIV/LOPWR Threshold
V
V
V
V
V
V
or V
or V
or V
Falling
Rising
= 1.19V
●
●
1.166
1.19
30
1.215
V
mV
nA
mV
V
TR
DCDIV
DCDIV
DCDIV
LOPWR
LOPWR
LOPWR
DCDIV/LOPWR Hysteresis Voltage
DCDIV/LOPWR Input Bias Current
Short-Circuit Comparator Threshold
Fast Power Path Turn-Off Threshold
THYS
BVT
I
20
200
115
7.9
V
V
V
– V , V ≥ 5V
90
6
100
7
TSC
SCP
SCN CC
Rising from V
CC
FTO
DCDIV
Overvoltage Shutdown Threshold as a
Percent of Programmed Charger Voltage
Rising from 0.8V until TGATE and BGATE
SET
Stop Switching
107
%
OVSD
DACs
I
I
I
Resolution
Guaranteed Monotonic
10
6
Bits
RES
DAC
DAC
Pulse Period:
Normal Mode
t
t
10
50
15
µs
ms
IP
ILOW
Wake-Up Mode
Charging Current Granularity
R
R
R
R
= (Short I
= 10k ±1%
= 33k ±1%
to GND)
1
2
4
4
mA
mA
mA
mA
ILIMIT
ILIMIT
ILIMIT
ILIMIT
LIMIT
= Open (or Short I
to V
)
)
LIMIT
CC2
CC2
I
I
Wake-Up Charging Current (Note 5)
Charging Current Limit
60
80
100
mA
WAKE_UP
LIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
R
ILIMIT
= 0 (Short I
= 10k ±1%
= 33k ±1%
to GND)
●
●
●
●
980
1000
2000
3000
4000
1070
2140
3210
4280
mA
mA
mA
mA
LIMIT
1960
2490
3920
= Open (or Short I
to V
LIMIT
V
V
Resolution
Guaranteed Monotonic (5V < V
< 25V)
11
Bits
RES
DAC
BAT
1760f
3
LTC1760
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V
SYMBOL
PARAMETER
Granularity
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
16
mV
STEP
DAC
Charging Voltage Limit
(Note 7)
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
R
VLIMIT
= 0 (Short V
= 10k ±1%
= 33k ±1%
= 100k ±1%
to GND)
●
●
●
●
●
8400
12608
16832
21024
8432
12640
16864
21056
32768
8464
12672
16896
21088
mV
mV
mV
mV
mV
LIMIT
LIMIT
= Open (or Short V
to V
)(Note 13)
LIMIT
CC2
Charge Mux Switches
t
t
GCH1/GCH2 Turn-On Time
GCH1/GCH2 Turn-Off Time
V
– V
> 3V, C = 3000pF
LOAD
5
10
ms
ONC
GCHX
GCHX
SCHX
V
V
– V
< 1V, from Time of
= 3000pF
15
µs
OFFC
SCHX
< V
– 30mV, C
LOAD
CSN
BATX
V
V
CH Gate Clamp Voltage
GCH1
GCH2
I
V
V
= 1µA
LOAD
CON
– V
– V
5
5
5.8
5.8
7
7
V
V
GCH1
GCH2
SCH1
SCH2
CH Gate Off Voltage
GCH1
GCH2
I
V
V
=10µA
LOAD
COFF
– V
– V
–0.8
–0.8
–0.4
–0.4
0
0
V
V
GCH1
GCH2
SCH1
SCH2
V
V
CH Switch Reverse Turn-Off Voltage
CH Switch Forward Regulation Voltage
V
V
V
– V , 5V ≤ V
≤ 28V
●
●
5
20
35
40
60
mV
mV
TOC
FC
BATX
CSN
BATX
– V
, 5V ≤ V
BATX
≤ 28V
15
CSN
BATX
GCH1/GCH2 Active Regulation:
Max Source Current
Max Sink Current
– V
= 1.5V
GCHX
SCHX
I
I
–2
2
µA
µA
OC(SRC)
OC(SNK)
V
BATX Voltage Below Which
Charging is Inhibited (Does Not Apply
to Wake-Up Mode)
3.5
4.7
V
CHMIN
PowerPath Switches
t
t
t
Blanking Period after UVLO Trip
Blanking Period after LOPWR Trip
GB1O/GB2O/GDCO Turn-On Time
Switches Held Off
250
1
ms
sec
µs
DLY
Switches in 3-Diode Mode
PPB
V
< –3V, from Time of Battery/DC
GS
●
●
5
10
7
ONPO
Removal, or LOPWR Indication, C
= 3000pF
= 3000pF
LOAD
t
GB1O/GB2O/GDCO Turn-Off Time
V
> –1V, from Time of Battery/DC
3
µs
OFFPO
GS
Removal, or LOPWR Indication, C
LOAD
V
Output Gate Clamp Voltage
I
LOAD
= 1µA
PONO
GB1O
GB2O
GDCO
Highest (V
Highest (V
Highest (V
or V ) – V
4.75
4.75
4.75
6.25
6.25
6.25
7
7
7
V
V
V
BAT1
BAT2
DCIN
SCP
GB1O
GB2O
GDCO
or V ) – V
SCP
or V ) – V
SCP
V
Output Gate Off Voltage
I
= –25µA
LOAD
POFFO
GB1O
GB2O
GDCO
Highest (V
Highest (V
Highest (V
or V ) – V
0.18
0.18
0.18
0.25
0.25
0.25
V
V
V
BAT1
BAT2
DCIN
SCP
GB1O
GB2O
GDCO
or V ) – V
SCP
or V ) – V
SCP
V
V
PowerPath Switch Reverse
Turn-Off Voltage
V
– V
SCP
or V
≤ 28V
– V
DCIN
●
●
5
0
20
60
mV
TOP
FP
SCP
BATX
SCP
6V ≤ V
PowerPath Switch Forward
Regulation Voltage
V
– V
or V
≤ 28V
– V
DCIN SCP
25
50
mV
BATX
SCP
6V ≤ V
SCP
GDCI/GB1I/GB2I Active Regulation:
Source Current
Sink Current
(Note 3)
I
I
–4
75
µA
µA
OP(SRC)
OP(SNK)
1760f
4
LTC1760
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
300
10
MAX
UNITS
µs
t
t
Gate B1I/B2I/DCI Turn-On Time
Gate B1I/B2I/DCI Turn-Off Time
V
V
< –3V, C
> –1V, C
= 3000pF (Note 4)
= 3000pF (Note 4)
ONPI
GS
GS
LOAD
LOAD
µs
OFFPI
V
Input Gate Clamp Voltage
I
= 1µA
LOAD
PONI
GB1I
GB2I
GDCI
Highest (V
Highest (V
Highest (V
or V ) – V
4.75
4.75
4.75
6.7
6.7
6.7
7.5
7.5
7.5
V
V
V
BAT1
BAT2
DCIN
SCP
GB1I
GB2I
GDCI
or V ) – V
SCP
or V ) – V
SCP
V
Input Gate Off Voltage
I
= –25µA
LOAD
POFFI
GB1I
GB2I
GDCI
Highest (V
Highest (V
Highest (V
or V ) – V
0.18
0.18
0.18
0.25
0.25
0.25
V
V
V
BAT1
BAT2
DCIN
SCP
GB1I
GB2I
GDCI
or V ) – V
SCP
or V ) – V
SCP
Thermistor
Thermistor Trip
(COLD-RANGE/OVER-RANGE)
C
= 300pF (Note 9)
●
●
●
●
95
100
30
105
32.5
3.15
575
kΩ
kΩ
kΩ
Ω
LOAD(MAX)
R1A = R2A = 1130Ω ±1%
R1B = R2B = 54900Ω ±1%
Thermistor Trip
(IDEAL-RANGE/COLD-RANGE)
C
= 300pF (Note 9)
28.5
2.85
425
LOAD(MAX)
R1A = R2A = 1130Ω ±1%
R1B = R2B = 54900Ω ±1%
Thermistor Trip
(HOT-RANGE/IDEAL-RANGE)
C
= 300pF (Note 9)
3
LOAD(MAX)
R1A = R2A = 1130Ω ±1%
R1B = R2B = 54900Ω ±1%
Thermistor Trip
C
= 300pF (Note 9)
500
LOAD(MAX)
(UNDER-RANGE/HOT-RANGE)
R1A = R2A = 1130Ω ±1%
R1B = R2B = 54900Ω ±1%
Logic Levels
SCL/SCL1/SCL2/SDA/SDA1/
●
●
●
●
0.8
V
V
SDA2 Input Low Voltage (V )
IL
SCL/SCL1/SCL2/SDA/SDA1/
2.1
–5
SDA2 Input High Voltage (V )
IH
SCL/SCL1/SCL2/SDA/SDA1/
SDA2 Input Leakage Current
V
V
, V , V
, V
,
5
5
µA
µA
µA
SDA SCL SDA1 SCL1
, V
= 0.8V
SDA2 SCL2
SCL/SCL1/SCL2/SDA/SDA1/
SDA2 Input Leakage Current
V
V
, V , V
, V
, V
,
–5
SDA SCL SDA1 SCL1 SDA2
= 2.1V
SCL2
I
SCL1/SDA1/SCL2/SDA2 Pull-Up
Current When Not Connected to
SMBus Host
V
V
= V
= V
= V = 0.4V
SDA2
165
220
350
PULLUP
SCL1
VCC2
SDA1
SCL2
= 4.85V and 5.55V (Current is Through
Internal Series Resistor and Schottky to V
)
CC2
SCL1/SDA1/SCL2/SDA2
Series Impedance to Host SMBus
V
, V
, V
, V
= 0.8V
●
●
●
300
0.4
0.4
Ω
V
SDA1 SCL1 SDA2 SCL2
SCL/SDA Output Low Voltage (V ).
LTC1760 Driving the Pin
I
I
= 350µA
OL
PULLUP
PULLUP
SCL1/SDA1/SCL2/SDA2 Pullup
Output Low Voltage (VOL).
Internal to LTC1760
V
LTC1760 Driving the Pin with Battery
SMBus not Connected to Host SMBus
SCL1/SDA1/SCL2/SDA2
I
= 350µA on Host Side
●
0.4
V
PULLUP
Output Low Voltage (V ).
OL
LTC1760 Driving the Pin with Battery
SMBus Connected to Host SMBus
1760f
5
LTC1760
ELECTRICAL CHARACTERISTICS
unless otherwise noted.
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SCL/SCL1/SCL2/SDA/SDA1/ SDA2/
SMBALERT Power Down Leakage
V
V
V
= 0V, V
SCL SCL1 SCL2 SDA
= 0V,
●
●
2
uA
VCC2
VDDS
, V
, V
, V
,
, V
, V
= 5.5V
SDA1 SDA2 SMBALERT
SMBALERT Output Low Voltage (V
)
I
= 500µA
PULLUP
0.4
17.5
1.5
V
OL
SMBALERT Output Pull-Up Current
V
= 0.4V
3.5
10
µA
SMBALERT
V
V
V
V
V
V
Input Low Voltage (V )
●
●
●
V
V
V
IL_VDDS
IH_VDDS
DDS
DDS
DDS
DDS
IL
Input High Voltage (V )
2.6
3
IH
Operating Voltage
Operating Current
5.5
18
V
V
V
, V
SCL SDA
= V
, V = 5V
VDDS
µA
VDDS
V
V
MODE Input Low Voltage (V )
= 4.85V
= 4.85V
●
●
●
●
V • 0.3
VCC2
V
V
IL_MODE
IH_MODE
IL
VCC2
VCC2
MODE Input High Voltage (V )
V
• 0.7
IH
VCC2
MODE Input Current (I )
MODE = V
MODE = V
• 0.7V, V
• 0.3V, V
= 4.85V
= 4.85V
–1
–1
1
1
µA
µA
IH
VCC2
VCC2
VCC2
MODE Input Current (I )
IL
VCC2
Charger Timing
t
Timeout for Wake-Up Charging and
Controlled Charging
●
140
175
1
210
sec
sec
TIMEOUT
t
Sampling Rate Used by the LTC1760 to
Update Charging Parameters
QUERY
SMBus Timing
SCL Serial-Clock High Period(t
)
)
At I
At I
= 350µA, C
= 350µA, C
= 150pF (Note 8)
= 150pF (Note 8)
●
●
●
●
●
●
●
●
4
µs
µs
ns
ns
V
HIGH
PULLUP
LOAD
LOAD
SCL Serial-Clock Low Period (t
4.7
LOW
PULLUP
SDA/SCL Rise Time (t )
C
C
= 150pF, RPU = 9.31k (Note 8)
= 150pF, RPU = 9.31k (Note 8)
1000
300
r
LOAD
LOAD
SDA/SCL Fall Time (t )
f
SMBus Accelerator Trip Voltage Range
Start-Condition Setup Time (t
0.8
4.7
4
1.42
)
µs
µs
ns
SU:STA
Start-Condition Hold Time (t
)
HD:STA
SDA to SCL Rising-Edge
250
Setup Time (t
)
SU:DAT
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data (t
●
●
300
25
ns
)
HD:DAT
t
The LTC1760 will Release the SMBus
and Terminate the Current Master or
Slave Command if the Command is not
Completed Before this Time
35
ms
TIMEOUT_SMB
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 6. The LTC1760C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet specified
performance at –40°C and 85°C, but is not tested at these extended
temperature limits.
Note 7. Charger servos to the value reported by a Voltage() query. This is
the internal cell voltage measured by the battery electronics and may be
lower than the terminal voltage. See “Operation Section 3.6” for more
information.
Note 2. Battery voltage must be adequate to drive gates of power path
P-channel FET switches. This does not affect charging voltage of the
battery, which can be zero volts during wake-up charging.
Note 3. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are
forced to 10.5V. SCP is set at 12V to measure source current at GDCI,
GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I
and GB2I.
Note 8. C
is the combined capacitance on the host’s SMBus
LOAD
connection and the selected battery’s SMBus connection.
Note 4. Extrapolated from testing with C = 50pF.
L
Note 9. C is the maximum allowed combined capacitance on
THxA, THxB and the battery’s SafetySignalx connections.
LOAD_MAX
Note 5. Accuracy dependent upon external sense resistor and
compensation components.
1760f
6
LTC1760
ELECTRICAL CHARACTERISTICS
Note 10. Does not include current supplied by V to V
(I
or
Note 12. Requested currents below 44mV/R may not servo correctly
SENSE
CC
CC2 VCC2_AC1
I
)
due to charger offsets. The charging current for requested currents below
4mV/R will be between 4mV/R and (Requested Current – 8mA).
VCC2_AC0
Note 11. Measured with thermistors not present, R
removed and SMBALERT = 1. See Applications Information section:
“Calculating IC Operating Current” for example on how to calculate total IC
and R
SENSE
SENSE
VILIM
ILIM
Refer to Applications Information: “Setting Charger Output Current Limit”
for values of R
.
SENSE
operating current.
Note 13. This limit is greater than the absolute maximum for the charger.
Therefore, there is no effective limitation for the voltage when this option
is selected.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Dual Battery Charge Time vs
Sequential Battery Charging
Charging Voltage Accuracy
Charging Current Accuracy
10
5
3500
3000
2500
2000
1500
1000
500
0
–5
BAT2
CURRENT
BAT1
CURRENT
SEQUENTIAL
0
–10
0
–5
3500
3000
2500
2000
1500
1000
500
BAT1
CURRENT
–15
–20
–25
–10
–15
–20
BAT2
DUAL
CURRENT
100
MINUTES
0
0
800
1600
2400
3200
4000
0
100
150
200 250
300
4700
7132
9564
11996 14428 16860
50
ChargingCurrent() (mA)
TIME (MINUTES)
ChargingVoltage() (mV)
1760 G02
1760 G01
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
REQUESTED CURRENT = 3A
REQUESTED VOLTAGE = 12.3V
MAX CHARGER CURRENT = 4.1A
1760 G03
Dual Battery Discharge Time vs
Sequential Battery Discharge
(Li-Ion)
Dual Battery Dischage Time vs
Sequential Battery Discharge
(NiMH)
Dual Charging Batteries with
Different Charge State
3500
3000
2500
2000
1500
1000
500
15
14
13
12
11
10
15
14
13
12
11
10
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
BAT2
VOLTAGE
BAT1
12.0
11.0
10.0
9.0
BAT1
VOLTAGE
DUAL
BAT2
VOLTAGE
DUAL
VOLTAGE
BAT2
VOLTAGE
BAT1
VOLTAGE
BAT2
8.0
BAT2
VOLTAGE
SEQUENTIAL
VOLTAGE
12.0
11.0
10.0
9.0
SEQUENTIAL
BAT1
CURRENT
BAT1
VOLTAGE
BAT1
BAT2
CURRENT
VOLTAGE
11
MINUTES
16
MINUTES
0
8.0
0
20
60
80
100
140
20 40 60 80 100
TIME (MINUTES)
140 160
40
120
0
120
160
180
0
20
60 80 100
140
40
120
TIME (MINUTES)
1760 G04
TIME (MINUTES)
BAT1 INITIAL CAPACITY = 0%
BAT2 INITIAL CAPACITY = 90%
PROGRAMMED CHARGER CURRENT = 3A
PROGRAMMED CHARGER VOLTAGE = 16.8V
BATTERY TYPE: 12V NiMH (MOLTECH NJ1020)
BATTERY TYPE: 10.8V Li-Ion (MOLTECH NI2020)
1760 G06
LOAD: 33W
LOAD CURRENT = 3A
1760 G05
1760f
7
LTC1760
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Charging Current
Load Regulation
Load Dump
100
90
80
70
60
50
40
30
20
10
0
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
14
12
10
8
BAT1
OUTPUT
V
= 20V
IN
VDAC = 12.29V
IDAC = 3000mA
LOAD CURRENT = 1A
T
= 25°C
A
6
LOAD
CONNECTED
4
V
IN
= 20V
VDAC = 12.288V
IDAC = 4000mA
LOAD
2
DISCONNECTED
T
A
= 25°C
0
0
1000
2000
3000
4000
–4 –2
6
8
10 12 14 16
0
2
4
0
0.025
0.10
0.50
2.5 4.0
TIME (ms)
CHARGE CURRENT (mA)
I
(A)
OUT
1760 G09
1760 G08
1760 G07
Power Path Switching 1 and 2
SMBus Accelerator Operation
16
15
14
13
12
11
10
9
C
I
A
= 20µF
V
C
T
= 5V
LOAD
LOAD
CC
LD
A
= 0.8A
= 200pF
5V
T
= 25°C
= 25°C
LTC1760
R
= 15k
PULLUP
LOPWR
THRESHOLD
0V
8
7
6
–50 –40 –30
–20 –10
0
10 20 30 40 50
1µs/DIV
TIME (µs)
1960 G10
1760 G11
U
U
U
PI FU CTIO S
Input Power Related
GDCO (Pin 6): DCIN Output Switch Gate Drive. Together
with GDCI, this pin drives the gate of the P-channel switch
in series with the DCIN input switch.
SCN (Pin 4): PowerPath Current Sensing Negative Input.
This pin should be connected directly to the “bottom”
(output side) of the low valued resistor in series with the
three PowerPath switch pairs, for detecting short-circuit
currentevents.AlsopowerstheLTC1760internalcircuitry
when all other sources are absent.
GDCI(Pin7):DCINInputSwitchGateDrive. Togetherwith
GDCO, this pin drives the gate of the P-channel switch
connected to the DCIN input.
GB1O (Pin 8): BAT1 Output Switch Gate Drive. Together
with GB1I, this pin drives the gate of the P-channel switch
in series with the BAT1 input switch.
SCP (Pin 5): PowerPath Current Sensing Positive Input.
This pin should be connected directly to the “top” (switch
side) of the low valued resistor in series with the three
PowerPath switch pairs, for detecting short-circuit cur-
rent events.
GB1I(Pin9):BAT1InputSwitchGateDrive. Togetherwith
GB1O, this pin drives the gate of the P-channel switch
connected to the BAT1 input.
1760f
8
LTC1760
U
U
U
PI FU CTIO S
GB2O (Pin 10): BAT2 Output Switch Gate Drive. Together
with GB2I, this pin drives the gate of the P-channel switch
in series with the BAT2 input switch.
COMP1 (Pin 37): This is the Compensation Node for the
Amplifier CL1. A capacitor is required from this pin to
GND if input current amplifier CL1 is used. At input
adapter current limit, this node rises to 1V. By forcing
COMP1 to GND, amplifier CL1 will be defeated (no
adapter current limit). COMP1 can source 10µA.
GB2I (Pin 11): BAT2 Input Switch Gate Drive. Together
withGB2O, thispindrivesthegateoftheP-channelswitch
connected to the BAT2 input.
BGATE (Pin 39): Drives the Gate of the Bottom External
MOSFET of the Battery Charger Buck Converter.
CLP (Pin 36): This is the Positive Input to the Supply
Current Limiting Amplifier CL1. The threshold is set at
100mV above the voltage at the DCIN pin. When used to
limit supply current, a filter is needed to filter out the
switching noise.
SW(Pin42):ConnectedtoSourceofTopExternalMOSFET
Switch. Used as reference for top gate driver.
BOOST (Pin 43): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below VCC to (DCIN + VCC).
Battery Charging Related
VSET (Pin 13): The Tap Point of a Programmable Resistor
Divider which Provides Battery Voltage Feedback to the
Charger. A capacitor from CSN to VSET and one from VSET
to GND provide necessary compensation and filtering for
the voltage loop.
TGATE (Pin 44): Drives the Gate of the Top External
MOSFET of the Battery Charger Buck Converter.
SCH1 (Pin 45), SCH2 (Pin 48): Charger MUX Switch
Source Returns. These two pins are connected to the
sources of Q3/Q4 and Q9/Q10 (see Typical Applications).
A small pull-down current source returns these nodes to
0V when the switches are turned off.
ITH (Pin 14): This is the Control Signal of the Inner Loop
of the Current Mode PWM. Higher ITH corresponds to
higher charging current in normal operation. A capacitor
ofatleast0.1µFtoGNDfiltersoutPWMripple.Typicalfull-
scale output current is 30µA. Nominal voltage range for
this pin is 0V to 2.4V.
GCH1 (Pin 46), GCH2 (Pin 47): Charger MUX Switch
Gate Drives. These two pins drive the gates of the back-
to-back N-channel switch pairs, Q3/Q4 and Q9/Q10,
between the charger output and the two batteries (see
Typical Applications).
ISET (Pin 15): A Capacitor from ISET to GND is Required to
FilterHigherFrequencyComponentsfromtheDelta-Sigma
IDAC.
External Power Supply Pins
ILIMIT (Pin 32): An external resistor (RILIMIT) is connected
between this pin and GND. The value of the external
resistor programs the range and resolution of the pro-
grammed charger current.
VPLUS (Pin 1): Supply. The VPLUS pin is connected via
four internal diodes to the DCIN, SCN, BAT1, and BAT2
pins. Bypass this pin with a 0.1µF capacitor and a 1µF
capacitor. See Typical Applications for complete circuit.
VLIMIT (Pin33):Anexternalresistor(RVLIMIT)isconnected
between this pin and GND. The value of the external
resistor programs the range and resolution of the voltage
DAC.
BAT1(Pin3),BAT2(Pin2):Thesetwopinsaretheinputs
from the two batteries for power to the LTC1760.
LOPWR (Pin 12): LOPWR Comparator Input from Exter-
nal Resistor Divider Connected from SCN to GND. If the
voltage at LOPWR pin is lower than the LOPWR com-
parator threshold, then system power has failed and
power is autonomously switched to a higher voltage
source, if available.
CSN(Pin34):CurrentAmplifierCA1Input. Connectthisto
the common output of the charger MUX switches.
CSP (Pin 35): Current Amplifier CA1 Input. This pin and
theCSNpinmeasurethevoltageacrossthesenseresistor,
R
SENSE, to provide the instantaneous current signals re-
quired for both peak and average current mode operation.
1760f
9
LTC1760
U
U
U
PI FU CTIO S
DCDIV (Pin 16): DCDIV Comparator Input from External SDA2 (Pin 21): SMBus Data Signal to Smart Battery 2. Do
Resistor Divider Connected from DCIN to GND. If the not connect to an external pull-up. The LTC1760 connects
voltage at DCDIV pin is above the DCDIV comparator this pin to an internal pull-up (IPULLUP) when required.
threshold, then the AC_PRESENT bit is set and the wall
SDA (Pin 22): SMBus Data Signal to SMBus Host. Also
adapterpowerisconsideredtobeadequatetochargethe
used to indicate charging status of Battery 2. Requires an
batteries. If DCDIV is taken more than 1.8V above VCC,
external pullup to VDDS. Connected to internal SMBus
then all of the power path switches are latched off until all
accelerator.
power is removed.
SDA1 (Pin 23): SMBus Data Signal to Smart Battery 1. Do
DCIN (Pin 41): Supply. External DC power source. A
not connect to an external pull-up. The LTC1760 connects
0.1µF bypass capacitor must be connected to this pin as
this pin to an internal pull-up (IPULLUP) when required.
close as possible. No series resistance is allowed, since
MODE (Pin 26): Used in conjunction with VDDS to allow
SCL, SDA and SMBALERT to indicate charging status.
May also be used as a hardware charge inhibit.
theadaptercurrentlimitcomparatorinputisalsothispin.
Internal Power Supply Pins
VDDS (Pin 20): Power Supply for SMBus Accelerators.
Also used in conjunction with MODE pin to modify the
LTC1760 operating mode.
TH2B (Pin 27): Thermistor Force/Sense Connection to
Smart Battery 2 SafetySignal. Connect to Battery 2 ther-
mistor through resistor network shown in “Typical
Application.”
GND (Pin 24): Ground for Low Power Circuitry.
VCC2 (Pin 25): The VCC2 Power Supply is used Primarily to TH2A (Pin 28): Thermistor Force/Sense Connection to
Power Internal Logic Circuitry. Must be connected to VCC. Smart Battery 2 SafetySignal. Connect to Battery 2 ther-
mistor through resistor network shown in “Typical
PGND (Pin 38): High Current Ground Return for BGATE
Application.”
Driver.
SMBALERT (Pin 29): Active Low Interrupt Pin. Signals
VCC (Pin 40): Internal Regulator Output. Bypass this
SMBus Host that there has been a change of status in
output with at least a 2µF to 4.7µF capacitor. Do not use
battery or AC presence. Open drain with weak current
this regulator output to supply external circuitry except
source pull-up to VCC2 (with Schottky to allow it to be
as shown in the application circuit.
pulled to 5V externally). Also used to indicate charging
SBS Interface Pins
status of Battery 1.
SCL2(Pin17):SMBusClockSignaltoSmartBattery2. Do
not connect to an external pull-up. The LTC1760 connects
this pin to an internal pull-up (IPULLUP) when required.
TH1A (Pin 30): Thermistor Force/Sense Connection to
Smart Battery 1 SafetySignal. Connect to Battery 1 ther-
mistor through resistor network shown in “Typical
Application.”
SCL (Pin 18): SMBus Clock Signal to SMBus Host. Also
used to determine flashing rate for stand-alone charge
indicators. Requires an external pullup to VDDS (normal
SMBus operating mode). Connected to internal SMBus
accelerator.
TH1B (Pin 31): Thermistor Force/Sense Connection to
Smart Battery 1 SafetySignal. Connect to Battery 1 ther-
mistor through resistor network shown in “Typical
Application.”
SCL1(Pin19):SMBusClockSignaltoSmartBattery1. Do
not connect to an external pull-up. The LTC1760 connects
this pin to an internal pull-up (IPULLUP) when required.
1760f
10
LTC1760
W
BLOCK DIAGRA
GB1I GB1O
GB2I GB2O
11 10
GDCI GDCO
9
8
7
6
100mV
SCP
SCN
5
4
+
SHORT CIRCUIT
100Ω
SWB1
DRIVER
SWB2
DRIVER
SWDC
DRIVER
–
I
32
33
LIMIT
LIMIT
DECODER
V
LIMIT
CHARGE
PUMP
V
CC2
DCIN
10µA
ON
–
GCH1
SCH1
46
45
+
SMBALERT
MODE
29
26
ON
–
+
SEQUENCER
GCH2
47
CSN
AC_PRESENT
V
20
18
22
19
23
17
DDS
SCH2
BAT1
48
3
SCL
SDA
SMBus
INTERFACE
2
BAT2
SCL1
SDA1
SCL2
CHARGE
V
1
SCN
PLUS
21 SDA2
V
25
40
24
CC2
V
CC
TH1A
TH1B
30
31
28
27
15
V
CC
REGULATOR
SAFETY
SIGNAL
GND
TH2A
TH2B
DECODER
+
–
16
DCDIV
I
PowerPath
CONTROLLER
10-BIT ∆Σ
CURRENT DAC
SET
+
–
LOPWR
DCIN
12
41
1.19V
CSP-CSN
3kΩ
–
0.86V
3k
3k
0V
–
CSP
CSN
35
34
CSN
OSCILLATOR
+
–
CA1
+
LOW DROP
DETECT
BGATE
T
Ω
ON
g
= 1.4m
–
+
m
CA2
43
44
42
BOOST
TGATE
SW
0.8V
BUFFERED I
+
TH
÷15
S
+
PWM
LOGIC
–
I
Q
CMP
V
CC
3mV
–
R
BGATE
PGND
39
38
–
+
I
REV
40mV
Ω
DCIN
100mV
g = 0.4m
m
+
400k
CL1
–
Ω
36
CLP
V
13
11-BIT ∆Σ
VOLTAGE DAC
SET
g
= 1.4m
m
EA
+
0.8V
37
COMP1
14
1760 BD
I
TH
1760f
11
LTC1760
U U
(For Operation Section)
TABLE OF CO TE TS
1
Overview.............................................................................................................................................................................................. 13
The SMBus Interface ........................................................................................................................................................................... 13
SMBus Interface Overview............................................................................................................................................................... 13
Data Bit Definition of Supported SMBus Functions.......................................................................................................................... 14
Description of Supported SMBus Functions .................................................................................................................................... 16
BatterySystemState() ('h01) ........................................................................................................................................................ 16
BatterySystemStateCont() ('h02) ................................................................................................................................................. 17
BatterySystemInfo() ('h04) .......................................................................................................................................................... 18
LTC() ('h3c) ................................................................................................................................................................................. 19
BatteryMode() ('h03) ................................................................................................................................................................... 19
Voltage() ('h09) ........................................................................................................................................................................... 19
Current() ('h0a)............................................................................................................................................................................ 20
ChargingCurrent() ('h14) ............................................................................................................................................................. 20
ChargingVoltage() ('h15) ............................................................................................................................................................. 20
AlarmWarning() ('h16) ................................................................................................................................................................ 20
AlertResponse() ........................................................................................................................................................................... 21
SMBus Dual Port Operation ............................................................................................................................................................. 21
LTC1760 SMBus Controller Operation ............................................................................................................................................. 22
LTC1760 SMBALERT Operation ...................................................................................................................................................... 24
Charging Algorithm Overview .............................................................................................................................................................. 24
Wake-Up Charging Initiation ............................................................................................................................................................ 24
Wake-Up Charging Termination....................................................................................................................................................... 24
Wake-Up Charging Current and Voltage Limits ............................................................................................................................... 25
Controlled Charging Initiation .......................................................................................................................................................... 25
Controlled Charging Termination ..................................................................................................................................................... 25
Controlled Charging Current and Voltage Programming .................................................................................................................. 26
System Power Management Algorithm and Battery Calibration .......................................................................................................... 27
Turning Off System Power............................................................................................................................................................... 27
Power-By Algorithm When No Battery is Being Calibrated .............................................................................................................. 27
Power-By Algorithm When a Battery is Being Calibrated ................................................................................................................. 27
Power-By Reporting ........................................................................................................................................................................ 27
Battery Calibration (Conditioning) ....................................................................................................................................................... 28
Selecting a Battery to be Calibrated ................................................................................................................................................. 28
Initiating Calibration of Selected Battery .......................................................................................................................................... 28
Terminating Calibration of Selected Battery ..................................................................................................................................... 28
MODE Pin Operation............................................................................................................................................................................ 29
Stand Alone Charge Indication......................................................................................................................................................... 29
Hardware Charge Inhibit .................................................................................................................................................................. 29
Charging When SCL and SDA are Low ............................................................................................................................................ 29
Charging With an SMBus Host ........................................................................................................................................................ 29
Battery Charger Controller ................................................................................................................................................................... 29
Charge MUX Switches ..................................................................................................................................................................... 30
Dual Charging .................................................................................................................................................................................. 30
PowerPath Controller .......................................................................................................................................................................... 31
Autonomous PowerPath Switching ................................................................................................................................................. 31
Short-Circuit Protection ................................................................................................................................................................... 31
Emergency Turn-Off ........................................................................................................................................................................ 32
Power-Up Strategy .......................................................................................................................................................................... 32
The Voltage DAC Block ........................................................................................................................................................................ 32
The Current DAC Block ........................................................................................................................................................................ 32
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.3.11
2.4
2.5
2.6
3
3.1
3.2
3.3
3.4
3.5
3.6
4
4.1
4.2
4.3
4.4
5
5.1
5.2
5.3
6
6.1
6.2
6.3
6.4
7
7.1
7.2
8
8.1
8.2
8.3
8.4
9
10
1760f
12
LTC1760
U
OPERATIO
(Refer to Block Diagram and Typical Application Figure)
1 Overview
The LTC1760 is composed of an SMBus interface with
dual port capability, a sequencer for managing system
power and the charging and discharging of two batteries,
abatterychargercontroller,chargemuxcontroller,power-
path controller, a 10-bit current DAC (IDAC) and 11-bit
voltage DAC (VDAC). When coupled with optional system
software for generating composite battery information, it
forms a complete Smart Battery System Manager for
charging and selecting two smart batteries. The battery
charger is controlled by the sequencer which uses the
level 3 SMBus interface to read ChargingVoltage(), Volt-
age(), ChargingCurrent(), Current(), Alarm() and
BatteryMode().Thisinformation,togetherwiththermistor
measurements allows the sequencer to select the charg-
ing battery and safely servo on voltage and current.
ChargingcanbeaccomplishedonlyifthevoltageatDCDIV
indicates that sufficient voltage is available from the input
power source, usually an AC adapter. The charge mux,
which selects the battery to be charged, is capable of
charging both batteries simultaneously. The charge mux
switch drivers are configured to allow charger current to
share between the two batteries and to prevent current
from flowing in a reverse direction in the switch. The
amount of current that each battery receives will depend
upon the relative capacity of each battery and the battery
voltage. This can result in significantly shorter charging
times (up to 50% for Li-Ion batteries) than sequential
charging of each battery.
diode-like behavior from the FET switches, without the
attendant high power dissipation from diodes. The HOST
is informed of this 3-Diode mode status when it polls the
powerpath status register via the SMBus interface. High
speed powerpath switching at the LOPWR trip point is
handled autonomously.
Simultaneous discharge of both batteries is supported.
The switch drivers prevent reverse current flow in the
switches and automatically discharge both batteries into
the load, sharing current according to the relative capacity
ofthebatteries.Simultaneousdualdischargecanincrease
battery operating time by up to 10% by reducing losses in
the switches and reducing internal battery losses associ-
ated with high discharge rates.
2 The SMBus Interface
2.1 SMBus Interface Overview
The SMBus interface allows the LTC1760 to communicate
with two batteries and the SMBus Host. The SMBus
Interfacesupportstruedualportoperationbyallowingthe
SMBus Host to be connected to the SMBus of either
battery. The LTC1760 is able to operate as an SMBus
master or slave device.
References:
Smart Battery System Manager Specification: Revision
1.1, SBS Implementers Forum.
The sequencer also selects which of the pairs of PFET
switches will provide power to the system load. If the
system voltage drops below the threshold set by the
LOPWR resistor divider, then all of the output-side PFETs
are turned on quickly. The input-side PFETs act as diodes
in this mode and power is taken from the highest voltage
source available at the DCIN, BAT1, or BAT2 inputs. The
input-sidepowerpathswitchdriverthatisdeliveringpower
then closes its input switch to reduce the power dissipa-
tion in the PFET bulk diode. In effect, this system provides
Smart Battery Data Specification: Revision 1.1, SBS
Implementers Forum.
Smart Battery Charger Specification: Revision 1.1, SBS
Implementers Forum
System Management Bus Specification: Revision 1.1,
SBS Implementers Forum
I2C-Bus and How to Use it: V1.0, Philips Semiconductor.
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2.2 Data Bit Definition of Supported SMBus Functions.
LTC1760
SMBus
Mode Access
Data Bit or Nibble Definition/Allowed Values
(See section 2.3 for Details)
SMBus
Address
Command Data
Function
Code
Type D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
BatterySystemState()
Slave
Read/ 7'b0001_010
Write
8'h01
Status/
Control
0
0
0/1 0/1
0
0
0/1 0/1
0
0
0/1 0/1
0
0 0/1 0/1
BatterySystemStateCont() Slave
Read/ 7'b0001_010
Write
8'h02
Status/
Control
0
0
0
0
0
0
0
0/1 0/1
0
0/1 0/1 0/1 0/1 1 0/1 0/1
BatterySystemInfo()
LTC()
Slave
Slave
Read 7'b0001_010
8'h04
8'h3c
Status
BATTERY
SYSTEM
REVISION
RESERVED
RESERVED
BATTERY
SUPPORTED
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
Read/ 7'b0001_010
Write
Status/
Control
0/1
0
0
0
0
0
1
0/1
0
0
0
0
0
0
1
BatteryMode()
Master
Read 7'b0001_011
8'h03
Status
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
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Data Bit or Nibble Definition/Allowed Values
(See section 2.3 for Details)
Type D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
LTC1760
Mode Access
SMBus
Address
Command Data
Code
Function
Current()
Master
Master
Master
Master
Master
Read 7'b0001_011
Read 7'b0001_011
Read 7'b0001_011
Read 7'b0001_011
7'b0001_011
8'h0a
Value
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Value
Voltage()
8'h09
8'h14
8'h15
8'h16
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Value
ChargingCurrent()
ChargingVoltage()
AlarmWarning ()
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Value
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Status
Read
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Register
AlertResponse ()
see (1)
Slave
Read 7'b0001_100
Byte
N/A
0
0
0
1
0
1
0
0
(1) Read-byte format. 'h14 is returned as the interrupt address of the LTC1760.
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2.3 Description of Supported SMBus Functions
The functions are described as follows:
Function Name() (command code)
Description:
• The LTC1760 autonomously changes the configura-
tion of the battery(s) being charged (Polling only).
Purpose:
Used by the SMBus Host to determine the present state of
the LTC1760 and the attached batteries. It also may be
used to determine the state of the battery system after the
LTC1760 notifies the SMBus Host of a change via
SMBALERT.
A brief description of the function.
Purpose:
The purpose of the function, and an example where
appropriate.
SMBus Protocol: Read or Write Word.
Input/Output: word – Refer to “Section 2.2” for bit
mapping.
SMBus Protocol: Refer to Section 2.5 and to the SMBus
specification for more details.
SMB_BAT[4:1]
Input, Output or Input/Output: A description of the data
supplied to, or returned by, the function.
Theread/writeSMB_BAT[4:1]nibbleisusedbytheSMBus
Host to select with which individual battery to communi-
cate or to determine with which individual battery it is
communicating.
Whenever the LTC1760 encounters a valid command with
invaliddata,itACK’sthecommand,andignorestheinvalid
data. For example, if an attempt is made to select battery
A and B to simultaneously communicate with the system
host, the LTC1760 will just ignore the request.
For example, an application that displays the remaining
capacity of all batteries would write to this nibble to
individually select each battery in turn and get its capacity.
2.3.1 BatterySystemState() ('h01)
Description:
Allowed values are:
'b0010: SMBus Host is communicating with Battery 2.
ThisfunctionreturnsthepresentstateoftheLTC1760and
allows access to individual batteries. The information is
broken into four nibbles that report:
'b0001: SMBus Host is communicating with Battery 1.
(Power On Reset Value)
To change this nibble, set only one of the lower two bits of
this nibble high. All other values will simply be ignored.
Which battery is communicating with the SMBus Host
Which battery(s), if any, or AC is powering the system
Which battery(s) is connected to the Smart Charger
Which battery(s) is present.
POWER_BY_BAT[4:1]
The read only POWER_BY_BAT[4:1] nibble is used by the
SMBusHosttodeterminewhichbattery(s)ispoweringthe
system. All writes to this nibble will be ignored.
The LTC1760 provides a mechanism to notify the system
whenever there is a change in its state. Specifically, the
LTC1760 provides the system with a notification when-
ever:
Allowed values are:
'b0011:SystembeingpoweredbyBattery2andBattery
1 simultaneously.
• Abatteryisaddedorremoved(PollingorSMBALERT).
'b0010: System being powered by Battery 2.
'b0001: System being powered by Battery 1.
'b0000: System being powered by AC.
• AC power is connected or disconnected (Polling or
SMBALERT).
• The LTC1760 autonomously changes the configura-
tion of the battery(s) supplying power (Polling only).
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CHARGE_BAT[4:1]
Purpose:
The read only CHARGE_BAT[4:1] nibble is used by the
SMBus Host to determine which, if any, battery is being
charged. All writes to this nibble will be ignored.
Used by the SMBus Host to retrieve additional state
information from the LTC1760 and the overall system
power configuration. It may also be used by the system to
prohibit any battery charging.
Allowed values are:
SMBus Protocol: Read or Write Word.
'b0011: Battery 2 and Battery 1 being charged.
'b0010: Battery 2 is being charged.
'b0001: Battery 1 is being charged.
'b0000: No Battery being charged.
Input/Output: word - Refer to “Section 2.2” for bit
mapping
AC_PRESENT Bit
The read only AC_PRESENT bit is used to show the user
the status of AC availability to power the system. It may be
used internally by the SMBus Host in conjunction with
other information to determine when it is appropriate to
allow a battery conditioning cycle. Whenever there is a
change in the AC status, the LTC1760 asserts SMBALERT
low. In response, the system has to read this register to
determine the actual presence of AC. The LTC1760 uses
the DCDIV pin to measure the presence of AC.
An indication that multiple batteries are being charged
simultaneously does not indicate that the batteries are
being charged at the same rate or that they will complete
their charge at the same time. To actually determine when
an individual battery will be fully charged, use the
SMB_BAT[4:1] nibble to individually select the battery of
interest and read the TimeToFull() value.
PRESENT_BAT[4:1]
Allowed values are:
The read only PRESENT_BAT[4:1] nibble is used by the
SMBus Host to determine how many and which batteries
are present. All writes to this nibble will be ignored.
'b1: The LTC1760 has determined that AC is present.
'b0:TheLTC1760hasdeterminedthatACisnotpresent.
POWER_NOT_GOOD Bit
Allowed values are:
'b0011: Battery 2 and Battery 1 are present.
'b0010: Battery 2 is present.
'b0001: Battery 1 is present.
'b0000: No batteries are present.
The read only POWER_NOT_GOOD bit is used to show
thatthevoltagedeliveredtothesystemloadisinadequate.
This is determined by the comparator on the LOPWR pin.
Allowed values are:
'b1: The LTC1760 has determined that the voltage
delivered to the system load is inadequate.
2.3.2 BatterySystemStateCont() ('h02)
Description:
'b0: The LTC1760 has determined that the voltage
delivered to the system load is adequate.
This function returns additional state information of the
LTC1760 and provides an interface to prohibit charging.
This command also removes any requirement for the
SMBus Host to communicate directly with the charger to
obtain AC presence information. When the LTC1760 is
used, access to the charger address, 'h12, is blocked.
CALIBRATE_REQUEST_SUPPORT Bit
The read only CALIBRATE_REQUEST_SUPPORT bit is
always set to indicate that the LTC1760 has a mechanism
todeterminewhenanyoftheattachedbatteriesareinneed
of a calibration cycle.
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CALIBRATE_REQUEST Bit
CALIBRATE_BAT[4:1] Nibble
The read only CALIBRATE_REQUEST bit is set whenever
the LTC1760 has determined that one or more of the
connected batteries need a calibration cycle.
Theread/writeCALIBRATE_BAT[4:1]nibbleisusedbythe
SMBus Host to select the battery to be calibrated or to
determine which individual battery is being calibrated.
Allowed values are:
Allowed read values are:
'b1: The LTC1760 has determined that one or both
batteries requires calibration.
'b0010: Battery 2 is being calibrated . CALIBRATE must
be 1.
'b0: The LTC1760 has determined that no batteries
require calibration.
'b0001: Battery 1 is being calibrated. CALIBRATE must
be 1.
CHARGING_INHIBIT Bit
'b0000: No batteries are being calibrated.
Allowed write values are:
The read/write CHARGING_INHIBIT is used by the SMBus
Host to inhibit charging or to determine if charging is
inhibited. This bit is also set if MODE is used to inhibit
charging.
'b0010: Select Battery 2 for calibration.
'b0001: Select Battery 1 for calibration.
'b0000: Allow LTC1760 to choose battery
to be calibrated.
Allowed values are:
'b1: The LTC1760 must not allow any battery charging
to occur.
All other values will simply be ignored. This provides a
mechanismtoupdatetheotherBatterySystemStateCont()
bits without altering this nibble.
'b0: The LTC1760 may charge batteries as needed,
(Power On Reset Value).
2.3.3 BatterySystemInfo ()('h04)
Description:
CHARGER_POR Bit
The read/write CHARGER_POR bit is used to force a
charger power on reset.
The SMBus Host uses this command to determine the
capabilities of the LTC1760.
Writing a 1 to this bit will cause a charger power on reset
with the following effects.
Purpose:
• Charging will be turned off and wake-up charging will
be resumed. This is the same as if the batteries were
removed and then reinserted.
Allows the SMBus Host to determine the number of
batteries the LTC1760 supports as well as the specifica-
tion revision implemented by the LTC1760.
• The three minute wake-up watchdog timer will be
restarted.
SMBus Protocol: Read Word
Input/Output: word — Refer to “Section 2.2” for bit
mapping.
Writing a 0 to this bit has no effect.
A read of this bit always returns a 0.
CALIBRATE Bit
BATTERIES_SUPPORTED Nibble
The read only BATTERIES_SUPPORTED nibble is used by
the SMBus Host to determine how many batteries the
LTC1760 can support. The two-battery LTC1760 always
returns 'b0011 for this nibble.
The read/write CALIBRATE bit is used either to show the
status of battery calibration cycles in the LTC1760 or to
begin or end a calibration cycle.
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2.3.5 BatteryMode() ('h03)
Description:
BATTERY_SYSTEM_REVISION Nibble
The read only BATTERY_SYSTEM_REVISION nibble re-
ports the version of the Smart Battery System Manager
specification supported.
This function is used by the LTC1760 to read the Battery
Mode register.
LTC1760returns'b1000forthisnibble,indicatingVersion
1.0 without optional PEC support.
Purpose:
Allows the LTC1760 to determine if a battery requires a
conditioning/calibration cycle.
2.3.4 LTC() ('h3c)
Description:
SMBus Protocol: Read Word. LTC1760 reads Battery 1 or
Battery 2 as an SMBus Master.
This function returns the LTC Version nibble and allows
the user to perform expanded Smart Battery System
Manager functions.
Input/Output: word — Refer to “Section 2.2” for bit
mapping.
CONDITION_FLAG Bit
Purpose:
The CONDITION_FLAG bit is set whenever the battery
requires calibration.
Used by the SMBus Host to determine the version of the
LTC1760 and to program and monitor TURBO and
POWER_OFF special functions.
Allowed values:
SMBus Protocol: Read or Write Word.
'b1 - Battery requires calibration. (Also known as a
Condition Cycle Request).
Input/Output: word — Refer to “Section 2.2” for bit
mapping.
'b0 - Battery does not require calibration.
POWER_OFF Bit
2.3.6 Voltage() ('h09)
Description:
Thisread/writebitallowstheLTC1760toturnoffallpower
path sources.
Allowed values:
This function is used by the LTC1760 to read the actual
cell-pack voltage .
'b1: All power path sources are off.
Purpose:
'b0: All power path sources are enabled. (Power
On Reset Value).
AllowstheLTC1760todeterminethecellpackvoltageand
close the charging voltage servo loop.
TURBO Bit
SMBus Protocol: Read Word. LTC1760 reads Battery 1 or
Battery 2 as an SMBus Master.
This read/write bit allows the LTC1760 to enter TURBO
charging mode.
Output: unsigned integer — battery terminal voltage in
Allowed values:
milli-volts. Refer to "Section 2.2" for bit mapping.
'b1: Turbo Charging mode enabled.
Units: mV.
'b0: Turbo Charging mode disabled. (Power On Reset
Value).
Range: 0 to 65,535 mV.
LTC_Version[3:0] Nibble
Thisreadonlynibblealwaysreturns'b0001astheLTC1760
version.
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OPERATIO
2.3.7 Current() ('h0a)
Purpose:
Description:
Allows the LTC1760 to determine the maximum charging
voltage.
This function is used by the LTC1760 to read the actual
current being supplied through the battery terminals.
SMBus Protocol: Read Word. LTC1760 reads Battery 1 or
Battery 2 as an SMBus Master.
Purpose:
Output:unsignedinteger—chargeroutputvoltageinmV.
Allows the LTC1760 to determine how much current a
battery is receiving through its terminals and close the
charging current servo loop.
Refer to Section 2.2 for bit mapping.
Units: mV.
SMBus Protocol: Read Word. LTC1760 reads Battery 1 or
Battery 2 as an SMBus Master.
Range: 0 to 65,534 mV.
2.3.10 AlarmWarning () ('h16)
Description:
Output: signed integer (2’s complement) — charge/dis-
charge rate in mA increments - positive for charge, nega-
tive for discharge. Refer to "Section 2.2" for bit mapping.
This function is used by the LTC1760 to read the Smart
Battery alarm register.
Units: mA.
Purpose:
Range: 0 to 32,767 mA for charge or 0 to -32,768 mA for
discharge.
AllowstheLTC1760todeterminethestateofallapplicable
alarm flags.
2.3.8 ChargingCurrent() ('h14)
Description:
SMBus Protocol: Read Word. LTC1760 reads Battery 1 or
Battery 2 as an SMBus Master.
This function is used by the LTC1760 to read the Smart
Battery’s desired charging current.
Output: unsigned integer – Refer to “Section 2.2” for bit
mapping.
Purpose:
OVER_CHARGED_ALARM Bit
Allows the LTC1760 to determine the maximum charging
current.
The read only OVER_CHARGED_ALARM bit is used by the
LTC1760 to determine if charging may continue.
SMBus Protocol: Read Word. LTC1760 reads Battery 1 or
Battery 2 as an SMBus Master.
Allowed values are:
'b1: The LTC1760 will not charge this battery.
Output: unsigned integer — maximum charger output
current in mA. Refer to "Section 2.2" for bit mapping.
'b0: The LTC1760 may charge this battery if other
conditions permit charging.
Units: mA.
TERMINATE_CHARGE_ALARM Bit
Range: 0 to 65,534 mA.
The read only TERMINATE_CHARGE_ALARM bit is used
by the LTC1760 to determine if charging may continue.
2.3.9 ChargingVoltage() ('h15)
Description:
Allowed values are:
This function is used by the LTC1760 to read the Smart
Battery’s desired charging voltage.
'b1: The LTC1760 will not charge this battery.
'b0: The LTC1760 may charge this battery if other
conditions permit charging.
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OPERATIO
'b0: The LTC1760 may continue discharging this
TERMINATE_CHARGE_RESERVED Bit
battery.
The read only TERMINATE_CHARGE_RESERVED bit is
used by the LTC1760 to determine if charging may con-
tinue.
2.3.11 AlertResponse ()
Description:
Allowed values are:
The SMBus Host uses the Alert Response Address (ARA)
to quickly identify the generator of an SMBALERT# event.
'b1: The LTC1760 will not charge this battery.
'b0: The LTC1760 may charge this battery if other
conditions permit charging.
Purpose:
The LTC1760 will respond to an ARA if the SMBALERT
signal is actively pulling down the SMBALERT# bus. The
LTC1760 will follow the prioritization reporting as defined
in the “System Management Bus Specification”.
OVER_TEMP_ALARM Bit
ThereadonlyOVER_TEMP_ALARMisusedbytheLTC1760
to determine if charging may continue.
Allowed values are:
SMBus Protocol:A 7-bit Addressable Device Responds to
an ARA.
'b1: The LTC1760 will not charge this battery.
Output:
'b0: The LTC1760 may charge this battery if other
conditions permit charging.
The device address will be sent to the SMBus Host. The
LTC1760 device address is 0x14 (or 0x0a if just looking at
the 7 bit address field).
TERMINATE_DISCHARGE_ALARM Bit
The read only TERMINATE_DISCHARGE_ALARM bit is
used by the LTC1760 to determine if discharge from the
battery is still allowed. This is used for power path man-
agement and battery calibration.
The following events will cause the LTC1760 to pull-down
the SMBALERT# bus through the SMBALERT pin:
• Change of AC_PRESENT in the
BatterySystemStateCont() function.
Allowed values are:
• Change of BATTERY_PRESENT in the
BatterySystemState() function.
'b1: The LTC1760 will terminate calibration and should
try to not use this battery in the power path. When all
other power paths fail the LTC1760 will ignore this
alarm and still try to supply system power from this
source.
• Internal power on reset condition.
Refer to "Section 2.2" for bit mapping.
2.4 SMBus Dual Port Operation
'b0: The LTC1760 may continue discharging this
battery.
The SMBus Interface includes the LTC1760’s SMBus
controller, as well as circuitry to arbitrate and connect the
battery and SMBus Host interfaces. The SMBus controller
generates and interprets all LTC1760 SMBus functions.
The dual port operation allows the SMBus Host to be
connected to the SMBus of either battery by setting the
SMB_BAT[4:1] nibble. Arbitration is handled by stretch-
ing an SMBus start sequence when a bus collision might
occur.Wheneverconfigurationsareswitched,theLTC1760
willgenerateaharmlessSMBusresetonSMB1andSMB2
as required. The four possible configurations are illus-
trated in Figure 1. Sample SMBus communications are
shown in Figures 2 and 3.
FULLY_DISCHARGED Bit
The read only FULLY_DISCHARGED bit is used by the
LTC1760 to determine if discharge from the battery is still
allowed. This is used for power path management and
battery calibration.
Allowed values are:
'b1: The LTC1760 will terminate calibration and should
try to not use this battery in the power path. When all
other power paths fail the LTC1760 will ignore this
alarm and still try to supply system power from this
source.
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OPERATIO
SMB2*
SMB1*
SMB2*
SMB1*
BAT2
BAT1
BAT2
BAT1
SMB*
SMB*
HOST
HOST
LTC1760
SMBus
CONTROLLER
LTC1760
SMBus
CONTROLLER
HOST, LTC1760 AND BAT1 CAN COMMUNICATE.
BAT2 ORIGINATED COMMANDS ARE IGNORED.
LTC1760 AND BAT2 CAN COMMUNICATE. HOST AND
BAT1 ORIGINATED COMMANDS ARE STRETCHED IF
THE LTC1760 IS COMMUNICATING WITH BAT2.
(1a)
(1b)
SMB2*
SMB2*
BAT2
BAT1
BAT2
BAT1
SMB*
SMB*
HOST
HOST
SMB1*
SMB1*
LTC1760
SMBus
CONTROLLER
LTC1760
SMBus
CONTROLLER
LTC1760 AND BAT1 CAN COMMUNICATE. HOST AND
BAT2 ORIGINATED COMMANDS ARE STRETCHED IF
THE LTC1760 IS COMMUNICATING WITH BAT1.
HOST, LTC1760 AND BAT2 CAN COMMUNICATE.
BAT1 ORIGINATED COMMANDS ARE IGNORED.
1760 F01
(1c)
(1d)
*SMB INCLUDES SCL AND SDA, SMB1 INCLUDES SCL1 AND SDA1, AND SMB2 INCLUDES SCL2 AND SDA2.
Figure 1. Switch Configurations Used by the LTC1760 for Managing Dual Port Battery Communication
the data transmission with the invalid data will still be
ACK’ed.
2.5 LTC1760 SMBus Controller Operation
SMBus communication with the LTC1760 is handled by
theSMBusController,asub-blockoftheSMBusInterface.
Data is clocked into the SMBus Controller block shift
registeraftertherisingSCLedge.Dataisclockedoutofthe
SMBus Control block shift register after the falling edge of
SCL.
When the LTC1760, acting as a bus master receives a
NACK, it will terminate the transmission and provide a
STOP condition on the bus.
Detection of a STOP condition, power on reset, or SMBus
time-out will reset the controller to an initial state at any
time.
The LTC1760 acting as a slave will acknowledge (ACK)
each byte of serial data. The Command byte will be
NACKed if an invalid command code is transmitted to the
LTC1760. The SMBus Controller must respond if ad-
dressed as a combined Smart Battery System Manager
(Address 14). A valid address includes a legal Read/Write
bit. TheSMBusControllerwillignoreinvaliddataalthough
The LTC1760 supports ARA, Word Write and Word Read
protocols as an SMBus slave. The LTC1760 supports
Word Read protocol as an SMBus master.
Refer to “System Management Bus Specification” for
complete description of required operation and symbols.
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OPERATIO
thermistor is reporting IDEAL-RANGE, and the battery
fails to respond to an SMBus query. This is an important
feature for handling deeply discharged NiMh batteries.
These batteries may begin to talk while being charged and
go silent once charging has stopped.
2.6 LTC1760 SMBALERT Operation
The SMBALERT pin allows the LTC1760 to signal to the
SMBus Host that there has been a change of status.
This pin is asserted low whenever there is a change in
battery presence, AC presence or after a power on reset
event. This pin is cleared during an Alert Response or
any of the following reads:
Wake-up charging is disabled if the battery thermistor is
COLD-RANGEorUNDER-RANGEandthebatteryhasbeen
charged for longer than tTIMEOUT
.
BatterySystemState(),BatterySystemStateCont(),
BatterySystemInfo(), or LTC().
3.2 Wake-Up Charging Termination
3 Charging Algorithm Overview
3.1 Wake-Up Charging Initiation
TheLTC1760willterminatewake-upchargingwhenanyof
the following conditions are met:
The following conditions must be met in order to allow
wake-up charging:
1. Battery removal (thermistor indicating OVER-RANGE)
2. AC is removed.
1. The battery thermistor must be COLD-RANGE, IDEAL-
RANGE, or UNDER-RANGE.
3. The SMBus Host issues a calibration request by setting
BatterySystemStateCont(CALIBRATE) high.
2. AC must be present.
4. Any response to an LTC1760 master read of
ChargingCurrent(), Current(), ChargingVoltage(), or Volt-
age(). Note that the LTC1760 ignores all writes from the
battery.
3.BatterySystemStateCont(CHARGING_INHIBIT)mustbe
de-asserted (or low).
4. Hardware controlled charging inhibit must be
de-asserted (MODE not low with VDDS high).
5. AnyofthefollowingAlarmWarning()bitsassertedhigh:
Wake-up charging initiates when a newly inserted battery
does not respond to any LTC1760 master read com-
mands. Only one battery will wake-up charge at a time.
When two batteries are inserted and both require wake-up
charging, Battery 1 will wake-up charge first. Battery 2 will
only wake-up charge when Battery 1 terminates wake-up
charging.
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM
TERMINATE_CHARGE_RESERVED
OVER_TEMP_ALARM
Note that the LTC1760 ignores all writes from the battery.
Eachbattery’schargealarmiscachedinsidetheLTC1760.
This bit will be set when any of the upper four bits of the
battery’s AlarmWarning() response are set. This bit will
remain set if a subsequent AlarmWarning() fails to re-
spond. The cached alarm will be cleared by any of the
following conditions.
Wake-up charging takes priority over controlled charging;
this prevents one battery from tying up the charger when
it would be advantageous to dual charge two deeply
discharged batteries.
The LTC1760 will attempt to reinitiate wake-up
charging on both batteries after the SMBus Host asserts
BatterySystemStateCont(CHARGER_POR) or a power on
reset event. This will reset any wake-up charging safety
timers and is equivalent to removing and reinserting both
batteries.
a) Associated battery is removed.
b) A subsequent AlarmWarning() clears all
charge alarm bits for the associated battery.
c) A power on reset event.
d) The SMBus Host asserts
BatterySystemStateCont(CHARGER_POR) high.
The LTC1760 will attempt to reinitiate wake-up charging
on a battery if the battery is not being charged, the
1760f
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LTC1760
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OPERATIO
6. An SMBus Host write asserts the LTC1760
BatterySystemStateCont(CHARGING_INHIBIT) high.
5. The battery responds to an LTC1760 master read of
Alarm() with all charge alarms deasserted.
7.Hardwarecontrolledcharginginhibitisasserted(MODE
low with VDDS high).
6. The battery responds to an LTC1760 master read of
ChargingVoltage() with a non zero voltage request value.
8. The thermistor of the battery being charged indicates
COLD-RANGE andthebatteryhasbeenchargedforlonger
7. The battery responds to an LTC1760 master read of
Voltage().
than tTIMEOUT
.
8. The battery responds to an LTC1760 master read of
ChargingCurrent() with a non zero current request value.
9. The thermistor of the battery being charged indicates
UNDER-RANGE and the battery has been charged for
9. The battery responds to an LTC1760 master read of
Current().
longer than tTIMEOUT
.
10. The thermistor of the battery being charged indicates
HOT-RANGE.
The following charging related functions are polled each
t
QUERY: Alarm(), ChargingVoltage(), Voltage(),
11. Any SMBus communication line is grounded for
longer than tQUERY.
ChargingCurrent(), and Current().
3.5 Controlled Charging Termination
12. BatterySystemStateCont(POWER_NOT_GOOD) is
high.
The LTC1760 will terminate controlled charging when any
of the following conditions are met:
13. Theemergencyofffeaturehasbeenassertedusingthe
DCDIV input pin.
1.Batteryremoval,orthermistorindicatingOVER-RANGE.
2. AC removal.
3.3 Wake-Up Charging Current and Voltage Limits
3. The SMBus Host issues a calibration request by setting
BatterySystemStateCont(CALIBRATE) high.
The wake-up charging current is fixed at IWAKE-UP for all
values of ILIMIT. Wake-up charging uses the low current
mode described in “Section 10”.
4. An LTC1760 master read of ChargingCurrent() return-
ing a zero current request.
The wake-up charging voltage is not limited by the VLIMIT
function.
5. An LTC1760 master read of ChargingVoltage() return-
ing a zero voltage request.
3.4 Controlled Charging Initiation
6. AnyofthefollowingAlarmWarning()bitsassertedhigh:
All of the following conditions must be met in order to
allow controlled charging of a given battery. One or both
batteries may be control charged at a time.
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM
TERMINATE_CHARGE_RESERVED
OVER_TEMP_ALARM
1. The battery thermistor must be COLD-RANGE, IDEAL-
RANGE, or UNDER-RANGE.
Note that the LTC1760 ignores all writes from the battery.
Eachbattery’schargealarmiscachedinsidetheLTC1760.
This bit will be set when any of the upper four bits of the
battery’s AlarmWarning() response are set.
2. AC must be present.
3.BatterySystemStateCont(CHARGING_INHIBIT)mustbe
de-asserted (or low).
4. Hardware controlled charging inhibit must be
de-asserted (MODE not low with VDDS high).
1760f
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LTC1760
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OPERATIO
This bit will remain set if a subsequent AlarmWarning()
fails to respond. The cached alarm will be cleared by any
of the following conditions.
b) The total programmed current equals the maximum
of the two requested currents + ILIMIT/32 and
LTC(TURBO) is de-asserted (or low).
c) Only one battery is charging and the programmed
current equals the requested current + ILIMIT/32.
a) Associated battery is removed.
b) A subsequent AlarmWarning() clears all charge
alarm bits for the associated battery.
d) The total programmed current equals ILIMIT
.
The programmed current is updated every tQUERY. It is
changed by the difference between the actual and re-
quested currents.
c) A power on reset event.
d) The SMBus Host asserts
BatterySystemStateCont(CHARGER_POR) high.
LTC(TURBO) provides a mechanism for the SMBus Host
to put additional current into both batteries. Normally the
LTC1760 will limit the current into both batteries to the
maximumofthetworequestedcurrents+ILIMIT/32. When
LTC(TURBO) is asserted, this restriction is removed,
allowing the charger to output as much as ILIMIT into both
batteries. Whenever changing conditions cause either
battery to stop charging, the current algorithm is reset to
zero.
7. An SMBus Host write asserts the LTC1760
BatterySystemStateCont(CHARGING_INHIBIT) high.
8.Hardwarecontrolledcharginginhibitisasserted(MODE
low with VDDS high).
9. The SMBus of the battery being charged has stopped
acknowledging SMBus read commands for longer than
tTIMEOUT.
10. The thermistor of the battery being charged indicates
HOT-RANGE.
The LTC1760 monitors the requested and actual voltages
in each battery and increases the programmed voltage by
16mV each tQUERY unless one of the following conditions
are met:
11. Any SMBus communication line is grounded for
longer than tQUERY
.
a) The actual voltage exceeds the requested voltage in
either battery.
12. BatterySystemStateCont(POWER_NOT_GOOD) is
high.
b) The actual voltage exceeds VLIMIT
.
13. Theemergencyofffeaturehasbeenassertedusingthe
DCDIV input pin.
This is an extremely important feature of the LTC1760
since it allows the charger to servo on the internal cell
voltage of the battery as determined by the Smart Battery.
This voltage may be significantly lower than the battery
packterminalvoltagewhichisusedbyallLevel2chargers.
The advantage for the LTC1760 is improved charge time,
safety, and a more completely charged battery.
Whenever changing conditions cause either battery to
stop charging, charging is stopped immediately for all
batteries and the voltage and current algorithms are reset
tozero. Chargingisnotresumeduntilalltheconditionsfor
controlled charging are met.
The voltage correction cannot exceed the minimum re-
questedvoltagebymorethan512mV.Whendecrementing,
3.6 Controlled Charging Current and Voltage
Programming
theprogrammedvoltageisreducedby16mVeachtQUERY
.
TheLTC1760monitorstherequestedandactualcurrentin
each battery and increases the programmed current un-
less one of the following conditions is met:
Whenever changing conditions cause either battery to
stop charging, the voltage algorithm is reset to zero.
a) The actual current exceeds the requested current in
either battery.
1760f
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LTC1760
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OPERATIO
4 System Power Management Algorithm and Battery
Calibration
4.4 Power-By Reporting
The following tables illustrate how BatterySystem
State(POWER_BY_BAT[4:1]) interprets power path
conditions.
4.1 Turning Off System Power
The LTC1760 allows the user to turn off system power
using the LTC(POWER_OFF) bit. When POWER_OFF is
asserted high all power management functions are by-
passed and the LTC1760 will turn off DCIN, BAT2 and
BAT1 power paths. This feature allows the user to power
down the system. Charging is still allowed when
POWER_OFF is asserted high.
Power Reporting for Batteries Being Calibrated
AC_PRESENT CALIBRATE_BAT2 CALIBRATE_BAT2 POWER_BY_BAT[4:1]
1
1
1
0
0
1
0
1
0
'b0000
'b0001
'b0010
*States not shown are not allowed
Power Reporting as a Function of Battery Presence
AC_PRESENT PRESENT_BAT2 PRESENT_BAT1 POWER_BY_BAT[4:1]
4.2 Power-By Algorithm When No Battery is Being
Calibrated
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
'b0000
'b0000
'b0001
'b0010
'b0011
The LTC1760 will always attempt to maintain system
power.Thepreferredconfigurationistoremainin3-Diode
mode. In 3-Diode mode, power will be provided by BAT1,
BAT2 and DCIN with the source at the highest voltage
potentialautomaticallyprovidingallthepower. Sourcesat
similar voltage potentials will share power based on their
capacity.
Power Reporting with AC_PRESENT Low and both Batteries
Present, as a Function of Power Alarms.
BATTERY 2
BATTERY 1
ThefollowingconditionswillcausetheLTC1760tomodify
its preferred power-by algorithm.
POWER ALARM POWER ALARM
AC_PRESENT
(NOTE 1)
(NOTE 1)
POWER_BY_BAT[4:1]
'b0011
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
1. A battery issues a terminate discharge alarm and
AC_PRESENT is high. The LTC1760 will select the other
battery and DCIN to power the system.
'b0010
'b0001
'b0011
2. A battery issues a terminate discharge alarm and
AC_PRESENT is low. The LTC1760 will select the other
battery to power the system.
'b0000
Note 1: A power alarm means that ALARM() has returned
TERMINATE_DISCHARGE=1 or FULLY_DISCHARGED_ALARM=1
3. A battery issues a terminate discharge alarm,
AC_PRESENT is low, and the other battery is not present
or has previously alarmed. The LTC1760 will autono-
mously try to restore power by entering 3-Diode mode.
The 3-Diode mode will ignore TERMINATE_DISCHARGE
and FULLY_DISCHARGED alarms.
Power Reporting When
BatterySystemStateCont(POWER_NOT_GOOD) is High
and the LTC1760 has Autonomously Entered 3-Diode Mode
AC_PRESENT PRESENT_BAT2 PRESENT_BAT1 POWER_BY_BAT[4:1]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
'b0000
'b0001
'b0010
'b0011
'b0000
'b0000
'b0000
'b0000
4.3 Power-By Algorithm When a Battery is Being
Calibrated
During battery calibration, the battery being calibrated is
the only device powering the system. This will be reflected
in the reported POWER_BY[4:1] bits. See “Section 5” for
more information on battery calibration.
1760f
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OPERATIO
5.2 Initiating Calibration of Selected Battery
5 Battery Calibration (Conditioning)
The SMBus Host initiates a calibration by writing to
BatterySystemStateCont(CALIBRATE).Followrulesofthe
previous section to preserve battery intended for calibra-
tion. The SMBus Host must only set the calibration bit
once per calibration.
Calibration allows the SMBus Host to fully discharge a
battery for conditioning purposes. The SMBus Host may
determine the battery to be discharged or allow the
LTC1760 to choose based on the batteries’ request to be
conditioned.
TheLTC1760willdischargetheselectedbatteryaslongas
the calibration is in progress (CALIBRATE high). Updates
to the cached BatteryMode(CONDITION_FLAG) will be
inhibited while CALIBRATE is asserted. This means that
discharge of the battery will continue even if the battery
clears the CONDITION_FLAG.
5.1 Selecting a Battery to be Calibrated
Option 1) SMBus Host chooses battery to be calibrated
using BatterySystemStateCont(CALIBRATE_BAT[4:1])
Allowed values:
'b0001: Set CALIBRATE_BAT1. Only has an effect if
Battery 1 BatteryMode(CONDITION_FLAG) is high .
May not be updated if a calibration is in progress.
5.3 Terminating Calibration of Selected Battery
Calibration will end when CALIBRATE is cleared. CALI-
BRATE will be cleared when:
'b0010: Set CALIBRATE_BAT2. Only has an effect if
Battery 2 BatteryMode(CONDITION_FLAG) is high.
May not be updated if a calibration is in progress.
• AC is removed.
• The battery being calibrated is removed. When the
battery being calibrated is removed, the LTC1760
will automatically calibrate the other battery if it is
requesting calibration.
'b0000: Clears CALIBRATE_BAT1 and
CALIBRATE_BAT2andallowsLTC1760tochose.Power
on reset default. May not be updated if a calibration is
in progress.
• BatterySystemStateCont(POWER_NOT_GOOD) is
high.
Option 2) SMBus Host allows LTC1760 to choose battery
to be calibrated.
• The battery sets Alarm Warning
(TERMINATE_DISCHARGE) high.
BatterySystemStateCont(CALIBRATE_BAT[4:1]) ='b0000.
See previous option.
• The battery sets Alarm Warning
(FULLY_DISCHARGED) high.
The LTC1760 determines that the battery requires calibra-
tion by reading BatteryMode(CONDITION_FLAG). This
flag is cached in the LTC1760. The LTC1760 sets
BatterySystemStateCont(CALIBRATE_REQUEST) high.
The LTC1760 will always select the battery that is request-
ing calibration. If both batteries are requesting calibration,
the LTC1760 will select Battery 1. If neither battery is
requesting calibration, then calibration cannot occur.
• A zero is written to the CALIBRATE bit.
TheLTC1760willattempttoinitiateachargecycleafterthe
discharge cycle is completed.
1760f
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OPERATIO
6 MODE Pin Operation
SCL is an input and is used to determine the blinking rate
of SDA and SMBALERT. Tie SCL high if blinking is not
desired. This will provide two different states to indicate
charging (output low) and not charging (output high).
The MODE pin is a multifunction pin that allows the
LTC1760 to: 1) display charging status in stand alone
operation; 2) activate hardware charge inhibit; 3) charge
when SCL and SDA are low and; 4) charge with an SMBus
Host.
6.2 Hardware Charge Inhibit
WhenMODEistiedtoGNDandVVDDS>VIH_VDDS,charging
is inhibited and BatterySystemStateCont(CHARGING_INHIBIT)
will report a logic high.
Summary of SDA, SCL and SMBALERT Operation as a Function
of MODE and VDDS Levels
CONDITION
LTC1760 OPERATING MODE
V
V
= V
SCL: Clock for Status Indicators
SDA: Battery 2 Status
SMBALERT: Battery 1 Status
MODE
VDDS
VSS
6.3 Charging When SCL And SDA Are Low
< V
ILVDDS
When MODE is tied to VCC2 and VDDS < VIL_VDDS, SDA and
SCL are not used and will not interfere with LTC1760
battery communication. This feature allows the LTC1760
to autonomously charge when SCL and SDA are not
available. This scenario might occur when SMBus Host
has powered down and is no longer pulling up on SCL and
SDA.
V
V
= V
SCL, SDA, SMBALERT: Normal Operation
LTC1760 Charging Inhibited
MODE
VDDS
VSS
> V
ILVDDS
V
V
= V
SCL, SDA Ignored and May Float Low
SMBALERT: Normal Operation
SCL1, SDA1, SCL2 and SDA2: Normal Operation and
Charging is Allowed
MODE
VDDS
VSS
< V
ILVDDS
V
V
= V
Normal Operation on all Pins, Charging is Allowed
MODE
VDDS
VSS
> V
ILVDDS
6.4 Charging With an SMBus Host
6.1 Stand Alone Charge Indication
WhenModeistiedtoVCC2 andVVDDS >VIL_VDDS, SDAand
SCL are used to communicate with the SMBus Host.
When MODE is tied to GND and VVDDS < VIL_VDDS, the
function of SDA, SMBALERT, and SCL are changed as
described below.
7 Battery Charger Controller
SDA is an output and is used to monitor charging status of
Battery 2.
The LTC1760 charger controller uses a constant off-time,
current mode step-down architecture. During normal op-
eration, the top MOSFET is turned on each cycle when the
oscillator sets the SR latch and turned off when the main
currentcomparatorICMP resetstheSRlatch. Whilethetop
MOSFET is off, the bottom MOSFET is turned on until
either the inductor current trips the current comparator
IREV, or the beginning of the next cycle. The oscillator uses
the equation.
Allowed valued are:
Low: Battery 2 is charging.
High: Battery 2 not charging (AC is not present or
battery is not present).
Blinking: Battery 2 charge complete (AC is present,
battery is present and not charging).
tOFF = (VDCIN - VBAT)/(VDCIN • fOSC
)
SMBALERT is used to monitor charging status of Bat-
tery1. Allowed valued are:
to set the bottom MOSFET on time. The result is quasi-
constant frequency operation where the converter fre-
quency remains nearly constant over a wide range of
output voltages. This activity is diagrammed in Figure 4.
Low: Battery 1 is charging.
High: Battery 1 not charging (AC is not present or
battery is not present).
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
Blinking: Battery 1 charge complete (AC is present,
battery is present and not charging).
1760f
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LTC1760
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OPERATIO
OFF
TGATE
ON
DCIN + 10V
(CHARGE PUMPED)
BAT1
CSN
TO
BATTERY
1
t
OFF
–
GCH1
SCH1
Q3
ON
EAC
35mV
20mV
FROM
CHARGER
BGATE
+
OFF
TRIP POINT SET BY I VOLTAGE
TH
INDUCTOR
CURRENT
+
CC
10k
–
Q4
OFF
Figure 4.
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
currentprogrammedbytheIDAC attheISET pinandadjusts
1760 F05
Figure 5. Charge MUX Switch Driver Equivalent Circuit
ITH for the desired voltage across RSENSE
.
the series connected MOSFETs to a low voltage and the
switch is off. When the charger controller is on, the charge
MUX driver will keep the MOSFETs off until the voltage at
CSN rises at least 35mV above the battery voltage. GCH1
is then driven with an error amplifier EAC until the voltage
betweenBAT1andCSNsatisfiestheerroramplifieroruntil
GCH1 is clamped by the internal Zener diode. The time
requiredtoclosetheswitchcouldbequitelong(manyms)
due to the small currents output by the error amp and
depending upon the size of the MOSFET switch.
The voltage at BAT is divided down by an internal resistor
divider set by the VDAC and is used by error amp EA to
decrease ITH if the divider voltage is above the 0.8V
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100 mV/
RCL). At input current limit, CL1 will decrease the ITH
voltage and thus reduce battery charging current.
An over-voltage comparator, OV, guards against transient
overshoots (>7.5%). In this case, the top MOSFET is
turned off until the over-voltage condition is cleared. This
feature is useful for batteries which “load dump” them-
selves by opening their protection switch to perform
functions such as calibration or pulse-mode charging.
If the voltage at CSN decreases below VBAT1 – 20mV a
comparator CC quickly turns off the MOSFETs to prevent
reverse current from flowing in the switches. In essence,
this system performs as a low forward voltage diode.
Operation is identical for BAT2.
The top MOSFET driver is powered from a floating boot-
strap capacitor C4. This capacitor is normally recharged
from VCC through an external diode when the top MOSFET
is turned off. As VIN decreases towards the selected
battery voltage, the converter will attempt to turn on the
top MOSFET continuously (“dropout’’). A dropout timer
detects this condition and forces the top MOSFET to turn
off, and the bottom MOSFET on, for about 200ns at 40µs
intervals to recharge the bootstrap capacitor.
7.2 Dual Charging
Note that the charge MUX switch drivers will operate
together to allow both batteries to be charged simulta-
neously. If both charge MUX switch drivers are enabled,
only the battery with the lowest voltage will be charged
until its voltage rises to equal the higher voltage battery.
The charge current will then share between the batteries
according to the capacity of each battery.
When batteries are controlled charging, only batteries
with voltages above VCHMIN are allowed to charge. When
a battery is wake-up charging this restriction does not
apply.
7.1 Charge MUX Switches
The equivalent circuit of a charge MUX switch driver is
shown in Figure 5. If the charger controller is not enabled,
the charge MUX drivers will drive the gate and source of
1760f
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OPERATIO
8.1 Autonomous PowerPath Switching
8 PowerPath Controller
The LOPWR comparator monitors the voltage at the load
through the resistor divider from pin SCN. If LTC
(POWER_OFF) is low and the LOPWR comparator trips,
then all of the switches are turned on (3-Diode mode) by
the Autonomous PowerPath Controller to ensure that the
system is powered from the source with the highest volt-
age.TheAutonomousPowerPathControllerwaitsapproxi-
mately 1second, to allow power to stabilize, and then re-
vertsbacktothePowerPathswitchconfigurationrequested
by the PowerPath Management Algorithm. A power fail
counter is incremented to indicate that a failure has oc-
curred. If the power fail counter equals a value of 3, then
the the Autonomous PowerPath Controller sets the
switches to 3-Diode mode and BatterySystem-
StateCont(POWER_NOT_GOOD) will be set, provided the
LOPWRcomparatorisstilldetectingalowpowerevent.This
isathree-strikes-and-you’re-outprocesswhichisintended
todebouncethePOWER_NOT_GOOD indicator.Thepower
fail counter is reset when battery or AC presence change.
The PowerPath switches are turned on and off by the
power management algorithm. The external PFETs are
usuallyconnectedasaninputswitchandanoutputswitch.
The output switch PFET is connected in series with the
input PFET and the positive side of the short-circuit
sensing resistor, RSC. The input switch is connected in
seriesbetweenthepowersourceandtheoutputPFET. The
PowerPath switch driver equivalent circuit is shown in
Figure6.TheoutputPFETisdrivenONorOFFbytheoutput
sidedrivercontrollingpinGB10.ThegateoftheinputPFET
is driven by an error amplifier which monitors the voltage
between the input power source (BAT1 in this case) and
SCP. If the switch is turned off, the two outputs are driven
to the higher of the two voltages present across the
input/SCP terminals of the switch. When the switch is
instructed to turn on, the output side driver immediately
drivesthegateoftheoutputPFETapproximately6Vbelow
the highest of the voltages present at the input/SCP. When
the output PFET turns on, the voltage at SCP will be pulled
up to a diode drop below the source voltage by the bulk
diode of the input PFET. If the source voltage is more than
25mV above SCP, EAP will drive the gate of the input PFET
low until the input PFET turns on and reduces the voltage
across the input/SCP to the EAP set point, or until the
Zener clamp engages to limit the voltage applied to the
input PFET. If the source voltage drops more than 20mV
below SCP, then comparator CP turns on SWP to quickly
prevent large reverse current in the switch. This operation
mimics a diode with a low forward voltage drop.
8.2 Short-Circuit Protection
Short-circuit protection operates in both a current mode
and a voltage mode. If the voltage between SCP and SCN
exceeds the short-circuit comparator threshold VTSC
for more than 15ms, then all of the PowerPath
switches are turned off and BatterySystemState-
Cont(POWER_NOT_GOOD)isset. Similarly, ifthevoltage
at SCN falls below 3V for more than 15ms, then all of
the PowerPath switches are turned off and
POWER_NOT_GOODissethigh.ThePOWER_NOT_GOOD
bitisresetbyremovingallpowersourcesandallowingthe
voltage at VPLUS to fall below the UVLO threshold. If the
POWER_NOT_GOOD bit is set, charging is disabled until
VPLUS exceeds the UVLO threshold and the Charger Algo-
rithm allows charging to resume.
20mV
OFF
–
+
CP
FROM
BATTERY
1
BAT1
SWP
–
+
GB1I
Q7
Q8
EAP
SCP
When a hard short-circuit occurs, it might pull all of the
power sources down to near 0V potentials. The capacitors
on VCC and VPLUS must be large enough to keep the circuit
operating correctly during the 15ms short-circuit event.
The charger will stop within a few microseconds, leaving
a small current which must be provided by the capacitor
on VPLUS. The recommended minimum values (1µF on
25mV
GB1O
OFF
R
SC
C
L
TO LOAD
1760 F06
Figure 6. PowerPath Driver Equivalent Circuit
1760f
31
LTC1760
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OPERATIO
VPLUS and 2µF on VCC, including tolerances) should keep
the LTC1760 operating above the UVLO trip voltage long
enough to perform the short-circuit function when the
input voltages are greater than 8V. Increasing the capaci-
tor across VCC to 4.7µF will allow operation down to the
recommended 6V minimum.
Capacitors CB1 and CB2 are used to average the voltage
present at the VSET pin as well as provide a zero in the
voltage loop to help stability and transient response time
to voltage variations.
10 The Current DAC Block
The current DAC is a delta-sigma modulator which
controls the effective value of an internal resistor,
8.3 Emergency Turn-Off
All of the PowerPath switches can be forced off by setting
the DCDIV pin to a voltage between 8V and 10V. This will
have the same effect as a short-circuit event. DCDIV must
be less than 5V and VPLUS must decrease below the UVLO
threshold to re-enable the PowerPath switches. The
LTC1760 can recover from this condition without remov-
ing power. Contact Applications Engineering for more
information.
R
SET = 18.77k, used to program the maximum charger
current. Figure 8 is a simplified diagram of the DAC opera-
tion. The delta-sigma modulator and switch convert the
IDAC value to a variable resistance equal to 1.25RSET
/
(IDAC(VALUE)/1023). In regulation, ISET is servo driven to
the0.8Vreferencevoltage,VREF,andthecurrentfromRSET
is matched against a current derived from the voltage
between pins CSP and CSN. This current is (VCSP – VCSN)/
3k.
8.4 Power-Up Strategy
Therefore programmed current is:
All three PowerPath switches are turned on after VPLUS
exceeds the UVLO threshold for more than 250ms. This
delayistopreventoscillationfromaturn-ontransientnear
the UVLO threshold.
ICHG = 0.8 VREF 3k/(RSNS RSET) • (IDAC(VALUE)/1023)
= (102.3mV/RSNS) • (IDAC(VALUE)/1023)
During wake-up current operation, the current DAC enters
alowcurrentmode.ThecurrentDACoutputispulse-width
modulated with a high frequency clock having a duty cycle
value of 1/8. Therefore, the maximum output current pro-
videdbythechargerisIMAX/8.Thedelta-sigmaoutputgates
this low duty cycle signal on and off. The delta-sigma shift
registersarethenclockedataslowerrate,about40ms/bit,
so that the charger has time to settle to the IMAX/8 value.
9 The Voltage DAC Block
ThevoltageDAC(VDAC)isadelta-sigmamodulatorwhich
controls the effective value of an internal resistor,
RVSET = 7.2k, used to program the maximum charger
voltage. Figure 7 is a simplified diagram of the VDAC
operation. The delta-sigma modulator and switch SWV
convert the VDAC value to a variable resistance equal to
(11/8)RVSET/(VDAC(VALUE)/2047). In regulation, VSET is
servo driven to the 0.8V reference voltage, VREF
.
CSN
(V
– V
)
CSN
CSP
3kΩ
R
VF
(FROM CA1 AMPLIFIER)
C
B2
C
405.3k
V
I
SET
SET
–
+
+
–
TO
TH
TO
EA
C
SET
I
I
TH
B1
V
REF
V
REF
R
VSET
7.2k
R
SET
18.77k
DAC
DAC
VALUE
(10 BITS)
1760 F08
11
10
∆Σ
MODULATOR
∆Σ
MODULATOR
SWV
VALUE
(11 BITS)
1760 F07
Figure 7. Voltage DAC Operation
Figure 8. Current Dac Operation
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Automatic Current Sharing
Capacityratingwillchangewithageanduseandhencethe
current sharing ratios can change over time.
In a dual parallel charge configuration, the LTC1760 does
notactuallycontrolthecurrentflowingintoeachindividual
battery. The capacity, or Amp-Hour rating, of each battery
determines how the charger current is shared. This auto-
matic steering of current is what allows both batteries to
reach their full capacity points at the same time. In other
words, givenallotherthingsequal, chargeterminationwill
happen simultaneously.
Adapter Limiting
An important feature of the LTC1760 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the prod-
uct to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
A battery can be modeled as a huge capacitor and hence maximum possible rate of which the adapter is capable.
governed by the same laws.
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across RCL, connected
between the CLP and DCIN pins. When this voltage ex-
ceeds 100mV, the amplifier will override programmed
charging current to limit adapter current to 100mV/RCL. A
lowpass filter formed by 5kΩ and 0.1µF is required to
eliminate switching noise. If the current limit is not used,
CLP should be connected to DCIN.
I = C • (dV/dt) where:
I = The current flowing through the capacitor
C = Capacity rating of battery (using amp-hour values
instead of capacitance)
dV = Change in voltage
dt = Change in time
The equivalent model of a set or parallel batteries is a set
of parallel capacitors. Since they are in parallel, the change
involtageoverchangeintimeisthesameforbothbatteries
one and two.
100mV
dV/dtBAT1 = dV/dtBAT2
CLP
+
–
0.1µF
From here we can simplify.
IBAT1/CBAT1 = dV/dt = IBAT2/CBAT2
IBAT2 = IBAT1 CBAT2/CBAT1
5kΩ
CL1
+
AC ADAPTER
INPUT
R
CL
*
DCIN
V
IN
+
1760 F09
C
IN
Atthispointyoucanseethatthecurrentdividesastheratio
of the two batteries capacity ratings. The sum of the
current into both batteries is the same as the current being
supply by the charger. This is independent of the mode of
the charger (CC or CV).
100mV
ADAPTER CURRENT LIMIT
*R
CL
=
Figure 9.
Setting Input Current Limit
ICHRG = IBAT1 + IBAT2
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 5% for the
input current limit tolerance and use that current to deter-
mine the resistor value.
From here we solve for the actual current for each battery.
IBAT2 = ICHRG CBAT2/(CBAT1 + CBAT2
)
)
IBAT1 = ICHRG CBAT1/(CBAT1 + CBAT2
RCL = 100mV/ILIM
Please note that the actual observed current sharing will
vary from manufacturer’s claimed capacity ratings since it
is actual physical capacity rating at the time of charge.
ILIM = Adapter Min Current
– (Adapter Min Current • 5%)
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As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Table 1).
in currents that greatly exceed the requested value and
potentiallydamagethebatteryoroverloadthewalladapter
if no input current limiting is provided.
Setting Charger Output Voltage Limit
Table 1. Common RCL Resistor Values
ThevalueofanexternalresistorconnectedfromtheVLIMIT
pin to GND determines one of five voltage limits that are
applied to the charger output value. See Table 3. These
limits provide a measure of safety with a hardware restric-
tion on charging voltage, which cannot be overridden by
software. This voltage sets the limit that will be applied to
the battery as reported by battery. Since the battery
internalvoltagemonitorpointistheactualcellvoltage,you
may see higher voltages, up to 512mV higher, at the
external charger terminals due to the voltage servo loop
action. See Operations section 3.6 for more information
on the voltage servo system.
Adapter
Rating A
RCL Value*
(Ω) 1%
RCL Power
Dissipation (W)
RCL Power
Rating (W)
1.5
1.8
2
0.06
0.05
0.135
0.162
0.18
0.25
0.25
0.25
0.25
0.5
0.045
0.039
0.036
0.033
0.030
2.3
2.5
2.7
3
0.206
0.225
0.241
0.27
0.5
0.5
*Values shown above are rounded to nearest standard value.
Extending System to More than 2 Batteries
The LTC1760 can be extended to manage systems with
more than 3 sources of power. Contact Linear Technology
Applications Engineering for more information.
Table 3. Recommended Resistor Values for RVLIM
V
R
VLIM
± 1%
MAX
Up to 8.4V
0Ω (Short to ground)
Up to 12.6V
10k
Charge Termination Issues
Up to 16.8V
33k
Batteries with constant-current charging and voltage-
based charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
Up to 21.0V
100k
Up to 32.7V (No Limit)
Open (or short to V
)
CC2
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases
with higher frequency and increases with higher VIN.
Setting Charger Output Current Limit
The LTC1760 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
Table 2. Recommended Resistor Values
IMAX (A)
RSENSE (Ω) 1%
0.100
RSENSE (W)
0.25
RILIM (Ω) 1%
⎛
⎞
1
VOUT
V
IN
1
2
3
4
0
∆IL =
VOUT 1−
⎜
⎟
⎝
⎠
f L
( )( )
0.05
0.25
10k
33k
Open
0.025
0.5
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). In no case should
∆IL exceed 0.6(IMAX) due to limits imposed by IREV and
0.025
0.5
Warning
DO NOT CHANGE THE VALUE OF RILIM DURING OPERA-
TION. The value must remain fixed and track the RSENSE
value at all times. Changing the current setting can result
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CA1. Remember the maximum ∆IL occurs at the maxi-
mum input voltage. In practice 10µH is the lowest value
recommended for use.
normalizedRDS(ON) vsTemperaturecurve,butδ=0.005/°C
canbeusedasanapproximationforlowvoltageMOSFETs.
CRSS is usually specified in the MOSFET characteristics.
The constant k = 1.7 can be used to estimate the contribu-
tions of the two terms in the main switch dissipation
equation.
Charger Switching Power MOSFET and Diode
Selection
Two external power MOSFETs must be selected for use
with the LTC1760 charger: An N-channel MOSFET for the
top (main) switch and an N-channel MOSFET for the
bottom (synchronous) switch.
If the LTC1760 charger is to operate in low dropout mode
or with a high duty cycle greater than 85%, then the
topside N-channel efficiency generally improves with a
largerMOSFET.UsingasymmetricalMOSFETsmayachieve
cost savings or efficiency gains.
The peak-to-peak gate drive levels are set by the VCC
voltage.Thisvoltageistypically5.2V.Consequently,logic-
level threshold MOSFETs must be used. Pay close atten-
tion to the BVDSS specification for the MOSFETs as well;
manyofthelogiclevelMOSFETsarelimitedto30Vorless.
The Schottky diode D1, shown in the Typical Application,
conducts during the dead-time between the conduction of
the two power MOSFETs. This prevents the body diode of
the bottom MOSFET from turning on and storing charge
during the dead-time, which could cost as much as 1% in
efficiency. A 1A Schottky is generally a good size for 4A
regulators due to the relatively small average current.
Largerdiodescanresultinadditionaltransitionlossesdue
to their larger junction capacitance. The diode may be
omitted if the efficiency loss can be tolerated.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance RDS(ON), reverse transfer capacitance CRSS
,
input voltage and maximum output current. The LTC1760
charger is always operating in continuous mode so the
duty cycles for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = VOUT/VIN
Calculating IC Operating Current
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN
This section shows how to use the values supplied in the
Electrical Characteristics table to estimate operating cur-
rent for a given application.
The MOSFET power dissipations at maximum output
current are given by:
PMAIN = VOUT/VIN(IMAX)2(1 + δ∆Τ)RDS(ON) + k(VIN)2
(IMAX)(CRSS)(f)
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δ∆Τ) RDS(ON)
The total IC operating current through DCIN when AC is
present and batteries are charging (IDCIN_CHG) is given by:
IDCIN_CHG = ICH1 + IVCC2_AC1 + ISAFETY1 + ISAFETY2
+
Where δ∆Τ isthetemperaturedependencyofRDS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside
N-channel equation includes an additional term for transi-
tion losses, which are highest at high input voltages. For
VIN < 20V the high current efficiency generally improves
with larger MOSFETs, while for VIN > 20V the transition
losses rapidly increase to the point that the use of a higher
RDS(ON) device with lower CRSS actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short-circuit when
the duty cycle in this switch is nearly 100%. The term
(1 + δ∆Τ) is generally given for a MOSFET in the form of a
IVLIM +IILIM +ISMB +ISMB_BAT1 +ISMB_BAT2 +ISMBALERT
where:
ICH1 is defined in “Electrical Characteristics.”
IVCC2_AC1 is defined in “Electrical Characteristics.”
ISAFETYXisthecurrentusedtotestthebattery thermistor
connected to SAFETY1 OR SAFETY2.
For thermistors that are OVER-RANGE:
ISAFETYX = 2/64 • VVCC2/(RXB + RTHX
)
For thermistors that are COLD-RANGE:
ISAFETYX = 4/64 • VVCC2/(RXB + RTHX
)
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For thermistors that are IDEAL-RANGE:
IDCIN_CHG = ICH1 + IVCC2_AC1 + ISAFETY1 + ISAFETY2 +
I
SAFETYX = 4/64 • VVCC2/(RXB + RTHX) + 2/64 • VVCC2
/
IVLIM + IILIM + ISMB + ISMB_BAT1 + ISMB_BAT2 +
(R1A +RTHX
For thermistors that are HOT-RANGE:
SAFETYX = 4/64 • VVCC2/(RXB + RTHX) + 4/64 • VVCC2
(R1A +RTHX
THX is the impedance of the battery’s thermistor to
ground.
)
ISMBALERT
= 1.3mA + 700µA + 218µA + 218µA +81µA + 81µA
+ 0µA + 5.4µA + 5.4µA + 0µA = 2.62mA
I
/
)
The total operating current through BAT1 and BAT2 when
AC is not present (IBAT_NOAC) is given by:
R
I
BAT_NOAC = IBAT + IVCC2_AC0 + ISAFETY1 + ISAFETY2
+
ISMB + ISMB_BAT1_AC0 + ISMB_BAT2_AC0 + ISMBALERT
RXB = 54.9k
where:
RXA = 1.13k
IBAT is defined in “Electrical Characteristics.”
Sample calculation of ISAFETYX with VVCC2 = 5.2V
IVCC2_AC0 is defined in “Electrical Characteristics.”
Thermistor Impedance
R
(Ω)
Thermistor Range
OVER_RANGE
I
(µA)
SAFETYX
ISAFETYX is the current used to test the battery
thermistor connected to SAFETY1 or SAFETY2.
THX
100k
3.3k
400
1.05
IDEAL_RANGE
UNDER_RANGE
42.2
218
ISAFETYX = 2/64 • VVCC2/(RXB + RTHX).
RTHX is the impedance of the battery’s thermistor to
ground.
IVLIM = VVCC2/(RVLIMIT + RLIM_PU).
IILIM = VVCC2/(RILIMIT + RLIM_PU).
RXB = 54.9k.
Sample calculation of ISAFETY with VVCC2 = 5.2V
RLIM_PU is the typical pull-up impedance at VLIMIT
and ILIMIT.
Thermistor Impedance
R
(Ω)
Thermistor Range
I
(µA)
SAFETYX
THX
RLIM_PU = 34k.
400
UNDER_RANGE
2.9
RVLIMIT is the value of the resistance from VLIMIT to
GND.
ISMB_BATX_ACO is the current used for communicat-
ing with Battery1 or Battery2 when AC in not present.
RILIMIT is the value of the resistance from ILIMIT to
GND.
ISMB_BATX_AC0 = 350µA • 0.00687 = 2.404µA.
ISMB is the current used for communicating with the
SMBus Host and depends on the amount of bus
traffic.
ISMB is the current used for communicating with the
SMBus Host and depends on the amount of bus
traffic.
ISMB_BATX is the current used for communicating
with Battery1 or Battery2.
Sample calculation with two Li-Ion batteries (RTHX
=
400), VCC2 = 5.2V, and no SMBus Host communication:
ISMB_BATX = 350µA • 0.0155 = 5.425µA.
IBAT_NOAC – IBAT + IVCC2_AC0 + ISAFETY1 + ISAFETY2
+
ISMB + ISMB_BAT1_AC0 + ISMB_BAT2_AC0 + ISMBALERT
= 175µA + 80µA + 2.9µA + 2.9µA + 0µA + 2.4µA +
2.4µA + 0µA = 265µA
ISMBALERT is defined in “Electrical Characteristics.”
Sample calculation of IDCIN_CHG with two Li-Ion batteries
(RTHX = 400), RVLIMIT = RILIMIT = 30k, VCC2 = 5.2V, and no
SMBus Host communication:
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is essentially DC. CB2 is the primary filter capacitor and
CB1 is used to provide a zero in the response to cancel the
poleassociatedwithCB2. AcceptablevoltagerippleatVSET
is about 10mVP-P. Since the period of the delta-sigma
switch closure, T∆Σ, is about 11µs and the internal VDAC
resistor, RVSET, is 7.2kΩ, the ripple voltage can be ap-
proximated by:
Calculating IC Power Dissipation
The power dissipation of the LTC1760 is dependent upon
the gate charge of QTG and QBG.(Refer to Typical
Application). The gate charge is determined from the
manufacturer’sdatasheetandisdependentuponboththe
gate voltage swing and the drain voltage swing of the FET.
PD = (VDCIN – VVCC) • fOSC • (QTG + QBG) + VDCIN
DCIN_CHG – VVCC • (ISAFETY1 + ISAFETY2
•
VREF • T∆∑
I
)
∆VVSET
=
RVSET CB1 ||CB2
(
)
where:
IDCIN_CHG, ISAFETY1, ISAFETY2 are defined in the
previous section.
Then the equation to extract CB1 || CB2 is:
VREF • T∆∑
Example:
VVCC = 5.2V, VDCIN = 19V, fOSC = 345kHz, QTG
CB1 ||CB2
=
R
VSET∆VVSET
=
QBG = 15nC, IDCIN_CHG = 2.62mA, ISAFETY1
ISAFETY2 = 218µA.
PD = 190mW
=
CB2 should be 10× to 20× CB1 to divide the ripple voltage
present at the charger output. Therefore CB1 = 0.01µF and
CB2 = 0.1µF are good starting values. In order to prevent
overshoot during start-up transients the time constant
associatedwithCB2 mustbeshorterthanthetimeconstant
of C5 at the ITH pin. If CB2 is increased to improve ripple
rejection, then C5 should be increased proportionally and
charger response time to voltage variation will degrade.
VSET/ISET Capacitors
Capacitor C7 is used to filter the delta-sigma modulation
frequency components to a level which is essentially DC.
Acceptable voltage ripple at ISET is about 10mVP-P. Since
the period of the delta-sigma switch closure, T∆Σ, is about
10µs and the internal IDAC resistor, RSET, is 18.77k, the
ripple voltage can be approximated by:
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application
section), theinputcapacitor(CIN)isassumedtoabsorball
input switching ripple current in the converter, so it must
have adequate ripple current rating. Worst-case RMS
ripple current will be equal to one half of output charging
current. Actual capacitance value is not critical. Solid
tantalum low ESR capacitors have high ripple current
rating in a relatively small surface mount package, but
caution must be used when tantalum capacitors are used
for input or output bypass. High input surge currents can
be created when the adapter is hot-plugged to the charger
or when a battery is connected to the charger. Solid
tantalum capacitors have a known failure mechanism
when subjected to very high turn-on surge currents. Only
Kemet T495 series of “Surge Robust” low ESR tantalums
are rated for high surge conditions such as battery to
ground.
VREF • T∆∑
∆V
=
ISET
RSET •C7
Then the equation to extract C7 is:
VREF • T∆∑
C7 =
∆VISET •RSET
= 0.8/0.01/18.77k(10µs) ≅ 0.043µF
In order to prevent overshoot during start-up transients
the time constant associated with C7 must be shorter than
the time constant of C5 at the ITH pin. If C7 is increased to
improve ripple rejection, then C5 should be increased
proportionally and charger response time to average cur-
rent variation will degrade.
Capacitors CB1 and CB2 are used to filter the VDAC delta-
sigma modulation frequency components to a level which
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The relatively high ESR of an aluminum electrolytic for
C15, located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance RDS(ON), input voltage and maximum output
current. For the N-channel charge path, the maximum
current is the maximum programmed current to be used.
For the P-channel discharge path maximum current typi-
cally occurs at end of life of the battery when using only
one battery. The upper limit of RDS(ON) value is a function
of the actual power dissipation capability of a given
MOSFET package that must take into account the PCB
layout. As a starting point, without knowing what the PCB
dissipation capability would be, derate the package power
rating by a factor of two.
Highest possible voltage rating on the capacitor will mini-
mizeproblems. Consultwiththemanufacturerbeforeuse.
Alternatives include new high capacity ceramic (at least
20µF) from Tokin, United Chemi-Con/Marcon, et al. Other
alternative capacitors include OSCON capacitors from
Sanyo.
The output capacitor (COUT) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
PMOSFET
RDS(ON)MAX
=
2
2 IMAX
V
BAT
0.29 (V ) 1 –
IfyouareusingadualMOSFETpackagewithbothMOSFETs
in series, you must cut the package power rating in half
again and recalculate.
BAT
(
)
V
DCIN
I
=
RMS
(L1)(f)
For example:
PMOSFETDUAL
RDS(ON)MAX
=
VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and
f = 300kHz, IRMS = 0.41A.
2
)
4 IMAX
(
If you use identical MOSFETs for both battery paths,
voltage drops will track over a wide current range. The
LTC1760 linear 25mV CV drop regulation will not occur
until the current has dropped below:
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
maybeaddedtoincreasebatteryimpedanceatthe300kHz
switching frequency. Switching ripple current splits be-
tween the battery and the output capacitor depending on
the ESR of the output capacitor and the battery imped-
ance. IftheESRofCOUTis0.2Ωandthebatteryimpedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
25mV
2RDS(ON)MAX
ILINEARMAX
=
However, if you try to use the above equation to determine
RDS(ON) to force linear mode at full current, the MOSFET
RDS(ON) value becomes unreasonably low for MOSFETs
available at this time. The need for the LTC1760 voltage
drop regulation only comes into play for parallel battery
configurations that terminate charge or discharge using
voltage. At first this seems to be a problem, but there are
several factors helping out:
Power Path and Charge MUX MOSFET Selection
Three pairs of P-channel MOSFETs must be used with the
wall adapter and the two battery discharge paths. Two
pairs of N-channel MOSFETs must be used with the
battery charge path. The nominal gate drive levels are set
by the clamp drive voltage of their respective control
circuitry. This voltage is typically 6.25V. Consequently,
logic-level threshold MOSFETs must be used. Pay close
attention to the BVDSS specification for the MOSFETs as
well; many of the logic level MOSFETs are limited to 30V
or less.
1. When batteries are in parallel current sharing, the
current flow through any one battery is less than if it is
running stand-alone.
2. Most batteries that charge in constant voltage mode,
such as Li-ion, charge terminate at a current value of
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C/10 or less which is well within the linear operation
adapter path with wall adapters of high voltage, large bulk
capacitance and low resistance DC cables between the
adapter and device are the most common failures.
Remember to only use the real wall adapter with a produc-
tionDCpowercordwhenperformingthewalladapterpath
test. Theuseofalaboratorypowersupplyisunrealisticfor
this test and will force you to over specify the MOSFET
ratings. A battery pack usually has enough series resis-
tance to limit the peak current or are too low in voltage to
create enough instantaneous power to damage their re-
spective power path MOSFETs.
range of the MOSFETs.
3. Voltage tracking for the discharge process does not
need such precise voltage tracking values.
The LTC1760 has two transient conditions that force the
dischargepathP-channelMOSFETstohavetwoadditional
parameters to consider. The parameters are gate charge
Q
GATE and single pulse power capability.
When the LTC1760 senses a LOW_POWER event, all the
P-channel MOSFETs are turned on simultaneously to
allow voltage recovery due to a loss of a given power
source. However, thereisadelayinthetimeittakestoturn
onalltheMOSFETs. SlowMOSFETswillrequiremorebulk
capacitance to hold up all the system’s power supply
functionduringthetransitionandfastMOSFETwillrequire
less bulk capacitance. The transition speed of a MOSFET
to an on or off state is a direct function of the MOSFET gate
charge.
Conditioning Systems With Large Loads
In systems where the load is too large to be used for
conditioning a single battery it may be necessary to
bypass the built in calibrate function and simply switch in
anexternalload. Aconvenientwaytoaccomplishthistask
isbyusinganSMBusbasedLTC1623loadswitchcontrol-
ler. See Figure 10.
t = QGATE/IDRIVE
IDRIVE is the fixed drive current into the gate from the
LTC1760 and “t” is the time it takes to move that charge to
a new state and change the MOSFET conduction mode.
Hence time is directly related to QGATE. Since QGATE goes
up with MOSFETs of lower RDS(ON), choosing such
MOSFETshasacounterproductiveincreaseingatecharge
makingtheMOSFETslower. PleasenotethattheLTC1760
recovery time specification only refers to the time it takes
for the voltage to recover to the level just prior to the
LOW_POWER event as opposed to full voltage.
TO
PowerPath
MUX
LOAD
LTC1760
CHARGE
MUX
SMBus
SMBus
TO/FROM
HOST
CONDITIONING
LOAD
LTC1623
The single pulse current rating of MOSFET is important
when a short-circuit takes place. The MOSFET must
survive a 15ms overload. MOSFETs of lower RDS(ON) or
MOSFETs that use more powerful thermal packages will
have a high power surge rating. Using too small of a pulse
rating will allow the MOSFET to blow to the open circuit
condition instantly like a fuse. Typically there is no
outward sign of failure because it happens so fast. Please
measure the surge current for all discharge power paths
under worse case conditions and consult the MOSFET
data sheet for the limitations. Voltage sources with the
highest voltage and the most bulk capacitance are often
the biggest risk. Specifically the MOSFETs in the wall
1760 F10
Figure 10
Unique Configuration Information
This section summarizes unique LTC1760 configurations
thatallowsome LTC1760featurestobeeliminated. These
configurations may be selected in any combination with-
out adversely affecting LTC1760 operation. Refer to the
Typical Application circuit diagram located at the back of
this data sheet.
1760f
39
LTC1760
W U U
U
APPLICATIO S I FOR ATIO
A) Single Battery Configuration.
5) Remove all components connected to COMP1, VSET
ITH, ISET, ILIMIT and VLIMIT pins.
,
TolimittheLTC1760toasinglebattery, modifythebattery
slot to be eliminated as follows:
6) Short ILIMIT and VLIMIT to VSS.
1) Remove both FETs (Q5, Q6 or Q7, Q8) involved in the
charge path.
6) Remove R1, C1 but short CLP to DCIN. Replace RCL
with a short/trace connection.
2) Remove both FETS (Q3, Q4 or Q9, Q10) involved in
the discharge path.
7)ShortCSPtoCSNbutleavethecombinationfloating.
8) Unless otherwise specified, leave the unused pins of
the LTC1760 floating.
3) Remove the thermistor sensing resistors (R1A, R1B
or R2A, R2B).
F) No DC Path And No Charge Configuration.
4) Short the thermistor sense lines together at the IC.
5) Remove the diode (D2 or D3) as required.
To limit the LTC1760 to battery discharge functions only,
merge the previous two configurations with the following:
6) Unless otherwise specified, leave the unused pins of
the LTC1760 floating.
1) Remove CIN.
2) Remove resistors tied to DCDIV and ground DCDIV.
B) No Short-Circuit Protection Configuration.
1) Replace RSC with a short.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electricalfieldradiationandhighfrequencyresonantprob-
lems,properlayoutofthecomponentsconnectedtotheIC
is essential. (See Figure 11.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
1. Input capacitors need to be placed as close as possible
toswitchingFET’ssupplyandgroundconnections. Short-
est copper trace connections possible. These parts must
be on the same layer of copper. Vias must not be used to
make this connection.
2. The control IC needs to be close to the switching FET’s
gateterminals.Keepthegatedrivesignalsshortforaclean
FET drive. This includes IC supply pins that connect to the
switching FET source pins. The IC can be placed on the
opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of this
trace. Make the trace width the minimum amount needed
to support current—no copper fills or pours. Avoid run-
ning the connection using multiple layers in parallel.
Minimize capacitance from this node to any other trace or
plane.
C) No LOPWR Protection.
1) Remove resistors R2 and R3 connected to LOPWR
and tie LOPWR to the VCC pin.
D) No DC Path Configuration.
To remove the DC input as part of the power path choices
to support the load:
1) Remove both FETs Q1 and Q2 involved in the DC
path.
2) Unless otherwise specified, leave the unused pins of
the LTC1760 floating.
E) No Charge Configuration.
To permanently disable the battery charger function:
1) Remove ALL FETs involved in the charge path (Q3,
Q4, Q9, Q10).
2) Remove switching FETs QTG, QBG, diode D1 and
inductor L1.
3) Remove diodes D2, D3, D4, capacitors C4, COUT and
Resistor R11 and RSENSE
.
4) Reduce CIN capacitor to 0.1µF.
1760f
40
LTC1760
W U U
U
APPLICATIO S I FOR ATIO
SWITCH NODE
9. A good rule of thumb for via count for a given high
current path is to use 0.5A per via. Be consistent.
L1
V
BAT
10. If possible, place all the parts listed above on the same
PCB layer.
HIGH
FREQUENCY
CIRCULATING
PATH
C
D1
C
OUT
V
IN
BAT
IN
11. Copper fills or pours are good for all power connec-
tions except as noted above in Rule 3. You can also use
copper planes on multiple layers in parallel too—this
helps with thermal management and lower trace induc-
tance improving EMI performance further.
1760 F10
Figure 11. High-Speed Switching Path
12. For best current programming accuracy provide a
Kelvin connection from RSENSE to CSP and BAT. See
Figure 12 as an example.
4. Place the output current sense resistor right next to the
inductor output but oriented such that the IC’s current
sense feedback traces going to resistor are not long. The
feedback traces need to be routed together as a single pair
on the same layer at any given time with smallest trace
spacing possible. Locate any filter component on these
traces next to the IC and not at the sense resistor location.
It is important to keep the parasitic capacitance on the RT,
CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.
5.Placeoutputcapacitorsnexttothesenseresistoroutput
and ground.
DIRECTION OF CHARGING CURRENT
6. Output capacitor ground connections need to feed into
same copper that connects to the input capacitor ground
before tying back into system ground.
R
SNS
1760 F11
General Rules
CSN
CSP
7. Connection of switching ground to system ground or
internal ground plane should be single point. If the system
hasaninternalsystemgroundplane, agoodwaytodothis
is to cluster vias into a single star point to make the
connection.
Figure 12. Kelvin Sensing of Charging Current
Important Safety Notes
Although every effort is made to meet and exceed all
required “SMBus Charger V1.1” safety features it is the
responsibility of the battery pack to protect itself from
excessive currents or voltages. The LTC1760 is not itself
a safety device. Consult your battery pack manufacturer
for more information.
8. Route analog ground as a trace tied back to IC ground
(analog ground pin if present) before connecting to any
other ground. Avoid using the system ground plane. CAD
trick: make analog ground a separate ground net and use
a 0Ω resistor to tie analog ground to system ground.
1760f
41
LTC1760
U
TYPICAL APPLICATIO
Application for a Dual Battery System (12.6V/4A)
PowerPath MUX
V
IN
C8, 1µF
R
CL
0.03Ω
R10, 100Ω
C9, 0.1µF
C1
0.1µF
Q1
Q6
Q5
Q7
Q8
R1
4.99k
LTC1760
Q2
36
41
3
1
V
CLP
DC
BAT1
PLUS
7
GDCI
6
IN
R4
12.7k
GDCO
9
2
GB1I
8
BAT2
GB1O
11
R
SC
0.02Ω
GB2I
10
GB2O
5
R5
SCP
4
1.21k
16
37
47
48
46
45
13
40
24
SCN
12
DCDIV
COMP1
GCH2
SCH2
GCH1
SCH1
LOAD
LOPWR
34
R2
CSN
35
280k
R7
49.9k
CL
20µF
C11
CSP
14
1800pF
I
R3
49.9k
TH
C3
0.012µF
15
I
SET
R9
3.3k
42
SW
V
SET
C12
1000pF
C7
0.1µF
43
BOOST
V
V
CC
SS
V
DDS
44
TGATE
39
C5
SMBALERT
SCL
BGATE
38
0.15µF
BAT2
R2A, 1.13k
R2B, 54.9k
SAFETY 2
PGND
28
25
29
18
22
20
33
32
26
R
R
PU
PU
TH2A
27
V
CC2
TH
TH2B
17
SMBALERT
SCL
SDA
SDA
SCL
SDA
SCL2
21
SDA2
30
V
TH1A
31
V
DDS
DDS
R1A, 1.13k SAFETY 1
BAT1
TH1B
19
V
LIMIT
SCL1
23
I
LIMIT
R
R1B, 54.9k
TH
VLIMIT
10k
SDA1
MODE
C1
0.1µF
SCL
SDA
BAT2
D2
BAT1
D3
C
IN
I6
I5
QTG
QBG
L1
10µH
20µF
R11
1k
D4
C
OUT
20µF
R
SENSE
0.025Ω
C4, 0.22µF
C6
4.7µF
C13
0.1µF
D1
CB2
CHARGE
MUX
0.47µF
R6
100Ω
CB1, 0.1µF
Q9
Si6928
Q4
Si6928
Q3
Si6928
Q10
Si6928
D1: MBR130T3
D2: IN4148 TYPE
Q1, Q2, Q5, Q6, Q7, Q8: Si4925DY
Q3, Q4, Q9, Q10, QTG, QBG: FDS6912A
1760 TA02
1760f
42
LTC1760
U
PACKAGE DESCRIPTIO
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
12.40 – 12.60*
(.488 – .496)
48
25
0.95 ±0.10
6.2 ±0.10
44
42
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
48 47 46 45
43
8.1 ±0.10
7.9 – 8.3
(.311 – .327)
1
24
0.32 ±0.05
0.50 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
6.0 – 6.2**
(.236 – .244)
0.25
REF
0° – 8°
-T-
-C-
0.10 C
FW48 TSSOP 0204
0.50
(.0197)
BSC
0.17 – 0.27
(.0067 – .0106)
TYP
0.09 – 0.20
(.0035 – .008)
0.45 – 0.75
(.018 – .029)
0.05 – 0.15
(.002 – .006)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
**
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1760f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
43
LTC1760
RELATED PARTS
PART NUMBER
LT1571
DESCRIPTION
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with Termination Timer; AC Adapter Current Limit and
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High Efficiency, Programmable Voltage
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Complete Charger for 3- or 4-Cell Lithium-Ion Batteries,
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Current Battery Charger
Constant Current/ Constant Voltage Switching Regulator;
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Limit and SafetySignal Sensor
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Smart Battery Charger Controller
SMBus Rev 1.1 Compliant
1760f
LT/TP 1004 1K • PRINTED IN USA
44 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
©LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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