LTC1768CGN#PBF [Linear]
IC,BALLAST/BACKLIGHT CONTROLLER/DRIVER,CMOS,SSOP,16PIN,PLASTIC;
| 型号： | LTC1768CGN#PBF |
| 厂家： | 
Linear |
| 描述： | IC,BALLAST/BACKLIGHT CONTROLLER/DRIVER,CMOS,SSOP,16PIN,PLASTIC 驱动 光电二极管 |
| 文件： | 总20页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1768
High Power CCFL Controller
for Wide Dimming Range and
Maximum Lamp Lifetime
DESCRIPTIO
U
FEATURES
■
Ultrawide Multimode DimmingTM Range
The LT®1768 is designed to control single or multiple cold
cathode fluorescent lamp (CCFL) displays. A unique Mul-
timodeDimmingscheme*combinesbothlinearandPWM
control functions to maximize lamp life, efficiency, and
dimming range. Accurate maximum and minimum lamp
currents can be easily set. The LT1768 can detect and
protect against lamp failures and overvoltage start-up
conditions. It is designed to provide maximum flexibility
with a minimum number of external components.
■
Multiple Lamp Capability
■
Programmable PWM Dimming Range and
Frequency
■
Precision Maximum and Minimum Lamp
Currents Maximize Lamp Lifetime
■
No Lamp Flicker Under All Supply and Load
Conditions
Open Lamp Detection and Protection
■
■
350kHz Switching Frequency
1.5A MOSFET Gate Driver
The LT1768 is a current mode PWM controller with a 1.5A
MOSFET driver for high power applications. It contains a
350kHz oscillator, 5V reference, and a current sense
comparator with a 100mV threshold. It operates from an
8Vto24Vinputvoltage.TheLT1768alsohasundervoltage
lockout, thermal limit, and a shutdown pin that reduces
supply current to 65µA. It is available in a small 16-lead
SSOP package.
■
■
100mV Current Sense Threshold
■
5V Reference Voltage Output
■
The 16-Lead SSOP Package
U
APPLICATIO S
■
Desktop Flat Panel Displays
■
Multiple Lamp Displays
, LTC and LT are registered trademarks of Linear Technology Corporation.
Multimode Dimming is a trademark of Linear Technology Corporation.
*Patent Pending
■
Notebook LCD Displays
Point of Sale Terminal Displays
■
U
TYPICAL APPLICATIO
33pF
LAMP
C4-WIMA MKP2
L1-COILTRONICS UP4-680
T1-2 CTX110607 IN PARALLEL
Q1-ZDT1048
6
10
LAMP
T1
33pF
V
*R5 CAN BE METAL PCB TRACE
IN
8V – 24V
4
1
5
3
2
Lamp Output and Dimming
Ratio vs Lamp Current
C1
33µF
C4
0.33µF
10000
1000
100
10
PGND
DI02
GATE
V
IN
250Ω
1/4W
5V
DIMMING RATIO (NITS/NITS)
LAMP OUTPUT (NITS)
DI01
V
REF
Q1
Q1
0.1µF
SENSE
FAULT
SHDN
LT1768
V
C
C2
L1
68µH
0.033µF
AGND
R
MIN
R4
16.2k
MBRS130T3
1
R2
40.2k
C
R
T
MAX
LAMP MANUFACTURERS
SPECIFIED CURRENT RANGE
C3
0.1µF
Si3456DY
PROG
PWM
0.1
PROG
0V TO 5V OR
1kHz PWM
100
0
2
4
6
8
10
R3
60.4k
LAMP CURRENT (mA)
C4
10µF
R1
49.9k
R5*
0.025
1768 TA01b
2200pF
1768 TA01
Figure 1. 14W CCFL Supply Produces a 100:1 Dimming Ratio While
Maintaining Minimum and Maximum Lamp Current Specifications
1
LT1768
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
Input Voltage (VIN Pin) ............................................ 28V
SHDN Pin Voltage.................................................... 28V
FAULT Pin Voltage ................................................... 28V
PROG Pin Voltage................................................... 5.5V
PWM Pin Voltage.................................................... 4.5V
CT Pin Voltage ........................................................ 4.5V
SENSE Pin Voltage .................................................... 1V
DIO1, DIO2 Input Current ................................... ±50mA
ORDER PART
NUMBER
TOP VIEW
PGND
DI01
1
2
3
4
5
6
7
8
GATE
16
15
14
13
12
11
10
9
V
IN
LT1768CGN
LT1768IGN
DI02
V
REF
SENSE
VC
FAULT
SHDN
AGND
R
MIN
GN PART
MARKING
C
T
R
MAX
RMAX Pin Source Current..................................... 750µA
PROG
PWM
RMIN Pin Source Current ..................................... 750µA
VREF Pin Source Current ....................................... 10mA
Operating Junction Temperature Range
1768
1768I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
LT1768C................................................ 0°C to 125°C
LT1768I ............................................ –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering 10 sec)................... 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VVIN = 12V, IDIO1/2 = 250µA, VPROG = 0V, VPWM = 2.5V, IRMAX = –100µA,
IRMIN = –100µA, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
9V< V < 24V
MIN
TYP
7
MAX
8
UNITS
mA
µA
µA
V
I
I
Supply Current
●
●
●
●
●
●
●
●
●
●
●
●
●
Q
VIN
Supply Current in Shutdown
SHDN Pin Pull-Up Current
SHDN Threshold Voltage
SHDN Threshold Hysteresis
V
V
V
= 0V
65
100
12
SHDN
SHDN
SHDN
SHDN
= 0V
4
7
Off to On
0.6
100
7.2
7.1
4.9
1.26
200
7.9
7.4
5
1.8
300
8.2
7.6
5.1
20
mV
V
V
V
Undervoltage Lockout
Undervoltage Lockout
V
V
Off to On
IN
IN
IN
IN
On to Off
= –1mA
V
V
REF Voltage
I
V
REF
REF
REF Line Regulation
REF Load Regulation
∆V 8V to 24V I = –1mA
VIN
7
mV
mV
V
REF
∆I –1mA to –10mA
REF
10
20
V
V
R
MAX
R
MIN
Pin Voltage
Pin Voltage
1.225
1.22
330
1.25
1.26
350
93
1.275
1.30
390
RMAX
RMIN
V
FSW
Switching Frequency
Maximum Duty Cycle
Minimum ON Time
V
V
V
V
= 0.75V, V
= 0.75V, V
= 0.75V, V
= 5V
= 0V
kHz
%
PROG
PROG
PROG
PROG
SENSE
SENSE
SENSE
= 0V
= 150mV
125
100
ns
I
PROG Pin Input Bias Current
●
500
nA
PROG
V
PROG Pin Voltage for Zero Lamp Current
PROG Pin Voltage for Minimum Lamp Current
PROG Pin Voltage for Maximum Lamp Current
(Note 2)
(Note 3)
(Note 4)
●
●
●
0.45
0.9
3.8
0.5
1
4
0.55
1.1
4.2
V
V
V
PROG
2
LT1768
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VVIN = 12V, IDIO1/2 = 250µA, VPROG = 0V, VPWM = 2.5V, IRMAX = –100µA,
IRMIN = –100µA, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.6
50
MAX
4
UNITS
µA
I
PWM Input Bias Current
PWM Duty Cycle
PWM Frequency
●
PWM
V
= 1.75
45
90
55
%
PROG
C = 0.22µF (Note 7)
T
110
130
Hz
V
V
DIO1/2 Positive Voltage
DIO1/2 Negative Voltage
I
I
= 14mA
= –14mA
1.7
–1.1
1.9
–1.3
V
V
DIO1/2
VCCLAMP
SENSE
DIO
DIO
VC High Clamp Voltage
VC Switching Threshold
V
V
= 4.5V (Note 8)
= 4.5V (Note 8)
3.6
0.5
3.7
0.7
3.9
0.95
V
V
PROG
PROG
I
SENSE Input Bias Current
V
= 0V
–25
–30
115
µA
SENSE
V
SENSE Threshold for Current Limit
V
V
= V
= V
, Duty Cycle <50%, V = 1V
PROG
85
94
100
90
mV
mV
SENSE
VC
VC
VCCLAMP
VCCLAMP
, Duty Cycle 80%, V
= 1V
PROG
I
I
to I
Ratio
Ratio
V
= 4.5V (Note 5)
●
●
98
104
A/A
DIO1/2
DIO1/2
RMAX
RMIN
PROG
V
= 4.5V, I
or I
= 0, V = 2.5V,
DIO2 VC
PROG
DIO1
(Note 5)
45
9
49
10
55
11
A/A
A/A
to I
V
< 0.75V (Note 6)
PROG
V
< 0.75V, I
or I
= 0, V = 2.5V,
DIO2 VC
PROG
DIO1
(Note 6)
9
10
11
A/A
I
GATE Drive Peak Source Current
GATE Drive Peak Sink Current
1.5
1.5
A
A
GATE
GATE Drive Saturation Voltage
GATE Drive Clamp Voltage
GATE Drive Low Saturation Voltage
Open LAMP Threshold
V
V
= 12V, I
= 24V, I
= –100mA, V = 4.5V
PROG
●
●
●
9.8
10.2
12.5
0.4
V
V
VIN
VIN
GATE
GATE
= –10mA, V
= 4.5V
14
0.6
150
0.3
100
PROG
I
= 100mA
V
GATE
(Note 9)
100
125
0.2
µA
V
FAULT Pin Saturation Voltage
FAULT Pin Leakage Current
Thermal ShutdownTemperature
I
= 1mA, I
= 5V
, I
= 0µA, V
= 4.5V
PROG
FAULT
DI01 DI02
V
20
nA
°C
FAULT
160
the value of the resistor from the R
lamp current is a function of the R
pin to ground. The lower value
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
MAX
and R
resistors, and the
MIN
MAX
voltages on the PWM and PROG pins. See Applications Information for
more details.
Note 2: This is the threshold voltage where the lamp current switches
from zero current to minimum lamp current. For V
threshold voltage, lamp current will be at zero. For V
less than the
PROG
Note 5: I
to I
VC
ratio is determined by setting I
to –100µA,
greater than the
DIO1/2
RMAX
RMAX
PROG
V
to 4.5V, V to 2.5V, and then ramping a DC current out of the
threshold voltage, lamp current will be equal to the minimum lamp
current. Minimum lamp current is set by the value of the resistor from the
PROG
+
R
MIN
pin to ground. See Applications Information for more details.
I
)/I
. See Applications Information for more details.
DIO2 RMAX
Note 3: This is the threshold voltage where the device starts to pulse width
modulate the lamp current. For V less than the threshold voltage,
Note 6: I
to I
ratio is determined by setting I to –100µA,
RMIN
DIO1/2
RMIN
PROG
V
to 0.75V, V to 2.5V, and then ramping a DC current out of the
lamp current will be equal to the minimum lamp current. For V
PROG
VC
PROG
DIO1/2 pins from zero until the DC current in the VC voltage source
current equals zero. The I to I ratio is then defined as (I +
DIO1
greater than the threshold voltage, lamp current will be pulse width
modulated between the minimum lamp current and some higher value.
Minimum lamp current is set by the value of the resistor from the R
DIO1/2
RMIN
I
)/I
. See Applications Information for more details.
pin
DIO2 RMIN
MIN
to ground. The higher value lamp current is a function of the R
to ground value, and the voltages on the PWM and PROG pins. See
Applications Information for more details.
resistor
Note 7: The PWM frequency is set by the equation PWMFREQ = 22Hz/
MAX
C (µF).
T
Note 8: For VC voltages less than the switching threshold, GATE switching
is disabled.
Note 4: This is the threshold voltage where the lamp current reaches its
maximum value. For V greater than the threshold voltage, there will
PROG
Note 9: An open lamp will be detected if either I
or I
is less than
DIO2
DIO1
be no increase in lamp current. For V
less than the threshold voltage,
PROG
the threshold current for at least 1 full PWM cycle.
lamp current will be at some lower value. Maximum lamp current is set by
3
LT1768
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current in Shutdown vs
Temperature
VREF vs Temperature
VRMIN, VRMAX vs Temperature
80
76
72
68
64
60
56
52
48
44
40
1.30
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
V
= 0V
I
I
= –100µA
= –100µA
SHDN
I
= –1mA
RMIN
RMAX
REF
V
RMIN(V)
V
RMAX(V)
50
0
TEMPERATURE (°C)
–50 –25
25
75
100 125
50
0
TEMPERATURE (°C)
50
TEMPERATURE (°C)
–50 –25
0
25
75
100 125
–50 –25
25
75
100 125
1768 G02
1768 G01
1768 G03
Supply Current in Shutdown vs
Input Voltage
Supply Current vs Input Voltage
Supply Current vs Temperature
10
8
100
80
60
40
20
0
7.40
7.30
7.20
7.10
7.00
6.90
6.80
6.70
6.60
6.50
6.40
V
= 0V
SHDN
6
4
2
0
10
INPUT VOLTAGE (V)
10
INPUT VOLTAGE (V)
0
5
15
20
25
0
5
15
20
25
50
TEMPERATURE (°C)
–50 –25
0
25
75
100 125
1768 G06
1768 G04
1768 G05
SHDN Pull-Up Current
vs Input Voltage
Shutdown Threshold Voltage vs
Temperature
Undervoltage Lockout Threshold
vs Temperature
10
8
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0
8.20
8.10
8.00
7.90
7.80
7.70
7.60
7.50
7.40
7.30
7.20
V
= 0V
SHDN
V
OFF TO ON
V
OFF TO ON
UVL
SHDN
6
4
V
ON TO OFF
SHDN
2
V
0
ON TO OFF
UVL
0
0
5
10
15
20
25
50
50
–50 –25
0
25
75
100 125
–50 –25
25
75
100 125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1768 G07
1768 G08
1768 G09
4
LT1768
U W
TYPICAL PERFOR A CE CHARACTERISTICS
FAULT Pin Saturation Voltage vs
Temperature
Switching Frequency vs Temperature
PWM Frequency vs Temperature
124
120
116
112
108
104
100
96
400
390
380
370
360
350
340
330
320
310
300
0.250
0.225
0.200
0.175
0.150
0.125
0.100
0.75
C
V
= 0.22µF
PWM
T
= 2.5V
92
0.50
I
I
I
= 0µA
= 0µA
FAULT
DIO1
DIO2
88
0.25
= 1mA
84
0
50
TEMPERATURE (°C)
50
TEMPERATURE (°C)
–50 –25
0
25
75
100 125
–50 –25
0
25
100 125
50
TEMPERATURE (°C)
75
–50 –25
0
25
75
100 125
1768 G10
1768 G11
1768 G12
Sense Pin Bias Current vs
Temperature
Maximum Gate Voltage vs
Temperature
FAULT Pin Saturation Voltage vs
Current
450
400
350
300
250
200
150
100
50
45
40
35
30
25
20
15
10
5
15.00
14.50
14.00
13.50
13.00
12.50
12.00
11.50
11.00
10.50
10.00
I
= –10mA
GATE
I
I
= 0µA
= 0µA
V
= 0V
DIO1
DIO2
SENSE
V
IN
= 24V
V
= 12V
75
IN
0
50
0
TEMPERATURE (°C)
50
2.0
3.0 3.5
–50 –25
25
75
100 125
–50 –25
0
25
100 125
0
0.5
1.0 1.5
2.5
I
(mA)
TEMPERATURE (°C)
FAULT
1768 G14
1768 G13
1768 G15
DIO Pin Voltage vs Current
DIO Pin Voltage vs Current
VC Clamp Voltage vs Current
–2.0
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
3.75
3.74
3.73
3.72
3.71
3.70
3.69
3.68
3.67
3.66
3.65
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–10
200
0
–2 –4 –6 –8
–12 –14 –16 –18 –20
0
50 100 150
V
250 300 350 400 450 500
10
0
2
4
6
8
12 14 16 18 20
DIO CURRENT (mA)
CURRENT (µA)
DIO CURRENT (mA)
C
1768 G20
1768 G25
1768 G24
5
LT1768
U W
TYPICAL PERFOR A CE CHARACTERISTICS
PWM Pin Input Current
vs Voltage
VC Switching Threshold
vs Temperature
VC Clamp Voltage vs Temperature
25
20
15
10
5
3.90
3.85
3.80
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
I
= 500µA
VC
0
0
1
2
3
4
5
50
0
TEMPERATURE (°C)
50
TEMPERATURE (°C)
–50 –25
25
75
100 125
–50 –25
0
25
75
100 125
PWM VOLTAGE (V)
1768 G28
1768 G26
1768 G27
PWM Pin Input Current vs
Temperature
Lamp Fault Current Threshold
vs Temperature
Maximum Sense Threshold
vs Gate Drive Duty Cycle
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
120
110
100
90
200
180
160
140
120
100
80
V
= 2.5V
PWM
80
70
60
50
60
40
40
30
20
20
0
50
TEMPERATURE (°C)
40
50 60 70 80 90 100
–50 –25
0
25
75
100 125
0
10 20 30
50
TEMPERATURE (°C)
–50 –25
0
25
75
100 125
GATE DUTY CYCLE (%)
1768 G29
1768 G32
1768 G31
IDIO1/2 to IRMAX Ratio vs RMAX
Current with a Lamp Fault
IDIO1/2 to IRMIN Ratio vs RMIN
Current
IDIO1/2 to IRMAX Ratio vs RMAX
Current
110
108
106
104
102
100
98
60
58
56
54
52
50
48
46
44
42
40
11.0
10.8
10.6
10.4
10.2
10.0
9.8
V
V
= 4.5V
V
V
= 0.75V
V
V
DI01
= 4.5V
PROG
VC
PROG
VC
PROG
VC
= 2.5V
= 2.5V
= 2.5V
I
OR I
= 0µA
DI02
96
9.6
94
9.4
92
9.2
90
9.0
–120
–120
–120
0
–60
–180
–240
–300
0
–60
–180
–240
–300
0
–60
–180
(µA)
–240
–300
I
(µA)
I
(µA)
I
RMIN
RMAX
RMAX
1768 G33
1768 G34
1768 G35
6
LT1768
U
U
U
PIN FUNCTIONS
PGND (Pin 1): The PGND pin is the high current ground
path. High switching current transients and lamp current
flow through the PGND pin.
provides lamp current averaging and single pole loop
compensation.
AGND (Pin 6): The AGND pin is the low current analog
ground. It is the negative sense terminal for the internal
reference and current sense amplifier. Connect critical
external components that terminate to ground directly to
this pin for best performance.
DIO1/DIO2 (Pins 3/2): Each DIO pin is the common
connectionbetweenthecathodeandanodeoftwointernal
diodes. The remaining terminals of the diodes are con-
nected to PGND. In a typical application, the DIO1/2 pins
are connected to the low voltage side of the lamps.
Bidirectional lamp current flows into the DIO1/2 pins and
their diodes conduct alternately on the half cycles. The
diodethatconductsonthenegativecyclehasapercentage
of its current diverted into the VC pin. This current nulls
against the programming current specified by the PROG
and PWM pins. A single capacitor on the VC pin provides
both stable loop compensation and an averaging function
to the half wave-rectified lamp current. The diode that
conducts on the positive cycle is used to detect open lamp
conditions. If the current in either of the DIO pins on the
positive cycle is less than 125µA for a minimum of 1 PWM
cycle, then the FAULT pin will be activated and the maxi-
mum source current into the VC pin will be reduced by
approximately 50%. If the current in both of the DIO pins
onthepositivecycleislessthan125µA,andtheVCpinhits
its clamp value (indicating either an open lamp or lamp
lowside short to ground fault condition) for a minimum of
1 PWM cycle, the gate drive will be latched off. The latch
can be cleared by setting the PROG voltage to zero or
placing the LT1768 in shutdown mode.
CT (Pin 7): The value of capacitance on the CT pin deter-
mines the PWM modulation frequency. The transfer func-
tion of capacitance to frequency equals 22Hz/CT(µF). The
frequency present on the CT pin also determines the
maximum time allowed for lamp fault conditions. If the
current in either DIO1 or DIO2 is less than 125µA for a
minimumof1PWMperiod, theFAULTpinisactivatedand
the maximum allowable lamp current is reduced by ap-
proximately 50%. If the current in both DIO1 and DIO2 is
absent for a minimum of 1 PWM period, and the VC pin is
clamped at 3.7V, the FAULT pin is activated and the gate
drive of the part is internally latched off. The latch can be
cleared by setting the PROG voltage to zero or placing the
LT1768 in shutdown mode.
PROG (Pin 8): The PROG pin controls the lamp current by
converting a DC input voltage range of 0V to 5V to source
current into the VC pin. The transfer function from pro-
grammingvoltagetoVCcurrentisillustratedinthefollow-
ing table.
PROG (V)
VC SOURCE CURRENT (µA)
SENSE (Pin 4): The SENSE pin is the input to the current
sense comparator. The threshold of the comparator is a
function of the voltage on the VC pin and the switch duty
cycle. The maximum threshold is set at 100mV for duty
cycle less than 50% which corresponds to approximately
3.7V on the VC pin. The SENSE pin has a bias current of
25µA, which flows out of the pin.
V
< 0.5
0
PROG
0.5 < V
1.0 < V
< 1.0
I
RMIN
PROG
< V
PWM Mode*
I
RMIN
PROG
PWM
V
V
> V
< V
CT
CT
PROG
5 • I
• ( V
– 1V)/ 3V
PWM
PROG
RMAX
V
> 4.0
5 • I
RMAX
PROG
*PWM Duty Cycle = [1 – (V
– V
)/(V
– 1V)] • 100%
PWM
PWM
PROG
VC (Pin 5): The VC pin is the summing junction for the
programming current and the half wave rectified lamp
current and is also an input to the current sense compara-
tor . A fraction of the voltage on the VC pin is compared to
the voltage on the SENSE pin (switch current) for switch
turnoff. During normal operation the VC pin sits between
0.7V (zero switch current) and 3.7V (maximum switch
current). A single capacitor between VC and AGND
PWM (Pin 9): The PWM pin controls the percentage of the
PROG range between 1V and 4V that is to be pulse width
modulated. The percentage is defined by [(VPWM-1)/ 3] •
100%. The minimum and maximum percentages are 25%
(1.75V) and 100% (4V) respectively. Taking the PWM pin
above the 4V maximum will cause significant PWM input
current to flow. (See PWM Input Current vs Voltage curve
in Typical Performance Characteristics).
7
LT1768
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PIN FUNCTIONS
RMAX (Pin 10): The RMAX pin outputs a regulated voltage
of 1.25V that is to be loaded with an external resistor. The
current through the external resistor sets the maximum
lamp current. Maximum lamp current in a dual lamp
applicationwillbeapproximatelyequalto100timesIRMAX
when the voltage on the PROG pin is greater than 4V. The
value of RRMAX must be greater than 5K and less than
[RRMIN • 2.5 • (VPWM–1/3)] for proper PWM operation.
FAULT (Pin 13): The FAULT pin is an open collector output
with a sink capability of 1mA that is activated when lamp
current falls below 125µA in either DIO1 or DIO2 for at least
1 full PWM cycle.
V
(Pin 14): The V pin is a regulated 5V output that is
REF
REF
derived from the V pin. The regulated voltage provides up
IN
to 10mA of current to power external circuitry. During
undervoltage lockout, shutdown mode or thermal
RMIN (Pin 11): The RMIN pin outputs a regulated voltage of
1.26V that is to be loaded with an external resistor. The
current through the external resistor sets the minimum
lamp current. Minimum lamp current in a dual lamp
application will be approximately 10 times the value of
shutdown, drive to the V
pin will be disabled.
REF
V (Pin 15): The V pin is the voltage supply pin for the
IN
IN
LT1768. Fornormaloperation, theV pinmustbeabovean
IN
undervoltagelockoutof7.9Vandbelowamaximumof24V.
GATE (Pin 16): The GATE pin is the output of a NPN high
current output stage used to drive the gate of an external
MOSFET. It has a dynamic source and sink capability of
1.5A. During normal operation, the GATE pin is driven high
at the beginning of each oscillator period and then low
when the appropriate current in the switch is reached. The
GATE pin has a minimum on time of 125ns and a maximum
duty cycle of 93% at a frequency of 350kHz. For input
voltages less than 13V the gate will be driven to within 2V
IRMIN when the voltage on the PROG pin is between 0.5V
and 1V. To set the minimum current to zero (IRMIN = 0µA)
for maximum dimming range, connect the RMIN pin to the
VREG pin. The value of RRMIN (RRMIN = ∞ when RMIN is
connected to VREG) must be greater than the value of
RRMAX/[0.4 • (VPWM–1)/3] for proper PWM operation.
SHDN (Pin 12): The SHDN pin controls the operation of
the LT1768. Pulling the SHDN pin above 1.26V or leaving
the pin open will result in normal operation of the LT1768.
Pulling the SHDN pin below 1V causes a complete shut-
down of the LT1768 which results in a typical quiescent
current of 65µA. The SHDN pin has an internal 7µA pull-up
source to VIN and 200mV of voltage hysteresis.
of V . For input voltages greater than 13V the gate pin high
IN
level will be clamped at a typical voltage of 12.5V.
8
LT1768
W
BLOCK DIAGRA
V
V
REF
OSC
15
12
IN
SHDN
16
GATE
V
GATE
IN
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
SW
BLANK
14
V
R
REF
11
10
1.26V
I
RMIN
MIN
S
R
R
MAX
Q
I
RMAX
1.25V
0
1V 4V
MODE CONTROL
PROG
I
8
VC
SLOPE
V
CCLAMP
FAULT
4
SENSE
V
PWM
PWM
9
7
1V
PWM PERIOD
C
T
(I
+ I
GAIN
)
DIO1 DIO2
PGND
FAULT
I
I
< 125µA
1
DIO1
DIO2
MULTI-MODE
DIMMING BLOCK
I
VC
13
< 125µA
1768 BD
6
5
3
2
VC
DI01 DIO2
AGND
Figure 2. LT1768 Block Diagram
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INTRODUCTION
sinusoidal CCFL drive also maximizes current to light
conversion, reduces display flicker, and minimizes EMI
and RF emissions. The LT1768 high power CCFL control-
ler, with its Multimode Dimming, provides the necessary
lamp drive to enable a wide dimming range while main-
taining lamp lifetime in multiple lamp CCFL applications.
Thecurrenttrendindesktopmonitordesignistomigrate
theLCD(liquidcrystaldisplay)technologyusedinlaptops
and instruments to the popular desktop display sizes. As
LCD size increases uniform backlighting requires mul-
tiple high power lamps. In addition, the lamps must have
a dimming range and lifetime expectancy comparable to
previous generations of desktop displays. Cold cathode
fluorescent lamps (CCFLs) provide the highest available
efficiency for backlighting LCD displays. The CCFL re-
quiresahighvoltagesupplyforoperation. Typically, over
1000 volts is required to initiate CCFL operation, with
sustaining voltages from 200V to 800V. A CCFL can
operate from DC, but migration effects damage the CCFL
and shorten its lifetime. To achieve maximum life CCFL
drive should be sinusoidal, contain zero DC component,
and not exceed the CCFL manufacturers minimum and
maximum operating current ratings. Low crest factor
BASIC OPERATION
Referring to the circuit in Figure 1, CCFL current is con-
trolledbyaDCvoltageonthePROGpinoftheLT1768. The
DCvoltageonthePROGpinfeedstheLT1768’sMultimode
Dimming block and is converted to source current into the
VC pin. As the VC pin voltage rises, the LT1768’s GATE pin
ispulsewidthmodulatedat350kHz. TheGATEpulsewidth
is determined on a cycle by cycle basis by the voltage on
the SENSE pin (L1’s current multiplied by SENSE resistor
R5) exceeding a predetermined voltage set by the VC pin.
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LT1768
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APPLICATIONS INFORMATION
The current mode pulse width modulation produces an
average current in inductor L1 proportional to the VC
voltage. Inductor L1 then acts as a switched mode current
source for a current driven Royer class converter with
efficiencies as high as 90%. T1, C4 and Q1 comprise the
Royer class converter which provides the CCFLs with a
zero DC, 60kHz sinusoidal waveform whose amplitude is
based on the average current in L1. Sinusoidal current
from both CCFLs is then returned to the LT1768 through
the DIO1/2 pins. A fraction of the CCFL current from the
negative half of its sine wave pulls against the internal
current source at the VC pin closing the loop. A single
capacitor on the VC pin provides loop compensation and
CCFL current averaging, which results in constant CCFL
current.Varyingthevalueoftheinternalcurrentsourcevia
theMultimodeDimmingblockvariestheCCFLcurrentand
resultant CCFL light intensity.
control loop by combining the error signal conversion
scheme and frequency compensation into a single capaci-
tor (VC pin). The control loop thus exhibits the response
of a single pole system, allows for faster loop transient
response and minimizes overshoot under start-up or
overload conditions.
Referring to Figure 2, the source current into the VC pin
from the Multimode Dimming block (and resultant CCFL
current)hasfivedistinctmodesofoperation. Whichmode
is in use is determined by the voltages on the PROG and
PWM pins, and the currents that flow out of the RMAX and
RMIN pins.
Off Mode (VPROG < 0.5V), sets the VC source current to
zero, activelypullsVCtoground, andinhibitstheGATEpin
from switching which results in zero lamp current.
Minimum current mode (0.5V < VPROG < 1V) sets the VC
source current equal to the current out of the 1.26V
referenced RMIN pin. The minimum VC source current
determines the dimming range of the display. Setting
RRMIN to produce the manufacturer’s minimum specified
CCFL current guarantees the maximum CCFL lifetime for
all PROG voltages, but limits the dimming range. Setting
RRMIN to produce currents less than the manufacturer’s
minimumspecifiedCCFLcurrentincreasesdimmingrange,
but places restrictions on the PROG voltage for normal
operation in order to maximize lifetime. To achieve the
maximum dimming ratio possible, IRMIN should be set to
zero by connecting the RMIN pin to the VREF pin.
Multimode Dimming
Previous backlighting solutions have used a traditional
erroramplifierinthecontrollooptoregulatelampcurrent.
The approach converted AC current into a DC voltage for
theinputoftheerroramplifier. Thisapproachusedseveral
time constants in order to provide stable loop compensa-
tion. This compensation scheme meant that the loop had
to be fairly slow and that the output overshoot with start-
uporloadconditionshadtobecarefullyevaluatedinterms
of transformer stress and breakdown voltage require-
ments. In addition, intensity control schemes were limited
tolinearorPWMcontrol.Linearintensitycontrolschemes
provide the highest efficiency backlight circuits but either
limit dimming range, or violate lamp minimum or maxi-
mum CCFL current specifications to achieve wide dim-
ming ratios. PWM control schemes offer wide dimming
range but produce waveforms that may degrade CCFL life,
and waste power at higher CCFL currents. The LT1768’s
Multimode Dimming eliminates the error amplifier con-
ceptentirelyandcombinesthebestofbothcontrolschemes
to extend CCFL life while providing the widest possible
dimming range.
For example, the circuit in Figure 1 produces a dimming
ratio of 100:1 at 1mA of lamp current, but sets the
minimum CCFL current to zero (RMIN is connected to
VREF). In this case, the PROG voltage must be kept above
1.12V to limit the CCFL current to 1mA (1mA is only a
typical minimum lamp current used for illustration, con-
sult lamp specifications for actual minimum allowable
value) during normal operation in order to meet CCFL
specificationsto maximize lifetime. Itshould be noted that
taking the PROG voltage in Figure 1 down to 1V (0mA
CCFL current) enables dimming ratios greater than 500:1,
but violates minimum CCFL current specifications in most
lamps and is not recommended. Alternatively, discon-
necting RMIN from VREF and adding a 10kΩresistor from
RMIN to AGND in Figure 1 sets the minimum CCFL current
The error amplifier is eliminated by summing the current
out of the Multimode Dimming block with a fraction of
feedback lamp current to form the control loop. This
topology reduces the number of time constants in the
10
LT1768
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APPLICATIONS INFORMATION
per lamp to 1mA for all PROG voltages but limits the mode. For example, in the circuit in Figure 1, linear mode
dimming ratio to 6:1.
runs from VPROG = 3V to VPROG = 4V with lamp current
equal to (3mA)(VPROG–1V)/1V.
Trace B in Figures 3a and 3b shows Figure 1’s CCFL
current waveform operating at 1mA in PWM mode.
InPWMMode(1V<VPROG <VPWM),theVCsourcecurrent
is modulated between the value set by minimum current
Maximum current mode (VPROG > 4V) sets the VC source
current to five times the current out of the 1.25V refer-
enced RMAX pin. Setting RRMAX to produce CCFL current
equal to the manufacturer’s maximum rating in this mode
insures no degradation in the specified lamp lifetime. For
example, setting R4 in the circuit in Figure 1 to 16.2k sets
the maximum CCFL current to 9mA (9mA is only a typical
maximum lamp current used for illustration, consult lamp
specifications for the actual value). Trace A in Figure 3a
and3bshowsFigure1’sCCFLcurrentwaveformoperating
at 9mA in maximum current mode.
mode and the value for IVC in linear mode with VPROG
=
VPWM. The PWM frequency is equal to 22Hz/CT(µF) with
its duty cycle set by the voltages on the PROG and PWM
pins and follows the equation:
DC = [1 – (VPWM – VPROG)/(VPWM – 1V)] • 100%
The LT1768’s PWM mode enables wide dimming ratios
while reducing the high crest factor found in PWM only
dimming solutions. In the example of Figure 1, PWM
mode runs from VPROG = 1V to VPROG = 3V with CCFL
current modulated between 0mA and 6mA. The PWM
modulation frequency is set to 220Hz by capacitor C3.
TRACE A
When combined, these five modes of operation allow
creationofaDCcontrolledCCFLcurrentprofilethatcanbe
tailored to each particular display. With linear mode CCFL
current control over the most widely used current range,
and PWM mode at the low end, the LT1768 enables wide
dimming ratios while maximizing CCFL lifetimes.
V
PROG = 4.5V
ILAMP = 9mARMS
TRACE B
PROG = 1.125V
ILAMP = 1mARMS
V
1ms/DIV
Lamp Feedback Current
Figure 3a. CCFL Current for Circuit in Figure 1
In a typical application, the DIO1/2 pins are connected to
the low voltage side of the lamps. Each DIO pin is the
common connection between the cathode and anode of
two internal diodes (see Block Diagram). The remaining
terminals of the diodes are connected to PGND. Bidirec-
tional lamp current flows into the DIO1/2 pins and their
diodes conduct alternately on the half cycles. The diode
that conducts on the negative cycle has a percentage of its
current diverted into the VC pin. This current nulls against
the VC source current specified by the Multimode Dim-
ming section. A single capacitor on the VC pin provides
both stable loop compensation and an averaging function
to the halfwave-rectified lamp current. Therefore, current
into the VC pin from the lamp current programming
section relates to average lamp current.
TRACE A
PROG = 4.5V
ILAMP = 9mARMS
V
TRACE B
PROG = 1.125V
ILAMP = 1mARMS
V
100µs/DIV
Figure 3b. CCFL Current for Circuit in Figure 1
In linear mode (VPWM < VPROG < 4V), VC source current is
controlled linearly with the voltage on the PROG pin. The
equation for the VC source current in linear mode is
IVC = (VPROG – 1V)/3V (IRMAX • 5). For the best current to
light conversion and highest efficiency, VPWM should be
set to make the LT1768 normally operate in the linear
The overall gain from the resistor current to average lamp
current is equal to the gain from the Multimode Dimming
block divided by the gain from the DIO pin to the VC pin,
11
LT1768
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APPLICATIONS INFORMATION
and is dependant on the operating mode. For dual lamp RRMIN adjusted to produce the specified current. If a wide
displays, the transfer function for minimum current mode dimming range is desired, VPROG should be set to 0.75V
(IDIO/IRMIN) is equal to 10A/A, and for maximum current and RRMIN adjusted to produce the required dimming
mode (IDIO RMAX
/I
) is equal to 100A/A.
ratio. Care must be taken when adjusting RRMIN to pro-
duce extreme dimming ratios. The minimum lamp current
set by RRMIN must be able to fully illuminate the lamp or
thermometering (uneven illumination) will occur. If the
desired dimming ratio can’t be achieved by adjusting
The transfer functions discussed above are between RMAX
and RMIN current and average lamp current not RMS lamp
current. Due to the differences between the average and
RMS functions, the actual overall transfer function be-
tweenactuallampcurrentandRMIN/RMAX currentmustbe
empiricallydetermined, andisdependantontheparticular
lamp/display housing combination used. For example, in
the circuit of Figure 1 setting RRMIN to 10kΩ and RRMAX to
16.8Ω, sets the minimum and maximum RMS lamp
R
RMIN, the minimum lamp current can be set to zero by
connecting the RMIN pin to the VREF pin. If the minimum
current is set to less than the open lamp threshold current
(approximately125µA), theFAULTpinwillbeactivatedfor
PROG voltages between 0.5V and 1V.
currentsfortheexampledisplayto1mAand9mAperlamp The values chosen for RRMAX and RRMIN are extremely
respectively.Figure4showsthelampcurrentvsprogram- critical in determining the lifetime of the display. It is
ming voltage for the circuit in Figure 1.
imperative that proper measurement techniques, such as
those cited in the references, be used when determining
RRMAX and RRMIN values.
MIN
CURRENT
MAX
CURRENT
LINEAR
9mA
6mA
PWM
(FREQ = 220Hz)
Lamp Fault Modes and Single Lamp Operation
100%
0%
The DIO pin diodes that conduct on the positive cycle are
used to detect open lamp fault conditions. If the current
in either of the DIO pins on the positive half cycle is less
than 125µA due to either an open lamp or lamp lowside
short to ground, for a minimum of 1 PWM cycle, then the
FAULT pin will be activated and the lamp programming
current into the VC pin in high level PWM mode, linear
mode, and maximum current mode, will be reduced by
approximately50%. HalvingtheVCsourcecurrentwillcut
the total lamp current to approximately one half of its
programmed value. This function insures that the maxi-
mum lamp current level set by RRMAX will not be exceeded
even under fault conditions. If the current in both of the
DIO pins on the positive cycle is less than 125µA, and the
VC pin hits its clamp value (indicating an open lamp or
lamp lowside short to ground fault condition) for a mini-
mumof1PWMcycle, thegatedrivewillbelatchedoff. The
latch can be cleared by setting the PROG voltage to zero or
placing the LT1768 in shutdown mode.
I
(mA)
CCFL
OFF
0mA
0.5 1.0
3V (V
4.0
5.0
PWM)
(V)
V
PROG
1768 F04
Figure 4. Lamp Current vs PROG Voltage for
the Circuit in Figure 1
Choosing RRMAX and RRMIN and VPWM
The value for RRMAX should be determined by setting
VPROG to 4.5V then adjusting RRMAX to produce the
maximum allowable current specified by the lamp manu-
facturer.
The voltage for the PWM pin should then be set so that the
LT1768 normally operates in linear mode. A typical value
for VPWM is approximately 2.5V, which limits the PWM
region to 50% of the VPROG input voltage range.
Since open lamp fault conditions produce high voltage AC
waveforms, it is imperative that proper layout spacings
between the high voltage and DIO lines be observed.
Coupling capacitance as low as 0.5pF between the high
The value for RRMIN should be chosen to either produce
the minimum manufacturer specified lamp current or
enable a wide dimming range. If a minimum specified
current is desired, the VPROG should be set to 0.75V and
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LT1768
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APPLICATIONS INFORMATION
voltage and DIO lines can cause enough current flow to
fool the open lamp detection. In situations where coupling
can’t be avoided, resistors can be added from the DIO pins
to ground to increase the open lamp threshold. When
resistors from the DIO pins to ground are added, the
values for RRMAX and RRMIN may need to be increased
fromtheirnominalvaluestocompensatefortheadditional
current.
start of every oscillator cycle. The GATE is driven back low
when the current reaches a threshold level proportional to
thevoltageontheVCpin. TheGATEthenremainslowuntil
the start of the next oscillator cycle. The peak current is
thus proportional to the VC voltage and controlled on a
cycle by cycle basis. The peak switch current is normally
sensedbyplacingasenseresistorinthesourceleadofthe
output MOSFET. This resistor converts the switch current
to a voltage that can be compared to a fraction of the VC
voltage [(VVC – VDIODE)/30] . For normal conditions and a
GATE duty cycle below 50%, the switch current limit will
correspond to IPK = 0.1/RSENSE. For GATE duty cycles
above 50% the switch current limit will be reduced
to approximately 90mV at 80% duty cycle to avoid
subharmonic oscillations associated with current mode
controllers.
For single lamp operation, the lowside of the lamp should
be connected to both DIO pins, and the values of RRMAX
and RRMIN increased to two times the values that would be
used in a dual lamp configuration. In single lamp mode all
fault detection will operate as in the dual lamp configura-
tion, but the open lamp threshold will double. If the
increase in the open lamp threshold is not acceptable, a
positive offset current can be added to reduce the open
lamp threshold by placing a resistor between the REF and
DIO pins (a 33k resistor will reduce the open lamp thresh-
WhenthelampcurrentisprogrammedtoPWMmode, the
VC pin will slew between voltages that represent the
minimum and maximum PWM lamp currents. The slew
time affects the line regulation at low duty cycle, and
should be kept low by making the sense resistor as small
as possible. The lowest value of sense resistor is deter-
mined by switching transients and other noise due to
layout configurations. A good rule of thumb is to set the
sense resistor so that the voltage on the VC pin equals
2.5V when the PWM current is in maximum mode (VPROG
= VPWM). Typical values of the sense resistor run in the
25mΩ to 50mΩ range for large displays, and can be
implemented with a copper trace on the PCB.
–
old by approximately 100µA ((VREF VDIO+)/33k). When
anoffsetcurrentisadded, thevaluesforRRMAX andRRMIN
may need to be increased from their nominal values to
compensate for the offset current.
VC Compensation
As previously mentioned a single capacitor on the VC pin
combines the error signal conversion, lamp current aver-
agingandfrequencycompensation. Carefulconsideration
should be given to the value of capacitance used. A large
value (1µF) will give excellent stability at high lamp cur-
rents but will result in degraded line regulation in PWM
mode. On the other hand , a small value (10nF) will give
excellentPWMresponsebutmightresultinovershootand
poor load regulation. The value chosen will depend on the
maximum load current and dimming range. After these
parametersaredecidedupon,thevalueoftheVCcapacitor
should be increased until the line regulation becomes
unacceptable. A typical value for the VC capacitor is
0.033µF. For further information on compensation please
refer to the references or consult the factory.
Since the maximum threshold at the SENSE pin is only
100mV, switching transients and other noise can prema-
turely trip the comparator. The LT1768 has a blanking
period of 100ns which prohibits premature switch turn
off, but further filtering the sense resistor voltage is
recommended. A simple RC filter is adequate for most
applications. (Figure 5.)
GATE
LT1768
100Ω
SENSE
Current Sense Comparator
0.025mΩ
2.2nF
The LT1768 is a current mode PWM controller. Under
normaloperatingconditionstheGATEisdrivenhighatthe
1768 •F05
Figure 5. Sense Pin Filter
13
LT1768
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APPLICATIONS INFORMATION
GATE
up current source. The LT1768 thermal shutdown tem-
perature is set at 160°C. A buffered version of the internal
5VispresentattheVREF pinandiscapableofsupplyingup
to 10mA of current. Note that using any substantial
amount of current from the VREF pin will increase power
dissipation in the device, which will reduce the useful
operating ambient temperature range.
The LT1768 has a single high current totem pole output
stage. This output stage is capable of driving up to ±1.5A
of output current. Cross-conduction current spikes in the
totem pole output have been eliminated. The GATE pin is
intended to drive an N-channel MOSFET switch. Rise and
fall times are typically 50ns with a 3000pF load. A clamp
is built into the device to prevent the GATE pin from rising
above 13V in order to protect the gate of the MOSFET
switch.
Supply and Input Voltage Sequencing
For most applications, where the SHDN pin is left floating,
and the voltages on the PWM and PROG pins are derived
from the VREF pin, the LT1768 will power-up and power-
down correctly when the voltage to the VIN pin is applied
and removed. In applications where the voltage inputs for
the VIN pin, SHDN pin, PWM pin, and the PROG pin
originatefromdifferentsources(powersupply,micropro-
cessors etc.), care must be taken during power up/down
sequences. For proper operation during the power-up
sequence, the voltage on the following pins must be taken
from zero to their appropriate values in the following
order; VIN pin, SHDN pin, PWM pin and PROG pin. For
proper operation during the power-down sequence, the
order must be reversed. For example, in the circuit of
Figure 1 where the SHDN pin is left floating, and the PWM
pin voltage is derived from a resistor divider to the VREF
pin, the proper power-up sequence would be to take the
VIN pin from zero to its value then apply either a voltage or
PWM signal to the PROG pin. The power-down sequence
for the circuit in Figure 1 would be to take the PROG pin
voltage to zero, then take the VIN pin voltage to zero.If the
PROGvoltageinthecircuitofFigure1ispresentbeforethe
VIN supplyvoltage, properpowersupplysequecingcanbe
achieved by implementing the circuit shown in Figure 7.
The GATE pin connects directly to the emitter of the upper
NPN drive transistor and the collector of the lower NPN
drivetransistorinthetotempole.Thecollectorofthelower
transistor, which is N-type silicon, forms a P-N junction
with the substrate of the device. This junction is reversed
biased during normal operation.
In some applications the parasitic LC of the external
MOSFET gate can ring and pull the GATE pin below
ground. If the GATE pin is pulled negative by more than a
diode drop the parasitic diode formed by the collector of
the GATE NPN and the substrate will turn on. This can
cause erratic operation of the device. In these cases a
Schottky clamp diode is recommended from the GATE pin
to ground. (Figure 6.)
BAT 85
LT1768
PGND
GATE
1768 • G06
Figure 6. Schottky Gate Clamp
Reference
V
IN
TheinternalreferenceoftheLT1768isatrimmedbandgap
reference. The reference is used to power the majority of
the LT1768 internal circuitry. The reference is inactive if
theLT1768isinundervoltagelockout,shutdownmode,or
thermal shutdown. The undervoltage lockout is active
when VIN is below 7.9V and the LT1768 is in shutdown
mode when the voltage on the SHDN pin is pulled below
1V. TheSHDNpinhas200mVofhysteresisanda7µApull-
LT1768
0 TO 5V
OR
1kHz PWM
49.9k
PROG
VN2222LL
10k
10µF
1768 F07
Figure 7. Circuit Insures Proper Supply Sequencing When
Dimming Voltage Exists Before Main Power Supply
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LT1768
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APPLICATIONS INFORMATION
Supply Bypass and Layout Considerations
together with minimum trace between them. If space
constraints prohibit the transformer T1 placement next to
C1, local bypassing (C2) for the center tap of transformer
T1 should be used.
Proper supply bypassing and layout techniques must be
used to insure proper regulation, avoid display flicker, and
insure long term reliability.
Special attention is also required for the layout of the high
voltage section to avoid any unpleasant surprises. Please
refer to the references for an extensive discussion on high
voltage layout techniques.
Figure8showstheapplication’scriticalhighcurrentpaths
in thick lines. Ideally, all components in the high current
path should be placed as close as possible and connected
with short thick traces. The most critical consideration is
that T1’s center tap, the Schottky diode D1, LT1768’s VIN
pin, and a low ESR capacitor (C1) be connected directly
Applications Support
Linear Technology invests an enormous amount of time,
resources, and technical expertise in understanding, de-
signing and evaluating backlight solutions for systems
designers. The design of an efficient and compact back-
light system is a study of compromise in a transduced
electronic system. Every aspect of the design is interre-
lated and any design change requires complete re-evalu-
ation for all other critical design parameters. Linear
Technology has engineered one of the most complete test
and evaluation setups for backlight designs and under-
stands the issues and trade-offs in achieving a compact,
efficient and economical customer solution. Linear Tech-
nology welcomes the opportunity to discuss, design,
evaluate, and optimize any backlight system with a cus-
tomer. For further information on backlight designs, con-
sult the references below.
T1
V
IN
C2
*OPTIONAL
L1
D1
LT1768
GATE
V
IN
C1
SENSE
PGND
References
1. Williams, Jim. November 1995. A Fourth Generation of
LCD Backlight Technology. Linear Technology Corpora-
tion, Application Note 65.
BOLD LINES INDICATE
HIGH CURRENT PATHS
1768 F08
Figure 8
15
LT1768
U
TYPICAL APPLICATIONS
DC Intensity Control
V
REF
PROG
LT1768
AGND
R1
100k
POT
1768 TA04
PWM Intensity Control
V
REF
R1
49.9k
0 – >5V
1kHz PWM
PROG
LT1768
AGND
C1
10µF
1768 TA05
PWM Intensity Control From 3.3V or 5V Logic
V
REF
PROG
LT1768
AGND
R1
10k
R1
49.9k
C1
10µF
R
ID
0 – >3.3V
OR 0 – >5V
1kHz PWM
Q1
VN2222LL
1768 TA06
16
LT1768
U
TYPICAL APPLICATIONS
2-Wire Serial interface Intensity Control
V
CC
SCL
V
REF
PROG
LT1768
AGND
V
SDA
OUT
LTC1663
GND
1768 TA08
Pushbutton Intensity Control
R1
50k
S1
S2
CLK1 SHDN
V
REF
PROG
LT1768
AGND
V
CC
CLK2
LTC1426
AGND
V
REF
R1
49.9k
PWM2 PWM1
C1
10µF
1768 TA07
17
LT1768
U
TYPICAL APPLICATIONS
18
LT1768
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT1768
U
TYPICAL APPLICATION
4 Watt Single Lamp CCFL Supply
C9
33pF
X1
LAMP
T1
CTX110607
V
= 9V TO 24V
IN
C1
33µF
C7
0.33µF
1
16
PGND
DI02
GATE
15
14
13
2
3
V
IN
R7
499Ω
5V
V
DI01
REF
Q1A
ZDT1048
Q1B
ZDT1048
C5
0.1µF
4
SENSE
FAULT
SHDN
FAULT
LT1768
12
11
5
6
R5
124k
V
C
SHUTDOWN
C2
L1
33µH
0.047µF
D2
AGND
R
MIN
R4
MBRS130LT3
7
8
10 31.6k
C
R
MAX
T
C3
0.22µF
Q2
Si3456DV
9
R2
39.2k
PROG
PWM
PROG
0V TO 5V OR
1kHz PWM
R1
49.9k
R2
100Ω
R3
61.9k
R6
0.05Ω
C8
1000pF
C4
10µF
C6
1µF
1768 TA09
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1170
Current Mode Switching Regulator
5.0A, 100kHz
LT1182/LT1183
CCFL/LCD Contrast Switching Regulators
3V ≤ V ≤ 30V, CCFL Switch: 1.25A, LCD Switch: 625mA,
Open Lamp Protection, Positive or Negative Contrast
IN
LT1184
LT1186
LT1372
LT1373
LT1786F
CCFL Current Mode Switching Regulator
CCFL Current Mode Switching Regulator
500kHz, 1.5A Switching Regulator
250kHz, 1.5A Switching Regulator
1.25A, 200kHz
1.25A, 100kHz, SMBus Interface
Small 4.7µH Inductor, Only 0.5 Square Inch of PCB
1mA I at 250kHz, Regulates Positive or Negative Outputs
Q
SMBus Controlled CCFL Switching Regulator
Precision 100µA Full Scale Current DAC
1768f LT/TP 0901 2K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2000
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