LTC1152CS8#TRPBF [Linear]
LTC1152 - Rail-to-Rail Input Rail-to-Rail Output Zero-Drift Op Amp; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;型号: | LTC1152CS8#TRPBF |
厂家: | Linear |
描述: | LTC1152 - Rail-to-Rail Input Rail-to-Rail Output Zero-Drift Op Amp; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 运算放大器 放大器电路 光电二极管 |
文件: | 总8页 (文件大小:242K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1152
Rail-to-Rail Input
Rail-to-Rail Output
Zero-Drift Op Amp
U
DESCRIPTIO
EATURE
S
F
TheLTC®1152isahighperformance, lowpowerzero-drift
op amp featuring an input stage that common modes to
both power supply rails and an output stage that provides
rail-to-rail swing, even into heavy loads. The wide input
common-mode range is achieved with a high frequency
on-board charge pump. This technique eliminates the
crossover distortion and limited CMRR imposed by com-
peting technologies. The LTC1152 is a C-LoadTM of amp,
enabling it to drive any capacitive load.
■
■
■
■
■
■
■
■
■
■
■
Input Common-Mode Range Includes Both Rails
Output Swings Rail to Rail
Output Will Drive 1kΩ Load
No External Components Required
Input Offset Voltage: 10µV Max
Input Offset Drift: 100nV/°C Max
Minimum CMRR: 115dB
Supply Current: 3.0mA Max
Shutdown Pin Drops Supply Current to 5µA Max
Output Configurable to Drive Any Capacitive Load
Operates from 2.7V to 14V Total Supply Voltage
The LTC1152 shares the excellent DC performance specs
of LTC’s other zero-drift amplifiers. Typical offset voltage
is 1µV and typical offset drift is 10nV/°C. CMRR and PSRR
are 130dB and 120dB and open-loop gain is 130dB. Input
noise voltage is 2µVP-P from 0.1Hz to 10Hz. Gain-band-
width product is 0.7MHz and slew rate is 0.5V/µs, all with
supply current of 3.0mA max over temperature. The
LTC1152 also includes a shutdown feature which drops
supply current to 1µA and puts the output stage in a high
impedance state.
O U
PPLICATI
S
A
■
■
■
■
■
■
Rail-to-Rail Amplifiers and Buffers
High Resolution Data Acquisition Systems
Supply Current Sensing in Either Rail
Low Supply Voltage Transducer Amplifiers
High Accuracy Instrumentation
Single Negative Supply Operation
The LTC1152 is available in 8-pin PDIP and 8-pin SO
packages and uses the standard op amp pinout, allowing
it to be a plug-in replacement for many standard op amps.
, LTC and LT are registered trademarks of Linear Technology Corporation.
C-Load is trademark of Linear Technology Corporation.
U
O
TYPICAL APPLICATI
Input and Output Waveforms
Rail-to-Rail Buffer
5V
5V
VOUT
2V/DIV
7
–
2
3
0V
5V
6
OUT
LTC1152
+
IN
VIN
2V/DIV
4
1152 TA01
0V
1152 TA02
1
LTC1152
W
U
W W W
U
ABSOLUTE AXI U RATI GS
/O
PACKAGE RDER I FOR ATIO
Total Supply Voltage (V+ to V–) ............................. 14V
Input Voltage ............................ V+ + 0.3V to V– – 0.3V
Output Short-Circuit Duration (Pin 6) ............. Indefinite
Operating Temperature Range
ORDER PART
NUMBER
TOP VIEW
SHDN
–IN
1
2
3
4
CP
8
7
6
5
+
LTC1152CN8
LTC1152CS8
LTC1152IN8
LTC1152IS8
V
+IN
OUT
LTC1152C............................................... 0°C to 70°C
LTC1152I.......................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
–
V
COMP
N8 PACKAGE
8-LEAD PDIP
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
1152
1152I
TJMAX = 110°C, θJA = 130°C/ W (N8)
TJMAX = 110°C, θJA = 200°C/ W (S8)
Consult factory for Military grade parts.
VS = 5V, TA = operating temperature range, unless otherwise specified.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
T = 25°C (Note 1)
A
MIN
TYP
±1
MAX
±10
UNITS
µV
V
Input Offset Voltage
Average Input Offset Drift
Long-Term Offset Drift
Input Bias Current
OS
∆V
(Note 1)
●
±10
±50
±10
±100
nV/°C
nV/√Mo
OS
I
I
T = 25°C (Note 2)
A
±100
±1000
pA
pA
B
●
●
Input Offset Current
T = 25°C (Note 2)
A
±20
±200
±500
pA
pA
OS
e
n
Input Noise Voltage (Note 3)
R = 100Ω, 0.1Hz to 10Hz
R = 100Ω, 0.1Hz to 1Hz
S
2
0.5
3
1
µV
µV
S
P-P
P-P
i
Input Noise Current
f = 10Hz
0.6
130
120
fA/√Hz
n
CMRR
PSRR
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
V
CM
= 0V to 5V
●
115
dB
V = 3V to 12V
S
110
105
dB
dB
●
●
A
V
Large-Signal Voltage Gain
R = 10k, V = 0.5V to 4.5V
L OUT
110
130
dB
VOL
Maximum Output Voltage Swing (Note 4)
R = 1k, V = Single 5V
●
●
4.0
±2.0
4.4
2.2
±2.49
V
V
V
OUT
L
S
R = 1k, V = ±2.5V
L
S
R = 100k, V = ±2.5V
L
S
SR
Slew Rate
R = 10k, C = 50pF, V = ±2.5V
0.5
0.7
V/µs
L
L
S
GBW
Gain-Bandwidth Product
Supply Current
R = 10k, C = 50pF, V = ±2.5V
MHz
L
L
S
I
No Load
Shutdown = 0V
●
●
2.2
1
3.0
5
mA
µA
S
I
Output Leakage Current
Shutdown = 0V
●
±10
7.3
2.5
4
±100
nA
V
OSD
V
V
V
Charge Pump Output Voltage
Shutdown Pin Input Low Voltage
Shutdown Pin Input High Voltage
Shutdown Pin Input Current
Internal Charge Pump Frequency
Internal Sampling Frequency
I
= 0
CP
CP
IL
V
V
IH
I
f
f
V
SHDN
= 0V
●
–1
4.7
2.3
–5
µA
MHz
kHz
IN
T = 25°C
A
CP
T = 25°C
A
SMPL
2
LTC1152
ELECTRICAL CHARACTERISTICS VS = 3V, TA = operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
Average Input Offset Drift
Input Bias Current
T = 25°C (Note 1)
±1
±10
µV
OS
A
∆V
(Note 1)
●
●
●
±10
±5
±100
nV/°C
OS
I
T = 25°C (Note 2)
A
±100
±1000
pA
pA
B
I
Input Offset Current
T = 25°C (Note 2)
A
±10
±200
±500
pA
pA
OS
e
n
Input Noise Voltage (Note 3)
R = 100Ω, 0.1Hz to 10Hz
R = 100Ω, 0.1Hz to 1Hz
S
2
0.75
µV
µV
S
P-P
P-P
i
Input Noise Current
f = 10Hz
0.6
130
130
fA/√Hz
dB
n
CMRR
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
V
CM
= 0V to 3V
●
●
●
A
V
R = 10k, V = 0.5V to 2.5V
L OUT
106
2.0
dB
VOL
OUT
Maximum Output Voltage Swing (Note 4)
R = 1k, V = Single 3V
2.5
±1.48
V
V
L
S
R = 100k, V = ±1.5V
L
S
SR
Slew Rate
R = 10k, C = 50pF, V = ±1.5V
0.4
0.5
V/µs
L
L
S
GBW
Gain-Bandwidth Product
Supply Current
R = 10k, C = 50pF, V = ±1.5V
MHz
L
L
S
I
No Load
Shutdown = 0V
●
●
1.8
1
2.5
5
mA
µA
S
I
Output Leakage Current
Shutdown = 0V
●
±10
4.5
1.2
2.3
–1
nA
V
OSD
V
V
V
Charge Pump Output Voltage
Shutdown Pin Input Low Voltage
Shutdown Pin Input High Voltage
Shutdown Pin Input Current
Internal Charge Pump Frequency
Internal Sampling Frequency
I
= 0
CP
CP
IL
V
V
IH
I
f
f
V
SHDN
= 0V
µA
MHz
kHz
IN
T = 25°C
A
4.2
2.1
CP
T = 25°C
A
SMPL
The
●
denotes specifications which apply over the full operating
filter at 0.1Hz. Contact LTC factory for sample tested or 100% tested noise
parts.
temperature range.
Note 1: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels during automated testing.
Note 2: At T ≤ 0°C these parameters are guaranteed by design and not
tested.
Note 4: All output swing measurements are taken with the load resistor
connected from output to ground. For single supply tests, only the positive
swing is specified (negative swing will be 0V due to the pull-down effect of
the load resistor). For dual supply operation, both positive and negative
swing are specified.
Note 3: 0.1Hz to 10Hz noise is specified DC coupled in a 10-sec window;
0.1Hz to 1Hz noise is specified in a 100-sec window with an RC highpass
3
LTC1152
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Common-Mode Range vs
Supply Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
3.0
2.5
2.0
1.5
1.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
8
6
T
= 25°C
V = 5V
S
A
4
2
0
–2
–4
–6
–8
6
1
2
3
4
5
7
0
2
6
8
10 12
14
–50 –25
0
25
50
75
100
4
POWER SUPPLY VOLTAGE (±V)
TOTAL SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
1152 G01
1152 G02
1152 G03
Output Short-Circuit Current vs
Supply Voltage
Open-Loop Output Resistance vs
Supply Voltage
Output Swing vs Load Resistance
40
30
20
10
0
300
250
200
150
100
6
5
4
3
2
1
0
T
= 25°C
A
T
= 25°C
T
A
= 25°C
SOURCE
A
V
S
= SINGLE 5V
SINK
V
S
= SINGLE 3V
V
= ±2.5V
= ±1.5V
S
V
S
2
4
6
8
10
12
14
2
4
6
8
10
12
14
0.2 0.5
1
2
5
10 20 50 100 200
TOTAL SUPPLY VOLTAGE (V)
TOTAL SUPPLY VOLTAGE (V)
LOAD RESISTANCE (kΩ)
1152 G05
1152 G06
1152 G04
Charge Pump Voltage vs
Supply Voltage
Charge Pump Voltage vs
Load Current
Input Bias Current vs Temperature
1000
100
10
3
2
1
0
3
2
1
0
V
S
= 5V
T
A
= 25°C
T
= 25°C
= 5V
A
S
V
120 140
0
20
40 60 80 100
160
–50 –25
0
25
50
75
100
2
6
8
10
12
14
4
LOAD CURRENT (µA)
TEMPERATURE (°C)
TOTAL SUPPLY VOLTAGE (V)
1152 G09
1152 G08
1152 G07
4
LTC1152
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Gain and Phase Shift vs
Frequency
Common-Mode Rejection Ratio vs
Frequency
Power Supply Rejection Ratio vs
Frequency
110
100
90
80
70
60
50
40
30
20
10
0
70
60
120
100
80
60
40
20
0
T
A
= 25°C
T
= 25°C
T
= 25°C
A
S
A
V
= ±2.5V
V
= ±2.5V
S
PHASE
GAIN
PIN 5 = NC
50
40
80
30
–PSRR
+PSRR
70
20
60
10
50
0
40
–10
–20
30
–10
0.1
1
10
100
1000
10
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
FREQUENCY (kHz)
FREQUENCY (Hz)
FREQUENCY (Hz)
1152 G14
1152 G13
1152 G10
Gain and Phase Shift vs
Frequency
0.1Hz to 10Hz Input Noise
Voltage Noise vs Frequency
2
1
70
60
150
125
100
75
120
100
80
T
V
C
= 25°C
A
S
= ±2.5V
PHASE
= 1000pF
COMP
50
40
60
30
40
0
20
20
10
0
50
GAIN
–1
–2
0
–20
–40
–60
25
–10
–20
0
1
10
100
1k
10k
0
2
4
6
8
10
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
TIME (SEC)
1152 G15
1152 G11
1152 G18
Gain and Phase Shift vs
Frequency
Small-Signal Transient Response
Large-Signal Transient Response
60
50
180
160
140
120
100
80
T
V
C
= 25°C
A
S
= ±2.5V
= 0.1µF
COMP
40
30
PHASE
20
10
0
60
–10
–20
–30
–40
40
GAIN
20
VS = ±2.5V
AV = 1
VS = ±2.5V
0
1152 G16
A
V = 1
1152 G17
–20
0.01
0.1
1
10
FREQUENCY (kHz)
1152 G12
5
LTC1152
PPLICATI
O U
W
U
A
S I FOR ATIO
V
CC
Rail-to-Rail Operation
(PIN 7)
INTERNAL
CHARGE
PUMP
V
+ 2V
CC
The LTC1152 is a rail-to-rail input common-mode range,
rail-to-rail output swing op amp. Most CMOS op amps,
including the entire LTC zero-drift amplifier line, and even
a few bipolar op amps, can and do, claim rail-to-rail output
swing. One obvious use for such a device is to provide a
unity-gainbufferfor0Vto5Vsignalsrunningfromasingle
5V power supply. This is not possible with the vast
majority of so-called “rail-to-rail” op amps; although the
output can swing to both rails, the negative input (which
isconnectedtotheoutput)willexceedthecommon-mode
input range of the device at some point (generally about
1.5V below the positive supply), opening the feedback
loop and causing unpredictable and sometimes bizarre
behavior.
CP (PIN 8)
0.1µF*
–
–IN
OUTPUT
INPUT
OUT
RAIL TO RAIL
+
+IN
*OPTIONAL EXTERNAL
CAPACITOR TO REDUCE
1152 F01
CHARGE PUMP FEEDTHROUGH
Figure 1. LTC1152 Internal Block Diagram
time. This diode can stand short-term peak currents of
about 50mA, allowing it to quickly charge external capaci-
tance to ground or V–. Large capacitors (>1µF) should not
be connected between pin 8 and ground or V– to prevent
excessive diode current from flowing at start-up. The
LTC1152 can withstand continuous short circuits be-
tween pin 8 and V+; however, short circuiting pin 8 to
ground or V– will cause large amounts of current to flow
through the diode, destroying the LTC1152. Don’t do it.
The LTC1152 is an exception to this rule. It features both
rail-to-rail output swing and rail-to-rail input common-
mode range (CMR); the input CMR actually extends be-
yond either rail by about 0.3V. This allows unity-gain
buffer circuits to operate with any input signal within the
powersupplyrails;inputsignalswingislimitedonlybythe
output stage swing into the load. Additionally, signals
occurring at either rail (power supply current sensing, for
example) can be amplified without any special circuitry.
Output Drive
The LTC1152 features an enhanced output stage that can
sink and source 10mA with a single 5V supply while
maintaining rail-to-rail output swing under most loading
conditions. The output stage can be modeled as a perfect
rail-to-rail voltage source with a resistor in series with it;
this open-loop output resistance limits the output swing
by creating a resistor divider with the output load.
Internal Charge Pump
The LTC1152 achieves its rail-to-rail input CMR by using
a charge pump to generate an internal voltage approxi-
mately 2V higher than V+. The input stages of the op amp
are run from this higher voltage, making signals at V+
appeartobe2Vbelowthefrontend’spowersupply(Figure
1). The charge pump is contained entirely within the
LTC1152; no external components are required.
The output resistance drops as total power supply voltage
increases, as shown in the typical performance curves. It
is typically 140Ω with a single 5V supply, allowing a 4.4V
output swing into a 1k resistor with a single 5V supply.
About 100µVP-P of residual charge pump switching noise
will be present on the output of the LTC1152. This
feedthrough is at 4.7MHz, higher than the gain-bandwidth
of the LTC1152, and will generally not cause any prob-
lems. Very sensitive applications can reduce this
feedthrough by connecting a capacitor from the CP pin
(pin 8) to V+(pin 7); a 0.1µF capacitor will reduce charge
pump feedthrough to negligible levels. The LTC1152 in-
cludes an internal diode from pin 8 to pin 7 to prevent
external parasitic capacitance from lengthening start-up
V
CC
(PIN 7)
R
LTC1152
OUTPUT
DRIVER
OUT
OUT (PIN 6)
≈140Ω AT 5V SUPPLY
R
LOAD
1152 F02
Figure 2. LTC1152 Output Resistance Model
6
LTC1152
O U
W
U
PPLICATI
S I FOR ATIO
A
Compensation/Bandwidth Limiting
is running from ±5V or ±3V supplies. The internal 1µA
pull-up also allows pin 1 to interface with open-collector/
open-drain devices or discrete transistors.
The LTC1152 is unity-gain stable with capacitive loads up
to 1000pF. Larger capacitive loads can be driven by
externally compensating the LTC1152. Adding 1000pF
between COMP (pin 5) and OUT (pin 6) allows capacitive
loadingofupto1µF;0.1µFbetweenpins5and6allowsthe
LTC1152 to drive infinite capacitive load (Figure 3).
The high impedance output in shutdown allows several
LTC1152s to be connected together as a MUX, with their
outputs tied in parallel and the active channel selected by
using the shutdown pins. Deselected (shutdown) chan-
nels will go to high impedance at the outputs, preventing
them from fighting with the active channel. This works
best when the individual LTC1152s are connected in
noninverting feedback configurations to prevent the feed-
back resistors from passing signals through deselected
channels. See the Typical Applications section for a circuit
example.
8
7
6
5
1
2
3
4
+
V
LTC1152
1N4148*
OUTPUT
1N4148*
–
V
C
C
*OPTIONAL DIODES TO PREVENT
1152 F03
LATCH-UP WITH C > 1µF
Zero-Drift Operation
C
The LTC1152 is a zero-drift op amp. Like other LTC zero-
drift op amps, it features virtually error-free DC perfor-
mance, verylittledriftovertimeandtemperature, andvery
low noise at low frequencies. The internal nulling clock
runs at about 2.3kHz (the charge pump frequency of
4.7MHz divided by 2048) and is synchronized to the
internal charge pump to prevent beat frequencies from
appearing at the output. The self-nulling circuit constantly
corrects the input offset voltage, keeping it typically below
±1µV over the entire input common-mode range. This has
the added benefit of providing exceptional CMRR and
PSRR at low frequencies––far better than competing rail-
to-rail op amps.
Figure 3. Output Compensation Connection
Large compensation capacitors can also be used to limit
the bandwidth of the LTC1152. With 0.1µF from pin 5 to
pin 6, the LTC1152’s gain-bandwidth product is reduced
from 700kHz to around 200Hz. Note that compensation
capacitors greater than 1µF can cause latch-up under
severe output fault conditions; this can be prevented by
clampingpin5toeachsupplywithstandardsignaldiodes,
as shown in Figure 3.
Shutdown
The LTC1152 includes a shutdown pin (pin 1). When this
pin is at V+, the LTC1152 operates normally. An internal
1µApull-upkeepsthepinhighifitisleftfloating. Whenpin
1 is pulled low, the part enters shutdown mode; supply
current drops to 1µA, all internal clocking stops and the
output enters a high impedance state. During shutdown
the voltage at the CP pin (pin 8) will drop to 0.5V belowV+.
When pin 1 is brought high again, about 10µs will elapse
before the charge pump regains full voltage. During this
timetheLTC1152willoperatenormally,buttheinputCMR
may not include V+. Pin 1 is compatible with CMOS logic
running from the same supply as the LTC1152. Addition-
ally, the input trip levels allow ground referenced CMOS
logicsignalstointerfacedirectlytopin1whentheLTC1152
Because it uses a sampling front end, the LTC1152 will
exhibit aliasing behavior and clock noise at frequencies
neartheinternal2.3kHzsamplingfrequency.TheLTC1152
includesaninternalanti-aliasingcircuittokeeptheseerror
terms to a minimum. As a rule, alias frequencies will be
down by (80dB – ACLG) in most standard amplifier con-
figurations, where ACLG is the closed-loop gain of the
LTC1152 circuit. Clock noise is also dependent on closed-
loopgain;itwillgenerallyconsistofspikesofabout100µV
in amplitude, input referred. In general, these error terms
are too small to affect most applications. For a more
detailed explanation of zero-drift amplifier behavior, see
the LTC1051/LTC1053 data sheet.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
7
LTC1152
PPLICATI
O U
W
U
A
S I FOR ATIO
High Precision Three-Input MUX
High Gain Amplifier with ±1.5V Supplies
1.5V
1.1k
10k
10Ω
100k
SEL1
2
3
1
2
3
7
–
–
6
6
LTC1152
LTC1152
OUT
IN 1
= 10
A
V
= 10k
= 80dB
+
IN
+
0.1µF
A
V
4
10Ω
10k
OUT
1152 TA03
–1.5V
SEL2
2
1
–
High-Side Power Supply Current Sensing
6
LTC1152
CHANGE SENSE RESISTOR
TO CHANGE SENSITIVITY
3
IN 2
+
A
V
= 1000
TO
0.01Ω
100Ω
5V
MEASURED
CIRCUIT
0.1µF
SEL3
3
2
1
+
–
10k
10k
6
6
LTC1152
LTC1152
2
IN 3
= 1
3
–
+
A
2
3
V
10k
–
+
OUT
1V/100mA
LOAD CURRENT IN
MEASURED CIRCUIT
6
100k
LT1097
SELECT INPUTS ARE CMOS LOGIC COMPATIBLE.
SELECT ONLY ONE CHANNEL AT ONCE!
1152 TA04
0.1µF
10k
GND
GND
1152 TA05
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead Plastic DIP
S8 Package
8-Lead Plastic SOIC
0.189 – 0.197*
(4.801 – 5.004)
0.400*
(10.160)
MAX
7
5
8
6
8
7
6
5
4
*THESE DIMENSIONS DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTURSIONS SHALL
NOT EXCEED 0.010 INCH (0.254mm).
0.255 ± 0.015*
(6.477 ± 0.381)
0.150 – 0.157*
(3.810 – 3.988)
*THESE DIMENSIONS DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL
NOT EXCEED 0.006 INCH (0.15mm).
0.228 – 0.244
(5.791 – 6.197)
1
2
3
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
1
2
3
4
0.045 – 0.065
(1.143 – 1.651)
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
0.125
(3.175)
MIN
0.015
(0.380)
MIN
+0.025
–0.015
SO8 0294
0.045 ± 0.015
(1.143 ± 0.381)
0.325
+0.635
8.255
(
)
–0.381
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
N8 0694
LT/GP 0195 10K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
8
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1995
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