AN10E40_技术文档

AN10E40

Preliminary Information

Field Programmable

Analog Array

The AN10E40 brings to analog what FPGAs brought to digital; extremely rapid production and prototype circuit

realization with field re-programmability. The AN10E40 consists of a 4 x 5 matrix of fully configurable switched

capacitor cells, enmeshed in a fabric of programmable interconnect resources. These programmable features are

directed by an on-chip SRAM configuration memory. The SRAM configuration memory is initialized on power up

via an on off chip serial PROM or through the AN10E40’s standard microprocessor peripheral interface.

A configuration memory image is easily constructed using the companion AnadigmDesigner software which

includes an extensive library of adjustable, proven, pre-built functions. The configurable analog blocks are often

consumed one at a time, though some of the more complex library functions may consume two or more blocks.

Specialized IO cells surround the core to bring your analog signals in and out of the array.

The AN10E40 coupled with the intuitive AnadigmDesigner software gives both digital and analog designers a

competitive advantage in designing analog circuits that can’t really be compared to any other design system in

existence. Quickly constructed, accurate, drift free, temperature compensated and programmable analog circuits

are now yours. Imagine the power of programmable with the versatility of analog.

Benefits

•

Extremely Rapid Analog Design – Minutes not weeks to re-spin a new design idea

In Circuit Programmable – Behavior can be changed as fast as 125 microseconds

Re-Configurable Using Conventional Logic, Serial PROMs or Microcontrollers

Extremely Stable over Voltage and Temperature

No Component Aging

•

Flexible Internal Clock and Routing Resources

No More Trimming Components

Reliable and Repeatable Performance

No More Tuning Components

Config. Logic

Configuration Data Shift Register

CAB

I

O

Z

I

O

Z

I

O

Z

I

O

Z

I

O

Z

Vref

X

Y

X

Y

X

Y

X

Y

X

Y

Anadigm reserves the right to make any changes without further notice to any

products herein. Anadigm makes no warranty, representation or guarantee

regarding the suitability of its products for any particular purpose, nor does

Anadigm assume any liability arising out of the application or use of any product or

circuit, and specifically disclaims any and all liability, including with limitation

consequential or incidental damages. “Typical” parameters can and do vary in

different applications. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. Anadigm

does not convey any license under its patent rights nor the rights of others.

Anadigm products are not designed, intended, or authorized for use as

components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which

the failure of the Anadigm product could create a situation where personal injury or

death may occur. Should buyer purchase or use Anadigm product for any such

unintended or unauthorized application, buyer shall indemnify and hold Anadigm

and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated

with such unintended or unauthorized use, even if such claim alleges that Anadigm

was negligent regarding the design or manufacture of the part.

AN10E40 Data Manual

i

Table of Contents

Features of AN10E40................................................................................................................................................ 1

Available IPmodule Functions................................................................................................................................... 1

How It Works............................................................................................................................................................. 1

AN10E40 Architecture............................................................................................................................................... 2

The Configurable Analog Block ................................................................................................................................ 3

A Quick Review of Switched Capacitor Circuits.................................................................................................... 3

CAB Details ........................................................................................................................................................... 4

Routing Resources.................................................................................................................................................... 4

Clock Generation ...................................................................................................................................................... 4

Voltage Reference .................................................................................................................................................... 5

Voltage Mid-Rail Generator....................................................................................................................................... 5

Analog Input Output Cell........................................................................................................................................... 6

Sallen Key Filtering................................................................................................................................................ 6

2^ndOrder Sallen-Key Filter for Output Smoothing................................................................................................. 7

4^thOrder Sallen-Key Filter for Output Smoothing ................................................................................................. 7

2^ndOrder Sallen-Key Filter for Input Anti-Aliasing................................................................................................. 7

4^thOrder Sallen-Key Filter for Input Anti-Aliasing ................................................................................................. 8

Configuration Engine................................................................................................................................................. 9

Mode 0 – Micro Mode.......................................................................................................................................... 10

Micro Mode Configuration Sequence .............................................................................................................. 13

Micro Mode Maximum Data Transfer Rate...................................................................................................... 13

Mode 1 – Boot from ROM (BFR Mode)............................................................................................................... 14

BFR Timing.......................................................................................................................................................... 15

Configuration Clock ............................................................................................................................................. 16

Reset Sequences.................................................................................................................................................... 17

Analog Power On Reset (APOR) & Power On Reset (POR).............................................................................. 17

Internal Reset Activity.......................................................................................................................................... 17

External Reset Assertion..................................................................................................................................... 17

Mechanical.............................................................................................................................................................. 17

Package Details................................................................................................................................................... 17

Pin Out Description.............................................................................................................................................. 18

Package Pin Electrical Characterization................................................................................................................. 21

Powers, Grounds and Bypassing............................................................................................................................ 21

Recommended Configuration for Power & Ground............................................................................................. 21

AVDD and AVSS................................................................................................................................................. 21

SVDD and SVSS................................................................................................................................................. 21

BVDD and BVSS................................................................................................................................................. 22

ESD_VDD and ESD_VSS................................................................................................................................... 22

CFG_VDD and CFG_VSS .................................................................................................................................. 22

OPAMVMR and CEXT ........................................................................................................................................ 22

The AN10E40 in Split Supply Systems............................................................................................................... 22

Electrical Parameters.............................................................................................................................................. 22

Absolute Maximum Ratings................................................................................................................................. 23

Recommended Operating Conditions ................................................................................................................. 23

Digital IO.............................................................................................................................................................. 23

Voltage Mid Rail .................................................................................................................................................. 23

Vref ...................................................................................................................................................................... 23

The Analog I/O Cell ............................................................................................................................................. 24

The Analog I/O Cell Configured as a Sallen-Key Filter....................................................................................... 25

A Programmable Inverting Gain Stage................................................................................................................ 26

A Programmable Low Pass Filter........................................................................................................................ 27

Sine Wave Oscillator ........................................................................................................................................... 28

Electrostatic Discharge Characterization................................................................................................................ 28

A Quick Review of ESD Basics........................................................................................................................... 28

Catastrophic Failure......................................................................................................................................... 28

Latent Defect.................................................................................................................................................... 28

ii

Basic ESD Events--What Causes Electronic Devices to Fail? ........................................................................28

Discharge to the Device...................................................................................................................................29

Discharge from the Device...............................................................................................................................29

Field Induced Discharges ................................................................................................................................29

AN10E40 ESD Classifications.............................................................................................................................29

Standard ESD Classifications..........................................................................................................................30

AN10E40 Data Manual

1

Features of AN10E40

•

20 Programmable Analog Cells

13 Analog IO Cells

•

Easy Power-On-Reset Self Boot Using Serial PROM

Microprocessor Boot Option

Intuitive Design Software

2 Spare Op-Amps

8 Bit Programmable Internal Vref Source

4 Programmable Internal Clock Sources

Drift Free Designs

Rapidly Configurable

Available IPmodule Functions

•

Gain Stages

•

Non/Inverting Comparators

1 and 2 Input Comparators

DC Reference Voltage Sources

Limiters

Summing Amplifiers

Sample and Hold

Track and Hold

High, Low and Band Pass/Stop Filters

High Q, Low Q Filters

Cosine Filters

Schmitt Triggers

Non/Inverting Integrators

Differentiators

Full and Half Non/Inverting Rectifiers

New IP Modules Continuously Available

How It Works

On power up, the AN10E40’s reset circuitry initializes the configuration engine. The configuration engine takes over

and first examines the state of the Mode port. The pin settings of the Mode port determine which of the boot

methods should be exercised. One popular option is to boot from an off chip Serial PROM. The configuration

engine takes care of taking data out of the Serial PROM and loading it into on-chip configuration SRAM. The whole

boot process takes just a few milliseconds. Once the configuration SRAM has been loaded, the analog circuitry is

automatically enabled and the configuration engine idled. The chip now performs the analog functions according to

the configuration bit stream just loaded.

Creating a configuration bit stream is no more complicated than using the device itself. The AnadigmDesigner

design tool provides the user an intuitive drag and drop GUI in which you simply select several of the IPmodule

functions from the extensive library, drop them onto a graphical representation of the chip, fill in some parametric

information about the IPmodule, wire up the internal and I/O connections, and hit a button to generate the bit

stream (or download it directly to the device on your bench).

The device internals are more complicated than the easy to use device may lead you to believe. The AN10E40

array is based on programmable switched capacitor op-amp cells with very flexible internal and external connection

and clocking resources. The AnadigmDesigner and the associated IPmodule library shields the user from these

complexities.

Switched capacitor circuits are remarkably stable over voltage, temperature and device aging. Using the AN10E40

for your analog circuit realization allows you to rest assured knowing that once a circuit has been designed, it will

continue perform as expected. Say goodbye to trim pots.

Another advantage of this technology is the tremendous decrease in design time. Along with the elimination of trim

pots, you’ll also be able to clear your bench of all the normal discrete R and C components. “Prototyping” is now a

drag and drop computer exercise. A simple push of a button and your design is downloaded into the AN10E40

nearly instantaneously.

The kicker to all of this is that it is infinitely re-programmable. If a single set of analog functions is not sufficient for

your system, then you can load new configuration files into the AN10E40 with only a very small interruption to the

analog signal stream. Consider how filter parameters can be changed to adapt to varying input signal conditions.

Consider how a single physical circuit can be used in all of your different system designs. Consider all the

advantages that programmable analog will bring to your designs.

2

AN10E40 Architecture

The AN10E40 is comprised of a 4x5 array of Configurable Analog Blocks (CABs), enmeshed in clocking, switching,

local and global routing resources. Nearly every element of the AN10E40 is programmable giving the user

tremendous flexibility in the sorts of processing circuits that can be realized.

Config. Logic

Configuration Data Shift Register

CAB

I

O

Z

I

O

Z

I

O

Z

I

O

Z

I

O

Z

Vref

X

Y

X

Y

X

Y

X

Y

X

Y

Figure 1. Block Level View of the AN10E40 array

The Configuration Logic and Shift Register work together whenever chip configuration is in process. The array of

CABs is surrounded on three sides by programmable analog input/output cells, 13 in all, with two spare

uncommitted op-amps. The lower region of the chip also contains a programmable reference voltage generator.

AN10E40 Data Manual

3

The Configurable Analog Block

The basic building block of the AN10E40 is the Configurable Analog Block. Each CAB is an op-amp surrounded by

capacitor banks, local routing resources, local switching and clocking resources, and global connection points. This

collection of hardware enables the CAB to perform many of the functions that could be achieved using an op-amp

and conventional passive components. All analog processing is accomplished with this switched capacitor circuit.

A Quick Review of Switched Capacitor Circuits

There are many excellent texts available which dive deeply into the details of sampled systems and MOS switch

capacitor circuit theory. The math gets very complex and may have kept you away from switched capacitor circuits

in the past. The good news is that the AnadigmDesigner software for Anadigm devices shields you from all the

complexities of using switched capacitor designs. Still though, it can be useful to review briefly how switched

capacitor circuits operate to eliminate the fear of the unknown.

Consider the following two circuits.

1

2

1

2

R

+

V1

-

+

V2

-

+

V1

-

+

V2

-

C

Conventional Circuit

Switched Capacitor Circuit

Figure 2. Switched Capacitor vs. Conventional Circuit

In the Figure 2, two circuits are shown that can both do the same job. The conventional circuit moves current

around the loop through the resistor. The amount of current of course is a function of the difference between V1

and V2 and the value of R.

The switched capacitor version of the circuit does the same job, but in a different way. With the switch in position 1,

charge moves from the V1 source to the capacitor C, when the switch is moved over to position 2, charge is then

moved from C to V2. As the switch is thrown back and forth, recognize that charge is moving over time, in other

words - current. The faster you throw the switch (and/or the bigger the capacitor is) the more current flows. Unlike

the conventional circuit, simply reprogramming the switching clock rate or the size of the capacitor allows you to

adjust the “resistance” between nodes 1 and 2.

Of course, since this is a sampled system you have to keep in mind the frequency of the signal that is being

processed by the circuit and the frequency at which it is being sampled (or switched). For signals with frequency

content constrained significantly below the sampling frequency the switched capacitor circuit works just like the

conventional circuit. In all cases, the sampling rate should be at least twice as high as the highest frequency of the

signal being processed.

4

CAB Details

The SRAM block which controls routing connections and CAB behavior is loaded during configuration time.

Configuration typically occurs at power up as an automatic process but can of course be re-initiated at any time.

The ability to re-configure the part at any time gives the user incredible flexibility in system design.

Programmable capacitor banks and local switching in both the input paths to the op-amp and a programmable

capacitor bank in the op-amp’s feedback path provide all the resources required to realize a very large number of

analog processing circuits.

Global Outputs

Local Outputs

OpAmp

Global In

Configuration Memory (SRAM)

Figure 3. Block Level View of the basic CAB

Connection between other CAB’s on the device and to the outside world are accomplished using the Local Inputs,

Local Output, and Global routing resources.

Routing Resources

The most expedient way to gain understanding of the routing resources available on the AN10E40 is to use the

associated AnadigmDesigner design software. The routing resources and your connections to them are

represented in an intuitively obvious fashion.

Local routing resources are only shown (as fly lines or rubber band lines) in the design software screen once they

are used. A CAB output may be connected to an input in any of its 8 adjacent neighbors, and additionally to the

CAB in the same row and to the right two locations.

Global routing resources allow you to move signals to disparate locations on the die. There are a total of 10

horizontal global routes and 12 vertical global routes within the array. A CAB’s output can be connected to either of

the two adjacent right or two adjacent down global routes. A CAB’s input can be driven by one of the two adjacent

right or adjacent down global routes (which one of these two routes alternates with location in the array).

Connections to the chip’s programmable reference voltage generator are only available using Global routing

resources.

Clock Generation

Recall from the discussion on switched capacitor basics that the behavior of our simple circuit was influenced by

both the value of the capacitor as well as the frequency of the clock. So it is with IPmodules placed into the CABs of

the AN10E40 array. IPmodule input clocks are all derived from the master CLOCK input pin. The maximum rated

frequency of this input is currently specified to be 20 MHz. The master clock is split into 4 pairs of non-overlapping

clocks and bussed to each of the CABs. CLOCK[3:0] are derived from the dividing the master CLOCK input down

by a factor of 1 or from 2 to 62 (in increments of two). The maximum allowable clock frequency into an IPmodule is

AN10E40 Data Manual

5

specified to be 1 MHz. You are free to drive CLOCK into the array at up to 20 MHz, then program and use

CLOCK[3:0] individually as your circuits might require.

The AN10E40 is designed such that all IPmodules along an analog signal path should use the same clock. While it

is possible to mix clocks along a signal path, it should not be done without full understanding of sampled data

systems, the effects of oversampling, undersampling and aliasing and careful consideration of possible unintended

consequences. The edges of divided clocks are synchronized only with the master clock edges, and therefor the

phase relationship of divided clocks is not guaranteed. For this reason, users are cautioned not to utilize two equal

frequency divided clocks with the exception of clocks that have a divisor of one are therefor equal to the master

clock.

Please note, the performance estimates for a placed IPmodule are based upon the known clock assignment and

divider ratios at the time of IPmodule placement. Any change in the top level chip clock settings may of course

affect your circuit behavior.

This section described the CLOCK input pin, not to be confused with the configuration clock pin CFG_CLK,

discussed below in the section Configuration Clock.

Voltage Reference

The AN10E40 provides a convenient programmable on-chip voltage reference. When your circuit requires a

comparator function against a known value, this voltage reference is easily programmed and enabled.

The value programmed into the Voltage Reference is always specified relative to signal ground. On the AN10E40,

signal ground is at VMR (see Voltage Mid-Rail Generator below).

Voltage Mid-Rail Generator

All analog signals within the array are referenced to Voltage Mid-Rail (VMR), typically 2.5 V with respect to AVSS.

The VMR signal is generated on chip, filtered with an external capacitor then routed back into the array for use by

the CABs.

Cext

10nF

The recommended connections are:

Bandgap

Reference

Generator

•

10 nF between CEXT and a quiet ground node

VMR unloaded

VMR

50

100 nF between OPAMPVMR and a quiet ground node

OpAmpVMR

100nF

To CABs

Figure 4. Filtering OpAmpVMR

The RC network provides a simple but effective low pass filter for the on-chip OpAmpVMR signal. It is not

recommended that OpAmpVMR be loaded externally with anything other than a low leakage current 100 nF

capacitor.

VMR is provided as a convenience outlet for the VMR signal. The system is designed only to drive the RC filter

network. If your system requires use of VMR, it is recommended that you first buffer it with a high impedance

amplifier. Conversely, should your system design establish a requirement for generating signal ground (VMR)

6

externally, the design software allows you to disable the on-chip VMR generator and instead drive the VMR pin

from off chip.

The Bandgap Reference Generator provides a nominal 2.5 V reference signal. Cext is a filtering cap used to quiet

any possible switching noise from getting coupled into this important reference voltage.

Analog Input Output Cell

The AN10E40 has a flexible analog IO cell that allows you to connect directly into the core’s internal circuitry, buffer

input and output signals to/from the core, and using very few external components, construct a Sallen-Key filter.

I

O

X

Y

Z

Figure 5. Analog Input Output Cell

The “I” and “O” pad designations are Input and Output; these names are relative to the IO Cell itself.

The most common configuration for use as an input is to leave the switch open and power up the buffer. Drive Y

with an external signal and connect O to an IPmodule's input. X and Z should be left unloaded.

The most common configuration for use as an output is to close the switch and power up the buffer. Drive I with an

IPmodule's output and connect an external load to Z. X and Y should be left unloaded.

Under certain circumstances it may be advantageous to leave the switch open and the buffer powered down. For

example, a single Input Output Cell can be used to simultaneously bring a pair of signals in and out of the array. I to

X is an output path from the array, and Z to O is an input path into the array. In doing so however, the external

signal driving Z will be loaded with the input impedance of the IPmodule connected to. This impedance is a function

of the IPmodule's clock speed and input capacitor size. Likewise, the user must stay alert to the external loading of

X which can affect the driving IPmodule's performance.

Another situation which might warrant such direct connections into the array is when your design's input stage will

not tolerate the non-zero offset voltage associated with an input buffer.

Sallen Key Filtering

The flexibility of the IO cell is best appreciated when considering the construction of Sallen-Key filters. Since the

array is based on switched capacitor circuits, your output signal may have unwanted switching noise present. Also,

since this is a sampled data system, some care should be taken to band limit input signals to avoid aliasing

artifacts. Sallen-Key filters are useful for filtering such frequency components out. The AN10E40 IO cells are

uniquely designed to facilitate easy construction of such filters.

The detailed derivation of the math and complete explanation of the theory of operation of these filters would be

better served by another dedicated document, however we are pleased to present the general circuit diagrams for

such filters and will instead refer you to Application Note 010. Also, there are quite a number of excellent analog

filter design tools currently on the market. The major advantage in using such a software package is that most of

them will implement the filter using standard value components, whereas the traditional cook book equation

approach often results in unrealistic component values. One good example of a filter design tool is Filter Wiz LE.

This effective and highly affordable PC based design tool is available on line from www.schematica.com.

For all such filters, as for all external ceramic capacitors in the signal path, only NPO or COG ceramic materials are

recommended (for better voltage coefficient). X7R or similar material can add noticeable distortion to the signal.

AN10E40 Data Manual

7

2^ndOrder Sallen-Key Filter for Output Smoothing

20

0

2^ndOrder

I

O

Z

-40dB/Decade

dB

X

Y

-20

-40

-60

Frequency [Hz]

Figure 6. A 2^ndOrder Sallen-Key Filter for Output Smoothing

4^thOrder Sallen-Key Filter for Output Smoothing

I

O

Z

I

O

Z

20

0

4^thOrder

-80dB/Decade

dB

X

Y

X

Y

-20

-40

-60

Frequency [Hz]

Figure 7. A 4^thOrder Sallen-Key Filter for Output Smoothing

Here, the first stage of filtering is handled by an otherwise unused IO cell. It can instead be one of the two spare op-

amps the AN10E40 provides. (See the Pin Out Description section for a description of pins 24, 25, 74 and 75.)

2^ndOrder Sallen-Key Filter for Input Anti-Aliasing

20

2^ndOrder

I

O

Z

-40dB/Decade

dB

0

-20

-40

-60

X

Y

Frequency [Hz]

Figure 8. A 2^ndOrder Sallen-Key Filter for Input Anti-Aliasing

8

4^thOrder Sallen-Key Filter for Input Anti-Aliasing

I

O

Z

I

O

Z

20

0

4^thOrder

-80dB/Decade

dB

X

Y

X

Y

-20

-40

-60

Frequency [Hz]

Figure 9. A 4^thOrder Sallen-Key Filter for Input Anti-Aliasing

AN10E40 Data Manual

9

Configuration Engine

The AN10E40 provides two modes of operation for loading the configuration SRAM. The simplest is Mode 1, Boot

From Serial ROM. This is the most common method of booting conventional SRAM based FPGA’s so consequently

the cost of compatible low pin count serial PROMs has been driven way down. Some designs may however want to

take advantage of the AN10E40’s on the fly reprogrammability. In this case the Micro Mode (Mode 0) may be the

appropriate configuration interface.

MODE

Pins

[2] [1] Description

x

0

1

0

1

x

Mode 0 – Micro Mode, a conventional byte wide microprocessor interface

Mode 1 – Boot from Serial PROM (a.k.a. Boot from ROM or BFR Mode)

AN10E40 generates its own configuration clocks (using an internal oscillator). CFG_CLK is an output.

Use an external clock for configuration. CFG_CLK is the input.

Figure 10. Mode Pin Settings for Configuration Options

The configuration SRAM for the AN10E40 contains 6864 bits. Configuration files will be slightly larger to facilitate

byte alignment of data as well as address and checksum information.

The pins involved with configuration of the device are given in the following table. The F[4:0] pins change behavior

based on the setting of the MODE[2:1] pins. The signal naming convention holds that active low signals are named

with a “b” suffix.

Pins Common to Configuration Modes

Pin Name

MODE[2:1]

CFG_CLK

Description

I

Used to establish the configuration mode.

I/O If MODE[2] is high, then configuration clock input, otherwise configuration clock output.

Pins used in Micro Mode (Mode 0)

POR

I

Complete chip reset sequence begins on rising edge of POR. (Usually tied low.)

Reset sequence begins on falling edge. Chip held in reset state as long as asserted low.

Configuration re-starts on release of RESETb.

RESETb

F[0] CSb

F[1] RDb

F[2] WRb

F[3] RS

I

When low, selects the AN10E40 for a data transfer transaction

Assert low for a Read transaction.

I

Assert low for a Write transaction.

I

Register Select. RS=0 to select Function register. RS=1 to select Data/Status register.

Asserted high when the device is not ready to accept data, i.e. while device is resetting,

or a data shift register to configuration SRAM transfer is taking place.

F[4] BUSY

O

DATA[7:0]

I/O Byte wide bi-directional data port

Pins used in BFR Mode (Mode 1)

POR

I

Complete chip reset sequence begins on rising edge of POR. Once complete, the

configuration sequence begins. (Usually tied low.)

Reset sequence begins on falling edge. Chip held in reset state as long as asserted low.

Configuration re-starts on release of RESETb.

RESETb

I

F[0] BFRb

F[1] ERRb

F[2] MEMCEb

F[3] PWRUP

F[4] END

I

On falling edge of BFRb, configuration sequence occurs.

Asserts low if a an error is detected in the configuration data stream. (Open Drain)

Asserts low to select the external memory device.

Tie to VDD.

O

I

O

I

Asserts high to signify configuration has completed.

Data clock to serial PROM.

DCLK

DATA[0]

Bit wide data input.

Figure 11. Configuration Pin Functions

10

Mode 0 – Micro Mode

The Micro Mode interface presents a conventional asynchronous byte wide peripheral interface. When CSb is

asserted, the DATA bus is used to write commands, read status, write and read configuration data. There are two

device configuration registers, the Function register (RS=0) and the Data/Status register (RS=1). Configuration

commands are written to the Function register. Subsequent behavior is specific to the command issued and is

documented in Figure 14.

The Data/Status register is either used to read or write configuration data or read device status. By popular

convention, RS is typically connected to the least significant bit of the processor’s address bus to map the Function

register to an even address and the Data/Status register to an odd address.

Figure 12 shows only those signals explicitly associated with Micro Mode configuration. Other signals including:

POR, OPAM_DISABLE, CEXT, OPAMP_VMR, powers, grounds and the switched capacitor CLOCK signal must

also be connected for proper operation. Please reference the Pin Out Description section for complete connection

details.

AN10E40

MODE[2]

F[0] - CSb

Microprocessor

Addr[n:0]

A[0]

F[3] - RS

WRITEb

READb

WAIT

F[2] - WRb

F[1] - RDb

F[4] - BUSY

D[7:0]

DATA[7:0]

CLK

CFG_CLK

RESETb

MODE[1]

CLK

RSTb

Figure 12. A conventional microprocessor interface for configuring AN10E40.

AN10E40 Data Manual

11

CSb

WRb

RS

1

4

2

3

5

6

DATA

BUSY

7

8

CSb

RDb

RS

1

4

2

3

9

10

DATA

7

BUSY

#

1

2

3

4

5

6

7

8

9

Characteristic

Min

Max Unit Notes

CSb Setup before RDb or WRb Falling Edge

RS Setup before RDb or WRb Falling Edge

RS Hold after RDb or WRb Falling Edge

Read or Write Pulse Width

10

50

20

10

50

0

ns

DATA[7:0] Setup to Rising Edge of WRb

DATA[7:0] Hold after Rising Edge of WRb

BUSY Inactive before end of Read or Write

BUSY Active after Write

20

40

10

ns

DATA[7:0] Access Time

20

0

10 DATA[7:0] Hold after Rising Edge of RDb

Figure 13. Micro Mode Write and Read Timing

12

DATA DATA

[7:4]

XXXX

[3:0]

0000

0001

Micro Mode Function Register Behavior

Normal Operation – No function performed.

Reset Device – Entire device configuration memory is reset. BUSY is asserted until the reset

sequence is complete.

XXXX

0010

Load Configuration – After writing this command, a complete configuration image should be

presented to the data register in 8 bit segments, starting with the configuration header block. At

any time during the loading process, a read from the data register will return status register

contents. As complete rows including Error Check Bytes (ECB) are loaded, BUSY is temporarily

asserted while row data is transferred from the internal data shift register to the currently

addressed SRAM memory row. Once this write operation is complete, BUSY is deasserted and

additional data can be written. Each time BUSY is deasserted, the status register should be

checked for incorrect ID or row configuration data errors. Once an error is detected, NO further

write accesses to the data shift register will be accepted until the device is reset, or another load

configuration command is issued.

XXXX

0011

0100

Reset Row – Indicates that the next data written to the data register will be a device row

address. After the address is written, the contents of that configuration memory row are reset.

BUSY is asserted after the address is written and deasserted when the operation is complete.

Load Row – Indicates that the next data written to the data register will be a device row address

followed by configuration date for that row including the terminating ECB. After the ECB is

written, BUSY will be asserted during the internal write and deasserted when the write

completes. Reading the data register returns status register contents. The status register should

be checked for row configuration data errors. Once an error has been detected, NO further write

accesses to the data register will be accepted until the device is reset or a load configuration

command is issued.

XXXX

0101

0110

Read Row – The next data written to the data register will be interpreted as a row address. After

the row address is written, BUSY is asserted while row data is copied into the data shift register.

BUSY is deasserted when the transfer is complete. Subsequent successive reads from the data

register will return row configuration data. No ECB is returned. The row data read back is the

same order as it was written, rightmost byte first.

Read Device ID – 4 subsequent reads form the data register will return the device ID. The most

significant ID byte is read first. The value of the device ID is 13 85 02 B7.

(Factory Reserved)

-

0111

1XXX

XXXX

(Factory Reserved)

1XXX

X1XX

(Factory Reserved)

Internal Oscillator Disable – Normally always enabled. If internal configuration clock is

selected, oscillator can not be disabled. Writing a 0 re-enables the oscillator.

(Factory Reserved)

XX1X

XXX1

XXXX

Analog Enable – Powers up Analog IO Cells and CAB Op-Amps.

Figure 14. Micro Mode Function Register Behavior

DATA

Micro Mode Status Register Contents

[7:0]

(Data[7:3] are factory reserved. Their function may change without notice.)

Incorrect Device ID detected in configuration data stream.

Row configuration data error (ECB mismatch).

XXXXXXX1

XXXXXX1X

XXXXX1XX

XXXX1XXX

XXX1XXXX

XX1XXXXX

X1XXXXXX

1XXXXXXX

Busy signal asserted. Allows software handshaking if hardware wait states are not to be used.

Asserted while last internal configuration SRAM row is being written.

Test_Count_0

End_Test

Last_Byte, asserted when last configuration byte is being written.

ID_Full, asserted when the ID has been written to the device.

Figure 15. Micro Mode Status Register Contents

AN10E40 Data Manual

13

Micro Mode Configuration Sequence

A

Micro

Mode

configuration

Monitor BUSY

Detect BUSY

l i n e o r r e a d

device status

register (RS=1).

Reset Device

sequence typically begins with

assertion of device reset. This can be

accomplished by either asserting

RESETb or by writing the reset

command into the function register.

Assert RESETb or write

r e s e t c o m m a n d t o

function register (RS=0).

No

After the reset sequence completes,

you have the option to specifically

address a single configuration row at

a time, but a more typical scenario

would be to instead write the Load

Configuration command into the

function register.

Write Load Configuration

Write load configuration

c o m m a n d t o f u n c t i o n

register (RS=0).

Write Data Byte

Write next configuration

data byte to the data

register (RS=1).

At this point, the device is expecting

that a complete configuration image

will be written to the data port

(RS=1). Simplistic software might

check for device busy after every

byte write. Device busy will assert

once a long internal shift register has

been filled, and the internal

configuration engine is moving the

contents of the register into a single

row of configuration SRAM.

Stop

Error

No

BUSY?

Monitor Status

Read device

status register

(RS=1).

Detect BUSY

l i n e o r r e a d

device status

register (RS=1).

Yes

BUSY

After the final row is loaded, re-

enable the bootstrap voltage and the

analog by writing 0x10 to the function

register.

Last Data?

Has a complete

configuration

f i l e b e e n

written?

It is possible to go in and uniquely

address specific rows of the

configuration SRAM. The details of

partial on-the-fly reconfiguration may

be covered in a separate application

note.

Yes

Enable Analog

Write 0x10 to function

register (RS=0).

Finished

Micro Mode Maximum Data Transfer Rate

The maximum Micro Mode data transfer rate is governed by the Read and Write timing diagrams shown above.

The host processor must only write data when BUSY is inactive. BUSY is only asserted when data cannot be

accepted at the maximum rate. The host processor can either monitor the device’s BUSY output, or read the Status

Register. If processor R/W cycles are faster than the timing shown, then external circuitry must be used to insert

wait states.

14

Mode 1 – Boot from ROM (BFR Mode)

In applications where the AN10E40 should boot from a serial memory device instead of a microprocessor, connect

as shown below in Figure 16. In this stand alone configuration, the AN10E40 handles all the reset and configuration

signaling. A standard serial EEPROM holds the configuration data. (Such serial memories are widely available as

FPGA boot devices.)

Holding MODE[1] high puts the AN10E40 in BFR mode. Holding MODE[2] low instructs the AN10E40 to generate

its own configuration clocks from its on-chip ring oscillator and sets CFG_CLK to be an output.

On power up, the internal power on reset sequence begins. As it concludes, the AN10E40 examines the state of

the RESETb pin. If held low, it does nothing. When the host system releases RESETb, the self configuration

sequence begins. Both CFG_CLK and DCLK go active and MEMCEb goes low. With MEMCEb asserted, the

EEPROM presents the first data bit. With every rising DCLK edge, the AN1E40 accepts the current data bit. Also

on this rising DLCK edge, the next data bit is clocked out of the serial PROM.

AN10E40

SERIAL

MODE[1]

F[0] - BFRb

F[3] - PWRUP

EEPROM

CEb

RST/OEb

Data_Out

CLK

F[2] - MEMCEb

DATA[0]

DCLK

RESETb

CFG_CLK

RESETb

ERRb-F[1]

END-F[4]

CFG_CLK

POR

MODE[2]

Figure 16. A typical Boot From ROM connection for the AN10E40.

After this automatic power on configuration has completed, there are two options for repeating a configuration

sequence. The first is the assertion of BFRb. On a falling edge of BFRb, the AN10E40 will repeat the complete

configuration sequence. BFRb may continue to be held low for an arbitrarily long period without effecting normal

operation. The second option is the assertion of RESETb. As long as RESETb is asserted low, the AN10E40 will

hold idle in a reset condition. On the rising edge of RESETb, the AN10E40 will repeat the configuration sequence.

If there is an error detected in the configuration bit stream, ERRb will assert low and the configuration sequence will

halt. ERRb is an open drain output. If the system has more than one FPAA on board, all the ERRb signals can be

wired together to provide a single indication that some configuration error was detected.

A speed up of the configuration process is possible by supplying your own CFG_CLK. If such a speed up is

desired, tie MODE[2] high and drive CFG_CLK (it is now an input) with a clock signal up to 40 MHz. DCLK will be

1/2 the frequency of CFG_CLK, so be sure to check your EEPROM specifications to be sure that it can go that fast.

The following Configuration Clock section has more detail on the relationship between these two signals.

Figure 16 shows only those signals explicitly associated with BFR Mode configuration. Other signals including:

OPAM_DISABLE, CEXT, OPAMP_VMR, powers, grounds and the switched capacitor CLOCK signal must also be

connected for proper operation. Please reference the Pin Out Description section for complete connection details.

AN10E40 Data Manual

15

BFR Timing

BFRb

1

CFG_CLK

MEMCEb

END

2

4

5

3

6

ERRb

7

DCLK

D[0]

8

9

#

1

2

3

4

5

6

7

8

9

Characteristic

Min

Max Unit Notes

BFRb Pulse Width

50

ns

BFRb Assertion to MEMCEb Deassertion

BFRb Assertion to END and ERRb Deassertion

BFRb Release to MEMCEb Assertion

END Assertion to MEMCEb Deassertion

Configuration Time

3

Clk

ns

2

14109

DCLK Period

2

20

0

2

DATA[0] Set Up Time

DATA[0] Hold Time

ns

Figure 17. BFR Mode Timing

16

Configuration Clock

CFG_CLK (in)

2

1

5

#

1

2

3

4

5

6

7

Characteristic

CFG_CLK Period

CFG_CLK Low

CFG_CLK High

Ring Osc Period

Ring Osc Low

Ring Osc High

DCLK Period

Min

50

10

25

10

Typ

Max

Unit

ns

3

ns

50

25

100

50

ns

(Internal Ring Osc.)

DCLK (out)

4

ns

50

ns

6

7

Always twice the period of

CFG_CLK.

(If MODE[2] = 1 then CFG_CLK is

an input. If MODE[2] = 0, then

CFG_CLK is an output running at

1

/

^ththe frequency of the internal

8

ring oscillator.)

Figure 18. Configuration Clock Specifications

If MODE[2] is held low, a divided down version of the ring oscillator output is used as the configuration logic clock.

CFG_CLK is set to be an output and reflects this clock. If instead MODE[2] is held high, CFG_CLK becomes the

configuration logic clock input. For shortest possible configuration times, use CFG_CLK as an input.

In a minimal system, you may want to take advantage of the AN10E40’s internal ring oscillator. The operating

frequency of the ring oscillator can vary from 10MHz up to 40MHz. This variation is expected and presents no

problems for the proper operation of the configuration engine. The ring oscillator is divided by 8 before use by the

configuration engine.

AN10E40

F3, PWRUP

Configuration

MODE[1]

RESETb

DCLK

Engine

High_4_BFR

Sys_Rst_Low

SPROM_Clk

RST POR

CLK

1/2

16

0

APOR

17 Bit APOR Pulse Stretcher

EN

CLK

POR

0

1

MODE[2]

Low_4_Int_Clk

Config_Clk

CFG_CLK

Ring

Oscillator

1/8

Figure 19. Block Diagram Showing Clocks and Resets

AN10E40 Data Manual

17

Reset Sequences

There are several sub-circuits which control the AN10E40 reset sequence and subsequent re-configuration. Each

interacts with the next to ensure reliable power up and system reset behavior.

Analog Power On Reset (APOR) & Power On Reset (POR)

When coming up cold (or at the onset of a brown out condition) the APOR circuit generates a pulse. This pulse

starts a companion 17 bit counter. This counter (driven by the internal configuration clock) serves as a digital APOR

pulse stretcher to produce a much longer POR signal to the configuration engine.

The AN10E40 provides a POR input pin so that the internal POR signal may be manually asserted. In a typical

application POR is tied to system VSS. There is otherwise rarely need for such fine control.

Internal Reset Activity

When either an external reset or internal POR reset is detected, a sequence of events transpires. First of course,

the configuration engine is reset and all the analog circuitry is powered down. Next, the configuration engine

continuously cycles through the SRAM configuration memory, repeatedly zeroing out the contents. This continues

until the 17 bit POR timer rolls over.

The length of the APOR pulse is dependant on VDD ramp rate, and then the entire reset process may be paced by

the widely varying ring oscillator. As such it is not possible to know a priori the exact length of the reset sequence,

but it can be bounded as shown in the performance characteristics section.

Setting MODE[2] high, and driving CFG_CLK with a known external frequency, yields a much more deterministic

configuration time. The only uncertainty is the width of the APOR pulse, but this is typically much less than half a

clock cycle.

Once the POR timer rolls over, the state of the external RESETb pin is examined. If RESETb is asserted low then

the configuration SRAM is cleared one more time and the chip is held in the reset state; configuration is held off

until RESETb is deasserted. If RESETb is instead high as the POR timer rolls over, the configuration SRAM is

cleared on more time and the configuration sequence begins. If the chip is in BFR mode, the configuration takes

place automatically. If the chip is instead in Micro Mode, then the configuration engine waits for writes to the

function register.

External Reset Assertion

Either POR or RESETb pins can be asserted to initiate a reset. If RESETb is not asserted, then the rising edge of

POR is detected and a complete reset/configuration sequence executes. POR should be dropped before the 17 bit

counter rolls over.

If instead POR is held low, a falling edge on RESETb can be detected which will clear SRAM a single time. If

RESETb is held low, configuration is held off until RESETb is deasserted, otherwise configuration proceeds

immediately after the SRAM clear.

In BFR mode, a falling edge of the BFRb signal is detected, and it too re-initiates a configuration sequence (but no

reset sequence).

Mechanical

Package Details

The AN10E40 is currently offered in a 80 pin QFP package. This package has been characterized to have a Θ_JAof

37 ^Cº/_W.

There are recommendations for dry pack handling of this device. If samples or production units are received without

sealed drypack then an 8 hour, 125 ºC oven bake is recommended before wave soldering. When received in

sealed drypacks, the devices should be mounted to a PCB within 48 hours of breaking the drypack seal.

18

Pin Out Description

The signal naming convention holds that active low signals are named with a “b” suffix.

1

Pin name

Type

Description

ARRAYCLKOUT

Digital Output

Programming allows one of the 4 internal clocks

to be presented here.

2

MODE[1]

Digital Input

Configuration mode control pin

0 = Micro Peripheral Interface Mode (Micro)

1 = Boot From Serial ROM (BFR)

Configuration mode control pin

3

MODE[2]

Digital Input

0 = Use Internal Clock (CFG_CLK is an output,

running at 1/8 internal ring oscillator frequency.)

1 = Use External Clock (CFG_CLK is the clock

input to the configuration logic.)

4

5

CFG_CLK

DCLK

Digital I/O

Configuration logic clock

Direction controlled by MODE[2]

Digital Output

SPROM Configuration clock output

1/2 frequency of CFG_CLK.

6

DATA[0]

Digital I/O

Data pins used for loading configuration data

and checking status. DATA[0] is used for serial

BFR mode, and the entire byte width is used in

Micro mode.

7

DATA[1]

Digital I/O

8

DATA[2]

Digital I/O

9

DATA[3]

Digital I/O

10

11

12

13

14

15

16

17

18

19

DATA[4]

Digital I/O

DATA[5]

Digital I/O

DATA[6]

Digital I/O

DATA[7]

Digital I/O

F[1] (ERRb, RDb)

F[2] (MEMCEb, WRb)

F[0] (BFRb, CSb)

F[3] (PWRUP, RS)

F[4] (END, BUSY)

OPAMP_DISABLE

O.D. Out, Digital In

Digital Out, Digital In

Digital Input

Digital Output

Digital Input

Configuration Function pins

(BFR mode function, Micro mode function)

F[1] is an Open Drain output. In multi-FPAA

systems, all the ERRb lines can be tied together

to provide a single error indicator.

Op-Amp disable input (normally tied to Vss, not

usually utilized in systems)

Takes precedence over BFR’s PWRUP input

and Micro’s Function Register Bit Position 4

(Analog Enable)

0 = Analog circuitry enabled

1 = Analog circuitry disabled

Chip RESET

20

RESETb

Digital Input

Falling edge detected to start Reset

Unbuffered Analog input

Buffered Analog input

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

IOLDX

IOLDY

IOLDZ

IOLDZ2

IOLDY2

IOLCZ

IOLCY

IOLCX

AVDD

AVSS

Analog Input

Analog Output

Analog Input

Analog Output

Analog Input

Power Supply

Analog Input

Analog Output

Buffered Analog output

Uncommitted op-amp output

Uncommitted op-amp input

Buffered op-amp output

Buffered Analog input

Unbuffered Analog input

Analog VDD, 5 Volts

Analog VSS, 0 Volts

SVSS

Substrate VSS, 0 Volts

IOLBX

IOLBY

IOLBZ

IOLAZ

Unbuffered Analog input

Buffered Analog input

Buffered analog output

Buffered op-amp output

AN10E40 Data Manual

19

36

37

38

39

40

41

IOLAY

IOLAX

VREFOUT

BVDD

BVSS

Analog Input

Analog Output

Power Supply

Analog Output

Buffered Analog input

Unbuffered Analog input

Reference voltage

Bandgap VDD, 5 Volts

Bandgap VSS, 0 Volts

VMR

Signal ground, 2.5 Volts

Normally left floating. Can be driven by off chip

generator if the on chip VMR generator is

disabled.

42

43

OPAMP_VMR

CEXT

Signal ground, 2.5 Volts

(usually loaded with 100nF to AVSS)

External Reference Generator Capacitor

(usually loaded with 10nF to AVSS)

Buffered op-amp output

Buffered Analog input

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

IOD5Z

IOD5Y

IOD5X

IOD4Z

IOD4Y

IOD4X

ESD_VDD

ESD_VSS

IOD3Z

IOD3Y

IOD3X

IOD2Z

IOD2Y

IOD2X

IOD1Z

IOD1Y

IOD1X

IORAX

IORAY

IORAZ

IORBZ

IORBY

IORBX

CFG_VDD

SVSS

Analog Output

Analog Input

Analog Output

Analog Input

Power Supply

Analog Output

Analog Input

Analog Output

Analog Input

Analog Output

Analog Input

Analog Output

Analog Input

Power Supply

Digital Input

Unbuffered Analog input

Buffered op-amp output

Buffered Analog input

Unbuffered Analog input

ESD Structures VDD, 5 Volts

ESD Structures VSS, 0 Volts

Buffered op-amp output

Buffered Analog input

Unbuffered Analog input

Buffered Analog output

Buffered Analog input

Unbuffered Analog input

Buffered Analog output

Buffered Analog input

Unbuffered Analog input

Buffered Analog input

Buffered Analog output

Buffered Analog input

Unbuffered Analog input

Configuration (Digital) VDD ,5 Volts

Substrate VSS, 0 Volts

SVDD

CLOCK

Substrate VDD, 5 Volts

System master clock

Used by clock generator which feeds all switch

capacitor analog circuitry.

Unbuffered Analog input

Buffered Analog Input

71

72

73

74

75

76

77

78

79

80

IORCX

IORCY

IORCZ

IORDY2

IORDZ2

CFG_VSS

IORDZ

IORDY

IORDX

POR

Analog Input

Analog Output

Analog Input

Analog Output

Power Supply

Analog Output

Analog Input

Digital Input

Buffered Analog output

Uncommitted op-amp input

Uncommitted op-amp output

Configuration (Digital) VSS, 0 Volts

Buffered Analog output

Buffered Analog input

Unbuffered Analog input

Power on Reset

Connection to VSS is typical. This input has an

active weak pull down device (capable of sinking 100

uA). If actively driving this pin, a pull up resistor may

be necessary to provide additional high state current.

20

80 LQFP Dimensions

0.22-0.38

b

e

(Lead width)

(Lead pitch)

0.65 Basic

Max. 0.100

Max. 0.130

16.95 - 17.45

0.73 - 1.03

1.60 Ref.

ccc (Coplanarity)

ddd (Bent lds)

D

E

L

(Lead to lead width)

(Lead to lead length)

(Foot length)

L1 (Lead length)

R

(Lead foot radius)

0.13 - 0.30

Min. 0.13

R1 (Lead shoulder radius)

A

(Overall height)

Max. 2.45

Max. 0.25

1.80 - 2.20

0.11 - 0.23

13.90 - 14.10

0º - 7º

A1 (Standoff)

A2 (Package thickness)

c

(Lead thickness)

D1 (Bottom package width)

E1 (Bottom package length)

D2 (Top package width)

E2 (Top package length)

@

(Lead flat angle)

@1 (Lead shoulder angle)

Min. 0º

DETAIL "B"

@2 (Top package draft angle)

@3 (Bottom package draft angle)

15º

AN10E40 Data Manual

21

Package Pin Electrical Characterization

Lead Inductance

Lself [nH]

Lmutual [nH]

Center

Corner

Center

Corner

4.22

5.23

1.93

2.55

Lead Capacitance

Cself [pF]

Cmutual [pF]

Center

Corner

Center

Corner

0.52

0.61

0.18

0.26

Lead Resistance

Lead Resistance [mΩ]

Lead Impedance – Z₀[Ω]

Center

Corner

Center

Corner

1.760

2.490

90.52

92.90

Center refers to a pin to die bond wire near the center of the package (pins 10, 20, 50 and 70). Corner refers to

those bond wires near the package and die corners.

Powers, Grounds and Bypassing

In order to ensure that your design benefits from the highest possible fidelity available, there are a few signals that

you should pay special consideration to when designing the host circuit board.

Recommended Configuration for Power & Ground

The most common configuration ties the following pins together to a quiet +5 V power plane: AVDD, SVDD, BVDD

and ESD_VDD with the shortest possible connection. The following pins should be brought down to a quiet ground

plane: AVSS, SVSS, BVSS and ESD_VSS also with the shortest possible connection.

CFG_VDD and CFG_VSS can also be connected as above, but the associated digital circuitry is not as sensitive to

noise, and therefor can be connected to your system’s “noisier” power rails.

Bypassing recommendations vary with the design of your power planes, but it is usually sufficient to recommend

the use of a parallel pair of capacitors connected between each VDD pin and its associated VSS plane. These

capacitor pairs should be placed as close as possible to: AVDD, SVDD, and BVDD and connected by the shortest

path possible to the associated ground plane. The recommended capacitors are .1 uF in parallel with .01 uF. Each

of these should be low leakage and low ESR type capacitors. Polyester (Mylar) capacitors are optimal for the job,

but the generic ceramic bypass capacitors are sufficient.

Bypassing CFG_VDD to CFG_VSS can be accomplished in a manner similar to that described above, but layout is

less critical.

Bypassing ESD_VDD to ESD_VSS is not required, but can serve to optimize the performance of the ESD

protection structures in the device’s IO cells, in the unlikely event that such a current path is ever called upon.

AVDD and AVSS

AVDD and AVSS supply the op-amp and comparator circuits with +5 V and 0 V respectively. Obviously then, care

should be taken then to ensure that the quietest possible supply and ground signals are provided.

SVDD and SVSS

The wafers used in the construction of the AN10E40 are P type, so substrate ties (SVSS) should be connected to a

quiet ground potential. The N type well ties on the wafer are all connected the SVDD pin and therefor need to be

biased to a quiet positive potential. Connecting SVDD to AVDD and SVSS to AVSS is a typical configuration.

22

BVDD and BVSS

BVDD and BVSS supply all the band-gap voltage references, VMR generator and bias current generators. Here

again, the typical connection is to AVDD and AVSS.

ESD_VDD and ESD_VSS

These two signals do not normally source or sink any current to the AN10E40. In the rare event that a device pin is

electrically overstressed by an ESD or EOS event (Electrostatic Discharge or Electrical Overstress), then current is

sourced or sunk though these rails. These two should be connected to quiet supplies and here again AVDD and

AVSS are the typical connections.

CFG_VDD and CFG_VSS

The CFG_VDD and CFG_VSS rails supply all the digital configuration circuitry, the on board ring oscillator, APOR

and POR generation circuitry with +5V and 0V respectively. With the possible exception of the on board ring

oscillator, any digital supply noise produced by this circuitry would not normally effect the performance of the

analog portion, so no particular care need be taken with these supply signals from the chip’s point of view. Your

system however may have both “noisy” and “clean” power rails available. If so, CFG_Vxx may be best connected

to the “noisy” rail, leaving the “clean” supply as unpolluted as possible.

OPAMVMR and CEXT

As mentioned above in the Voltage Mid-Rail Generator section, both OPAMPVMR and CEXT should be bypassed

to a quiet ground node to ensure optimal performance. Generally, a good configuration consists of a Polyester

(Mylar) 10nF capacitor between CEXT and AVSS. A similar bypassing connection for OPAMPVMR is also

recommended. Care should be exercised in the placement of these components to minimize the signal path

between the array and the bypass capacitors.

The AN10E40 in Split Supply Systems

All analog signal processing within the AN10E40 is

+2.5 V

referenced to its internal VMR node (Voltage Mid Rail,

normally 2.5 V above AVSS). For those applications

where a split supply (±2.5 V) is necessary, it is

VDD

possible to connect the AN10E40 as shown in Figure

20.

Analog

AN10E40

Interface

Ground

Referenced

Analog

Here the AN10E40's internal VMR generator is

disabled (a feature available via AnadigmDesigner)

and the chip's VMR pin is instead driven externally by

the system's ground plane.

Boot

VMR

PROM

(or Micro)

System

Naturally, logic circuits which interface to the AN10E40

must also be powered off the split rail as shown.

VSS

Under some circumstances, it may be more practical

to instead power the AN10E40 off a single 5 V supply

and AC coupled the ground referenced input signal.

-2.5 V

Figure 20. Connecting to a Split Rail System

Electrical Parameters

Because the AN10E40 is programmable, performance characteristics are reported for representative pieces of the

device rather than for the entire device. The following graphs and numbers provide you with conservative estimates

of the sort of performance you can expect for your particular design.

AN10E40 Data Manual

23

Absolute Maximum Ratings

Min.

Typ.

Max.

Notes

1

Supply Voltages (A,B,D,SVDD)

Analog Input Voltage

-0.5 V

-65 C

6.5 V

AVDD+0.5V

DVDD+0.5V

150 C

Digital Input Voltage

Storage Temperature

1 - Operation with Vdd > 5.5 V may reduce device operating lifetime.

Recommended Operating Conditions

Min.

Typ.

5.0 V

Max.

Notes

Supply Voltages (A,B,D,SVDD)

Analog Input Voltage

4.5 V

5.5 V

AVDD-0.5V

0.5 V

1k9 || 100pF

10k9 || 100pF

Standard Analog Load (small signal)

Standard Analog Load (large signal)

Standard Digital Load

1 kΩ in parallel with 100 pF

10 kΩ in parallel with 100 pF

50 pF to DVSS

50 pF

Ambient Operating Temperature

-40 C

+85 C

Digital IO

Min.

Typ.

Max.

Notes

Output Voltage High (V_oh)

Input High Voltage (V_ih)

0.8 Vdd

0.7 Vdd

Input Low Voltage (V_il)

0.3 Vdd

0.2 Vdd

Output Voltage Low (V_ol)

Tri-State Leakage Current (I_ozhor I_ozl)

negligible

Voltage Mid Rail

The array supplies its own internal analog ground reference known as VMR. VMR is 2.5 V above AVSS. Noise on

VMR degrades system performance so great care has been taken to provide the AN10E40 with an extremely quiet

analog reference generator.

Min.

Typ.

2.5 V

Max.

Notes

VMR

Vref

3

2

1

0

-1

-2

-3

-2

-1

0

1

2

3

Vref Programed

24

The Analog I/O Cell

The AN10E40 Analog I/O cells are carefully designed to provide robust drive without sacrificing bandwidth figures.

You can see from the plot below that the bandwidth of the I/O cells well exceeds the sort of signals typically

processed within the device.

Min.

Typ.

2 mV

Max.

Notes

Input Offset Voltage

Unity Gain

-0.02 dB

0 dB

+0.02 dB 1 kHz, Sine, 1.0 VRMS

Slew Rate

10 kΩ , 100 pF load

20 V/µs

10.8 MHz

-3dB Bandwidth

Input Voltage Range

AVSS

0.5

AVDD

Pins IOxxZ - When used as a

direct input to the device core cells.

Pins IOxxX and IOxxY - When the

I/O cell is used as a powered input

buffer. (Input range is limited by I/O

buffer output swing limitations.)

Pins IOxxZ - When I/O cell is used

as a powered output buffer.

Input Voltage Range

AVDD- 0.5

Output Voltage Range

AVDD- 0.5

0.5

Small Signal Load Defined as:

1 k9|| 100 pF

Pins IOxxX and IOxxY - When I/O

cell is used as a direct output from

a device core cell.

Output Voltage Range

Pins IOxxZ - When I/O cell is used

as a powered output buffer.

Large Signal Load Defined as:

10 k9|| 100 pF

Pins IOxxX and IOxxY - When I/O

cell is used as a direct output from

a device core cell.

AN10E40 Data Manual

25

The Analog I/O Cell Configured as a Sallen-Key Filter

The AN10E40 Analog I/O cells are especially designed to accommodate the construction of Sallen-Key topology

filters. These filters are easily constructed and are handy for input anti-aliasing or output switching noise filtering. In

this particular test, the filter was designed to roll off at 200 kHz.

Many of the measurements shown below are repeated several times with different weighting factors. CCIR IEC

468-3 Weighted and A-Weighted measurements are two standard Psophometric weightings common to audio and

communications equipment manufacture.

Min.

Typ.

85 dB

88 dB

87 dB

94 dB

0.015%

Max.

Notes

SNR, >500 kHz Bandwidth

SNR, 80 kHz Bandwidth

SNR, 468-3 Weighted

1 kHz, Sine, 1.0 Vrms

80 kHz

SNR, A Weighted

Total Harmonic Distortion (THD+N)

26

A Programmable Inverting Gain Stage

In this example, a CAB was programmed to serve as an inverting gain stage with the Gain parameter set to 2.

Notice the dead flat response throughout the band swept.

Min.

Typ.

Max.

Notes

SNR, >500 kHz Bandwidth

SNR, 80 kHz Bandwidth

SNR, 468-3 Weighted

SNR, A Weighted

74 dB

1 kHz, Sine, 0.5 Vrms

1 kHz, Sine, 0.5Vrms

1 kHz, Sine, 0.5 Vrms

80 kHz

76 dB

77 dB

85 dB

Total Harmonic Distortion (THD+N)

Gain Set to 0.01

0.011%

+1.27%

-1.14%

-1.71%

Gain Set Error

Gain Set to 1.00

Gain Set Error

Gain Set to 100.0

Gain Set Error

AN10E40 Data Manual

27

A Programmable Low Pass Filter

With a CAB programmed as a low pass (fc = 20 kHz), low Q (Q = 0.707) with a Gain of 2, the following

performance can be expected.

Min.

Typ.

Max.

Notes

SNR, >500 kHz Bandwidth

SNR, 80 kHz Bandwidth

SNR, 468-3 Weighted

70 dB

1 kHz, Sine, 0.5 Vrms

80 kHz

75 dB

70 dB

SNR, A Weighted

78 dB

Total Harmonic Distortion (THD+N)

Gain Set to 0.01

0.05%

+0.46%

-0.12%

-0.54%

+0.84%

-1.25%

+0.30%

+0.01%

Gain Set Error

Gain Set to 1.00

Gain Set Error

Gain Set to 100.0

Gain Set Error

fc set to 50.0 Hz, CLK at 16.13 kHz

fc set to 100.0 Hz, CLK at 16.13 kHz

fc set to 1.0 kHz, CLK at 100.0 kHz

fc set to 10.0 kHz, CLK at 250.0 kHz

Error in -3 db Corner Frequency

28

Sine Wave Oscillator

The test circuit is a Sine Wave Oscillator IPmodule, programmed to generate a 1.0 V Peak, 1 kHz Sine wave. The

input clock was running at 35.714 kHz. From the plot you can see that the most significant spur at 3 kHz is nearly

60 dB down from the fundamental. Other less significant spurs are noted at 2, 5, 7 and 9 kHz.

Electrostatic Discharge Characterization

The following excerpts were copied with permission from and gratitude to: The Electrostatic Discharge Association.

An excellent tutorial on the subject of ESD and EOS can be found on their web site at http://www.esda.org/.

A Quick Review of ESD Basics

Electrostatic Discharge (ESD) damage results from handling the devices in uncontrolled surroundings or when poor

ESD control practices are used. Generally damage is classified as either a catastrophic failure or a latent defect.

Catastrophic Failure

When an electronic device is exposed to an ESD event it may no longer function. The ESD event may have caused

a metal melt, junction breakdown, or oxide failure. The device's circuitry is permanently damaged causing the

device fail.

Latent Defect

A latent defect, on the other hand, is more difficult to identify. A device that is exposed to an ESD event may be

partially degraded, yet continue to perform its intended function. However, the operating life of the device may be

reduced.

Basic ESD Events--What Causes Electronic Devices to Fail?

ESD damage is usually caused by one of three events: direct electrostatic discharge to the device; electrostatic

discharge from the device or field induced discharges.

AN10E40 Data Manual

29

Discharge to the Device

An ESD event can occur when any charged conductor (including the human body) discharges to an ESDS

(electrostatic discharge sensitive) device. The most common cause of electrostatic damage is the direct transfer of

electrostatic charge from the human body or a charged material to the electrostatic discharge sensitive (ESDS)

device. When one walks across a floor, an electrostatic charge accumulates on the body. Simple contact of a finger

to the leads of an ESDS device or assembly allows the body to discharge, possibly causing device damage. The

model used to simulate this event is the Human Body Model (HBM).

A similar discharge can occur from a charged conductive object, such as a metallic tool or fixture. The model used

to characterize this event is known as the Machine Model.

Discharge from the Device

The transfer of charge from an ESDS device is also an ESD event. The trend towards automated assembly would

seem to solve the problems of HBM ESD events. However, it has been shown that components may be more

sensitive to damage when assembled by automated equipment. A device may become charged, for example, from

sliding down the feeder. If it then contacts the insertion head or another conductive surface, a rapid discharge

occurs from the device to the metal object. This event is known as the Charged Device Model (CDM) event, and

can be more destructive than the HBM for some devices. Although the duration of the discharge is very short--often

less than one nanosecond--the peak current can reach several tens of amperes.

Field Induced Discharges

Another event that can directly or indirectly damage devices is termed Field Induction. As noted earlier, whenever

any object becomes electrostatically charged, there is an electrostatic field associated with that charge. If an ESDS

device is placed in that electrostatic field, a charge may be induced on the device. If the device is then momentarily

grounded while within the electrostatic field, a transfer of charge from the device occurs.

AN10E40 ESD Classifications

Pin Type

Classifications

Class 2

Notes

Digital Inputs

M4 and C6 classifications are based

on estimated performance based on