AN110_技术文档

AN110

16-BIT PWM USING AN ON-CHIP TIMER

The example also configures the target board to

sample the PWM output using the on-chip ADC.

This DAC implementation may be used to evaluate

the C8051F220/1/6’s ADC.

Relevant Devices

This application note applies to the following

devices:

C8051F000, C8051F001, C8051F002,

C8051F005, C8051F006, C8051F007,

C8051F010, C8051F011, C8051F012, C8051F015,

C8051F016, C8051F017, C8051F220,

C8051F221, C8051F226, C8051F230,

C8051F231, and C8051F236.

Key Points

•

The C8051F2xx family SoC’s feature three on-

board 16-bit timers that can be used for PWM

generation. This example uses Timer 0 to pro-

duce the PWM wave which is output to a gen-

eral-purpose port pin.

Note: the C8051F0xx devices have an on-chip

PCA which may be more suitable for PWM gener-

ation. See AN007 for more information.

•

The C8051F2xx family of SoC’s have an 8-bit

ADC that is used in the provided example to

sample the output of the PWM DAC.

The C8051F226-TB target board features a

low-pass filter that can readily be used for the

PWM DAC and configured to be sampled by

the on-chip ADC without soldering or adding

extra wiring. Target board use is assumed in the

provided example.

Introduction

This document describes how to implement a 16-

bit pulse width modulator (PWM) digital-to-analog

converter (DAC). The PWM consists of two parts:

1. A timer to produce a PWM waveform of a

given period and specified duty cycle.

Generating the PWM Input

Waveform

2. A low-pass filter to convert the PWM wave to

an analog voltage level output.

Pulse-Width Modulation (PWM) is a method of

encoding data by varying the width of a pulse or

changing the duty cycle of a periodic waveform.

Adjusting the duty cycle of this waveform, we con-

trol the voltage output from the low-pass filter. This

can be thought of as a type of digital-to-analog con-

vertor (DAC). In this example, we use Timer 0 to

time the toggling of a general purpose port pin to

create the PWM waveform.

A PWM coupled with a low-pass filter can be used

as a simple, low cost digital to analog converter

(DAC). This output can be used to drive to a volt-

age controlled device, or used in a feedback control

system where an analog-to-digital convertor

(ADC) is used to sample a controlled parameter.

PWM’s are often used in motor control applica-

tions.

Configuring Timer 0

Implementation software and hardware is dis-

cussed in this application note. An example of a

PWM using an on-chip timer and a low-pass filter

on the C8051F226-TB target board is provided.

In order to create a PWM wave with a user speci-

fied duty cycle, we use Timer 0 in 16-bit counter/

timer mode. To do so, we configure the Timer

Rev. 1.2 12/03

AN110-DS12

AN110

Mode register (TMOD), and the Clock Control reg- service routine takes 14 cycles to take the PWM

ister (CKCON), to set Timer 0 to use the system wave from high to low. Thus, the maximum value

clock (undivided) as follows:

that can be used is 65,522. The variable

pulse_width is defined as follows:

;Set TIMER0 in 16-bit counter ;mode

orl TMOD,#01h

;define variable for user to

;set duty cycle of PWM wave

;input to the low-pass filter

;Set TIMER0 to use system clk/1

orl CKCON,#08h

pulse_widthEQU 35000d

Timer 0 is used to set the amount of time the PWM

wave will be high during one cycle. When the timer Note the example code sets pulse_width equal to

overflows, the program vectors to an interrupt ser- 35,000. As an example, 35,000 will create a duty

vice routine (ISR) to take a port pin high or low to cycle of 53.4%. Duty cycle is calculated as follows:

produce the PWM wave. We enable the Timer 0

interrupts by setting the ET0 bit to 1 as follows:

pulsewidth

------------------------------

dutycycle%=

× 100

65, 536

;Enable Timer 0 interrupts

setb ET0

Equation 1. Calculating Duty Cycle

The duty cycle also describes the average time that

the waveform is high. This time will be converted

into a voltage in the low-pass filter. The average

output voltage for a given pulse_width value is cal-

culated as follows:

Additionally, interrupts must be enabled globally:

;enable interrupts globally

setb EA

pulsewidth

------------------------------

Voutput = VDD ×

The last step in configuring Timer 0 is to start the

timer by setting the TR0 bit:

65, 536

Equation 2. Calculating Average

Output Voltage

;start Timer0

setb TR0

Hardware Configuration

Port pin P2.7 will be used for the PWM waveform

output to the PWM filter. We configure P2.7 as

‘push-pull’ by setting the Port 2 Configuration

Register (PRT2CF):

A variable called pulse_width defines the duty

cycle of the PWM wave. This determines the

amount of time the waveform is high during one

period of the wave, and is loaded into Timer 0. The

duty cycle can be set with 16-bit resolution. How-

ever, due to the number of cycles it takes to execute

the Timer 0 interrupt service routine (to be dis-

cussed later), the smallest pulse width that can be

assigned is 19 clock cycles. Likewise, the interrupt

;Set p2.7 as push-pull

orl PRT2CF, #80h

2

Rev. 1.2

AN110

Additionally, if using Silicon Lab’s C8051F226-TB Upon a return from an ISR (reti instruction), the

target board, a shorting jumper must be placed on MCU will jump back to the sjmp instruction. Here,

the “PWMIN” jumper in order to connect port pin the program will loop back to set the IDLE Mode

P2.7 to the low-pass filter.

bit and wait for the next interrupt condition to

occur.

Waiting For Interrupts

Generating the PWM Wave in

Software with Timer 0 ISR

The Timer 0 ISR (Timer 0 overflow interrupt ser-

vice routine) is used to generate the PWM wave by

toggling the port pin P2.7. After programming the

various peripherals, one may use a simple jump to

the current address instruction in a loop to wait for

interrupts, which is most common. However, the

ISR is being used to generate a PWM waveform,

and there will be a small amount undesirable of

timing jitter caused by the small variation in delay

due to interrupt latency. This variation occurs

because the C8051 completes the current instruc-

tion before branching to the interrupt service vec-

tor. Thus, the time to branch to the ISR will vary

depending on where in the 2-cycle jump instruction

the MCU is when the interrupt condition occurs. To

avoid this, we make use of the C8051 MCU IDLE

Mode. The MCU will automatically “wake up”

from IDLE Mode when an enabled interrupt

occurs. This removes variations in interrupt latency

because the core is always in the same state when

an interrupt occurs. Note that all peripherals (such

as timers) continue to operate when in IDLE Mode.

The PWM wave is produced by toggling a port pin

in an interrupt service routine (ISR). This ISR is a

state machine with two states. In one state, the out-

put pin is high (the high part of the PWM wave-

form). In this state, Timer 0 is loaded with the

value pulse_width and the MCU exits the ISR.

Next, the port pin is taken ‘low’ by clearing the bit

P2.7. In the low state, the value -pulse_width is

loaded. This sets the low time of the PWM wave-

form. At the next overflow, bit P2.7 is tested and

then set to go to the high part of the waveform for

the next period. In this way, the duty cycle can be

varied but the period of the PWM wave will be the

same.

The Timer 0 ISR is written as follows:

TIMER0_ISR:

;Test to see if low/high in ;wave-

form

Setting the Idle Mode Select bit in the Power Con-

trol Register (PCON) places the C8051 in IDLE

Mode. A jump statement is used to send the pro-

gram counter back to the instruction to set the

IDLE mode upon a return from an interrupt:

jbc P2.7,LO

setb P2.7

; Set the low time of the

; PWM waveform

;Wait for interrupts in IDLE

;mode

; Stop Timer 0 prior to load

clr TR0

IDLE:

orlPCON,#01h

sjmpIDLE

mov TH0,#HIGH(-

pulse_width)

Rev. 1.2

3

AN110

mov TL0,#LOW(-pulse_width)

In our example, we use a single-pole RC filter

installed on the C8051F226-TB target board by

placing a shorting jumper on the two pin jumper

labeled “PWMIN”. The filter used is shown in

Figure 1..

; Restart Timer 0

setb TR0

;Go to the reti statement

jmp RETURN

PWM Wave input

PWM Output

R

C

;Set low time of PWM Wave

LO:

; Stop Timer 0

Figure 1. Low-Pass Filter

clr TR0

The filter in Figure 1 is a simple single pole filter.

Its transfer function is:

mov TH0,#HIGH(pulse_width)

mov TL0,#LOW(pulse_width)

; Restart Timer 0

setb TR0

ω_c

= --------------- , ω_c= --------

Vout(s)

1







RC

---------------------



Vin(s)

s + ω_c

Equation 3. RC Filter Transfer Function

;Return to MAIN and wait for

;interrupt

The RC filter must have a relatively low cutoff fre-

quency in order to remove enough high frequency

components of the wave to give a relatively con-

stant DC voltage level. However, if the RC con-

stant is too large, it will take too long for the RC

voltage to rise to a constant level (i.e., long settling

time.) This trade off can be easily tested in a com-

puter model or a lab to choose good resistor/capac-

itor values.

RETURN:reti

The Low-Pass Filter

The PWM wave generated with specified duty

cycle is input into a low-pass filter. This filter will

remove most of the high frequency components of

the PWM wave. In terms of the time domain, the

RC circuit will be charged to a voltage level pro-

portional to the percentage of the period that the

PWM wave input is positive (duty cycle). In short,

the low-pass filter converts the set high time of the

PWM wave to a voltage at the output of the system.

Because the system inputs a digital number and

outputs a desired voltage, the PWM and low-pass

filter may be considered a form of digital-to-analog

convertor (DAC).

This filter has only a single pole and so does not fil-

ter out all of the high frequency components of the

rectangular PWM waveform. The capacitor is

undergoing alternating cycles of charge and dis-

charge, so the output will not be a constant DC

voltage. (See Figure 2 below.) The output voltage

will have some “ripple” (Vripple in Figure 2) asso-

ciated with the filter’s time constant τ=RC. In the

frequency domain, the voltage ripple can be

thought of as the relationship between the filter’s

4

Rev. 1.2

AN110

cutoff frequency (ω=1/RC) and the frequency of low-pass filter, and with respect to the PWM wave

the PWM wave.

frequency this will characterize how much of the

high frequency components will be filtered from

When designing the low-pass filter, it may be the rectangular PWM waveform.

important to predict, or characterize the deviation

from the desired constant, DC voltage output. We The RC circuit on the target board uses a 220 kΩ

refer to this as voltage ripple (Vripple). In order to resistor and a 0.47 µF capacitor. These values were

characterize the Vripple, we use the formulae that chosen to show a relatively constant voltage level

describes the voltage of a capacitor in an RC cir- with 8-bit ADC sampling and still have a reason-

cuit.

able settling time.

Figure 2 illustrates the input PWM wave and the If the ideal output is a constant DC voltage, then

resulting low-pass filter output. The output wave is the ripple in the output voltage can be considered

exaggerated to show the alternating charge and dis- as the error. To calculate this error when designing

charge of the capacitor in the RC circuit. The ripple the filter (or to evaluate using a simple RC filter),

for a 50% duty cycle (worst case ripple) for this fil- we must know the frequency of the PWM wave,

ter is calculated by using the following expression and the time constant (τ). Using the RC values on

given R,C, and the period of the PWM wave, T:

the target board, τ=RC=0.1034 seconds. If the 16-

bit timer is running with system clock speed of

16 MHz, the PWM period in this example is:

T





2e^–-----

2τ





Vripple = VDD 1 – -------------------- ,τ = RC





_T

1 + e^–-----



2¹⁶

^2τ

65, 536

-------------------

T = ----------------- =

≈ 4ms

16×10⁶

sysclk

Equation 4. Voltage Ripple In Filter

Circuit

In this example, the predicted Vripple is calculated

Equation 4 is derived using the formulae that

describe the voltage of a capacitor in an RC circuit

and by taking advantage of the symmetry of the

PWM waveform as a square wave (i.e., 50% duty

cycle). Note that the worst case ripple is deter-

mined by both the frequency (f=1/T), and the RC

to be 200 mV using Equation 4.

Sampling the PWM Output

With the On-Chip ADC

time constant (τ). This makes sense, as the RC The C8051F226-TB target board includes a

combination determines the cutoff frequency of the C8051F226 SoC that features an 8-bit analog-to-

PWM Waveform

LPF Output

Vripple

Time

Figure 2. PWM Waveform and Filter Output

Rev. 1.2

5

AN110

; PGA gain = 1

digital convertor (ADC). In this example, we wish

to sample the output voltage with the ADC. Alter-

natively, the output can also be measured using a

voltmeter at the test point labeled “PWM” on the

target board. To use the ADC we must configure a

port for ADC input and program the ADC to sam-

ple at a desired rate to measure the PWM output.

;Timer 2 overflow

mov ADC0CN, #01001100b

Finally, we enable the ADC. This bit is located in

the ADC0CN register which is bit addressable, and

so we use setb:

Configuring the ADC

The C8051F2xx family of devices can use any gen-

eral purpose port pin as an input for analog signals.

The AMX0SL register configures the ADC’s mul-

tiplexer (AMUX) to select which port pin will be

the input to the ADC. The target board used in this

example provides a circuit for easily placing the

PWM output to port pin P3.0, which is configured

as the ADC input as follows:

;enable ADC

setb ADCEN

In this example, we use the VDD voltage supply as

the ADC voltage reference. This is set in the

REF0CN register:

;set ADC to use VDD as Vref

mov REF0CN, #03h

;enable AMUX and configure for

;P3.0 as an input port pin

mov AMX0SL,#38h

Before we can use Timer 2 overflows to initiate

ADC conversions, we must configure and start

Timer 2. We place a value called ADCsampl in

Timer 2 to initialize its operation, and place the

same value into the Timer 2 Capture registers,

RCAP2H:RCAP2L, so that it will overflow at the

desired sampling frequency. Timer 2 has an auto-

reload feature making this convenient. A sampling

frequency that is independent of PWM wave fre-

quency is desirable because the output of the filter

will have a periodic variation in the DC level

because the filter is not ideal (charging and dis-

charging of our capacitor causing Vripple.) Sam-

pling at a different frequency will allow us to

observe the voltage ripple with the ADC. In this

example, we use a sampling frequency of 1.6 kHz.

The ADC0CF configuration register sets the SAR

conversion clock based on the system clock, and

sets the programmable gain amplifier (PGA) gain.

The maximum frequency the SAR clock should be

set to is 2 MHz. The system clock is operating at

16 MHz, thus, the SAR conversion clock is set to 1/

8 of the system clock frequency (i.e., SAR conver-

sion clock = sysclk/8). We also program the PGA

for a gain of one as follows:

;set conv clk at one sys clk and

;PGA at gain = 1

mov ADC0CF, #60h

ADC0CN is the ADC control register. This register

is set to configure the ADC to start conversions

upon a Timer 2 overflow and set the ADC to low

power tracking mode (tracking starts with Timer 2

overflow):

Configuring Timer 2:

;initialize T2 for ADC sampling

;rate of 1.6 kHz with 16 MHz

;sysclk

; SAR clock = SYSCLK/8

mov TL2,#LOW(ADCsampl)

6

Rev. 1.2

AN110

mov TH2,#HIGH(ADCsampl)

orl P3MODE, #01h

;Load autoreload values for ;sam-

pling rate of ADC

Note that we must physically connect the PWM

output to the ADC input. One could solder a wire

or design a PCB to provide this connection. The

target board in this example conveniently provides

headers that allow easy configuration using short-

ing jumpers to connect the provided PWM low-

pass filter to port pin P3.0. No soldering or external

wiring is necessary for this demonstration.

mov RCAP2L,#HIGH(ADCsampl)

mov RCAP2H,#HIGH(ADCsampl)

;Set Timer 2 to use sysclk/1

orl CKCON, #20h

To configure external circuitry to input the PWM

output to port pin P3.0 (set for ADC input), place a

shorting jumper onto header J6, connecting

“PWM” pin to “P3.0AIN”. P3.0AIN is connected

to the P3.0 port pin on the device.

;start Timer 2

setb TR2

The ADC Interrupt Service

Routine

We must enable ADC end of conversion interrupts

so we can process ADC samples. To enable ADC

interrupts, we configure the Extended Interrupt

Enable 2 register (EIE2):

The ADC interrupt service routine’s only function

in our example is to clear the ADC interrupt flag,

the ADCINT bit. This flag must be cleared in soft-

ware, and we do so as follows:

;enable ADC interrupts

orl EIE2,#00000010b

ADC_ISR:

clr ADCINT

The ADC is now configured for sampling an input

from P3.0 using Timer 2 to set the sampling fre-

quency. All that is required now is to configure the

port pin for analog use described in the following

section, and connect it to the low-pass filter output.

reti ;return from interrupt

The ADC ISR is a convenient place to read the

sampled data from the ADC data registers and pro-

cess the data. This example leaves the data in the

word register (ADC0H) and will be overwritten

with each new sample. This data may be observed

by using Silicon Lab’s Integrated Development

Environment (IDE) tool to view the special func-

tion register, ADC0H which holds the ADC con-

version results.

Configuring the Port For the

ADC

The ADC has been configured to input analog from

P3.0. We now must configure the port for analog

input use.

The port pins default to digital input mode upon

reset. We place port pin P3.0 in analog input mode

by configuring the Port 3 Digital/Analog Port

Mode register, P3MODE:

Interpreting the Results

The PWM outputs a voltage level corresponding to

the pulse_width variable which determines the

;Set p3.0 in analog input mode

Rev. 1.2

7

AN110

PWM wave duty cycle. As aforementioned, the

voltage level output can be calculated using

Equation 2 on page 3.

VDD refers to the supply voltage of the device. The

number 65,536 is the highest number that can be

represented in 16 bits (as our PWM timer is a 16 bit

counter/timer). Voutput is the value one would

measure at the output of the PWM’s low-pass filter.

Note that due to the number of cycles is takes to

execute the Timer 0 ISR, the minimum number that

can be effectively used as the pulse_width is 19.

Thus, the lowest Voutput that can be generated is

0.028% of VDD. Any number used for pulse_width

less than 19 will yield the same result as entering

19. Similarly, it takes 14 cycles for the Timer 0 ISR

to process the falling edge of the PWM waveform.

Thus, the maximum effective pulse_width is

65,522 (65,536-14). Therefore, the resulting output

will be 99.98% of VDD. There are no other limita-

tions due to software inside of the 0.028%-99.98%

range other than the quantization imposed by 16-bit

timer resolution. If, for example, VDD=3.0V, then

the voltage resolution will be 46 µV with code and

the range of the output voltage values is 0.87 mV to

2.9994 V.

In our example, we measure the PWM output with

the on-chip ADC. The result in the ADC register

(ADC0H) will be a number between 0 and 255 (8-

bit ADC). This example uses VDD as the reference

for the ADC conversion. The ADC output number

can be interpreted as follows:

ADC0H

---------------------

Vresult = VDD ×

256

Note that Vresult may not match the ideal Voutput

calculated as output from the PWM. This is due to

the aforementioned Vripple (see section, “The

Low-Pass Filter”).

8

Rev. 1.2

AN110

Software

;Implementing an 16-bit PWM on SA_TB4PCB-002 target board and sampling to test

; the 8-bit analog-to-digital convertor (ADC). The following program will

; configure on-chip peripherals and use a low-pass filter on the target board.

;

;FILE:

PWM_200.asm

;DEVICE: C8051F2xx

;TOOL:

Cygnal IDE, 8051 assembler (Metalink)

;AUTHOR: LS

;-----------------------------------------------------------------------

$MOD8F200

;-----------------------------------------------------------------------

;

;Reset Vector

;

org

jmp

00h

MAIN

;

;-----------------------------------------------------------------------

;

;ISR Vectors

org

jmp

0Bh

TIMER0_ISR

org

jmp

7Bh

ADC_ISR

;-----------------------------------------------------------------------

;CONSTANTS

pulse_width EQU

35000d

; Value to load into TIMER0 which

; adjusts

; pulse width (duty cycle)

; in PWM and thus sets the

; DC bias level output from the

; low-pass

; filter. Set from 19-65522d.

; 32768 = VDD/2

ADCsampl

EQU

55536d

; Load into TIMER2 for ADC sampling rate

;-Start of MAIN code----------------------------------------------------

org0B3h

MAIN:

mov

orl

OSCICN,#07h

WDTCN,#0DEh

WDTCN,#0ADh

P3MODE,#0FEh

PRT2CF,#80h

; Configure internal OSC for 15MHz

; Configure P3.0 for analog input

; Configure P2.7 as push-pull input to ;

low-pass filter

orl CKCON,#28h

; Set TIMER0 and TIMER2 to use SYSCLK/1

Rev. 1.2

9

AN110

mov

TMOD,#01h

RCAP2L,#LOW(ADCsampl)

; Set TIMER0 in 16-bit counter mode

; Load autoreload values for sampling

; rate of ADC

mov

RCAP2H,#HIGH(ADCsampl)

TL2,#LOW(ADCsampl)

; using TIMER2 overflow for ADC

; conversion start

; initialize T2 for ADC sampling

; rate=1.6KHz

mov

TH2,#HIGH(ADCsampl)

AMX0SL,#38h

ADC0CF,#60h

; Set AMUX for P3.0 input/Enable AMUX

; SAR clock = SYSCLK/8, and GAIN = 1

; Set the ADC to start a conversion on

; Timer2 overflow

ADC0CN,#00001100b

orl

setb ET0

REF0CN,#03h

EIE2,#00000010b

; Set to the internal reference

; Enable ADC end of conv. interrupts

; Enable timer0 interrupts

; Global interrupt enable

; Start TIMER0

setb EA

setb TR0

setb TR2

setb ADCEN

; Start TIMER2

; Enable the ADC

IDLE:

orl

PCON,#01h

; BWCLD

sjmp IDLE

;------TIMER0 ISR----------------------------------------------------------

TIMER0_ISR:

jbc

setb P2.7

clr

mov

P2.7,LO

; Test to see if low/high in waveform

; Transition low to high

; Stop Timer 0 during reload

; Set length of pulse for DC bias level

;

TR0

TL0,#LOW(-pulse_width)

TH0,#HIGH(-pulse_width)

setb TR0

; Restart Timer 0

jmp

clr

mov

RETURN

TR0

TL0,#LOW(pulse_width)

TH0,#HIGH(pulse_width)

LO:

; Stop Timer 0 for reload

; Set low time of duty cycle

setb TR0

RETURN:reti

; Restart Timer 0

;------ADC ISR-------------------------------------------------------------

ADC_ISR:

clr

ADCINT

; flag must be cleared in software

reti

;---------------------------------------------------------------------------

;End of program

;All your base are belong to us.

END

10

Rev. 1.2

AN110

Notes:

Rev. 1.2

11

AN110

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Tel: 1+(512) 416-8500

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12

Rev. 1.2


型号：	AN110
厂家：	SILICON
描述：	16-BIT PWM USING AN ON-CHIP TIMER 16位PWM采用片上定时器
文件：	总12页 (文件大小：239K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AN110 [SILICON]

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