ML13155-5P [LANSDALE]
Wideband FM IF; WIDEBAND FM IF
| 型号： | ML13155-5P |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Wideband FM IF |
| 文件： | 总16页 (文件大小：1017K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML13155
Wideband FM IF
SEMICONDUCTOR TECHNICAL DATA
Legacy Device: Motorola MC13155
The ML13155 is a complete wideband FM detector designed for
satellite TV and other wideband data and analog FM applica-
tions. This device may be cascaded for higher IF gain and
extended Receive Signal Strength Indicator (RSSI) range.
16
1
• 12 MHz Video/Baseband Demodulator
• Ideal for Wideband Data and Analog FM Systems
• Limiter Output for Cascade Operation
• Low Drain Current: 7.0 mA
SO–16 = -5P
PLASTIC PACKAGE
CASE 751B
(SO–16)
• Low Supply Voltage: 3.0 to 6.0 V
• Operates to 300 Mhz
• Operating Temperature Range T = –40 to +85°C
A
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
SO 16
MOTOROLA
MC13155D
LANSDALE
ML13155-5P
MAXIMUM RATINGS
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Rating
Pin
11, 14
1, 16
–
Symbol
V (max)
EE
Value
6.5
Unit
Vdc
Vrms
°C
Power Supply Voltage
Input Voltage
V
in
1.0
Junction Temperature
Storage Temperature Range
T
J
+150
–
T
stg
– 65 to +150
°C
NOTE: Devices should not be operated at or outside these values. The “Recommended
PIN CONNECTIONS
Operating Conditions” provide for actual device operation.
Input
1
2
3
4
5
6
7
8
Input
16
15
14
13
12
11
10
9
Figure 1. Representative Block Diagram
Decouple
Decouple
Buffered
RSSI
Output
V
1
V
1
EE
CC
RSSI
Output
Limiter
Output
Decouple
15
Output
Output
RSSI Buffer
RSSI
13
12
10
16
1
V
2
V
2
9
8
CC
EE
Input
Input
Three Stage
Amplifier
Quad
Coil
Limiter Out
Quad Coil
Limiter Out
Quad Coil
Detector
(Top View)
2
Decouple
4
5
7
Balanced
Outputs
Limiter
Output
NOTE: This device requires careful layout and decoupling to ensure stable operation.
Page 1 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
RECOMMENDED OPERATING CONDITIONS
Rating
Pin
Symbol
Value
Unit
Power Supply Voltage (T = 25°C)
11, 14
3, 6
V
V
– 3.0 to – 6.0
Grounded
Vdc
A
EE
CC
– 40C
T
A
85°C
≤
≤
Maximum Input Frequency
Ambient Temperature Range
1, 16
–
f
300
MHz
°C
in
T
– 40 to + 85
J
DC ELECTRICAL CHARACTERISTICS (T = 25°C, no input signal.)
A
Characteristic
Pin
Symbol
Min
Ty p
Max
Unit
Drain Current
11
14
14
I
I
I
2.0
3.0
3.0
2.8
4.3
4.3
4.0
6.0
6.0
mA
11
14
14
(V
EE
(V
EE
= – 5.0 Vdc)
= – 5.0 Vdc)
Drain Current Total (see Figure 3)
11, 14
I
5.0
5.0
5.0
4.7
7.1
7.5
7.5
6.6
10
mA
To t a l
(V
EE
(V
EE
(V
EE
= – 5.0 Vdc)
= – 6.0 Vdc)
= – 3.0 Vdc)
10.5
10.5
9.5
AC ELECTRICAL CHARACTERISTICS (T = 25°C, f = 70 MHz, V
IF
= – 5.0 Vdc Figure 2, unless otherwise noted.)
EE
A
Characteristic
Input for – 3 dB Limiting Sensitivity
Differential Detector Output Voltage (V = 10 mVrms)
Pin
1, 16
4, 5
Min
Ty p
Max
Unit
–
1.0
2.0
mVrms
mV
p–p
in
(f
dev
=
3.0 MHz) (V
= – 6.0 Vdc)
= – 5.0 Vdc)
= – 3.0 Vdc)
470
450
380
590
570
500
700
680
620
EE
EE
EE
(V
(V
Detector DC Offset Voltage
RSSI Slope
4, 5
13
– 250
1.4
–
250
2.8
39
mVdc
µA/dB
dB
2.1
35
RSSI Dynamic Range
RSSI Output
13
31
12
µA
(V = 100 µVrms)
in
–
–
16
–
2.1
2.4
24
65
75
–
–
36
–
(V = 1.0 mVrms)
in
(V = 10 mVrms)
in
(V = 100 mVrms)
in
(V = 500 mVrms)
in
–
–
RSSI Buffer Maximum Output Current (V = 10 mVrms)
in
13
–
2.3
–
mAdc
Differential Limiter Output
mVrms
(V = 1.0 mVrms)
(V = 10 mVrms)
in
7, 10
100
–
140
180
–
–
in
Demodulator Video 3.0 dB Bandwidth
4, 5
–
12
–
MHz
Input Impedance (Figure 14)
1, 16
@ 70 MHz Rp (V
= – 5.0 Vdc)
–
–
450
4.8
–
–
Ω
pF
EE
@ 70 MHz Cp (C =C = 100 p)
2
15
Differential IF Power Gain
1, 7, 10, 16
–
46
–
dB
NOTE: Positive currents are out of the pins of the device.
Page 2 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
CIRCUIT DESCRIPTION
The ML13155 consists of a wideband three–stage limiting
amplifier, a wideband quadrature detector which may be
operated up to 200 MHz, and a received signal strength
indicator (RSSI) circuit which provides a current output lin-
early proportional to the IF input signal level for approxi-
mately 35 dB range of input level.
Figure 2. Test Circuit
1.0n
1.0n
27
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
IN2
in
10n
49.9
DEC1
DEC2
V
1
V
1
CC
EE
V
EE
1.0n
100n
1.0k
10
µ
µ
+
+
RSSI
Buffer
DETO1
DETO2
Video
Output
RSSI
V
V
EE
1.0n
1.0n
V
2
V
2
CC
EE
EE
10
100n
Limiter 1
Output
Limiter 2
Output
LIMO1
LIMO2
1.0n
1.0n
330
330
QUAD1
QUAD2
499
20p
L1 – Coilcraft part number 146–09J08S
L1
260n
APPLICATIONS INFORMATION
EVALUATION PC BOARD
The evaluation PCB shown in Figures 19 and 20 is very ver-
satile and is designed to cascade two ICs. The center section
of the board provides an area for attaching all surface mount
components to the circuit side and radial leaded components
feedback network at Pins 2 and 15.
Scattering parameter (S–parameter) characterization of the IF
as a two port linear amplifier is useful to implement maxi-
to the component ground side of the PCB (see Figures 17 and mum stable power gain, input matching, and stability over a
18). Additionally, the peripheral area surrounding the RF
core provides pads to add supporting and interface circuitry
desired bandpass response and to ensure stable operation out-
side the bandpass as well. The ML13155 is unconditionally
as a particular application dictates. This evaluation board will stable over most of its useful operating frequency range; how-
be discussed and referenced in this section.
ever, it can be made unconditionally stable over its entire
operating range with the proper decoupling of Pins 2 and 15.
Relatively small decoupling capacitors of about 100 pF have a
significant effect on the wideband response and stability.
LIMITING AMPLIFIER
Differential input and output ports interfacing the three stage
limiting amplifier provide a differential power gain of typical- This is shown in the scattering parameter tables where
ly 46 dB and useable frequency range of 300 MHz. The IF
gain flatness may be controlled by decoupling of the internal
S–parameters are shown for various values of C2 and C15
and at V of –3.0 and –5.0 V DC.
EE
Page 3 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
TYPICAL PERFORMANCE AT TEMPERATURE
(See Figure 2. Test Circuit)
Figure 4. RSSI Output versus Frequency and
Input Signal Level
Figure 3. Drain Current versus Supply Voltage
10
100
80
T
= 25°C
V
= – 5.0Vdc
A
EE
0 dBm
8.0
I
= I + I
Total 14 11
–10 dBm
60
6.0
4.0
2.0
0.0
I
14
– 20 dBm
40
20
0
– 30 dBm
– 40 dBm
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
10
100
f, FREQUENCY (MHz)
1000
V
, SUPPLY VOLTAGE (–Vdc)
EE
Figure 5. Total Drain Current versus Ambient
Temperature and Supply Voltage
Figure 6. Detector Drain Current and Limiter
Drain Current versus Ambient Temperature
9.0
8.5
8.0
5.5
5.0
f = 70 MHz
V
= – 5.0 Vdc
– 5.0 Vdc
EE
V
= – 6.0 Vdc
– 3.0 Vdc
EE
I
14
4.5
4.0
3.5
3.0
2.5
7.5
7.0
6.5
I
11
6.0
5.5
5.0
2.0
– 50
– 30
–10
10
30
50
70
90
110
– 50
– 30
–10
10
30
50
70
90
110
T
AMBIENT TEMPERATURE (°C)
T
A,
AMBIENT TEMPERATURE (°C)
A,
Figure 7. RSSI Output versus Ambient
Temperature and Supply Voltage
Figure 8. RSSI Output versus Input Signal
Voltage (V at Temperature)
in
25.0
24.5
100
80
V
= – 6.0 Vdc
EE
T
= + 85°C
A
24.0
23.5
23.0
22.5
22.0
21.5
+ 25°C
– 40°C
60
V
= – 5.0 Vdc
EE
40
20
0
V
= – 3.0 Vdc
EE
– 50
– 30
– 10
10
30
50
70
90
110
0.1
1.0
10
V , INPUT VOLTAGE (mVrms)
in
100
1000
T
AMBIENT TEMPERATURE (°C)
A,
Page 4 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
Figure 9. Differential Detector Output
Voltage versus Ambient Temperature
and Supply Voltage
Figure 10. Differential Limiter Output Voltage
versus Ambient Temperature
(V = 1 and 10 mVrms)
in
750
700
650
600
220
200
180
V
= – 6.0 Vdc
f = 70 MHz
= – 5.0 Vdc
EE
V
= 10 mVrms
in
V
EE
– 5.0 Vdc
– 3.0 Vdc
550
500
450
400
350
160
140
120
V
= 1.0 mVrms
in
– 50
– 30
–10
10
30
50
70
90
110
– 50
– 30
–10
T AMBIENT TEMPERATURE (C)
A,
10
30
50
70
90
T
AMBIENT TEMPERATURE (C)
A,
Figure 11A. Differential Detector Output Voltage
versus Q of Quadrature LC Tank
Figure 11B. Differential Detector Output Voltage
versus Q of Quadrature LC Tank
1600
1400
2400
2000
1600
1200
800
V
V
f
= – 30 dBm
= – 5.0 Vdc
= 70 MHz
V
V
f
= – 30 dBm
= – 5.0 Vdc
= 70 MHz
in
EE
c
in
EE
c
f
=
6.0 MHz
dev
f
=
6.0 MHz
5.0 MHz
4.0 MHz
dev
f
= 1.0 MHz
f
= 1.0 MHz
1200 mod
mod
5.0 MHz
4.0 MHz
(Figure 16 no external capacitors
1000 between Pins 7, 8 and 9, 10)
(Figure 16 no external capacitors
between Pins 7, 8 and 9, 10)
3.0 MHz
2.0 MHz
800
600
400
200
0
3.0 MHz
2.0 MHz
1.0 MHz
1.0 MHz
5.5
400
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
6.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Q OF QUADRATURE LC TANK
Q OF QUADRATURE LC TANK
Figure 12. RSSI Output Voltage versus IF Input
Figure 13. S+N, N versus IF Input
10
0
0
V
f
= – 5.0 Vdc
= 70 MHz
EE
c
S+N
Capacitively coupled
interstage: no attenuation
–1.0
(See Figure 16)
–10
– 20
– 30
– 40
– 50
– 60
– 70
–2.0
–3.0
15 dB Interstage
Attenuator
–4.0
–5.0
f
f
f
= 70 MHz
c
N
= 1.0 MHz
mod
dev
EE
=
5.0 MHz
V
= – 5.0 Vdc
– 80
– 60
– 40
– 20
0
20
– 90
– 70
– 50
– 30
– 10
10
IF INPUT, (dBm)
IF INPUT (dBm)
Page 5 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
In the S–parameters measurements, the IF is treated as a
two–port linear class A amplifier. The IF amplifier is meas-
ured with a single–ended input and output configuration in
which the Pins 16 and 7 are terminated in the series combina-
values for the stability and factor (K) and the Maximum
Available Gain (MAG). These terms are related in the follow-
ing equations:
2
2
2
K = (1–IS I –IS I + I∆I )/(2 I S I)
S
11 22 12 21
tion of a 47 resistor and a 10 nF capacitor to V
(see Figure 14. S–Parameter Test Circuit).
ground
where: I ∆ I = I S S –S I.
S
CC
11 22 12 21
2
1/2
I
MAG = 10 log I S I/I S I + 10 log I K–(K –1)
21 12
where: K >1. The necessary and sufficient conditions for
unconditional stability are given as K>1:
The S–parameters are in polar form a the magnitude (MAG)
and angle (ANG). Also listed in the tables are the calculated
2
2
2
B1 = 1 + I S I – I S I – I ∆ I > 0
11 22
Figure 14. S–Parameter Test Circuit
1.0n
C15
SMA
1.0n
47
IF
Input
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
IN2
C2
DEC1
DEC2
V
V
1
V
1
EE
CC
EE
1.0n
100n
10µ
+
RSSI
Buffer
DETO1
DETO2
RSSI
V
2
V
2
CC
EE
SMA
IF
Output
LIMO1
LIMO2
1.0n
1.0n
47
QUAD1
QUAD2
Page 6 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
S–Parameters (V
= – 5.0 Vdc, T = 25°C, C and C = 0 pF)
15
EE
Input S11
A
2
Frequency
Forward S21
Rev S12
Output S22
MAG
K
MAG
dB
32
MHz
1.0
2.0
5.0
7.0
10
MAG
0.94
0.78
0.48
0.59
0.75
0.95
0.98
0.95
0.93
0.91
0.87
0.89
0.61
0.56
0.54
ANG
–13
–2 3
1.0
MAG
ANG
143
109
51
MAG
ANG
7.0
ANG
– 22
– 31
–17
–13
–1.0
0
MAG
2.2
8.2
23.5
39.2
40.3
40.9
42.9
42.2
39.8
44.2
39.5
34.9
11.1
3.5
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.002
0.022
0.03
0.87
0.64
0.34
0.33
0.41
0.45
0.52
0.54
0.53
0.50
0.42
0.40
0.52
0.47
0.44
– 40
– 97
– 41
– 82
– 42
– 9.0
112
80
4.2
33.5
33.7
34.6
36.7
46.4
–
8.7
15
34
10.6
5.7
17
19
20
7.0
– 6.0
– 48
– 68
– 93
–139
–179
– 58
–164
92
1.05
0.29
1.05
0.76
0.94
0.97
0.75
2.6
50
–10
–16
–2 3
–3 4
–4 7
–103
–156
162
131
– 3.0
–16
– 22
– 34
– 44
–117
179
112
70
46.4
–
100
150
200
500
700
900
1000
106
77
–
–
57
–
0
13.7
4.5
0.4
1.2
0.048
0.072
– 44
– 48
4.7
0.8
42
76
5.1
S–Parameters (V
= – 5.0 Vdc, T = 25°C, C and C = 100 pF)
15
EE
Input S11
A
2
Frequency
Forward S21
Rev S12
Output S22
K
MAG
1.2
6.0
4.2
3.1
2.4
2.4
2.3
2.2
1.3
1.4
1.3
1.7
6.3
13.3
12.5
MAG
dB
MHz
1.0
2.0
5.0
7.0
10
MAG
0.98
0.50
0.87
0.90
0.92
0.92
0.91
0.91
0.91
0.90
0.86
0.80
0.62
0.56
0.54
ANG
–15
MAG
ANG
174
MAG
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.002
0.012
0.013
0.020
0.034
ANG
–14
–108
100
– 40
– 40
– 87
85
MAG
0.84
0.62
0.47
0.45
0.44
0.49
0.50
0.52
0.50
0.43
0.43
0.57
0.49
0.44
0.44
ANG
– 27
– 35
– 9.0
– 8.0
– 5.0
– 6.0
– 5.0
– 4.0
–11
11.7
39.2
39.9
40.4
41
37.4
35.5
39.2
40.3
41.8
41.9
42
– 2.0
8.0
85.5
19
5.0
9.0
3.0
1.0
20
– 2.0
– 8.0
–11
42.4
41.2
39.1
43.4
38.2
35.5
8.3
–14
50
– 45
– 63
– 84
–126
–160
– 9.0
– 95
–171
154
70
76
41.6
43.6
41.8
39.4
23.5
12.5
2.8
100
150
200
500
700
900
1000
–15
85
– 22
– 33
– 66
– 96
–120
–136
96
– 22
– 21
– 63
–111
–150
–179
78
75
2.9
50
1.0
53
0.69
65
– 0.8
Page 7 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
S–Parameters (V
= – 5.0 Vdc, T = 25°C, C and C = 680 pF)
15
EE
Input S11
A
2
Frequency
Forward S21
Rev S12
MAG
Output S22
MAG
K
MAG
0.58
1.4
MAG
dB
MHz
1.0
2.0
5.0
7.0
10
MAG
0.74
0.90
0.91
0.91
0.91
0.91
0.90
0.90
0.91
0.94
0.95
0.82
0.66
0.56
0.54
ANG
4.0
MAG
ANG
110
55
ANG
101
60
ANG
– 35
– 34
– 60
– 67
– 67
–15
53.6
70.8
87.1
90.3
92.4
95.5
89.7
82.6
77.12
62.0
56.9
12.3
3.8
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.003
0.007
0.014
0.028
0.048
0.97
0.68
0.33
0.25
0.14
0.12
0.24
0.33
0.42
0.42
0.33
0.44
0.40
0.39
0.41
–
3.0
45.6
49
0
21
–121
–18
33
1.1
0
11
1.2
48.4
47.5
48.2
46.5
47.4
49
– 2.0
– 4.0
– 8.0
–10
–14
– 20
– 33
– 63
– 98
–122
–139
2.0
1.5
20
–16
– 50
–70
–93
–122
–148
–12
–107
177
141
63
1.3
50
– 43
92
26
1.8
70
21
1.4
100
150
200
500
700
900
1000
23
–1.0
– 22
– 62
– 67
–115
–166
165
1.05
0.54
0.75
1.8
96
–
146
79
–
26.9
14.6
4.7
84
4.8
1.3
78
8.0
0.87
76
7.4
0.96
S–Parameters (V
= – 3.0 Vdc, T = 25°C, C and C = 0 pF)
15
EE
Input S11
A
2
Frequency
Forward S21
Rev S12
Output S22
K
MAG
3.2
3.5
10.6
9.1
5.7
0.94
1.4
2.2
3.0
1.7
2.4
2.4
3.0
5.1
7.5
MAG
dB
MHz
1.0
2.0
5.0
7.0
10
MAG
0.89
0.76
0.52
0.59
0.78
0.95
0.96
0.93
0.91
0.86
0.81
0.70
0.62
0.39
0.44
ANG
–14
– 22
5.0
MAG
ANG
136
105
46
MAG
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.003
0.015
0.049
0.11
ANG
2.0
MAG
0.84
0.67
0.40
0.40
0.40
0.51
0.48
0.52
0.51
0.49
0.55
0.40
0.40
0.25
0.33
ANG
– 27
– 37
–13
9.3
30.7
34.3
33.3
34.6
36.3
–
24.2
35.7
38.1
37.2
38.2
39.1
36.8
34.7
33.8
27.8
6.2
– 90
– 32
– 41
– 92
47
12
34
–10
15
16
–1.0
– 4.0
– 6.0
–13
20
5.0
– 9.0
– 50
– 71
– 99
–143
86
50
–11
–17
– 25
– 37
– 49
– 93
–144
–176
166
–103
– 76
–152
53
43.7
41.4
39.0
39.1
35.1
19.5
8.25
–1.9
– 4.8
70
100
150
200
500
700
900
1000
–19
– 34
– 56
–110
–150
163
76
– 41
–133
125
80
93
1.9
56
0.72
0.49
–18
– 52
0.10
127
Page 8 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
S–Parameters (V
= – 3.0 Vdc, T = 25°C, C and C = 100 pF)
15
EE
Input S11
A
2
Frequency
Forward S21
Rev S12
MAG
Output S22
MAG
K
MAG
1.4
6.0
3.4
2.3
2.0
1.9
2.3
2.3
1.7
1.6
1.7
1.9
4.1
10.0
15.4
MAG
dB
MHz
1.0
2.0
5.0
7.0
10
MAG
0.97
0.53
0.88
0.90
0.92
0.92
0.91
0.91
0.91
0.89
0.86
0.78
0.64
0.54
0.53
ANG
–15
MAG
ANG
171
80
ANG
– 4.0
– 91
– 9.0
–11
– 59
29
ANG
– 27
– 31
– 7.0
– 7.0
– 9.0
– 3.0
– 7.0
– 8.0
–13
11.7
37.1
37.7
37.7
38.3
39.6
38.5
36.1
39.6
34.4
32
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.002
0.013
0.027
0.040
0.043
0.84
0.57
0.48
0.49
0.51
0.48
0.51
0.50
0.52
0.48
0.40
0.46
0.42
0.35
0.38
36.8
34.8
39.7
41
2.0
7.0
18
5.0
8.0
2.0
1.0
41.8
42.5
41.4
40.8
37.8
40.1
37.8
22.1
10.1
– 0.14
– 4.52
20
– 2.0
– 8.0
–11
–15
– 46
– 64
– 85
–128
–163
–12
–102
179
144
50
– 21
49
70
100
150
200
500
700
900
1000
–15
114
120
86
– 22
– 33
– 64
– 98
–122
–136
– 23
– 26
– 71
–109
–147
–171
7.6
94
2.3
58
0.78
0.47
38.6
23
S–Parameters (V
= – 3.0 Vdc, T = 25°C, C and C = 680 pF)
15
EE
Input S11
A
2
Frequency
Forward S21
MAG ANG
Rev S12
Output S22
K
MAG
1.1
MAG
dB
MHz
1.0
2.0
5.0
7.0
10
MAG
0.81
0.90
0.91
0.90
0.91
0.91
0.90
0.90
0.91
0.93
0.90
0.79
0.65
0.56
0.55
ANG
3.0
MAG
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.001
0.003
0.008
0.016
0.031
0.50
ANG
–19
– 82
104
– 76
105
59
MAG
0.90
0.66
0.37
0.26
0.18
0.11
0.22
0.29
0.36
0.35
0.17
0.44
0.38
0.38
0.41
ANG
– 32
– 39
– 56
– 55
– 52
–13
33
37
101
52.7
20
43.5
–
2.0
47.8
58.9
60.3
61.8
63.8
60.0
56.5
52.7
44.5
41.2
7.3
0.72
2.3
0
44
–1
11
2.04
2.2
44
– 2.0
– 4.0
– 8.0
–11
3.0
43.9
44.1
43.7
43.2
43
20
– 15
– 48
– 67
– 91
–126
–162
–13
–107
174
137
2.0
50
96
2.3
70
113
177
155
144
80
15
2.3
100
150
200
500
700
900
1000
–14
– 21
– 43
– 65
– 97
–122
–139
5.0
2.0
–17
– 31
– 75
–124
–174
157
1.8
42.7
34.1
22
1.6
3.0
2.3
86
7.1
10.2
0.37
– 3.4
0.80
0.52
73
12
71
11.3
Page 9 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
DC BIASING CONSIDERATIONS
and its output voltage swing is adjusted by selection of the resistor
The DC biasing scheme utilizes two VCC connections (Pins 3 and
6) and two V connections (Pins 14 and 11). V 1 (Pin 14) is
from Pin 12 to V . The RSSI slope is typically 2.1 µA/dB; thus,
EE
for a dynamic range of 35 dB, the current output is approximately
74 µA. A 47 k resistor will yield an RSSI output voltage swing of
3.5 Vdc. The RSSI buffer output at Pin 13 is an emitter–follower
EE
EE
connected internally to the IF and RSSI circuits’ negative supply bus
while the V 2 (Pin 11) is connected internally to the quadrature
EE
detector’s negative bus. Under positive ground operation, this
unique configuration offers the ability to bias the RSSI and IF sepa-
rately from the quadrature detector. When two ICs are cascaded as
shown in the 70 MHz application circuit and provided by the PCB
(see Figures 17 and 18), the first ML13155 is used without biasing
its quadrature detector, thereby saving approximately 3.0 mA. A
total current of 7.0 mA is used to fully bias each IC, thus the total
and needs an external emitter resistor of 10 k to V
.
EE
In a cascaded configuration (see circuit application in Figure 16),
only one of the RSSI Buffer outputs (Pin 13) is used; the RSSI out-
puts (Pin 12 of each IC) are tied together and the one closest to the
V
supply trace is decoupled to VCC ground. The two pins are
EE
connected to V through a 47 k resistor. This resistor sources a
EE
current in the application circuit is approximately 11 mA. Both V
pins are biased by the same supply. V 1 (Pin 3) is connected inter-
CC
nally to the positive bus of the first half of the IF limiting amplifier,
RSSI current which is proportional to the signal level at the IF input;
typically 1.0 mVms (–47 dBm) is required to place the ML13155
into limiting. The measured RSSI output voltage response of the
application circuit is shown in Figure 12. Since the RSSI current
output is dependent upon the input signal level at the IF input, a
careful accounting of filter losses, matching and other losses and
gains must be made in the entire receiver system. In the block dia-
gram of the application circuit shown below, an accounting of the
signal levels at points throughout the system shows how the RSSI
response in Figure 12 is justified.
CC
while V 2 is internally connected to the positive bus of the RSSI,
CC
the quadrature detector circuit, and the second half of the IF limiting
amplifier (see Figure 15). This distribution of the V
stability of the IC.
enhances the
CC
RSSI CIRCUITRY
The RSSI circuitry provides typically 35 dB of linear dynamic range
Block Diagram of 70 MHz Video Receiver Application Circuit
Input
Level:
– 45 dBm
1.26 mVrms
– 70 dBm
71 Vrms
– 72 dBm
57 Vrms
– 32 dBm
57 Vrms
– 47 dBm
1.0 mVrms
Minimum Input to Acquire
Limiting in ML13155
µ
µ
µ
IF
Input
16
1
16
1
10
7
Saw
Filter
ML13155
ML13155
1:4
Transformer
2.0 dB
(Insertion Loss)
– 25 dB
(Insertion Loss)
40 dB Gain
–15 dB
(Attenuator)
40 dB Gain
CASCADING STAGES
selecting the insertion loss. A network topology shown below may
The limiting IF output is pinned–out differentially, cascading is easi- be used to provide a bandpass response with the desired insertion loss.
ly achieved by AC coupling stage to stage. In the evaluation PCB,
AC coupling is shown, however interstage filtering may be desirable
in some application. In which case, the S–parameters provide a
means to implement a low loss interstage match and better receiver
Network Topology
1.0n
sensitivity.
10
7
16
1
Where a linear response of the RSSI output is desired when cascad-
ing the ICs, it is necessary to provide at least 10 dB of interstage
loss. Figure 12 shows the RSSI response with and without interstage
loss. A 15 dB resistive attenuator is an inexpensive way to linearize
the RSSI response. This has its drawbacks since it is a wideband
noise source that is dependent upon the source and load impedance
and the amount of attenuation that it provides. A better, although
more costly, solution would be a bandpass filter designed to the
desired center frequency and bandpass response while carefully
0.22µ
1.0n
Page 10 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
The value of the total damping resistor to obtain the required
loaded Q of 5 can be calculated by rearranging Equation 1:
RT = Q(2πfl)
QUADRATURE DETECTOR
The quadrature detector is coupled to the IF with internal 2.0
pF. capacitors between Pins 7 and 8 and Pins 9 and 10. For
wideband data applications, such as FM video and satellite
receivers, the drive to the the detector can be increased with
additional external capacitors between these pins, thus, the
recovered video signal level output is increased for a given
bandwidth (see Figure 11A and Figure 11B).
RT = 5(2π)(70)(0.22) - 483.8 Ω
The internal resistance, Rint between the quadrature tank Pins
8 and 9 is approximately 3200 Ω and is considered in deter-
mining the external resistance, Rext which is calculated from:
Rext = ((R )(Rint))/(Rint–R )
T
T
Rext = 570, thus, choose the standard value
Rext = 560 Ω
The wideband performance of the detector is controlled by
the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's band-
width:
SAW FILTER
In wideband video data applications, the IF occupied band-
(1) width may be several MHz wide. A good rule of thumb is to
choose the IF frequency about 10 or more times greater than
Q=R /X
T L
where: R is the equivalent shunt resistance across the LC
T
Tank and X is the reactance of the quadrature inductor at the the IF occupied bandwidth. The IF bandpass filter is a SAW
L
IF frequency (X = 2πfL).
filter in video data applications where a very selective
response is needed (i.e., very sharp bandpass response). The
L
The inductor and capacitor are chosen to form a resonant LC evaluation PCB is laid out to accommodate two SAW filter
Tank with the PCB and parasitic device capacitance at the
package types: 1) A five–leaded plastic SIP package.
desired IF center frequency as predicted by:
–1
Recommended part numbers are Siemens X6950M which
operates at 70 MHz; 10.4 Mhz 3 dB passband, X6951M
(X252.8) which operates at 70 Mhz; 9.2 MHz 3 dB passband;
and X6958M which operates at 70 MHz, 6.3 MHz 3 dB pass-
band, and 2) A four–leaded TO–39 metal can package.
Typical insertion loss in a wide bandpass SAW filter is 25 dB.
(2)
fc = (2π √(LC ))
p
where: L is the parallel tank inductor and C is the equivalent
p
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a wideband detector at
70 MHz and a loaded Q of 5. The loaded Q of the quadrature
detector is chosen somewhat less than the Q of the IF band-
pass. For an IF frequency of 70 MHz and an IF bandpass of
10.9 MHz, the IF bandpass Q is approximately 6.4.
The above SAW filters require source and load impedances of
50 Ω to assure stable operation. On the PC board layout,
space is provided to add a matching network, such as a 1:4
surface mount transformer between the SAW filter output and
the input to the ML13155. A 1:4 transformer, made by
Coilcraft and Mini Circuits, provides a suitable interface (see
Figures 16, 17 and 18). In the circuit and layout, the SAW fil-
ter and the ML13155 are differentially configured with inter-
connect traces which are equal in length and symmetrical.
This balanced feed enhances RF stability, phase linearity, and
noise performance.
Example:
Let thE external Cext = 20 pF. (The minimum value here
should be greater than 15 pF making it greater than the inter-
nal device and PCB parasitic capacitance. Cint ≈ 3.0 pF).
C = Cint + Cext = 23 pF
p
Rewrite Equation 2 and solve for L:
2
2
L = (0.159) /(C fc )
p
L = 198 nH, thus, a standard value is chosen.
L = 0.22 µH (tunable shielded inductor).
Page 11 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
Page 12 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
Figure 16. 70 MHz Video Receiver Application Circuit
If Input
1:4
1
5
4
SAW Filter
2
3
220
SAW Filter is Siemens
Part Number X6950M
1.0n
1.0n
RSSI
Output
ML13155
1
2
3
4
5
6
7
8
IN1
DEC1
IN2 16
DEC2 15
10k
100p
100p
10n
V
1
V
1
14
13
CC
EE
RSSI
Buffer
47k
DETO1
DETO2
100n
RSSI 12
11
LIMO2 10
1.0n
10n
V
2
V
2
CC
EE
LIMO1
QUAD1
QUAD2
9
V
1
EE
10µ
+
820
820
820
820
1.0n
1.0n
ML13155
1
2
3
4
5
6
7
8
IN1
IN2 16
DEC1
DEC2 15
100p
100p
10n
V
1
V
1
14
13
CC
EE
100n
RSSI
Buffer
DETO1
DETO2
Detector
Output
33p 1.0k
33p
RSSI 12
11
LIMO2 10
QUAD2
1.0k
100n
V
2
V
2
V
2
CC
EE
EE
10µ
10n
+
LIMO1
2.0p
2.0p
QUAD1
9
560
20p
L
L– Coilcraft part number 146–08J08S
0.22µ
Page 13 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 17. Component Placement (Circuit Side)
Figure 18. Component Placement (Ground Side)
Page 14 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 19. Circuit Side View
4.0"
4.0"
Figure 20. Ground Side View
Page 15 of 16
www.lansdale.com
Issue A
ML13155
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SO–16 = -5P
(ML13155-5P)
PLASTIC PACKAGE
CASE 751B
(SO–16)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. 751B–03 IS OBSOLETE, NEW STANDARD
751B–04.
–A
–
16
1
9
8
M
M
0.25 (0.010)
B
–B
–
P
C
8 PL
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
G
R X 45
F
1.25
1.27 BSC
0.050 BSC
G
J
K
M
P
R
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
–T
–
J
M
F
D
16 PL
K
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 16 of 16
www.lansdale.com
Issue A
相关型号：
©2020 ICPDF网 联系我们和版权申明