ML13158 [LANSDALE]
Wideband FM IF Subsystem For Dect and Digital Applications; 宽带调频中频子系统，用于DECT和数字应用
| 型号： | ML13158 |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Wideband FM IF Subsystem For Dect and Digital Applications |
| 文件： | 总23页 (文件大小：1006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML13158
Wideband FM IF Subsystem
For Dect and Digital Applications
Legacy Device: Motorola MC13158
The ML13158 is a wideband IF subsystem that is designed for high per-
formance data and analog applications. The ML13158 has an on–board
grounded collector VCO transistor that may be used with a fundamental
or overtone crystal in single channel operation or with a PLL in
multi–channel operation. The mixer is useful to 500 MHz and may be
used in a balanced differential or a single ended configuration. The IF
amplifier is split to accommodate two low cost cascaded filters. RSSI
output is derived by summing the output of both IF sections. A precision
data shaper has an Off function to shut the output off to save current. An
enable control is provided to power down the IC for power management
in battery operated applications.
QFP 32 = 8P
PLASTIC QFP PACKAGE
CASE 873
CROSS REFERENCE/ORDERING INFORMATION
Applications include DECT, wideband wireless data links for personal
and portable laptop computers and other battery operated radio systems
which utilize GFSK, FSK or FM modulation.
PACKAGE
MOTOROLA
LANSDALE
QFP 32
MC13158FTB
ML13158-8P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Designed for DECT Applications
• 1.8 to 6.0 Vdc Operating Voltage
• Low Power Consumption in Active and Standby Mode
• Greater than 600 kHz Detector Bandwidth
• Data Slicer with Special Off Function
• Enable Function for Power Down of Battery Operated Systems
• RSSI Dynamic Range of 80 dB Minimum
• Low External Component Count
• Operating Temperature Range – T = –40 to +85°C
A
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CIRCUIT DESCRIPTION
GENERAL
The output of this buffer has an active pull–up but no pull–down,
so it can also be used as a peak detector. The negative slew rate is
determined by external capacitance and resistance to the negative
supply.
The ML13158 is a low power single conversion wideband FM receiver
incorporating a split IF. This device can be used as the backend in digi-
tal FM systems such as Digital European Cordless Telephone (DECT)
and wide band data links with data rates up to 2.0 Mbps. It contains a
mixer, oscillator, Received Signal Strength Indicator (RSSI), IF ampli-
fier, limiting IF, quadrature detector, power down or enable function,
and a data slicer with output off function. Further details are covered in
the Pin Function Description which shows the equivalent internal cir-
cuit and external circuit requirements.
IF AMPLIFIER
The first IF amplifier section is composed of three differential
stages with the second and third stages contributing to the RSSI.
This section has internal DC feedback and external input decou-
pling for improved symmetry and stability. The total gain of the IF
amplifier block is approximately 40 dB at 10.7 MHz.
CURRENT REGULATION
Temperature compensating voltage independent current regulators
which are controlled by the enable pin (Pin 25) where “low” pow-
ers up and “high” powers down the entire circuit.
The fixed internal input impedance is 330 Ω. When using ceramic
filters requiring source and loss impedances of 330 Ω, no external
matching is necessary. Overall RSSI linearity is dependent on hav-
ing total midband attenuation of 10 dB (4.0 dB insertion loss plus
6.0 dB impedance matching loss) for the filter. The output of the IF
amplifier is buffered and the impedance is 330 Ω.
MIXER
The mixer is a double–balanced four quadrant multiplier and is
designed to work up to 500 MHz. It can be used in differential or
in single–ended mode by connecting the other input to the positive
supply rail. The linear gain of the mixer is approximately 22 dB at
100 mVrms LO drive level. The mixer gain and noise figure have
been emphasized at the expense of intermodulation performance.
RSSI measurements are added in the mixer to extend the range to
higher signal levels. The single–ended parallel equivalent input
impedance of the mixer is Rp ~ 1.0 kΩ and Cp ~ 2.0 pF. The
buffered output of the mixer is internally loaded resulting in an out-
put impedance of 330 Ω.
LIMITER
The limiter section is similar to the IF amplifier section except that
five differential stages are used. The fixed internal input impedance
is 330 Ω. The total gain of the limiting amplifier section is approxi-
mately 70 dB. This IF limiting amplifier section internally drives
the quadrature detector section and it is also brought out on Pin 12.
QUADRATURE DETECTOR
The quadrature detector is a doubly balanced four quadrant multi-
plier with an internal 5.0 pF quadrature capacitor between Pins 12
and 13. An external capacitor may be added between these pins to
increase the IF signal to the external parallel RLC resonant circuit
that provides the 90 degree phase shift and drives the quadrature
detector. A single pin (Pin 13) provides for the external LC parallel
resonant network and the internal connection to the quadrature
detector.
LOCAL OSCILLATOR
The on–chip transistor operates with crystal and LC resonant ele-
ments up to 220 MHz. Series resonant, overtone crystals are used
to achieve excellent local oscillator stability. Third overtone crys-
tals are used through about 65 to 70 MHz. Operation from 70 MHz
up to 180 MHz is feasible using the on–chip transistor with a 5th
or 7th overtone crystal. To enhance operation using an overtone
crystal, the internal transistor bias is increased by adding an exter-
Internal low pass filter capacitors have been selected to control the
bandwidth of the detector. The recovered signal is brought out by
the inverting amplifier buffer. An external feedback resistor from
the output (Pin 17) to the output amplitude; it is combined with
another external resistor from the input to the negative supply (Pin
15) controls the output amplitude; it is combined with another
external resistor from the input to the negative supply (Pin 16) to
set the output DC level. For a resistor ratio of 1, the DC level at the
nal resistor from Pin 29 to V , however, with an external resistor,
EE
the oscillator stays on during power down. Typically, –10 dBm of
local oscillator drive is needed to adequately drive the mixer. With
an external oscillator source, the IC can be operated up to 500
MHz.
RSSI
The Received Signal Strength Indicator (RSSI) output is a current
proportional to the log of the received signal amplitude. The RSSI
current output is derived by summing the currents from the mixer,
IF and limiting amplifier stages. An increase in RSSI dynamic
range, particularly at higher input signal levels is achieved. The
RSSI circuit is designed to provide typically 85 dB of dynamic
range with temperature compensation.
detector output is 2.0 V
across the first resistor (from Pin 17 to 15) can be used to reduce
the bandwidth.
(see Figure 12). A small capacitor C
17
BE
DATA SLICER
The data slicer is a comparator that is designed to square up the
data signal. Across the data slicer inputs (Pins 18 and 20) are back
to back diodes.
Linearity of the RSSI is optimized by using external ceramic band-
pass filters which have an insertion loss of 4.0 dB and 330 Ω
source and load impedance. For higher data rates used in DECT
and related applications, LC bandpass filtering is necessary to
acquire the desired bandpass response; however, the RSSI linearity
will require the same insertion loss.
The recovered data signal from the quadrature detector can be DC
coupled to the data slicer DS IN1 (Pin 18). In the application cir-
cuit shown in Figure 1 it will be centered at 2.0 V
and allowed
. A capacitor is placed from DS IN2 (Pin 20) to
BE
to swing
EE
V
BE
V
. The size of this capacitor and the nature of the data slicer
shapes up the recovered signal. The time constant is short for large
peak to peak voltage swings or when there is a change in DC level
at the detector output. For small signal or for continuous bits of the
same polarity which drift close to the threshold voltage, the time
RSSI BUFFER
The RSSI output current creates a voltage across an external resis-
tor. A unity voltage–gain amplifier is used to buffer this voltage.
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ML13158
constant is longer.
shut off by shutting down the base drive to the output transistor.
When a channel is being monitored to make an RSSI measurement,
A unique feature of the data slicer is that inverting switching stages but not to collect data, the data output may be shut off to save cur-
in the comparator are supplied through the emitter pin of the output rent.
transistor (Pin 22 – DS Gnd) to V rather than internally to V
.
EE EE
This is provided in order to reduce switching feedback to the front
end. A control pin is provided to shut the data slicer output off (DS
“off” – Pin 19). With DS “off” pin at V
the data slicer output is
CC
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Legacy Applications Information
APPLICATIONS INFORMATION
EVALUATION PC BOARD
COMPONENT SELECTION
The evaluation PCB is very versatile and is intended to be used
across the entire useful frequency range of this device. The center
section of the board provides an area for attaching all SMT compo-
The evaluation PC board is designed to accommodate specific
components, while also being versatile enough to use components
from various manufacturers and coil types. Figures 13 and 14 show
nents to the circuit side and radial leaded components to the compo- the placement for the components specified in the application cir-
nent ground side (see Figures 29 and 30). Additionally, the peripher- cuit (Figure 12). The application circuit schematic specifies particu-
al area surrounding the RF core provides pads to add supporting and lar components that were used to achieve the results shown in the
interface circuitry as a particular application requires. This evalua-
tion board will be discussed and referenced in this section.
typical curves and tables but alternate components should give sim-
ilar results.
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Legacy Applications Information
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INPUT MATCHING/COMPONENTS
kΩ in parallel with 2.0 pF; thus, no or little input matching is
required between the SAW filter and the mixer.
It is desirable to use a SAW filter before the mixer to provide addi-
tional selectivity and adjacent channel rejection. In a wideband sys-
tem the primary sensitivity of the receiver backend may be
The Siemens SAW filter has an insertion loss of typically 10 dB
achieved before the last mixer. Bandpass filtering in the limiting IF and a 3.0 dB bandwidth of 1.0 MHz. The relatively high insertion
is costly and difficult to achieve for bandwidths greater than 280
kHz.
loss significantly contributes to the system noise and a filter having
lower insertion loss would be desirable. In existing low loss SAW
filters, the required load impedance is 50 Ω; thus, interface match-
ing between the filter and the mixer will be required. Figure 15 is a
The SAW filter should be selected to easily interface with the
mixer differential input impedance of approximately 2.0 kΩ in par- table of the single–ended mixer input impedance. A careful noise
allel with 1.0 pF. The PC board is dedicated to the Siemens SAW
analysis is necessary to determine the secondary contribution to
filter (part number Y6970M); the part is designed for DECT at 112 system noise.
MHz 1st IF frequency. It is designed for a load impedance of 2.0
SYSTEM NOISE CONSIDERATIONS
The system block diagram in Figure 16 shows the cascaded noise
F3 = the Noise factor of the Mixer
Note: the proceeding terms are defined as linear relationships and
stages contributing to the system noise; it represents the application are related to the log form for gain and noise figure by the follow-
circuit in Figure 12 and a low noise preamp using a MRF941 trans- ing:
–1
F = log [(NF in dB)/10] and similarly
lator (see Figure 17). The preamp is designed for a conjugately
matched input and output at 2.0 Vdc. V and 3.0 mAdc I . S-
CE
c
–1
parameters at 2.0 V, 3.0 mA and 100 MHz are:
G = log [(NF in dB)/10]
S11 = 0.86, –20
S21 = 9.0, 164
S12 = 0.02, 79
S22 = 0.96, –12
The noise figure and gain measured in dB are shown in the system
block diagram. The mixer noise figure is typically 14 dB and the
SAW filter adds typically 10 dB insertion loss. Addition of a low
noise preamp having a 18 dB gain and 2.7 dB noise figure not only
improves th system noise figure but it increases the reverse isola-
tion from the local oscillator to the antenna input at the receiver.
Calculating in terms of gain and noise factor yields the following:
F1 = 1.86; G1 = 63.1
The bias network and V at 2.0 V and I at 3.0 mA for V = 3.0
CE
c
CC
to 3.5 Vdc. The preamp operates with 18 dB gain and 2.7 dB noise
figure.
In the cascaded noise analysis the system noise equation is:
Fsystem = F1 + [(F2–1)/G1] + [(F3–1)]/[(G1)(G2)]
where:
F2 = 10; G2 = 0.1
F1 = the Noise Factor of the Preamp
G1= the Gain of the Preamp
F2 = the Noise factor of the SAW filter
G2 = the Gain of the SAW filter
F3 = 25.12
Thus, substituting in the equation for system noise factor:
Fsystem = 5.82; NFsystem = 7.7 dB
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Legacy Applications Information
LOCAL OSCILLATORS
VHF APPLICATIONS
The on–chip grounded collector transistor may be used for HF and
VHF local oscillator with higher order overtone crystals. The local
traces and tap capacitors. Parasitic oscillations often occur in the
200 to 800 MHz range. A small resistor is placed in series with the
base (Pin 28) to cancel the negative resistance associated with this
oscillator in the application circuit (Figure 12) shows a 5th overtone undesired mode of oscillation. Since the base input impedance is so
oscillator at 122.7 MHz. This circuit uses a Butler overtone oscilla- large a small resistor in the range of 27 to 68 Ω has very little effect
tor configuration. The amplifier is an emitter follower. The crystal
is driven from the emitter and is coupled to the high impedance
base through a capacitive tap network. Operation at the desired
overtone frequency is ensured by the parallel resonant circuit
formed by the variable inductor and the tap capacitor and parasitic
capacitances of the on–chip transistor and PC board. The variable
inductor specified in the schematic could be replaced with a high
tolerance, high Q ceramic or air wound surface mount component
if the other components have tight enough tolerances. A variable
on the desired Butler mode of oscillation.
The crystal parallel capacitance, C , provides a feedback path that
o
is low enough in reactance at frequencies of 5th overtones or higher
to cause trouble. C has little effect near resonance because of the
o
low impedance of the crystal motional arm (R –L –C ). As the
m
m
m
tunable inductor which forms the resonant tank with the tap capaci-
tors is tuned “off” the crystal resonant frequency it may be difficult
to tell if the oscillation is under crystal control. Frequency jumps
inductor provides an adjustment for gain and frequency of the reso- may occur as the inductor is tuned. In order to eliminate this behav-
nant tank ensuring lock up and start– up of the crystal oscillator. ior an inductor, L , is placed in parallel with the crystal. L is cho-
The overtone crystal is chosen with ESR of typically 80 Ω and 120 sen to be resonant with he crystal parallel capacitance, C , at the
o
o
o
Ω maximum; if the resistive loss in the crystal is too high the per-
formance of oscillator may be impacted by lower gain margins.
desired operation frequency. The inductor provides a feedback path
at frequencies well below resonance; however, the parallel tank net-
work of the tap capacitors and tunable inductor prevent oscillation
A series LC network to ground (which is V ) is comprised of the at these frequencies.
CC
inductance of the base lead of the on–chip transistor and PC board
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Legacy Applications Information
IF FILTERING/MATCHING
Substitue for Requivalent and solve for Rext
In wideband data systems the IF bandpass needed is greater than
can be found in low cost ceramic filters operating at 10.7 MHz. It
is necessary to bandpass limit with LC networks or series–parallel
ceramic filter networks. Murata offers a series–parallel resonator
pair (part number KMFC545) with a 3.0 dB band width of 325
kHz and a maximum insertion loss of 5.0 dB. The application PC
board is laid out to accommodate this filter pair (a filter pair is used
at both locations of the split IF). However, even using a series par-
allel ceramic filter network yields only a maximum bandpass of
650 kHz. In some applications a wider band IF bandpass is neces-
sary.
330(Rext) = 110 (Rext) + (330)(110)
Rext = (330)(110)/220
Rext - 165 Ω
The IF is 10.7 Mhz although any IF between 10 to 20 MHz could
be used. The value of the coil is lowered from that used in the
quadrature circuit because the unloaded Q must be maintained in a
surface mount component. A standard value component having an
unloaded Q = 100 at 10.7 MHz is 330 nH; therefore the capacitor
is 669 pF. Standard values have been chosen for these components;
Rext = 150 Q
C = 680 pF
L = 330 nH
A simple LC network yields a bandpass wider than the SAW filter
but it does reduce an appreciable amount of wideband IF noise. In
the application circuit an LC network is specified using surface
mount components. The parallel LC components are placed from
Computation of the loaded Q of the is LCR network is
Q = Requivalent/X
L
where XL = 2πfl and Requivalent is 103 Ω
Thus, Q = 4.65
the outputs of the mixer and IF amplifier to the V
trace; internal
The total system loss is
CC
330Ω loads are connected from the mixer and IF amplifier outputs
DEC2 (Pin 5 and 10 respectively). This loads the outputs with the
optimal load impedance but creates a low insertion loss filter. An
external shunt resistor may be used to widen the bandpass and to
acquire the 10 dB composite loss necessary to linearize the RSSI
output. The equivalent circuit is shown in Figure 18.
20 log (103/433) = –12.5 dB
QUADRATURE DETECTOR
The quadrature detector is coupled to the IF with an internal 5.0 pF
capacitor between Pins 12 and 13. For wideband data applications,
the drive to the detector can be increased with an additional exter-
nal capacitor between these pins; thus, the recovered signal level
output is increased for a given bandwidth.
The wideband performance of the detector is controlled by the
loaded Q of the LC tank circuit. The following equation defines the
components which set the detector circuit’s bandwidth:
Q = R /X
[1]
T L
where RT is the equivalent shunt resistance across the LC Tank
XL is the reactance of the quadrature inductor at the IF fre-
quency (X = 2πfl).
L
The inductor and capacitator are chosen to form a resonant LC tank
with the PCB and parasitic device capacitance at the desired IF
center frequency as predicted by
1/2 –1
fc = [2π (LC )
]
[2]
p
where L is the parallel tank inductor Cp is the equivalent parallel
capacitance of the parallel resonant tank circuit.
The following is a design example for a wideband detector at 10.7
MHz and a loaded Q of 18. The loaded Q of the quadrature detec-
tor is chosen somewhat less than the Q of the IF bandpass. For an
IF frequency of 10.7 MHz and an IF bandpass of 600 kHz, the IF
bandpass Q is approximately 6.4.
The following equations satisfy the 12 dB loss
(1:4 resistive ratio):
(Rext)(330)/(Rext + 330) = Requivalent
Requivalent/Requivalent + 330) = 1/4
Solve for Requivalent:
4(Requivalent) = Requivalent + 330
3(Requivalent) = 330
Requivalent = 110
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Legacy Applications Information
EXAMPLE:
Let the external Cext = 139 pF. (The miminum value here should
be much greater than the internal device and PCB parasitic capaci-
tance, Cint = 3.0 pF.). Thus, Cp = Cint + Cext = 142 pF.
Rewrite equation (2) and solve for L
2
2
L = (0.159) /(Cpfc )
L = 1.56 µH; Thus, a standard value is chosen:
L = 1.56 µH (tunable shielded inductor)
The value of the total damping resistor to obtain the required
loaded Q of 18 can be calculated by rearranging equation (1):
R = Q(2πfl)
T
R = 18(2π)(10.7)(1.5) = 1815Ω
T
The internal resistance, Rint at the quadrature tank Pin 13 is
approximately 13 kΩ and is considered in determining the external
resistance, Rext which is calculated from
DATA SLICER CIRCUIT
at the input of the data slicer is chosen to maintian a time con-
Rext = ((R )(Rint))/(Rint – R )
C
20
T
T
Rext = 2110; Thus choose the standard value
Rext = 2.2 kΩ
stant long enought to hold the charge on the capacitor for the
longest strings of bits at the same polarity. For a data rate of 576
kHz a bit stream of 15 bits at the same plarity would equate to an
apparent data rate of approximately 77 kbps or 38 kHz. The time
constant would be approximately 26 µs. The following expression
equates the time constant t, to the external components;
It is important to set the DC level of the detector output at Pin 17 to
center the peak to peak swing of the recovered signal. In the equiv-
alent internal circuit shown in the Pin Function Description, the ref-
erence voltage at the positive terminal of the inverting, op amp
buffer amplifier is set at 1.0 V . The detector DC level, V is
t = 2π (R )(C )
BE
17
18 20
determined by the following equation:
Solve for C :
20
V
17
= [((R /R ) + 1 )/(R /R )] V
C
20
= t/2π (R )
15 17 15 17 BE
18
where the effective resistance R is a complex function of the
Thus for a 1:1 ratio of R /R , V = 2.0 V = 1.4 Vdc.
Similarly for a 2:1, V = 1.5 V = 1.05 Vdc; and for 3:1, V
17 BE 17
1.33 V = 0.93 Vdc.
BE
18
15 17 17 BE
demodulator feedback resistance and data slicer input circuit. In the
data input network the back to back diodes form a charge and dis-
charge path for the capacitor at Pin 20; however, the diodes create a
non–linear response. This resistance is loaded by the ß, beta of the
detector output transistor; beta = 100 is a typical value (see Figure
21). Thus, the apparent value of the resitance at Pin 18 (DS IN1) is
approximately equal to:
=
Figure 19 shows the detector “S–Curves”, in which the resistor
ratio is varied while maintaining a constant gain (R is held at 62
17
kΩ). R is 62 kΩ for a 1:1 ratio; while R = 120 kΩ and 180 kΩ
15
15
to produce the 2:1 and 3:1 ratio. The IF signal into the detector is
swept 500 KHz about the 10.7 MHz, IF center frequency. The
resulting curve show how the resistor ratio and the supply voltage
effects the symmetry of the “S–curve” (Figure 21 Test Setup). For
R
18
~ R /100
17
where R is 82 kΩ, the feedback resistor from Pin 17 to 15.
17
Therefore, substituting for R and solving for C :
18
20
C
20
= 15.9 (t)/R = 5.04 nF
the 3:1 and 2:1 ratio, symmetry is maintained with V from 2.0 to
17
S
The closest standard value is 4.7 nF.
5.0 Vdc; however, for the 1:1 ratio, symmetry is lost at 2.0 Vdc.
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Legacy Applications Information
RSSI
In Figure 22, the RSSI versus RF Input Level shows the linear
response of RSSI over a 65 dB range but it has extended capability
over 80 dB from –80 dBm to +10 dBm. The RSSI is measured in
the application circuit (Figure 12) in which a SAW filter is used
before the mixer; thus, the overall sensitivity is traded off for the
sake of selectivity. The curves are shown for three filters having
different bandwidths:
1) LCR Filter with 2.3 MHz 3.0 dBm BW (Circuit and
Component Placement is shown in Figure 12)
2) Series–Parallel Ceramic Filter with 650 kHz 3.0 dB BW
(Murata Part # KMFC - 545)
3) Ceramic Filter with 280 kHz 3.0 dB BW.
SINAD PERFORMANCE
Figure 24 shows a test setup for a narrowband demodulator output
response in which a C–message filter and an active de–emphasis
filter is used following the demodulator. The input is matched using
a 1:4 impedance transformer. The SINAD performance is shown in
Figure 25 with no preamp and in Figure 26 with a preamp
(Preamp–Figure 16). The 12 dB SINAD sensitivity is –101 dBm
with no preamp and –113 dBm with the preamp.
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Legacy Applications Information
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Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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