MC13156FB [LANSDALE]
Wideband FM IF System; 宽带FM IF系统
| 型号： | MC13156FB |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Wideband FM IF System |
| 文件： | 总21页 (文件大小：3523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML13156
Wideband FM IF System
Legacy Device: Motorola MC13156
The ML13156 is a wideband FM IF subsystem targeted at high per-
formance data and analog applications. The ML13156 has an onboard
grounded collector VCO transistor that may be used with a fundamen-
tal or overtone crystal in single channel operation or with a PLL in
multichannel operation. The mixer is useful to 500 MHz and may be
used in a balanced–differential, or single–ended configuration. The IF
amplifier is split to accommodate two low cost cascaded filters. RSSI
output is derived by summing the output of both IF sections. A preci-
sion data shaper has a hold function to preset the shaper for fast recov-
ery of new data.
SO 24W = -6P
PLASTIC PACKAGE
CASE 751E
24
(SO-24L)
1
QFP 32 = -8P
32
PLASTIC QFP PACKAGE
CASE 873
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
Applications for the ML13156 include CT–2, wideband data links
and other radio systems utilizing GMSK, FSK, or FM modulation.
SO 24W
QFP 32
MC13156DW
MC13156FB
ML13156-6P
ML13156-8P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• 2.0 to 6.0 Vdc Operation
• Typical Sensitivity at 200 MHz of 2.0 µV for 12 dB SINAD
• RSSI Dynamic Range Typically 80 dB
• High Performance Data Shaper for Enhanced CT–2 Operation
• Internal 330 Ω and 1.4 kΩ Terminations for 10.7 Mhz and 455 kHz
Filters
• Split IF for Improved Filtering and Extended RSSI Range
• 3rd Order Intercept (Input) of –25 dBm (Input Matched)
PIN CONNECTIONS
Function
SO–24L
QFP
31
RF Input 1
1
RF Input 2
2
32
Mixer Output
3
1
V
4
2
CC1
• Operating Temperature Range – T = –40 to +85°C
A
IF Amp Input
5
3
IF Amp Decoupling 1
IF Amp Decoupling 2
6
4
7
5
V
Connect (N/C Internal)
–
6
CC
IF Amp Output
8
7
Simplified Block Diagram
V
9
8
CC2
Limiter IF Input
10
11
12
–
9
LO
In
LO
Emit
CAR
Det
DS
Hold
Data
Out
DS
Gnd
DS
In
Quad
Coil
Limiter Decoupling 1
Limiter Decoupling 2
10
V
RSSI
20
V
Demod
14
EE1
22
EE2
19
11
24
23
21
18
17
16
15
13
V
Connect (N/C Internal)
12, 13, 14
CC
Quad Coil
13
14
15
–
15
16
Demodulator Output
Data Slicer Input
17
V
Connect (N/C Internal)
CC
18
Mixer
Data
Slicer
5.0
pF
Data Slicer Ground
Data Slicer Output
Data Slicer Hold
16
17
18
19
20
21
22
23
24
–
19
20
Bias
Bias
21
V
22
EE2
LIM Amp
IF Amp
RSSI Output/Carrier Detect In
23
Carrier Detect Output
24
V
and Substrate
25
EE1
LO Emitter
26
LO Base
27
1
2
3
4
5
6
7
8
9
10
11
12
V
Connect (N/C Internal)
28, 29, 30
CC
RF
In 1
RF
In 2
Mix
Out
V
IF
In
IF
IF
IF
Out
V
LIM
In
LIM
LIM
CC1
CC2
DEC 1 DEC 2
DEC 1 DEC 2
NOTE: Pin Numbers shown for SOIC package only. Refer to Pin Assignments Table.
This device contains 197 active transistors.
Page 1 of 21
www.lansdale.com
Issue A
ML13156
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS
Rating
Pin
Symbol
Value
–6.5
Unit
Vdc
°C
Power Supply Voltage
Junction Temperature
Storage Temperature Range
16, 19, 22
V
EE(max)
–
–
T
150
J(max)
T
stg
–65 to +150
°C
NOTES: 1. Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" table provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Rating
Pin
Symbol
Value
Unit
Power Supply Voltage @ T = 25°C
4, 9
16, 19, 22
V
V
EE
0 (Ground)
–2.0 to –6.0
Vdc
A
CC
–40°C ≤ T ≤ +85°C
A
Input Frequency
1, 2
–
f
500
–40 to +85
200
MHz
°C
in
Ambient Temperature Range
Input Signal Level
T
A
1, 2
V
mVrms
in
DC ELECTRICAL CHARACTERISTICS (T = 25°C, V
= V
= 0, no input signal.)
A
CC1
CC2
Pin
19, 22
Characteristic
Symbol
Min
Typ
Max
Unit
Total Drain Current (See Figure 2)
I
mA
Total
V
EE
V
EE
V
EE
V
EE
= –2.0 Vdc
= –3.0 Vdc
= –5.0 Vdc
= –6.0 Vdc
–
3.0
–
4.8
5.0
5.2
5.4
–
8.0
–
–
–
Drain Current, I (See Figure 3)
22
22
I
mA
mA
22
19
V
EE
V
EE
V
EE
V
EE
= –2.0 Vdc
= –3.0 Vdc
= –5.0 Vdc
= –6.0 Vdc
–
–
–
–
3.0
3.1
3.3
3.4
–
–
–
–
Drain Current, I (See Figure 3)
19
19
I
V
EE
V
EE
V
EE
V
EE
= –2.0 Vdc
= –3.0 Vdc
= –5.0 Vdc
= –6.0 Vdc
–
–
–
–
1.8
1.9
1.9
2.0
–
–
–
–
DATA SLICER (Input Voltage Referenced to V
EE
= –3.0 Vdc, no input signal; See Figure 15.)
Input Threshold Voltage (High V )
in
15
17
V
1.0
–
1.1
1.7
1.2
–
Vdc
mA
15
Output Current (Low V )
in
Data Slicer Enabled (No Hold)
I
17
V
15
V
18
> 1.1 Vdc
= 0 Vdc
AC ELECTRICAL CHARACTERISTICS (T = 25°C, V
circuit, unless otherwise specified.)
= –3.0 Vdc, f
= 130 MHz, f
= 140.7 MHz, Figure 1 test
A
EE
RF
LO
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
12 dB SINAD Sensitivity (See Figures 17, 23)
1, 14
–
–
–
–100
–
dBm
f
in
= 144.45 MHz; f
= 1.0 kHz; f = 75 kHz
dev
mod
MIXER
Conversion Gain
1, 3
1, 2
3
–
22
–
dB
P
in
= –37 dBm (Figure 4)
Mixer Input Impedance
Single–Ended (Table 1)
R
C
–
–
1.0
4.0
–
–
kΩ
pF
p
p
Mixer Output Impedance
–
–
330
–
Ω
IF AMPLIFIER SECTION
IF RSSI Slope (Figure 6)
IF Gain (Figure 5)
20
5, 8
5
–
–
–
–
0.2
–
0.4
39
0.6
–
µA/dB
dB
Input Impedance
–
1.4
290
–
kΩ
Output Impedance
8
–
–
Ω
Page 2 of 21
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML13156
AC ELECTRICAL CHARACTERISTICS (continued) (T = 25°C, V
circuit, unless otherwise specified.)
= –3.0 Vdc, f
= 130 MHz, f
= 140.7 MHz, Figure 1 test
LO
A
EE
RF
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
LIMITING AMPLIFIER SECTION
Limiter RSSI Slope (Figure 7)
Limiter Gain
20
–
–
–
–
0.2
–
0.4
55
0.6
–
µA/dB
dB
Input Impedance
10
–
1.4
–
kΩ
CARRIER DETECT
Output Current – Carrier Detect (High V )
in
21
21
20
–
–
–
–
–
0
–
–
µA
mA
Vdc
Output Current – Carrier Detect (Low V )
in
3.0
1.2
Input Threshold Voltage – Carrier Detect
0.9
1.4
Input Voltage Referenced to V
EE
= –3.0 Vdc
Figure 1. Test Circuit
Local
Oscillator
Input
140.7MHz
ML13156
50
1:4
TR 1
(1)
200m Vrms
Mixer
RF Input
130MHz
24
1
200
23
22
21
20
19
18
17
16
15
2
A
A
1.0 n
Carrier
Detect
3
4
5
V
1.0
µ
Mixer
Output
EE
+
100 n
1.0 n
330
50
V
CC
Bias
RSSI
Output
V
IF Input
A
A
EE
IF Amp
6
1.0 n
1.0 µ
+
V
EE
100 n
1.0 n
1.0 n
Data Slicer
Hold
7
Data
Slicer
Data Output
A
V
IF Output
Bias
8
9
1.0 n
330
50
1.0 n
V
CC
V
EE
LIM Amp
Limiter
Input
100 n
1.0 n
10
SMA
100 k
14
13
11
1.0 n
1.0 n
100 k
12
5.0 p
(3)
1.0 µH
150 p
NOTES: 1. TR 1 Coilcraft 1:4 impedance transformer.
2. V is DC Ground.
CC
3. 1.5 µH variable shielded inductor:
Toko Part # 292SNS–T1373 or Equivalent.
Issue A
Page 3 of 21
www.lansdale.com
ML13156
LANSDALE Semiconductor, Inc.
Figure 2. Total Drain Current versus Supply
Voltage and Temperature
Figure 3. Drain Currents versus Supply Voltage
6.5
6.0
5.5
5.0
4.5
4.0
3.6
3.2
2.8
2.4
T
= 25°C
A
T
= 85°C
A
I
22
55°C
25°C
–10°C
–40°C
I
19
4.0
3.5
2.0
1.6
1.0
2.0
3.0
4.0
5.0
6.0
7.0
1.0
2.0
3.0
V , SUPPLY VOLTAGE (–Vdc)
EE
4.0
5.0
6.0
7.0
V
, SUPPLY VOLTAGE (–Vdc)
EE
Figure 5. IF Amplifier Gain versus Input
Signal Level and Ambient Temperature
Figure 4. Mixer Gain versus Input Signal Level
25.0
22.5
20.0
17.5
15.0
40
38
36
34
32
30
T
= 25°C
A
85°C
55°C
25°C
–10°C
–40°C
V
= –5.0 Vdc
EE
12.5
10.0
28
26
f = 10.7 MHz
–90
–80
–70
–60
–50
–40
–30
–20
–10
–65
–60
–55
P , IF INPUT SIGNAL LEVEL (dBm)
in
–50
–45
–40
–35
–30
P
, RF INPUT SIGNAL LEVEL (dBm)
in
Figure 6. IF Amplifier RSSI Output Current versus
Input Signal Level and Ambient Temperature
Figure 7. Limiter Amplifier RSSI Output Current
versus Input Signal Level and Temperature
20.0
17.5
15.0
12.5
10.0
7.5
30
25
20
15
10
T
= 25° to 85°C
T
= 25° to 85°C
A
A
V
= –5.0 Vdc
V
= – 5.0 Vdc
EE
f = 10.7 MHz
EE
f = 10.7 MHz
–10°C
–40°C
–10°C
–40°C
5.0
5.0
0
2.5
0
–50
–40
–30
–20
–10
0
10
–70
–60
–50
–40
P , INPUT SIGNAL LEVEL (dBm)
in
–30
–20
–10
0
10
P
, IF INPUT SIGNAL LEVEL (dBm)
in
Page 4 of 21
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML13156
Page 5 of 21
www.lansdale.com
Issue A
ML13156
LANSDALE Semiconductor, Inc.
CIRCUIT DESCRIPTION
GENERAL
RSSI current output is derived by summing the currents for the
IF and limiting amplifier stages. An external resistor at Pin 20
sets the voltage range or swing of the RSSI output voltage.
Linearity of the RSSI is optimized by using external ceramic or
crystal bandpass filters which have and insertion loss of 8.0 dB.
The RSSI circuit is designed to provide 70+ dB of dynamic
range with temperature compensation (see Figures 6 and 7
which show RSSI responses of the IF and Limiter amplifiers).
Variation in the RSSI output current with supply voltage is 5 ma
total delta (see Figure 11).
The ML13156 is a low power single conversion wideband FM
receiver incorporating a split IF. This device can be used as a single
conversion receiver or as the backend in digital FM systems such as
CT–2 and wide band data links with data rates up to 500 kbaud. It
contains a mixer, oscillator, signal strength meter drive, IF amplifi-
er, limiting IF, quadrature detector and a data slicer with a hold
function (refer to Figure 8, Simplified Internal Circuit Schematic).
CURRENT REGULATION
Temperature compensating voltage independent current regula-
tors are used throughout.
CARRIER DETECT
When the meter current flowing through the meter load resist-
ance reaches 1.2 Vdc above ground, the comparator flips, caus-
ing the carrier detect output to go high. Hysteresis can be
accomplished by adding a very large resistor for positive feed-
back between the output and the input of the comparator.
MIXER
The mixer is a double–balanced four quadrant multiplier and is
designed to work up to 500 MHz. It can be used in differential
or in single–ended mode by connecting the other input to the
positive supply rail.
IF AMPLIFIER
Figure 4 shows the mixer gain and saturated output response as
a function of input signal drive. The circuit used to measure this
is shown in Figure 1. The linear gain of the mixer is approxi-
mately 22 dB. Figure 9 shows the mixer gain versus the IF out-
put frequency with the local oscillator of 150 MHz at 100
mVms LO drive level. The RF frequency is swept. The sensitivi-
ty of the IF output of the mixer is shown in Figure 10 for an RF
input drive of 10 mVrms at 140 MHz and IF at 10 MHz.
The first IF amplifier section is composed of three differential
stages with the second and third stages contributing to the RSSI.
This section has internal dc feedback and external input decou-
pling for improved symmetry and stability. The total gain of the
IF amplifier block is approximately 39 dB at 10.7 MHz. Figure
5 shows the gain and saturated output response of the IF ampli-
fier over temperature, while Figure 12 shows the IF amplifier
gain as a function of the IF frequency.
The single–ended parallel equivalent input impedance of the
mixer is Rp ~ 1.0 kΩ and Cp ~ 4.0 pF (see Table 1 for details).
The buffered output of the mixer is internally loaded resulting in
an output impedance of 330 Ω.
The fixed internal input impedance is 1.4kΩ. It is designed for
application where a 455 kHz ceramic filter is used and no exter-
nal output matching is necessary since the filter requires a 1.4
kΩ source and load impedance.
LOCAL OSCILLATOR
For 10.7 Mhz ceramic filter applications, an external 430 Ω
resistor must be added in parallel to provide the equivalent load
impedance of 330 Ω that is required by the filter; however, no
external matching is necessary at the input since the mixer out-
put matches the 330 Ω source impedance of the filter. For 455
kHz applications, an external 1.1 kΩ resistor must be added in
series with the mixer output to obtain the required matching
impedance of 1.4 kΩ of the filter input resistance. Overall RSSI
linearity is dependent on having total midband attenuation of 12
dB (6.0 dB insertion loss plus 6.0 dB impedance matching loss)
for the filter. The output of the IF amplifier is buffered and the
impedance is 290 Ω.
The on–chip transistor operates with crystal and LC resonant
elements up to 220 MHz. Series resonant, overtone crystals are
used to achieve excellent local oscillator stability. 3rd overtone
crystals are used through about 65 to 70 MHz. Operation from
70 MHz up to 180 MHz is feasible using the on–chip transistor
with a 5th or 7th overtone crystal. To enhance operation using
an overtone crystal, the internal transistor’s bias is increased by
adding an external resistor from Pin 23 to VEE. –10 dBm of
local oscillator drive is needed to adequately drive the mixer
(Figure 10).
The oscillator configurations specified above, and two others
using an external transistor, are described in the application sec-
tion:
1) A 133 MHz oscillator multiplier using a 3rd overtone
crystal, and
2) A 307.8 to 309.3 MHz manually tuned, varactor
controlled local oscillator.
LIMITER
The limiter section is similar to the IF amplifier section except
that four stages are used with the last three contributing to the
RSSI. The fixed internal input impedance is 1.4 kΩ. The total
gain of the limiting amplifier sections is approximately 55 dB.
This IF limiting amplifier section internally drives the quadra-
ture detector section.
RSSI
The Received Signal Strength Indicator (RSSI) output is a cur-
rent proportional to the log of the received signal amplitude. The
Page 6 of 21
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML13156
Figure 10. Mixer IF Output Level versus
Local Oscillator Input Level
Figure 9. Mixer Gain versus IF Frequency
20
15
–5.0
–10
–15
–20
–25
–30
–35
–40
–45
V
= –3.0 Vdc
EE
= 25°C
T
A
V
V
R
R
= –3.0 Vdc
= 1.0 mVrms (–47 dBm)
= 330 Ω
EE
in
O
in
10
= 50
Ω
BW(3.0 dB) = 21.7 MHz
5.0
f
f
V
= f
– f
IF LO RF
LO
LO
= 150 MHz
= 100 mVrms
f
= 140 MHz; f
= 150 MHz
LO
RF
RF Input Level = –27 dBm
(10 mVrms)
0
R
= 50
Ω
; R = 330 Ω
in
O
–5.0
0.1
1.0
10
100
–50
–40
–30
–20
LO DRIVE (dBm)
–10
0
10
f
, IF FREQUENCY (MHz)
IF
Figure 11. RSSI Output Current versus
Supply Voltage and RF Input Signal Level
Figure 12. IF Amplifier Gain versus IF Frequency
40
60
50
40
30
20
V
=
T = 25°C
A
in
35
30
25
20
15
10
5.0
0
–20 dBm
–40 dBm
–60 dBm
V
R
R
= 100 µV
= 50 Ω
in
in
O
–80 dBm
= 330
Ω
BW(3.0 dB) = 26.8 MHz
–100 dBm
10
0
T
= 25°C
A
1.0
2.0
3.0
4.0
5.0
6.0
7.0
0.1
1.0
10
100
V
, SUPPLY VOLTAGE (–Vdc)
f, FREQUENCY (MHz)
EE
Figure 13. Recovered Audio Output Voltage
versus Supply Voltage
400
300
200
100
0
f
f
f
= 1.0 kHz
mod
dev
RF
=
75 kHz
= 140 MHz
RF Input Level = 1.0 mVrms
T
= 25°C
A
1.0
2.0
3.0
4.0
5.0
6.0
7.0
V
, SUPPLY VOLTAGE (–Vdc)
EE
Page 7 of 21
www.lansdale.com
Issue A
ML13156
LANSDALE Semiconductor, Inc.
QUADRATURE DETECTOR
The quadrature detector is a doubly balanced four quadrant
Q3 and Q2. When the data slicer input (Pin 15) is pulled up,
Q1 turns off; Q2 turns on, thereby clamping the input at 2.0
multiplier with an internal 5.0 pF quadrature capacitor to cou- V . On the other hand, when Pin 15 is pulled down, Q1
be
ple the IF signal to the external parallel RLC resonant circuit
that provides the 90 degree phase shift and drives the quadra-
ture detector. A single pin (Pin 13) provides for the external
LC parallel resonant network and the internal connection to
the quadrature detector.
turns on; Q2 turns off, thereby clamping the input at 1.0 V .
be
The recovered data signal from the quadrature detector is ac
coupled to the data slicer via an input coupling capacitor. The
size of the capacitor and the nature of the data signal deter-
mine how faithfully the data slicer shapes up the recovered
The bandwidth of the detector allows for recovery of relative- signal. The time constant is short for large peak to peak volt-
ly high data rate modulation. The recovered signal is convert- age swings or when there is a change in dc level at the detec-
ed from differential to single ended through a push–pull
NPN/PNP output stage. Variation in recovered audio output
tor output. For small signal or for continuous bits of the same
polarity which drift close to the threshold voltage, the time
voltage with supply voltage is very small (see Figure 13). The constant is longer. When centered there is no input current
output drive capability is approximately 9.0 µA for a fre-
quency deviation of 75 kHz and 1.0 kHz modulating fre-
quency (see Application Circuit)
allowed, which is to say, that the input looks high in imped-
ance.
Another unique feature of the data slicer is that it responds to
various logic levels applied to the Data Slicer Hold Control
pin (Pin 18). Figure 15 illustrates how the input and output
currents under “no hold” condition relate to the input voltage.
Figure 16 shows how the input current and input voltage
relate to the both the “no hold” and “hold” condition.
DATA SLICER
The data slicer input (Pin 15) is self centering around 1.1 V
with clamping occurring at 1.1 0.5 V Vdc. It is designed
be
to square up the data signal. Figure 14 shows a detailed
schematic of the data slicer.
The Voltage Regulator sets up to 1.1 Vdc on the base of Q12,
the Differential Input Amplifier. There is a potential of 1.0
The Hold control (Pin 18) does three separate tasks:
1) With Pin 18 at 1.0 V or greater, the output is shut off
be
V
V
on the base–collector of transistor diode Q11 and 2.0
on the base–collector of Q10. This sets up a 1.5 V
be
(sets high). Q19 turns on which shunts the base drive
from Q20, thereby turning the output off.
be
be
(~1.1 Vdc) on the node between the 36 kΩ resistors which is
connected to the base of Q12. The differential output of the
data slicer Q12 and Q13 is converted to a single–ended out-
put by the Driver Circuit. Additional circuitry, not shown in
Figure 14, tends to keep the data slicer input centered at 1.1
Vdc as input signal levels vary.
2) With Pin 18 at 2.0 V or greater, internal clamping diodes
be
are open circuited and the comparator input is shut off and
effectively open circuited. This is accomplished by turning
off the current source to emitters of the input differential
amplifier, thus, the input differential amplifier is shut off.
3) When the input is shut off, it allows the input capacitor to
hold its charge during transmit to improve recovery at the
beginning of the next receive period. When it is turned on,
it allows for very fast charging of the input capacitor for
quick recovery of new tuning or data average. The above
features are very desirable in a TDD digital FM system.
The Input Diode Clamp Circuit provides the clamping at 1.0
V
be
(0.75 Vdc) and 2.0 V (1.45 Vdc). Transistor diodes Q7
be
and Q8 are on , thus, providing a 2.0 V potential at the base
be
of Q1. Also, the voltage regulator circuit provides a potential
of 2.0 V on the base of Q3 and 1.0 V on the emitter of
be
be
Page 8 of 21
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Figure 14. Data Slicer Circuit
9
15
V
CC
DS In
8.0 k
8.0 k
Data Out
17
Q15
Q14
Q10
Q3
36 k
36 k
Q20
Q1
Q12 Q13
Q7
Q5
Q2
Q8
16
DS Gnd
32 k
Q6
Q18
Q11
Q4
Q19
Q9
Q16
Q17
64 k
16 k
16 k
64 k
V
EE
64 k
19
Input Diode
Clamp Circuit
(Q1 to Q9)
Voltage
Regulator
(Q10, Q11)
Differential
Input Amplifier
(Q12, Q13)
Driver and
Output Circuit
(Q14, Q20)
18
DS Hold
Figure 15. Data Slicer Input/Output Currents
versus Input Voltage
Figure 16. Data Slicer Input Current
versus Input Voltage
2.5
0.5
0.3
150
100
50
Hold
V
= –3.0 Vdc
EE
V
≥1
No Hold
= 0 Vdc
18
1.5
V
Output Current
18
(I
)
17
0.5
0.1
–0.5
–1.5
–2.5
–0.1
–0.3
–0.5
0
Input Current
(I
V
V
= –3.0 Vdc
= 0 Vdc
EE
18
–50
)
15
No Hold
1.0
Hold
(No Hold)
–100
–1.0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
–0.5
0
0.5
1.5
2.0
2.5
3.0
V
, INPUT VOLTAGE (Vdc)
V
, INPUT VOLTAGE (Vdc)
15
15
Page 9 of 21
www.lansdale.com
Issue A
ML13156
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 17. MC13156DW Application Circuit
+
1.0
(6)
µ
15 k
0.146
µ
MMBR5179
100 p
(5) 0.82
µ
ML13156
68 p
7.5 p
50 p
144.455 MHz
RF Input
Mixer
5.6 k
24
1
2
3
4
5
470
43 p
(1)
0.1
(4) 3rd O.T.
XTAL
SMA
µ
133.755 MHz
Osc/Tripler
23
22
21
20
19
18
17
16
1.0 k
10 n
10 n
V
EE
Carrier
Detect
(2) 10.7 MHz
Ceramic
Filter
V
CC
Bias
100 k
RSSI
Output
10 n
10 n
47 k
IF Amp
10 n
430
6
7
V
EE
Data Slicer
Hold
10 n
Data
Slicer
10 k
Bias
8
Data
Output
(2) 10.7 MHz
Ceramic
Filter
V
V
CC
9
CC
V
EE
100 n
LIM Amp
15
10
11
12
180 p
10 n
430
100 k
14
13
100 k
10 n
5.0 p
(3)
1.5
V
CC
µ
150 p
10 k
+
1.0
µ
NOTES: 1. 0.1 µH Variable Shielded Inductor: Coilcraft part # M1283–A or equivalent.
2. 10.7 MHz Ceramic Filter: Toko part # SK107M5–A0–10X or Murata Erie part # SFE10.7MHY–A.
3. 1.5 µH Variable Shielded Inductor: Toko part # 292SNS–T1373.
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.585 MHz.
5. 0.814 µH Variable Shielded Inductor: Coilcraft part # 143–18J12S.
6. 0.146 µH Variable Inductor: Coilcraft part # 146–04J08.
Page 10 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Page 11 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
COMPONENT SELECTION
transistor. Selecting a transistor having good phase noise perform-
ance is important; a mandatory criteria is for the device to have
good linearity of beta over several decades of collector current. In
other words, if the low current beta is suppressed, it will not offer
good 1/f noise performance. A third overtone series resonant crystal
having at least 25 ppm tolerance over the operating temperature is
recommended. The local oscillator is an impedance inversion third
overtone Colpitts network and harmonic generator. In this circuit a
560 to 1.0 kΩ resistor shunts the crystal to ensure that it operates in
its overtone mode; thus, a blocking capacitor is needed to eliminate
the dc path to ground. The resulting parallel LC network should
“free–run” near the crystal frequency if a short to ground is placed
across the crystal. To provide sufficient output loading at the collec-
tor, a high Q variable inductor is used that is tuned to self resonate
at the 3rd harmonic of the overtone crystal frequency.
The evaluation PC board is designed to accommodate specific
components, while also being versatile enough to use components
from various manufacturers and coil types. Figures 18 and 19 show
the placement for the components specified in the application cir-
cuit (Figure 17). The application circuit schematic specifies particu-
lar components that were used to achieve the results shown in the
typical curves and tables but equivalent components should give
similar results.
INPUT MATCHING NETWORKS.COMPONENTS
The input matching circuit shown in the application circuit
schematic is passive high pass network which offers effective image
rejection when the local oscillator is below the RF input frequency.
Silver mica capacitors are used for their high Q and tight tolerance.
The PC board is not dedicated to any particular input matching net-
work topology; space is provided for the designer to breadboard as
desired.
The on–chip grounded collector transistor may be used for HF and
VHF local oscillator with higher order overtone crystals. Figure 18
shows a 5th overtone oscillator at 93.3 MHz and Figure 19 shows a
7th overtone oscillator at 148.3 MHz. Both circuits use a Butler
overtone oscillator configuration. The amplifier is an emitter fol-
lower. The crystal is driven from the emitter and is coupled to the
high impedance base through a capacitive tap network. Operation at
the desired overtone frequency is ensured by the parallel resonant
circuit formed by the variable inductor and the tap transistor and
PC board. The variable inductor specified in the schematic could be
replaced with a high tolerance, high Q ceramic or air wound sur-
face mount component. if the other component have good toler-
ance. A variable inductor provides an adjustment for gain and fre-
quency of the resonant tank ensuring lock up and start up of the
crystal oscillator. The overtone crystal is chosen with ESR of typi-
cally 80 Ω and 120 Ω maximum; if the resistive loss in the crystal
is too high, the performance of the oscillator may be impacted by
lower gain margins.
Alternate matching networks using 4:1 surface mount transformers
or BALUNs provide satisfactory performance. The 12 dB SINAD
sensitivity using the above matching networks is typically –100
dBm for f
MHz and f
OSC
= 1.0 kHz and f
dev
= 75 kHz at f = 144.45
IN
mod
= 133.75 MHz (see Figure 23).
It is desirable to use a SAW filter before the mixer to provide addi-
tional selectivity and adjacent channel rejection and improved sen-
sitivity. The SAW filter should be designed to interface with the
mixer input impedance of approximately 1.0 kΩ. Table 1 displays
the series equivalent single–ended mixer input impedance.
LOCAL OSCILLATORS
VHF APPLICATIONS – The local oscillator circuit shown in the
application schematic utilizes a third overtone crystal and an RF
Table 1. Mixer Input Impedance Data
(Single–ended configuration, V = 3.0 Vdc, local oscillator drive = 100 mVrms)
CC
Series Equivalent
Complex Impedance
(R + jX)
Parallel
Resistance
Rp
Parallel
Capacitance
Cp
Frequency
(MHz)
(Ω)
(Ω)
(pF)
90
190 – j380
160 – j360
130 – j340
110 – j320
97 – j300
82 – j280
71 – j270
59 – j260
52 – j240
44 – j230
38 – j220
950
970
4.7
4.4
4.2
4.2
4.0
4.0
4.0
3.9
3.9
3.8
3.8
100
110
120
130
140
150
160
170
180
190
1020
1040
1030
1040
1100
1200
1160
1250
1300
Page 12 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Page 13 of 21
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Issue A
ML13156
LANSDALE Semiconductor, Inc.
Legacy Applications Information
A series LC network to ground (which is V ) is comprised of the The input matching network uses a 1:4 impedance matching trans-
CC
inductance of the base lead of the on–chip transistor and PC board
traces and tap capacitors. Parasitic oscillations often occur in the
200 to 800 MHz range. A small resistor is placed in series with the
base (Pin 24) to cancel the negative resistance associated with this
former (Recommended sources are Mini–Circuits and Coilcraft).
Using the same IF ceramic filters and quadrature detector circuit as
specified in the applications circuit in Figure 17, the 12 dB SINAD
undesired mode of oscillation. Since the base input impedance is so performance is –95 dBm for a f
large a small resistor in the range of 27 to 68 Ω has very little effect form and f
= 1.0 kHz sinusoidal wave-
mod
40 kHz.
dev
on the desired Butler mode of oscillation.
This circuit is breadboarded using the evaluation PC bard shown in
Figures 32 and 33. The RF ground is V and path lengths are
minimized. High quality surface mount components were used
except where specified. The absolute values of the components
used will vary with layout placement and component parasitics.
The crystal parallel capacitance, C , provides a feedback path that
o
CC
is low enough in reactance at frequencies of 5th overtone or higher
to cause trouble. C has little effect near resonance because of the
o
low impedance of the crystal motional arm (R –L –C ). As the
m
m
m
tunable inductor which forms the resonant tank with the tap capaci-
tors is tuned off the crystal resonant frequency, it may be difficult
to tell if the oscillation is under crystal control. Frequency jumps
RSSI RESPONSE
Figure 24 shows the full RSSI response in the application circuit.
may occur as the inductor is tuned. In order to eliminate this behav- The 10.7 MHz, 110 kHz wide bandpass ceramic filters (recom-
ior an inductor (L ) is placed in parallel with the crystal. L is cho- mended sources are TOKO part # SK107M5–AO–10X or Murata
o
o
sen to resonant with the crystal parallel capacitance (C ) at the
Erie SFE10.7MHY–A) provide the correct band pass insertion loss
o
desired operation frequency. The inductor provides a feedback path to linearize the curve between the limiter and IF portions of RSSI.
at frequencies well below resonance; however, the parallel tank net- Figure 23 shows that limiting occurs at an input of –100 dBm. As
work of the tap capacitors and tunable inductor prevent oscillation
at these frequencies.
shown in Figure 24, the RSSI output linear from –100 dBm to –30
dBm.
UHF APPLICATION
The RSSI rise and fall times for various RF input signal levels and
R20 values are measures at Pin 20 without 10 nF filter capacitor. A
10 kHz square wave pulses the RF input signal on and off. Figure
25 shows that the rise and fall times are short enough to recover
greater than 10 kHz ASK data; with a wider IF band pass filters
data rates up to 50 kHz may be achieved. The circuit used is the
application circuit in Figure 17 with no RSSI output filter capacitor.
Figure 20 shows a 318.5 to 320 MHz receiver which drives the
mixer with an external varactor controlled (307.8 to 309.3 MHz)
LC oscillator using an MPS901 (RF low power transistor in a
TO–92 plastic package; also MMBR901 is available in a SOT–23
surface mount package). With the 50 kΩ 10 turn potentiomenter
this oscillator is tunable over a range of approximately 1.5 MHz.
The MMBV909L is a low voltage varactor suitable for UHF appli-
cations; it is a dual back–to–back varactor in a SOT–23 package.
Figure 18. MC13156DW Application Circuit
= 104 MHz; f = 93.30 MHz
f
RF
LO
5th Overtone Crystal Oscillator
(4)
0.135 µH
33
+
1.0
µ
(2)
10 p
104 MHz
RF Input
Mixer
27 p
120 p
(1)
24
1
2
3
1.0 µH
SMA
(3)
30 p
10 n
3.0 p
0.1 µ
23
10 n
5th OT
XTAL
4.7 k
22
V
EE
V
CC
To Filter
NOTES: 1. 0.1 µH Variable Shielded Inductor: Coilcraft part # M1283–A or equivalent.
2. Capacitors are Silver Mica.
3. 5th Overtone, Series Resonant, 25 PPM Crystal at 93.300 MHz.
4. 0.135 µH Variable Shielded Inductor: Coilcraft part # 146–05J08S or equivalent.
Page 14 of 21
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Issue A
LANSDALE Semiconductor, Inc.
ML13156
Legacy Applications Information
Figure 19. MC13156DW Application Circuit
f
= 159 MHz; f
7th Overtone Crystal Oscillator
= 148.30 MHz
RF
LO
(4)
76 nH
+
33
1.0
µ
(2)
5.0 p
27 p
Mixer
50 p
159 MHz
RF Input
24
1
2
3
0.22 µH
(1)
0.08
SMA
47 p
µH
23
(3)
7th OT
XTAL
10 n
4.7 k
22
470
V
EE
10 n
V
CC
To IF Filter
NOTES: 1. 0.08 µH Variable Shielded Inductor: Toko part # 292SNS–T1365Z or equivalent.
2. Capacitors are Silver Mica.
3. 7th Overtone, Series Resonant, 25 PPM Crystal at 148.300 MHz.
4. 76 nH Variable Shielded Inductor: Coilcraft part # 150≠03J08S or equivalent.
Figure 20. MC13156DW Varactor Controlled LC Oscillator
(2)
47 k
50 k
V
+
VCO
(6)
1.0
µ
4.7 k
0.1 µ
1.0 M
MPS901
6.8 p
24 p
(1)
Mixer
318.5 to
320 MHz
1:4 Transformer
24
1
2
3
20 p
24 p
RF Input
(4)
MMBV909L
SMA
23
22
12 k
(3)
18.5 nH
1.8 k
V
EE
1.0 n
307.8–309.3 MHz
LC Varactor
Controlled Oscillator
V
= 3.3 Vdc (Reg)
CC
NOTES: 1. 1:4 Impedance Transformer: Mini Circuits.
2. 50 k Potentiometer, 10 turns.
3. Spring Coil; Coilcraft A05T.
4. Dual Varactor in SOT–23 Package.
5. All other components are surface mount components.
6. Ferrite beads through loop of 24 AWG wire.
Page 15 of 21
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Issue A
ML13156
LANSDALE Semiconductor, Inc.
Legacy Applications Information
45 MHZ NARROWBAND RECEIVER
The above application examples utilize a 10.7 MHz IF. In this sec-
tion a narrowband receiver with a 455 kHz IF will be described.
Figure 21 shows a full schematic of a 45 MHz reciever that uses a
3rd overtone crystal with the on–chip oscillator transistor. The
oscillator configuration is similar to the one used in Figure 17; it is
called an impedance inversion Colpitts. A 44.545 Mhz 3rd over-
tone, series resonant crystal is used to achieve an IF frequency at
455 kHz. The ceramic IF filters selected are Murata Erie part #
SFG455A3. 1.2 kΩ chip resistors are used in series with the filters
to achieve the terminating resistance of 1.4 kΩ to the filter. The IF
decoupling is very important; 0.1 µF chip capacitors are used at
Pins 6, 7, 11 and 12. The quadrature detector tank circuit uses a
455 kHz quadrature tank from Toko.
The 12 dB SINAD performance is –109 dBm for a f
and a f
dev
80 db of linear range (see Figure 22).
= 1.0 kHz
= 4.0 kHz. The RSSI dynamic range is approximately
mod
RECEIVER DESIGN CONSIDERATIONS
The curves of signal levels at various portions of the application
receiver with respect to RF input level are shown in Figure 26. This
information helps determine the network topology and gain blocks
required ahead of the MC13156 to achieve the desired sensitivity
and dynamic range of the receiver system. In the application circuit
the input third order intercept (IP3) performance of the system is
approximately –25 dBm (see Figure 27).
Figure 21. MC13156DW Application Circuit at 45 MHz
1.8 µH
+
1.0
µ
(6)
(1)
0.33 µH
10 n
33 p
45 Hz
RF Input
Mixer
24
1
2
3
4
5
(4) 3rd OT
XTAL
44.545
56 p
39 p
SMA
(5) 0.416 µH
180 p
470 k
23
22
21
20
19
18
17
16
15
MHz
10 k
1.2 k
10 n
V
EE
10 n
Carrier
Detect
(2) 455 kHz
Ceramic
Filter
V
CC
Bias
100 k
RSSI
Output
10 n
47 k
IF Amp
0.1
µ
6
7
V
EE
10 n
0.1
µ
Data Slicer
Hold
Data
Slicer
10 k
1.2 k
Bias
8
Data
Output
(2) 455 kHz
Ceramic
Filter
V
V
CC
9
CC
V
EE
100 n
10
11
12
Audio To
C–Message
Filter and
Amp.
LIM Amp
0.1
µ
100 k
100 k
14
13
1.0 n
0.1
µ
5.0 p
(3)
V
= 2.0 to 5.0 Vdc
CC
680 µH
180 p
27 k
+
NOTES: 1. 0.33 µH Variable Shielded Inductor: Coilcraft part # 7M3–331 or equivalent.
2. 455 kHz Ceramic Filter: Murata Erie part # SFG455A3.
3. 455 kHz Quadrature Tank: Toko part # 7MC8128Z.
1.0
µ
4. 3rd Overtone, Series Resonant, 25 PPM Crystal at 44.540 MHz.
5. 0.416 µH Variable Shielded Inductor: Coilcraft part # 143–10J12S.
6. 1.8 µH Molded Inductor.
Page 16 of 21
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Issue A
ML13156
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 22. RSSI Output Voltage
versus Input Signal Level
Figure 23. S + N/N versus RF Input Signal Level
10
0
1.8
1.6
1.4
1.2
S + N
V
f
= 5.0 Vdc
CC
dev
–10
–20
f
V
= 45.00 MHz
= 2.0 Vdc
=
75 kHz
RF
CC
f
f
= 1.0 kHz
= 144.45 MHz
mod
12 dB SINAD @ –109 dBm
(0.8 Vrms)
(See Figure 21)
in
µ
1.0
0.8
0.6
(See Figure 17)
–30
–40
–50
N
0.4
–120
–100
–80
–60
–40
20
–110 –100
–90
–80
–70
–60
–50
–40
–30
–20
–20
0
SIGNAL INPUT LEVEL (dBm)
RF INPUT SIGNAL (dBm)
Figure 25. RSSI Output Rise and Fall Times
versus RF Input Signal Level
Figure 24. RSSI Output Voltage
versus Input Signal Level
1.4
1.2
1.0
0.8
0.6
0.4
35
30
25
20
t
t
t
t
t
t
@ 22 k
@ 22 k
@ 47 k
@ 47 k
@ 100 k
@ 100 k
r
f
r
f
r
f
15
10
5.0
0
V
= 5.0 Vdc
= 144.455 MHz
= 133.755 MHz
CC
f
f
c
LO
Low Loss 10.7 MHz
Ceramic Filter
(See Figure 17)
0.2
–120
–100
–80
–60
–40
–20
0
0
–20
–40
–60
–80
SIGNAL INPUT LEVEL (dBm)
RF INPUT SIGNAL LEVEL (dBm)
Figure 26. Signal Levels versus
RF Input Signal Level
Figure 27. 1.0 dB Compression Pt. and Input
Third Order Intercept Pt. versus Input Power
0
–10
–20
–30
–40
–50
–60
10
0
LO Level = –2.0 dBm
(See Figure 17)
V
= 5.0 Vdc
= 144.4 MHz
= 144.5 MHz
= 133.75 MHz
= –2.0 dBm
IF Output
Limiter Input
CC
RF1
RF2
1.0 dB Comp. Pt.
= –37 dBm
f
f
f
IP3 = –25 dBm
–10
LO
P
LO
(See Figure 17)
–20
–30
–40
–50
–60
–70
–70
–100
–90
–80
–70
–60
–50
–40
–30
–100
–80
–60
–40
–20
0
RF INPUT SIGNAL LEVEL (dBm)
RF INPUT POWER (dBm)
Page 17 of 21
www.lansdale.com
Issue A
ML13156
LANSDALE Semiconductor, Inc.
BER TESTING AND PERORMANCE
DESCRIPTION
Figure 28. Bit Error Rate versus RF
Input Signal Level and IF Bandpass Filter
The test setup shown in Figure 29 is configured so that the function
generator supplies a 100 kHz clock source to the bit error rate
tester. This device generates and receives a repeating data pattern
and drives a 5 pole baseband data filter. The filter effectively
reduces harmonic content of the base band data which is used to
modulate the RF generator which is running at 144.45 MHz.
Following processing of the signal by the receiver (ML13156), the
recovered baseband sinewave (data) is AC coupled to the data
slicer. The data slicer is essentially an auto–threshold comparator
which tracks the zero crossing of the incoming sinewave and pro-
vides logic level data at its output. Data errors associated with the
recovered data are collected by the bit error rate receiver and dis-
played.
–1
–3
–5
–7
10
10
10
10
V
= 4.0 Vdc
CC
Data Pattern = 2E09 Prbs NRZ
Baseband Filter f = 50 kHz
c
f
= 32 kHz
dev
IF Filter BW
110 kHz
IF Filter BW
230 kHz
–90
–85
–80
–75
–70
Bit error rate versus RF signal input level and IF filter bandwidth
are shown in Figure 28. The bit error rate data was taken under the
following test conditions:
RF INPUT SIGNAL LEVEL (dBm)
EVALUATION PC BOARD
The evaluation PCB is very versatile and is intended to be used
across the entire useful frequency range of this device. The center
section of the board provides an area for attaching all SMT compo-
nents to the component ground side (see Figures 32 and 33).
Additionally, the peripheral area surrounding the RF core provides
pads to add supporting and interface circuitry as a particular appli-
cation dictates
• Data rate = 100kbps
• Filter cutoff frequency set to 39% of the data rate or 39 kHz.
• Filter type is a 5 pole equal–ripple with 0.5° phase error.
• V
= 4.0 Vdc
CC
• Frequency deviation = 32 kHz.
Page 18 of 21
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Issue A
ML13156
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 29. Bit Error Rate Test Setup
Function Generator
Wavetek Model No. 164
Bit Error Rate Tester
HP3780A or Equivalent
RF Generator
HP8640B
Gen
Clock
Input
Rcr
Clock
Input
Rcr
Data
Input
Clock
Out
Generator
Output
Modulation
Input
RF
Output
5 Pole
Bandpass
Filter
Data Slicer
Output
Mixer
Input
MC13156
UUT
Page 19 of 21
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Issue A
ML13156
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLASTIC QFP PACKAGE
(ML13156-8P)
CASE 873–01
ISSUE A
L
17
24
25
16
–B–
B
–A–
V
L
B
P
B
DETAIL A
32
9
1
8
–A–, –B–, –D–
DETAIL A
–D–
A
M
S
S
0.20 (0.008)
C
A–B
D
0.05 (0.002) A–B
S
F
BASE
METAL
M
S
S
0.20 (0.008)
H
A–B
D
DETAIL C
M
N
J
E
C
DATUM
–H–
D
PLANE
–C–
M
S
S
0.01 (0.004)
0.20 (0.008)
C
A–B
D
SEATING
PLANE
M
H
G
SECTION B–B
VIEW ROTATED 90 CLOCKWISE
U
MILLIMETERS
INCHES
MIN MAX
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
DIM
A
B
C
D
E
MIN
6.95
6.95
1.40
0.273
1.30
MAX
7.10
7.10
1.60
0.373
1.50
–––
0.274
0.274
0.055
0.010
0.051
0.010
0.280
0.280
0.063
0.015
0.059
–––
T
F
0.273
R
–H–
DATUM
PLANE
G
H
J
K
L
M
N
P
0.80 BSC
0.031 BSC
–––
0.119
0.33
0.20
0.197
0.57
–––
0.005
0.013
0.008
0.008
0.022
5.6 REF
0.220 REF
K
6°
8°
6°
8°
Q
0.119
0.135
0.005
0.005
X
0.40 BSC
0.016 BSC
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
Q
R
S
T
U
V
5°
0.15
8.85
0.15
5°
10°
5°
0.006
0.348
0.006
5°
10°
0.010
0.360
0.010
11°
DETAIL C
0.25
9.15
0.25
11°
8.85
9.15
0.348
0.360
X
1.00 REF
0.039 REF
Page 20 of 21
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Issue A
ML13156
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLASTIC PACKAGE
(ML13156-6P)
CASE 751E–04
(SO–24L)
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
24
13
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– 12X P
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
15.25
7.40
2.35
0.35
0.41
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
0.601
0.292
0.093
0.014
0.016
F
R X 45°
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0°
0.32
0.29
8°
0.009
0.005
0°
0.013
0.011
8°
C
K
–T–
SEATING
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
22X G
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 21 of 21
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Issue A
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