SIHFP240-E3 [KERSEMI]
Dynamic dV/dt Rating Repetitive Avalanche Rated; 动态的dv / dt额定值额定重复性雪崩
| 型号： | SIHFP240-E3 |
| 厂家： | 
Kersemi Electronic Co., Ltd. |
| 描述： | Dynamic dV/dt Rating Repetitive Avalanche Rated |
| 文件： | 总7页 (文件大小：3998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFP240, SiHFP240
FEATURES
• Dynamic dV/dt Rating
PRODUCT SUMMARY
VDS (V)
200
• Repetitive Avalanche Rated
• Isolated Central Mounting Hole
• Fast Switching
Available
RDS(on) (Ω)
VGS = 10 V
0.18
RoHS*
Qg (Max.) (nC)
70
13
COMPLIANT
Q
gs (nC)
• Ease of Paralleling
Qgd (nC)
39
• Simple Drive Requirements
• Lead (Pb)-free Available
Configuration
Single
D
DESCRIPTION
TO-247
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
G
The TO-247 package is preferred for commercial-industrial
applications where higher power levels preclude the use of
TO-220 devices. The TO-247 is similar but superior to the
earlier TO-218 package because its isolated mounting hole.
It also provides greater creepage distances between pins to
meet the requirements of most safety specifications.
S
D
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247
IRFP240PbF
SiHFP240-E3
IRFP240
Lead (Pb)-free
SnPb
SiHFP240
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
VGS
200
V
20
TC = 25 °C
20
Continuous Drain Current
V
GS at 10 V
ID
TC = 100 °C
12
A
Pulsed Drain Currenta
IDM
80
Linear Derating Factor
1.2
W/°C
mJ
A
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
EAS
IAR
510
20
EAR
15
150
mJ
W
Maximum Power Dissipation
TC = 25 °C
PD
Peak Diode Recovery dV/dtc
dV/dt
TJ, Tstg
5.0
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
- 55 to + 150
300d
°C
for 10 s
10
lbf · in
N · m
Mounting Torque
6-32 or M3 screw
1.1
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 1.9 mH, RG = 25 Ω, IAS = 20 A (see fig. 12).
c. ISD ≤ 18 A, dI/dt ≤ 150 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
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1
IRFP240, SiHFP240
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
40
UNIT
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
RthJA
RthCS
RthJC
-
0.24
-
-
°C/W
0.83
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
ΔVDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 µA
200
-
-
-
V
V/°C
V
-
0.29
2.0
-
-
-
-
-
-
4.0
100
25
250
0.18
-
VGS
VDS = 200 V, VGS = 0 V
VDS = 160 V, VGS = 0 V, TJ = 125 °C
VGS = 10 V
ID = 12 Ab
VDS = 50 V, ID = 12 Ab
=
20 V
-
nA
-
-
Zero Gate Voltage Drain Current
IDSS
µA
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
-
Ω
6.9
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Ciss
Coss
Crss
Qg
-
-
-
-
-
-
-
-
-
-
1300
400
130
-
-
-
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
pF
-
70
13
39
-
ID = 18 A, VDS = 160 V,
see fig. 6 and 13b
Qgs
Qgd
td(on)
tr
VGS = 10 V
-
nC
-
14
51
45
36
-
VDD = 100 V, ID = 18 A,
ns
RG = 9.1 Ω, RD = 5.4 Ω,
Turn-Off Delay Time
Fall Time
td(off)
tf
-
see fig. 10b
-
D
Between lead,
Internal Drain Inductance
LD
LS
-
-
5.0
13
-
-
6 mm (0.25") from
package and center of
die contact
nH
G
Internal Source Inductance
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
IS
-
-
-
-
20
80
A
G
Pulsed Diode Forward Currenta
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = 20 A, VGS = 0 Vb
-
-
-
-
2.0
610
7.1
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
300
3.4
ns
µC
TJ = 25 °C, IF = 18 A, dI/dt = 100 A/µsb
Qrr
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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IRFP240, SiHFP240
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 2 - Typical Output Characteristics, TC = 150 °C
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3
IRFP240, SiHFP240
Fig. 5 - Typical Capacitance vs. Drain-to-Source
Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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4
IRFP240, SiHFP240
RD
VDS
VGS
D.U.T.
RG
+
V
-
DD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on) tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFP240, SiHFP240
L
VDS
VDS
Vary tp to obtain
required IAS
tp
VDD
D.U.T
IAS
RG
+
-
VDD
VDS
10 V
0.01 Ω
tp
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
-
VDS
D.U.T.
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
Fig. 13a - Basic Gate Charge Waveform
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6
IRFP240, SiHFP240
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T.
• Low leakage inductance
current transformer
-
+
-
-
+
RG
• dV/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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