IRFR320 [KERSEMI]
Power MOSFET; 功率MOSFET
| 型号： | IRFR320 |
| 厂家： | 
Kersemi Electronic Co., Ltd. |
| 描述： | Power MOSFET |
| 文件： | 总7页 (文件大小：4076K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFR320, IRFU320, SiHFR320, SiHFU320
Power MOSFET
FEATURES
• Dynamic dV/dt Rating
PRODUCT SUMMARY
VDS (V)
400
Available
• Repetitive Avalanche Rated
RoHS*
• Surface Mount (IRFR320/SiHFR320)
COMPLIANT
R
DS(on) (Ω)
VGS = 10 V
1.8
Qg (Max.) (nC)
Qgs (nC)
20
3.3
• Straight Lead (IRFU320/SiHFU320)
• Available in Tape and Reel
• Fast Switching
Qgd (nC)
11
Configuration
Single
• Ease of Paralleling
D
• Lead (Pb)-free Available
DPAK
(TO-252)
IPAK
(TO-251)
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
G
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
IRFR320PbF
SiHFR320-E3
IRFR320
DPAK (TO-252)
IRFR320TRLPbFa
SiHFR320TL-E3a
IRFR320TRLa
DPAK (TO-252)
IRFR320TRPbFa
SiHFR320T-E3a
IRFR320TRa
DPAK (TO-252)
IRFR320TRRPbFa
SiHFR320TR-E3a
IRFR320TRRa
IPAK (TO-251)
IRFU320PbF
SiHFU320-E3
IRFU320
Lead (Pb)-free
SnPb
SiHFR320
SiHFR320TLa
SiHFR320Ta
SiHFR320TRa
SiHFU320
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
400
20
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
TC = 25 °C
TC =100°C
3.1
Continuous Drain Current
VGS at 10 V
ID
2.0
A
Pulsed Drain Currenta
IDM
12
Linear Derating Factor
0.33
0.020
160
3.1
W/°C
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
EAS
IAR
mJ
A
Repetitive Avalanche Energya
EAR
4.2
mJ
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
TC = 25 °C
42
PD
W
V/ns
°C
TA = 25 °C
2.5
dV/dt
4.0
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
TJ, Tstg
- 55 to + 150
260d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 29 mH, RG = 25 Ω, IAS = 3.1 A (see fig. 12).
c. ISD ≤ 3.1 A, dI/dt ≤ 65 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
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1
IRFR320, IRFU320, SiHFR320, SiHFU320
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
RthJC
-
-
-
-
50
°C/W
Maximum Junction-to-Case (Drain)
3.0
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS
ΔVDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 µA
400
-
-
V
V/°C
V
V
DS Temperature Coefficient
-
0.51
-
Gate-Source Threshold Voltage
Gate-Source Leakage
2.0
-
-
-
-
-
-
4.0
100
25
250
1.8
-
VGS
=
20 V
-
nA
VDS = 400 V, VGS = 0 V
-
-
Zero Gate Voltage Drain Current
IDSS
µA
VDS = 320 V, VGS = 0 V, TJ = 125 °C
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
VGS = 10 V
ID = 1.9 Ab
-
Ω
VDS = 50 V, ID = 1.9 A
1.7
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Ciss
Coss
Crss
Qg
-
-
-
-
-
-
-
-
-
-
350
120
47
-
-
-
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
pF
nC
-
20
3.3
11
-
ID = 3.3 A, VDS = 320 V,
see fig. 6 and 13b
Qgs
Qgd
td(on)
tr
VGS = 10 V
-
-
10
14
30
13
-
VDD = 200 V, ID = 3.3 A,
ns
RG = 18 Ω, RD = 56 Ω, see fig. 10b
Turn-Off Delay Time
Fall Time
td(off)
tf
-
-
D
Between lead,
6 mm (0.25") from
package and center of
die contact
Internal Drain Inductance
LD
LS
-
-
4.5
7.5
-
-
nH
G
Internal Source Inductance
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
D
MOSFET symbol
showing the
integral reverse
p - n junction diode
IS
-
-
-
-
3.1
12
A
G
Pulsed Diode Forward Currenta
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = 3.1 A, VGS = 0 Vb
-
-
-
-
1.6
600
3.0
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
270
1.4
ns
µC
TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/µsb
Qrr
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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IRFR320, IRFU320, SiHFR320, SiHFU320
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 2 - Typical Output Characteristics, TC = 150 °C
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IRFR320, IRFU320, SiHFR320, SiHFU320
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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IRFR320, IRFU320, SiHFR320, SiHFU320
RD
VDS
VGS
D.U.T.
RG
+
V
-
DD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on) tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR320, IRFU320, SiHFR320, SiHFU320
L
VDS
VDS
Vary tp to obtain
required IAS
tp
VDD
D.U.T
IAS
RG
+
-
VDD
VDS
10 V
0.01 Ω
tp
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
-
VDS
D.U.T.
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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IRFR320, IRFU320, SiHFR320, SiHFU320
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T
• Low leakage inductance
current transformer
-
+
-
-
+
RG
• dV/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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相关型号：
IRFR320BTM
Power Field-Effect Transistor, 3.1A I(D), 400V, 1.75ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, DPAK-3
FAIRCHILD
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