IRFR310TRLA [KERSEMI]
Power MOSFET; 功率MOSFET
| 型号： | IRFR310TRLA |
| 厂家： | 
Kersemi Electronic Co., Ltd. |
| 描述： | Power MOSFET |
| 文件： | 总7页 (文件大小：3933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFR310, IRFU310, SiHFR310, SiHFU310
Power MOSFET
FEATURES
• Dynamic dV/dt Rating
PRODUCT SUMMARY
VDS (V)
400
Available
• Repetitive Avalanche Rated
3.6
RDS(on) (Ω)
VGS = 10 V
RoHS*
• Surface Mount (IRFR310/SiHFR310)
COMPLIANT
Qg (Max.) (nC)
12
1.9
6.5
• Straight Lead (IRFU310/SiHFU310)
• Available in Tape and Reel
• Fast Switching
Q
gs (nC)
Qgd (nC)
Configuration
Single
• Fully Avalanche Rated
• Lead (Pb)-free Available
D
DPAK
IPAK
(TO-252)
(TO-251)
DESCRIPTION
Third generation Power MOSFETs form Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
G
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
IRFR310PbF
SiHFR310-E3
IRFR310
DPAK (TO-252)
DPAK (TO-252)
IRFR310TRPbFa
SiHFR310T-E3a
IRFR310TRa
DPAK (TO-252)
IRFR310TRRPbFa
SiHFR310TR-E3a
IPAK (TO-251)
IRFU310PbF
SiHFU310-E3
IRFU310
IRFR310TRLPbFa
SiHFR310TL-E3a
IRFR310TRLa
Lead (Pb)-free
-
-
SnPb
SiHFR310
SiHFR310TLa
SiHFR310Ta
SiHFU310
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
400
20
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
TC = 25 °C
1.7
Continuous Drain Current
VGS at 10 V
ID
TC = 100 °C
1.1
A
Pulsed Drain Currenta
IDM
6.0
Linear Derating Factor
0.20
0.020
86
W/°C
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
EAS
IAR
mJ
A
1.7
Repetitive Avalanche Energya
EAR
2.5
mJ
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
TC = 25 °C
25
PD
W
V/ns
°C
TA = 25 °C
2.5
dV/dt
4.0
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
TJ, Tstg
- 55 to + 150
260d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 52 mH, RG = 25 Ω, IAS = 1.7 A (see fig. 12).
c. ISD ≤ 1.7 A, dI/dt ≤ 40 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1” square PCB (FR-4 or G-10 material).
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1
IRFR310, IRFU310, SiHFR310, SiHFU310
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
(PCB Mounted, steady-state)a
RthJA
-
50
°C/W
Maximum Junction-to-Ambient
Maximum Junction-to-Case
RthJA
RthJC
-
-
110
5.0
Note
a. When mounted on 1" square PCB ( FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS
ΔVDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 µA
400
-
-
V
V/°C
V
V
DS Temperature Coefficient
-
0.47
-
Gate-Source Threshold Voltage
Gate-Source Leakage
2.0
-
-
-
-
-
-
4.0
100
25
250
3.6
-
VGS
VDS = 400 V, VGS = 0 V
VDS = 320 V, VGS = 0 V, TJ = 125 °C
VGS = 10 V
ID = 1.0 Ab
=
20 V
-
nA
-
Zero Gate Voltage Drain Current
IDSS
µA
-
-
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
Ω
VDS = 50 V, ID = 1.0 Ab
0.97
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Ciss
Coss
Crss
Qg
-
-
-
-
-
-
-
-
-
-
170
34
6.3
-
-
VGS = 0 V,
VDS = 25 V,
-
-
pF
nC
f = 1.0 MHz, see fig. 5c
12
1.9
6.5
-
ID = 2.0 A, VDS = 320 V,
see fig. 6 and 13b, c
Qgs
Qgd
td(on)
tr
V
GS = 10 V
-
-
7.9
9.9
21
11
-
V
DD = 200 V, ID = 2.0 A,
RG = 24 Ω, RD = 95 Ω,
see fig. 10b, c
ns
Turn-Off Delay Time
Fall Time
td(off)
tf
-
-
D
Between lead,
Internal Drain Inductance
Internal Source Inductance
LD
LS
-
-
4.5
7.5
-
-
6 mm (0.25") from
package and center of
die contact
nH
G
S
Drain-Source Body Diode Characteristics
D
MOSFET symbol
showing the
integral reverse
p - n junction diode
Continuous Source-Drain Diode Current
IS
-
-
-
-
1.7
6.0
A
G
Pulsed Diode Forward Currenta
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = 1.7 A, VGS = 0 Vb
-
-
-
-
1.6
540
1.6
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
240
0.85
ns
µC
TJ = 25 °C, IF = 2.0 A, dI/dt = 100 A/µsb
Qrr
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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IRFR310, IRFU310, SiHFR310, SiHFU310
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFR310, IRFU310, SiHFR310, SiHFU310
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Maximum Safe Operating Area
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IRFR310, IRFU310, SiHFR310, SiHFU310
RD
VDS
VGS
D.U.T.
RG
+
V
-
DD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on) tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
VDS
VDS
Vary tp to obtain
required IAS
tp
VDD
D.U.T.
RG
+
-
VDD
VDS
IAS
10 V
0.01 Ω
tp
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
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IRFR310, IRFU310, SiHFR310, SiHFU310
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
-
VDS
D.U.T.
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
Fig. 13a - Basic Gate Charge Waveform
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IRFR310, IRFU310, SiHFR310, SiHFU310
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T.
• Low leakage inductance
current transformer
-
+
-
-
+
RG
+
-
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = 5 V for logic level and 3 V drive devices
Fig. 14 - For N-Channel
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相关型号：
IRFR310TRR
Power Field-Effect Transistor, 1.7A I(D), 400V, 3.6ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA
VISHAY
IRFR312
Power Field-Effect Transistor, 1A I(D), 400V, 5ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET
SAMSUNG
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