IRF9630 [KERSEMI]

Power MOSFET; 功率MOSFET
IRF9630
型号: IRF9630
厂家: Kersemi Electronic Co., Ltd.    Kersemi Electronic Co., Ltd.
描述:

Power MOSFET
功率MOSFET

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IRF9630, SiHF9630  
Power MOSFET  
FEATURES  
• Dynamic dV/dt Rating  
PRODUCT SUMMARY  
VDS (V)  
- 200  
Available  
• Repetitive Avalanche Rated  
• P-Channel  
RDS(on) (Max.) (Ω)  
VGS = - 10 V  
0.80  
RoHS*  
Qg (Max.) (nC)  
29  
5.4  
COMPLIANT  
• Fast Switching  
Q
Q
gs (nC)  
gd (nC)  
• Ease of Paralleling  
• Simple Drive Requirements  
• Lead (Pb)-free Available  
15  
Configuration  
Single  
S
DESCRIPTION  
TO-220  
Third generation Power MOSFETs from Vishay provide the  
designer with the best combination of fast switching,  
ruggedized device design, low on-resistance and  
cost-effectiveness.  
G
The TO-220 package is universally preferred for all  
commercial-industrial applications at power dissipation  
levels to approximately 50 W. The low thermal resistance  
and low package cost of the TO-220 contribute to its wide  
acceptance throughout the industry.  
S
D
D
G
P-Channel MOSFET  
ORDERING INFORMATION  
Package  
TO-220  
IRF9630PbF  
SiHF9630-E3  
IRF9630  
Lead (Pb)-free  
SnPb  
SiHF9630  
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted  
PARAMETER  
SYMBOL  
LIMIT  
- 200  
20  
UNIT  
Drain-Source Voltage  
Gate-Source Voltage  
VDS  
V
VGS  
T
C = 25 °C  
- 6.5  
- 4.0  
- 26  
Continuous Drain Current  
VGS at - 10 V  
ID  
TC = 100 °C  
A
Pulsed Drain Currenta  
IDM  
Linear Derating Factor  
0.59  
500  
W/°C  
mJ  
A
Single Pulse Avalanche Energyb  
Repetitive Avalanche Currenta  
Repetitive Avalanche Energya  
EAS  
IAR  
- 6.4  
7.4  
EAR  
mJ  
W
Maximum Power Dissipation  
T
C = 25 °C  
PD  
74  
Peak Diode Recovery dV/dtc  
dV/dt  
TJ, Tstg  
- 5.0  
- 55 to + 150  
300d  
10  
V/ns  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak Temperature)  
°C  
for 10 s  
6-32 or M3 screw  
lbf · in  
N · m  
Mounting Torque  
1.1  
Notes  
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).  
b. VDD = - 50 V, starting TJ = 25 °C, L = 17 mH, RG = 25 Ω, IAS = - 6.5 A (see fig. 12).  
c. ISD - 6.5 A, dI/dt ≤ 120 A/µs, VDD VDS, TJ 150 °C.  
d. 1.6 mm from case.  
www.kersemi.com  
1
IRF9630, SiHF9630  
THERMAL RESISTANCE RATINGS  
PARAMETER  
SYMBOL  
TYP.  
MAX.  
62  
UNIT  
Maximum Junction-to-Ambient  
Case-to-Sink, Flat, Greased Surface  
Maximum Junction-to-Case (Drain)  
RthJA  
RthCS  
RthJC  
-
0.50  
-
-
°C/W  
1.7  
SPECIFICATIONS TJ = 25 °C, unless otherwise noted  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Static  
Drain-Source Breakdown Voltage  
VDS Temperature Coefficient  
Gate-Source Threshold Voltage  
Gate-Source Leakage  
VDS  
ΔVDS/TJ  
VGS(th)  
IGSS  
VGS = 0 V, ID = - 250 µA  
- 200  
-
-
-
V
V/°C  
V
Reference to 25 °C, ID = - 1 mA  
VDS = VGS, ID = - 250 µA  
-
- 0.24  
- 2.0  
-
-
-
-
-
-
- 4.0  
VGS  
=
20 V  
-
100  
- 100  
- 500  
0.80  
-
nA  
VDS = - 200 V, VGS = 0 V  
-
-
Zero Gate Voltage Drain Current  
IDSS  
µA  
VDS = - 160 V, VGS = 0 V, TJ = 125 °C  
Drain-Source On-State Resistance  
Forward Transconductance  
Dynamic  
RDS(on)  
gfs  
VGS = - 10 V  
ID = - 3.9 Ab  
-
Ω
VDS = - 50 V, ID = - 3.9 Ab  
2.8  
S
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
Turn-On Delay Time  
Rise Time  
Ciss  
Coss  
Crss  
Qg  
-
-
-
-
-
-
-
-
-
-
700  
200  
40  
-
-
-
VGS = 0 V,  
VDS = - 25 V,  
f = 1.0 MHz, see fig. 5  
pF  
nC  
-
29  
5.4  
15  
-
ID = - 6.5 A,  
Qgs  
Qgd  
td(on)  
tr  
VGS = - 10 V  
VDS = - 160 V,  
-
see fig. 6 and 13b  
-
12  
27  
28  
24  
-
VDD = - 100 V, ID = - 6.5 A,  
ns  
Turn-Off Delay Time  
Fall Time  
td(off)  
tf  
r
G = 12 Ω, rD = 15 Ω, see fig. 10b  
-
-
D
Between lead,  
Internal Drain Inductance  
Internal Source Inductance  
LD  
LS  
-
-
4.5  
7.5  
-
-
6 mm (0.25") from  
package and center of  
die contact  
nH  
G
S
Drain-Source Body Diode Characteristics  
MOSFET symbol  
showing the  
integral reverse  
p - n junction diode  
D
Continuous Source-Drain Diode Current  
IS  
-
-
-
-
- 6.5  
- 26  
A
G
Pulsed Diode Forward Currenta  
ISM  
S
Body Diode Voltage  
VSD  
trr  
TJ = 25 °C, IS = - 6.5 A, VGS = 0 Vb  
-
-
-
-
- 6.5  
300  
2.9  
V
Body Diode Reverse Recovery Time  
Body Diode Reverse Recovery Charge  
Forward Turn-On Time  
200  
1.9  
ns  
µC  
TJ = 25 °C, IF = - 6.5 A, dI/dt = 100 A/µsb  
Qrr  
ton  
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)  
Notes  
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).  
b. Pulse width 300 µs; duty cycle 2 %.  
www.kersemi.com  
2
IRF9630, SiHF9630  
Fig. 1 - Typical Output Characteristics, TC = 25 °C  
Fig. 3 - Typical Transfer Characteristics  
Fig. 4 - Normalized On-Resistance vs. Temperature  
Fig. 2 - Typical Output Characteristics, TC = 150 °C  
www.kersemi.com  
3
IRF9630, SiHF9630  
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage  
Fig. 7 - Typical Source-Drain Diode Forward Voltage  
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage  
Fig. 8 - Maximum Safe Operating Area  
www.kersemi.com  
4
IRF9630, SiHF9630  
RD  
VDS  
VGS  
D.U.T.  
RG  
+
-
V
DD  
- 10 V  
Pulse width 1 µs  
Duty factor 0.1 %  
Fig. 10a - Switching Time Test Circuit  
td(on) tr  
td(off) tf  
VGS  
10 %  
90 %  
VDS  
Fig. 9 - Maximum Drain Current vs. Case Temperature  
Fig. 10b - Switching Time Waveforms  
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case  
IAS  
L
VDS  
Vary tp to obtain  
required IAS  
VDS  
D.U.T  
IAS  
RG  
-
V
+
DD  
VDD  
tp  
- 10 V  
A
0.01 Ω  
tp  
VDS  
Fig. 12b - Unclamped Inductive Waveforms  
Fig. 12a - Unclamped Inductive Test Circuit  
www.kersemi.com  
5
IRF9630, SiHF9630  
Fig. 12c - Maximum Avalanche Energy vs. Drain Current  
Current regulator  
Same type as D.U.T.  
50 kΩ  
QG  
- 10 V  
12 V  
0.2 µF  
0.3 µF  
-
QGS  
QGD  
V
+
DS  
D.U.T.  
VG  
VGS  
- 3 mA  
Charge  
IG  
ID  
Current sampling resistors  
Fig. 13b - Gate Charge Test Circuit  
Fig. 13a - Basic Gate Charge Waveform  
www.kersemi.com  
6
IRF9630, SiHF9630  
Peak Diode Recovery dV/dt Test Circuit  
D.U.T.  
+
Circuit layout considerations  
Low stray inductance  
Ground plane  
Low leakage inductance  
current transformer  
-
+
-
+
-
RG  
+
-
dV/dt controlled by RG  
ISD controlled by duty factor "D"  
D.U.T. - device under test  
VDD  
Compliment N-Channel of D.U.T. for driver  
Driver gate drive  
P.W.  
Period  
Period  
D =  
P.W.  
V
= - 10 V*  
GS  
D.U.T. I waveform  
SD  
Reverse  
recovery  
current  
Body diode forward  
current  
dI/dt  
D.U.T. V waveform  
DS  
Diode recovery  
dV/dt  
V
DD  
Re-applied  
voltage  
Body diode forward drop  
Ripple 5 %  
Inductor current  
I
SD  
* VGS = - 5 V for logic level and - 3 V drive devices  
Fig. 14 - For P-Channel  
www.kersemi.com  
7

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