IS61WV20488BLL [ISSI]
2M x 8 HIGH-SPEED CMOS STATIC RAM; 2M ×8高速CMOS静态RAM
| 型号： | IS61WV20488BLL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 2M x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总20页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
PRELIMINARYINFORMATION
JANUARY2006
2M x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
DESCRIPTION
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
TheISSIIS61WV20488ALL/BLLandIS64WV20488BLL
are very high-speed, low power, 2M-word by 8-bit CMOS
static RAM. The IS61WV20488ALL/BLL and
IS64WV20488BLLarefabricatedusingISSI'shigh-
performance CMOS technology. This highly reliable
process coupled with innovative circuit design tech-
niques, yields higher performance and low power con-
sumption devices.
options
• CE power-down
• Fully static operation: no clock or refresh
required
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• TTL compatible inputs and outputs
• Single power supply
TheIS61WV20488ALL/BLLandIS64WV20488BLL
operate from a single power supply and all inputs are
TTL-compatible.
– VDD 1.65V to 2.2V (IS61WV20488ALL)
speed = 20ns for Vcc = 1.65V to 2.2V
– VDD 2.4V to 3.6V (IS61/64WV20488BLL)
speed = 10ns for Vcc = 2.4V to 3.6V
speed = 8ns for Vcc = 3.3V + 5%
• Packages available:
TheIS61WV20488ALL/BLLandIS64WV20488BLLare
available in 48 ball mini BGA and 44-pin TSOP (Type II)
packages.
–
48-ball miniBGA (9mm x 11mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
2M X 8
MEMORY ARRAY
A0-A20
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
PIN CONFIGURATION
48-pin Mini BGA (M ) (9mm x 11mm)
44-pin TSOP (Type II )
1
2
3
4
5
6
NC
NC
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
2
NC
3
A20
A18
A17
A16
A15
OE
A1
4
A2
5
A3
6
A
B
C
D
E
F
NC
NC
OE
NC
NC
NC
NC
NC
A19
A8
A0
A3
A1
A4
A2
CE
NC
I/O0
I/O2
A4
7
CE
8
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
9
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
A19
NC
NC
A5
A6
I/O1
I/O3
I/O4
I/O5
WE
A11
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
A17
NC
A14
A12
A9
A7
VDD
VDD
A16
A15
A13
A10
GND
I/O6
I/O7
A20
NC
NC
G
H
A6
A18
A7
A8
A9
NC
NC
NC
PIN DESCRIPTIONS
A0-A20
CE
Address Inputs
Chip Enable Input
OE
Output Enable Input
Write Enable Input
Data Input / Output
Power
WE
I/O0-I/O7
VDD
GND
NC
Ground
NoConnection
2
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Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
TRUTH TABLE
Mode
WE CE OE I/OOperation VDD Current
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
OutputDisabled H
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Read
Write
H
L
X
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
V
°C
W
VTERM
VDD
Terminal Voltage with Respect to GND
VDD Relates to GND
–0.5 to VDD + 0.5
–0.3 to 4.0
–65 to +150
1.0
TSTG
PT
StorageTemperature
PowerDissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
CI/O
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
OPERATING RANGE (VDD) (IS61WV20488ALL)
Range
AmbientTemperature
0°C to +70°C
VDD (20 nS)
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Commercial
Industrial
Automotive
–40°Cto+85°C
–40°Cto+125°C
OPERATING RANGE (VDD) (IS61WV20488BLL)(1)
Range
Commercial
Industrial
AmbientTemperature
0°C to +70°C
VDD (8 nS)
3.3V + 5%
3.3V + 5%
VDD (10 nS)
2.4V-3.6V
2.4V-3.6V
–40°Cto+85°C
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of
3.3V + 5%, the device meets 8ns.
OPERATING RANGE (VDD) (IS64WV20488BLL)
Range
AmbientTemperature
VDD (10 nS)
Automotive
–40°Cto+125°C
2.4V-3.6V
4
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Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2
VDD + 0.3
V
–0.3
–1
0.8
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL(min.)=–0.3VDC;VIL (min.)=–2.0VAC(pulsewidth-2.0ns).Not100%tested.
IH(max.)=VDD +0.3VDC;VIH(max.)=VDD+2.0VAC(pulsewidth-2.0ns).Not100%tested.
V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter
TestConditions
Min.
1.8
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 1.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
InputLOWVoltage(1)
InputLeakage
0.4
V
2.0
–0.3
–1
VDD + 0.3
V
0.8
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL(min.)=–0.3VDC;VIL(min.)=–2.0VAC(pulsewidth-2.0ns).Not100%tested.
IH(max.)=VDD +0.3VDC;VIH(max.)=VDD+2.0VAC(pulsewidth-2.0ns).Not100%tested.
V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter
TestConditions
IOH = -0.1 mA
IOL = 0.1 mA
VDD
Min.
1.4
—
Max.
Unit
V
VOH
VOL
VIH
OutputHIGHVoltage
1.65-2.2V
1.65-2.2V
1.65-2.2V
1.65-2.2V
—
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
InputLeakage
0.2
V
1.4
–0.2
–1
VDD + 0.2
V
(1)
VIL
ILI
0.4
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1. VIL(min.)=–0.3VDC;VIL(min.)=–2.0VAC(pulsewidth-2.0ns).Not100%tested.
VIH(max.)=VDD +0.3VDC;VIH(max.)=VDD+2.0VAC(pulsewidth-2.0ns).Not100%tested.
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Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
AC TEST CONDITIONS (HIGH SPEED)
Parameter
Unit
Unit
Unit
(2.4V-3.6V)
0.4V to VDD-0.3V
1.5ns
(3.3V + 5%)
0.4V to VDD-0.3V
1.5ns
(1.65V-2.2V)
0.4V to VDD-0.2V
1.5ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
VDD/2
VDD/2 + 0.05
VDD/2
andReferenceLevel(VRef)
OutputLoad
See Figures 1 and 2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.
Figure 2.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
-10
Min. Max.
-20
Min. Max.
Symbol Parameter
Test Conditions
Min.
Max.
Unit
ICC
VDD Dynamic Operating VDD = Max.,
Com.
Ind.
—
—
—
120
125
—
—
—
—
95
100
140
—
—
—
90
100
140
mA
Supply Current
IOUT = 0 mA, f = fMAX
Auto.
typ.(2)
60
ICC1
Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
35
35
—
—
—
—
30
40
60
—
—
—
30
40
70
mA
mA
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
30
35
—
—
—
—
30
35
70
—
—
—
30
35
70
ISB2
CMOS Standby
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
VDD = Max.,
Com.
Ind.
—
—
—
20
25
—
—
—
—
20
25
70
—
—
—
15
20
70
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Auto.
typ.(2)
4
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
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Rev. 00C
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IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
-10
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
AA
OHA
ACE
DOE
ReadCycleTime
AddressAccessTime
OutputHoldTime
CEAccessTime
OEAccessTime
OEtoHigh-ZOutput
OEtoLow-ZOutput
CEtoHigh-ZOutput
CEtoLow-ZOutput
PowerUpTime
8
—
2
—
8
10
—
2
—
10
—
10
6.5
4
t
t
—
8
t
—
—
—
0
—
—
—
0
t
5.5
3
(2)
tHZOE
(2)
tLZOE
—
3
—
4
(2
t
HZCE
0
0
(2)
tLZCE
3
—
—
8
3
—
—
10
tPU
0
0
tPD
PowerDownTime
—
—
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0Vandoutputloading
specifiedinFigure1.
2. TestedwiththeloadinFigure2. Transitionismeasured 500mVfromsteady-statevoltage.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns
Symbol
tRC
Parameter
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
PowerUpTime
20
—
2.5
—
—
0
—
20
—
20
8
tAA
tOHA
tACE
tDOE
(2)
tHZOE
8
(2)
tLZOE
0
—
8
(2
tHZCE
0
(2)
tLZCE
3
—
—
20
tPU
0
tPD
PowerDownTime
—
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
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Rev. 00C
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IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t
RC
ADDRESS
t
AA
t
OHA
OE
CE
t
HZOE
t
DOE
t
t
LZOE
ACE
t
HZCE
t
LZCE
HIGH-Z
D
OUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
10
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Rev. 00C
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IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-10
Symbol
Parameter
Min.
8
Max.
—
Min.
10
8
Max.
—
Unit
t
WC
SCE
AW
WriteCycleTime
CEtoWriteEnd
ns
ns
ns
t
6.5
6.5
—
—
t
AddressSetupTime
toWriteEnd
—
8
—
t
HA
SA
PWE
PWE
SD
HD
HZWE
AddressHoldfromWriteEnd
AddressSetupTime
0
0
—
—
—
—
—
—
3.5
—
0
0
—
—
—
—
—
—
5
ns
ns
ns
ns
ns
ns
ns
ns
t
t
1
WEPulseWidth(OE=HIGH)
WEPulseWidth (OE=LOW)
DataSetuptoWriteEnd
6.5
8.0
5
8
t
2
10
6
t
t
DataHoldfromWriteEnd
WELOWtoHigh-ZOutput
WEHIGHtoLow-ZOutput
0
0
(2)
(2)
t
—
2
—
2
tLZWE
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edgeofthesignalthatterminatesthewrite.Shadedareaproductindevelopment
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Rev. 00C
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IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20 ns
Symbol
tWC
Parameter
Min. Max.
Unit
ns
Write Cycle Time
CE to Write End
20
12
12
—
—
—
tSCE
ns
tAW
Address Setup Time
to Write End
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
9
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPWE1
tPWE2
tSD
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
12
17
9
tHD
0
(3)
tHZWE
—
3
(3)
tLZWE
—
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V,
input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input
Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
12
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Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
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Rev. 00C
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IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
14
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Rev. 00C
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IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
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Rev. 00C
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IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Min.
Max.
Unit
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 1.2V, CE ≥ VDD – 0.2V
1.2
3.6
V
IDR
Ind.
—
—
25
60
3
mA
Auto.
typ.(1)
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
—
—
ns
ns
tRC
Note:
1. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
t
SDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CE ≥ VDD - 0.2V
CE
GND
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
01/09/06
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
®
ISSI
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
10(81)
IS61WV20488BLL-10MI
48 mini BGA (9mm x 11mm)
IS61WV20488BLL-10MLI 48 mini BGA (9mm x 11mm), Lead-free
IS61WV20488BLL-10TI
IS61WV20488BLL-10TLI
TSOP (Type II)
TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.3V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed(ns)
Order Part No.
Package
20
IS61WV20488ALL-20MI
IS61WV20488ALL-20TI
48 mini BGA (9mm x 11mm)
TSOP (Type II)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed(ns)
Order Part No.
Package
10
IS64WV20488BLL-10MA3 48 mini BGA (9mm x 11mm)
IS64WV20488BLL-10TA3 TSOP (Type II)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
17
Rev. 00C
01/09/06
®
PACKAGING INFORMATION
Mini Ball Grid Array
ISSI
Package Code: M (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controlling dimensions are in millimeters.
A2
A
A1
SEATING PLANE
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
®
PACKAGING INFORMATION
Mini Ball Grid Array
ISSI
Package Code: M (48-pin)
mBGA - 6mm x 8mm
MILLIMETERS
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
—
—
—
—
1.20
0.40
—
.—
0.010 — 0.016
0.024
— 0.047
A1
A2
D
0.25
0.60
—
—
7.90 8.00 8.10
5.60BSC
0.311 0.314 0.319
0.220BSC
D1
E
5.90 6.00 6.10
4.00BSC
0.232 0.236 0.240
0.157BSC
E1
e
0.80BSC
0.031BSC
b
0.40 0.45 0.50
0.016 0.018 0.020
mBGA - 7.2mm x 8.7mm
mBGA - 9mm x 11mm
MILLIMETERS
INCHES
MILLIMETERS
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
48
Leads
48
A
—
—
—
—
1.20
0.30
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
1.20
0.30
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0 .24
0.60
0.009
0.024
A1
A2
D
0.24
0.60
0.009
0.024
8.60 8.70 8.80
5.25BSC
0.339 0.343 0.346
0.207BSC
10.90 11.00 11.10
5.25BSC
0.429 0.433 0.437
0.207BSC
D1
E
D1
E
7.10 7.20 7.30
3.75BSC
0.280 0.283 0.287
0.148BSC
8.90 9.00 9.10
3.75BSC
0.350 0.354 0.358
0.148BSC
E1
e
E1
e
0.75BSC
0.030BSC
0.75BSC
0.030BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.D
01/15/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
相关型号：
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