IS61WV204816ALL-10BL [ISSI]
Standard SRAM, 2MX16, 10ns, CMOS, PBGA48, MINIBGA-48;
| 型号： | IS61WV204816ALL-10BL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 2MX16, 10ns, CMOS, PBGA48, MINIBGA-48 静态存储器 |
| 文件： | 总17页 (文件大小：628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61/64WV204816ALL
IS61/64WV204816BLL
OCTOBER 2016
2Mx16 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY
FEATURES
High-speed access time: 10ns, 12ns
High- performance, low power CMOS process
Multiple center power and ground pins for
greater noise immunity
DESCRIPTION
The ISSI IS61/64WV204816ALL/BLL are high-speed, 32M
bit static RAMs organized as 2048K words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technology.
Easy memory expansion with CS# and OE#
TTL compatible inputs and outputs
Single power supply
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
–
–
1.65V-2.2V VDD (IS61/64WV204816ALL)
2.4V-3.6V VDD (IS61/64WV204816BLL)
When CS# is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels. Easy memory
expansion is provided by using Chip Enable and Output
Enable inputs. The active LOW Write Enable (WE#)
controls both writing and reading of the memory. A data
byte allows Upper Byte (UB#) and Lower Byte (LB#) access.
Packages available :
- 48 ball mini BGA (6mm x 8mm)
- 48 pin TSOP (Type I)
Industrial and Automotive temperature support
Lead-free available
The device is packaged in the JEDEC standard 48-Pin
TSOP (TYPE I) and 48-pin mini BGA (6mm x 8mm).
Data Control for upper and lower bytes
FUNCTIONAL BLOCK DIAGRAM
2048K x16
MEMORY
ARRAY
DECODER
A0 – A20
VDD
VSS
I/O0– I/O7
Lower Byte
I/ O
DATA
COLUMN IO
I/O8– I/O15
CIRCUIT
Upper Byte
CS#
CONTROL
CIRCUIT
OE#
WE#
UB#
LB#
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
1
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PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
48-Pin TSOP ,TYPE I ( 12mm x 20mm )
1
2
3
4
5
6
A5
A6
1
48
A4
2
3
47
A3
A2
A
B
46
45
44
43
A7
LB#
OE#
A0
A1
A2
NC
A8
4
5
A1
A0
NC
OE#
6
7
8
9
UB#
LB#
42
41
40
39
CS#
I/O0
I/O8
I/O9
UB#
A3
A5
A4
A6
CE#
I/O1
I/O0
I/O2
I/O15
I/O14
I/O1
I/
2
O
I/O13
I/O12
10
11
I/O10
C
D
I/O3
38
37
VSS
VDD
I/O11
I/O10
I/O9
I/O8
A20
12
VDD
VSS
I/O4
36
35
34
33
32
31
30
13
14
VSS
VDD
I/O11
I/O12
A17
NC
A7
I/O3
I/O4
VDD
VSS
I/O5
I/O6
15
16
17
18
19
20
I/O7
WE#
E
A16
A 9
NC
A19
29
28
A10
A11
A12
A13
A14
21
A18
A17
22
23
24
27
26
25
F
I/O14
I/O15
A18
I/O13
A19
A8
A14
A12
A9
A15
A13
A10
I/O5
WE#
A11
I/O6
I/O7
A20
A16
A15
G
H
PIN DESCRIPTIONS
A0-A20
I/O0-I/O15
CS#
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE#
WE#
LB#
Lower-byte Control
(I/O0-I/O7)
UB#
Upper-byte Control
(I/O8-I/O15)
NC
No Connection
Power
VDD
VSS
Ground
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FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high
impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-
15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a
byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified
on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location.
READ MODE
Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output
buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a
byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from
memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
POWER UP INITIALIZATION
The device includes on-chip voltage sensor used to launch POWER-UP initialization process.
When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization
process.
When initialization is complete, the device is ready for normal operation.
tPU 150 us
Stable VDD
VDD
Device Initialization
Device for Normal Operation
0V
TRUTH TABLE
Mode
CS#
WE#
OE#
LB#
UB#
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
H
L
L
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
H
L
L
L
X
X
X
X
L
H
L
H
L
L
X
L
L
H
L
L
H
L
L
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
ISB1, ISB2
Output Disabled
ICC
Read
ICC
ICC
Write
L
L
H
L
High-Z
DIN
DIN
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ABSOLUTE MAXIMUM RATINGS AND Operating Range
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Parameter
Terminal Voltage with Respect to VSS
VDD Related to VSS
Value
–0.5 to VDD + 0.5V
Unit
V
VDD
tStg
PT
–0.3 to 4.0
–65 to +150
1.0
V
Storage Temperature
C
W
Power Dissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PIN CAPACITANCE (1)
Parameter
Symbol
CIN
Test Condition
Max
6
Units
pF
Input capacitance
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
DQ capacitance (IO0–IO15)
CI/O
8
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
OPERATING RANGE
Range
Ambient
PART NUMBER
VDD
SPEED (MAX)
Temperature
1.65V – 2.2V
2.4V – 3.6V
1.65V – 2.2V
2.4V – 3.6V
1.65V – 2.2V
2.4V – 3.6V
IS61WV204816ALL
IS61WV204816BLL
IS61WV204816ALL
IS61WV204816BLL
IS64WV204816ALL
IS64WV204816BLL
Commercial
Industrial
10 ns
0C to +70C
10 ns
12 ns
-40C to +85C
-40C to +125C
Automotive (A3)
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
Unit
(1.65V~2.2V)
(2.4V~3.6V)
Input Pulse Level
Input Rise and Fall Time
Output Timing Reference Level
R1 (ohm)
0V to VDD
0V to VDD
1.5 ns
½ VDD
13500
10800
1.8V
1.5 ns
½ VDD
319
R2 (ohm)
353
VTM (V)
3.3V
Output Load Conditions
Refer to Figure 1 and 2
AC TEST LOADS
FIGURE 1
FIGURE 2
R1
VTM
Zo = 50 ohm
50 ohm
VDD/2
30 pF,
OUTPUT
Output
5pF,
Including
jig
Including
jig
and scope
R2
and scope
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DC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
VDD = 1.65V – 2.2V
Symbol
VOH
Parameter
Test Conditions
IOH = -0.1 mA
IOL = 0.1 mA
Min.
1.4
—
Max.
Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
—
VOL
0.2
V
(1)
VIH
1.4
–0.2
–1
VDD + 0.2
V
(1)
VIL
0.4
1
V
ILI
GND < VIN < VDD
µA
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
Note:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (MAX) = VDD + 1.0V AC (PULSE WIDTH < 10NS). NOT 100% TESTED.
VDD = 2.4V – 3.6V
Min.
Max.
Unit
Symbol
Parameter
2.4V ~ 2.7V
Test Conditions
VDD = Min., IOH = -1.0 mA
VDD = Min., IOH = -4.0 mA
VDD = Min., IOL = 2.0 mA
VDD = Min., IOL = 8.0 mA
VOH
Output HIGH
Voltage
2.0
2.2
—
V
—
2.7V ~ 3.6V
2.4V ~ 2.7V
2.7V ~ 3.6V
2.4V ~ 2.7V
2.7V ~ 3.6V
2.4V ~ 2.7V
2.7V ~ 3.6V
VOL
Output LOW
Voltage
V
0.4
0.4
—
(1)
VIH
Input HIGH Voltage
2.0
2.0
–0.3
–0.3
–2
V
V
VDD + 0.3
(1)
VIL
Input LOW Voltage
0.6
0.8
2
ILI
Input Leakage
VSS < VIN < VDD
µA
µA
ILO
Output Leakage
VSS < VIN < VDD, Output Disabled
–2
2
Note:
1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested.
VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested.
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POWER SUPPLY CHARACTERISTICS-II FOR POWER (1, 2) (OVER THE OPERATING RANGE)
IS61/64WV204816ALL (VDD = 1.65V – 2.2V) & IS61/64WV204816BLL (VDD = 2.4V – 3.6V)
-10
-12
Symbol
Parameter
Test Conditions
Grade
Unit
Max. Max.
Com.
90
100
140
80
90
110
60
70
110
50
85
95
135
80
90
110
60
70
110
50
VDD Dynamic Operating
Supply Current
ICC
VDD = MAX, IOU T = 0 mA, f = fMAX Ind.
Auto.
mA
Com.
Ind.
Auto.
Com.
Ind.
VDD = MAX,
IOUT = 0 mA, f = 0
ICC1
ISB1
Operating Supply Current
mA
mA
VDD = MAX,
VIN = VIH or VIL
CS#≥ VIH , f = 0
TTL Standby Current
(TTL Inputs)
Auto.
Com.
Ind.
VDD = MAX,
60
60
CMOS Standby Current
(CMOS Inputs)
CS#≥ VDD - 0.2V
VIN ≥ VDD - 0.2V , or VIN ≤ 0.2V
, f = 0
ISB2
mA
100
Auto.
Typ. (2)
100
10
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change.
2. Typical values are measured at VDD = 3.0V/1.8V, TA = 25 °C and not 100% tested.
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AC CHARACTERISTICS (OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
-10(1)
-12(1)
Parameter
Symbol
unit notes
Min
10
-
Min
-
Min
12
-
Max
Read Cycle Time
tRC
-
12
-
ns
ns
ns
ns
ns
Address Access Time
Output Hold Time
tAA
10
-
tOHA
tACE
tDOE
tHZOE
tLZOE
tHZCE
tLZCE
tBA
2.5
-
2.5
-
CS# Access Time
10
6
12
7
6
-
OE# Access Time
-
-
OE# to High-Z Output
OE# to Low-Z Output
CS# to High-Z Output
CS# to Low-Z Output
UB#, LB# Access Time
0
5
0
ns
ns
ns
ns
ns
ns
ns
2
2
2
2
0
-
0
0
5
0
6
-
3
-
3
-
6
-
7
6
-
UB#, LB# to High-Z Output tHZB
UB#, LB# to Low-Z Output tLZB
0
5
0
2
2
0
-
0
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of VDD/2, input pulse levels of 0V to VDD and output
loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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AC WAVEFORMS
READ CYCLE NO. 1(1) (Address Controlled, CS# = OE# = UB# = LB# = LOW, WE# = HIGH)
tRC
Address
tAA
tOHA
DATA VALID
tOHA
DQ 0-15
PREVIOUS DATA VALID
Note:
1. The device is continuously selected.
READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH)
tRC
ADDRESS
tAA
tOHA
tDOE
OE#
tHZOE
tLZOE
CS#
tHZCS
tACS
tLZCS
UB#,LB#
tHZB
tBA
tLZB
HIGH-Z
DOUT
LOW-Z
DATA VALID
Note:
1. Address is valid prior to or coincident with CS# LOW transition.
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WRITE CYCLE AC CHARACTERISTICS
-12(1)
Max
-10(1)
Parameter
Symbol
unit
notes
Min Max
Min
12
9
Write Cycle Time
tWC
10
8
-
-
-
-
-
-
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
-
5
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCS
tAW
CS# to Write End
Address Setup Time to Write End
UB#,LB# to Write End
Address Hold from Write End
Address Setup Time
8
9
tPWB
tHA
8
9
0
0
tSA
0
0
tPWE1
tPWE2
tSD
8
9
WE# Pulse Width
10
6
12
7
2
WE# Pulse Width (OE# = LOW)
Data Setup to Write End
Data Hold from Write End
WE# LOW to High-Z Output
WE# HIGH to Low-Z Output
tHD
0
0
tHZWE
tLZWE
-
-
2
2
Notes:
1
The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All conditions must be in valid states
to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2
Tested tPWE > tHZWE + tSD when OE# is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS# CONTROLLED, OE# = HIGH OR LOW)
tWC
ADDRESS
tSCS
tSA
tHA
CS#
tAW
tPWE
WE#
tPWB
UB#,LB#
tHZWE
tLZWE
tHD
HIGH-Z
tSD
DATA UNDEFINED(1)
DOUT
DIN
DATA UNDEFINED (2)
DATA IN VALID
Note:
1. tHZWE is is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before
Write Cycle.
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WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
tWC
ADDRESS
tSCS
tHA
CS#
tAW
tPWE
WE#
tSA
tPWB
UB#,LB#
OE#
DOUT
DIN
tHZOE
HIGH-Z
tHD
DATA UNDEFINED(1)
tSD
DATA UNDEFINED (2)
DATA IN VALID
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
tWC
ADDRESS
OE# = LOW
CS#=LOW
tHA
tAW
tPWE2
tPWB
WE#
tSA
UB#,LB#
tHZWE
tLZWE
HIGHZ
tSD
DOUT
DIN
DATA UNDEFINED
tHD
DATA IN VALID
Note:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
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WRITE CYCLE NO. 4(1, 2, 3) (UB# & LB# Controlled, CS# = OE# = LOW)
tWC
tWC
ADDRESS
ADDRESS 1
ADDRESS 2
CS#=LOW
OE#=LOW
tSA
tHA
tSA
tHA
WE#
tPWB
tPWB
UB#, LB#
WORD 1
WORD 2
tHZWE
tLZWE
HIGH-Z
DOUT
DIN
DATA UNDEFINED
tHD
tSD
DATA IN
VALID
DATA IN
VALID
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
2. Due to the restriction of note1, OE# is recommended to be HIGH during write period.
3. WE# stays LOW in this example. If WE# toggles,, tPWE and tHZWE must be considered.
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DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
OPTION
Min. Typ.(2) Max. Unit
VDD = 2.4V to 3.6V
2.0
1.2
3.6
3.6
VDD for Data
Retention
VDR
See Data Retention Waveform
V
VDD = 1.65V to 2.2V
Com.
Ind.
-
-
-
10
-
50
60
Data Retention
Current
VDD= VDR(min),
CS# ≥ VDD – 0.2V
IDR
mA
Auto
-
100
Data Retention
Setup Time
tSDR
See Data Retention Waveform
See Data Retention Waveform
0
-
-
-
-
ns
ns
tRDR
Recovery Time
tRC
Notes:
1. If CS# > VDD–0.2V, all other inputs including UB# and LB# must meet this condition.
2. Typical values are measured at VDD = VDR (Min), TA = 25 °C and not 100% tested.
DATA RETENTION WAVEFORM (CS# CONTROLLED)
Data Retention Mode
tSDR
tRDR
VDD
VDR
CS# > VDD – 0.2V
CS#
GND
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ORDERING INFORMATION
IS61/64WV204816ALL (1.65V – 2.2V)
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
10
10
10
10
IS61WV204816ALL-10B
IS61WV204816ALL-10BL
IS61WV204816ALL-10T
IS61WV204816ALL-10TL
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I)
TSOP (Type I), Lead-free
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
10
10
10
10
IS61WV204816ALL-10BI
IS61WV204816ALL-10BLI
IS61WV204816ALL-10TII
IS61WV204816ALL-10TLI
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I)
TSOP (Type I), Lead-free
Automotive (A3) Range: –40°C to +125°C
Speed (ns)
Order Part No.
Package
12
12
12
IS64WV204816ALL-12BA3
IS64WV204816ALL-12BLA3
IS64WV204816ALL-12CTLA3
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I), Copper Lead-frame, Lead-free
Integrated Silicon Solution, Inc.- www.issi.com
14
Rev. A
10/27/2016
IS61/64WV204816ALL
IS61/64WV204816BLL
IS61/64WV204816BLL (2.2V - 3.6V)
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
10
10
10
10
IS61WV204816BLL-10B
IS61WV204816BLL-10BL
IS61WV204816BLL-10T
IS61WV204816BLL-10TL
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I)
TSOP (Type I), Lead-free
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
10
10
10
10
IS61WV204816BLL-10BI
IS61WV204816BLL-10BLI
IS61WV204816BLL-10TI
IS61WV204816BLL-10TLI
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I)
TSOP (Type I), Lead-free
Automotive (A3) Range: –40°C to +125°C
Speed (ns)
Order Part No.
Package
12
12
12
IS64WV204816BLL-12BA3
IS64WV204816BLL-12BLA3
IS64WV204816BLL-12CTLA3
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I), Copper Lead-frame, Lead-free
Integrated Silicon Solution, Inc.- www.issi.com
15
Rev. A
10/27/2016
IS61/64WV204816ALL
IS61/64WV204816BLL
PACKAGE INFORMATION
Integrated Silicon Solution, Inc.- www.issi.com
16
Rev. A
10/27/2016
IS61/64WV204816ALL
IS61/64WV204816BLL
Integrated Silicon Solution, Inc.- www.issi.com
17
Rev. A
10/27/2016
相关型号：
IS61WV204816BLL-10BLI
Standard SRAM, 2MX16, 10ns, CMOS, PBGA48, 6 X 8 MM, LEAD FREE, MO-207, TFBGA-48
ISSI
IS61WV204816BLL-10TLI
Standard SRAM, 2MX16, 10ns, CMOS, PDSO48, 12 X 20 MM, LEAD FREE, TSOP1-48
ISSI
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