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IS42S16400E-7TL [ISSI]

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM; 1梅格位×16位× 4银行（ 64兆位）同步动态RAM
IS42S16400E-7TL
型号： IS42S16400E-7TL
厂家： INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述：

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
1梅格位×16位× 4银行（ 64兆位）同步动态RAM
文件： 总55页 (文件大小：790K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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performance.TheꢀsynchronousꢀDRAMsꢀachieveꢀhigh-speedꢀ  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
                                                                
IS42S16400E  
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
AUGUST 2009  
FEATURES  
OVERVIEW  
ISSI'sꢀ 64Mbꢀ Synchronousꢀ DRAMꢀ IS42S16400Eꢀ isꢀ  
•ꢀ Clockꢀfrequency:ꢀ166,ꢀ143ꢀMHz  
organizedꢀasꢀ1,048,576ꢀbitsꢀxꢀ16-bitꢀxꢀ4-bankꢀforꢀimprovedꢀ  
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ  
positive clock edge  
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge  
•ꢀ Singleꢀ3.3Vꢀpowerꢀsupply  
•ꢀ LVTTLꢀinterface  
PIN CONFIGURATIONS  
54-Pin TSOP (Type II)  
•ꢀ Programmableꢀburstꢀlengthꢀ  
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
GNDQ  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
GNDQ  
DQ7  
VDD  
LDQM  
WE  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
GND  
DQ15  
GNDQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
GNDQ  
DQ10  
DQ9  
VDDQ  
DQ8  
GND  
NC  
•ꢀ Programmableꢀburstꢀsequence:ꢀ  
Sequential/Interleave  
2
3
4
5
•ꢀ Selfꢀrefreshꢀmodes  
6
7
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms  
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle  
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ  
UDQM  
CLK  
CKE  
NC  
operations capability  
CAS  
RAS  
CS  
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ  
BA0  
BA1  
A10  
A11  
command  
A9  
A8  
•ꢀ ByteꢀcontrolledꢀbyꢀLDQMꢀandꢀUDQM  
•ꢀ Package:ꢀꢀ400-milꢀ54-pinꢀTSOPꢀII  
•ꢀ Lead-freeꢀpackageꢀisꢀavailable  
•ꢀ AvailableꢀinꢀIndustrialꢀtemperature  
A0  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VDD  
GND  
PIN DESCRIPTIONS  
WEꢀ  
ꢀ
ꢀ
WriteꢀEnable  
A0-A11ꢀ ꢀ  
AddressꢀInput  
LDQMꢀ  
LowerꢀBye,ꢀInput/OutputꢀMask  
UpperꢀBye,ꢀInput/OutputꢀMask  
Power  
BA0,ꢀBA1ꢀ  
BankꢀSelectꢀAddress  
DataꢀI/O  
UDQMꢀ ꢀ  
DQ0ꢀtoꢀDQ15ꢀ  
VDDꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
CLKꢀ  
CKEꢀ  
CS  
ꢀ
ꢀ
SystemꢀClockꢀInput  
ClockꢀEnable  
GNDꢀ  
VDDqꢀ  
GNDqꢀ  
NC  
Ground  
PowerꢀSupplyꢀforꢀDQꢀPin  
GroundꢀforꢀDQꢀPin  
No Connection  
Chip Select  
RASꢀ  
CAS  
ꢀ
RowꢀAddressꢀStrobeꢀCommand  
Column Address Strobe Command  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. C  
08/07/09  
IS42S16400E  
GENERAL DESCRIPTION  
Theꢀ 64Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ  
random-accessꢀ memoryꢀ designedꢀ toꢀ operateꢀ inꢀ 3.3Vꢀ  
memoryꢀsystemsꢀcontainingꢀ67,108,864ꢀbits.ꢀꢀInternallyꢀ  
configuredꢀasꢀaꢀquad-bankꢀDRAMꢀwithꢀaꢀsynchronousꢀ  
interface.ꢀꢀEachꢀ16,777,216-bitꢀbankꢀisꢀorganizedꢀasꢀ4,096ꢀ  
rowsꢀbyꢀ256ꢀcolumnsꢀbyꢀ16ꢀbits.  
otherthreebankswillhidetheprechargecyclesandprovide  
seamless,ꢀhigh-speed,ꢀrandom-accessꢀoperation.  
SDRAM readandwriteaccessesareburstorientedstarting  
at a selected location and continuing for a programmed  
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ ꢀTheꢀ  
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ  
followedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ  
command in conjunction with address bits registered are  
usedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0,ꢀ  
BA1ꢀselectꢀtheꢀbank;ꢀA0-A11ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ  
orꢀWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ  
registered are used to select the starting column location  
for the burst access.  
Theꢀ64MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀ  
andꢀaꢀpower-saving,ꢀpower-downꢀmode.ꢀAllꢀsignalsꢀareꢀ  
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀ  
AllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀcompatible.  
Theꢀ64MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ  
dataꢀatꢀaꢀhighꢀdataꢀrateꢀwithꢀautomaticꢀcolumn-addressꢀ  
generation, theabilitytointerleavebetweeninternalbanks  
to hide precharge time and the capability to randomly  
change column addresses on each clock cycle during  
burst access.  
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ  
1,ꢀ2,ꢀ4ꢀandꢀ8ꢀlocations,ꢀorꢀfullꢀpage,ꢀwithꢀaꢀburstꢀterminateꢀ  
option.  
Aꢀself-timedꢀrowꢀprechargeꢀinitiatedꢀatꢀtheꢀendꢀofꢀtheꢀburstꢀ  
sequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀ  
enabled. Precharge one bank while accessing one of the  
FUNCTIONAL BLOCK DIAGRAM  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQM  
DATA IN  
BUFFER  
COMMAND  
DECODER  
&
CLOCK  
GENERATOR  
16  
16  
REFRESH  
CONTROLLER  
MODE  
REGISTER  
DQ 0-15  
A10  
12  
V
DD/VDDQ  
SELF  
DATA OUT  
BUFFER  
REFRESH  
GND/GNDQ  
A11  
CONTROLLER  
16  
16  
A9  
A8  
A7  
A6  
REFRESH  
COUNTER  
A5  
A4  
4096  
A3  
A2  
A1  
A0  
BA0  
BA1  
4096  
MEMORY CELL  
ARRAY  
4096  
4096  
12  
BANK 0  
ROW  
ADDRESS  
LATCH  
ROW  
ADDRESS  
BUFFER  
12  
12  
SENSE AMP I/O GATE  
256K  
(x 16)  
COLUMN  
ADDRESS LATCH  
BANK CONTROL LOGIC  
8
BURST COUNTER  
COLUMN DECODER  
COLUMN  
ADDRESS BUFFER  
8
2
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
PIN FUNCTIONS  
Symbol  
TSOP Pin No.  
23ꢀtoꢀ26ꢀ  
29ꢀtoꢀ34  
22,ꢀ35  
Type  
Function (In Detail)  
ꢀ
ꢀ
A0-A11ꢀ  
InputꢀPin  
ꢀ
AddressꢀInputs:ꢀA0-A11ꢀareꢀsampledꢀduringꢀtheꢀACTIVE  
commandꢀ(row-addressꢀA0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(A0-A7  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
withꢀA10ꢀdefiningꢀautoꢀprecharge)ꢀtoꢀselectꢀoneꢀlocationꢀoutꢀofꢀtheꢀmemoryꢀarray  
inꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀcommandꢀtoꢀdeter-  
mineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀselectedꢀby  
BA0,ꢀBA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀLOADꢀ  
MODEꢀREGISTERꢀcommand.  
BA0,ꢀBA1  
CAS  
20,ꢀ21ꢀ  
17ꢀ  
InputꢀPin  
InputꢀPin  
InputꢀPin  
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ  
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.  
CAS, in conjunction with the RAS and WE, forms the device command. See the  
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ  
ꢀ
ꢀ
CKEꢀ  
37ꢀ  
ꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ  
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ  
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ  
refresh mode. CKEꢀisꢀan asynchronous input.  
CLKꢀ  
38ꢀ  
19ꢀ  
InputꢀPin  
ꢀ
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ  
areꢀacquiredꢀinꢀsynchronizationꢀwithꢀtheꢀrisingꢀedgeꢀofꢀthisꢀpin.  
CS  
InputꢀPin  
TheꢀCS input determines whether command input is enabled within the device.  
Command input is enabled when CSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ  
device remains in the previous state when CSꢀisꢀHIGH.  
ꢀ
ꢀ
DQ0ꢀtoꢀ  
DQ15ꢀ  
2,ꢀ4,ꢀ5,ꢀ7,ꢀ8,ꢀ10,ꢀ  
11,13,ꢀ42,ꢀ44,ꢀ45,  
47,ꢀ48,ꢀ50,ꢀ51,ꢀ53  
15,ꢀ39ꢀ  
DQꢀPin  
ꢀ
ꢀ
DQ0ꢀtoꢀDQ15ꢀareꢀI/Oꢀpins.ꢀI/Oꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀinꢀbyteꢀunits  
usingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.  
ꢀ
ꢀ
ꢀ
LDQM,ꢀ  
UDQMꢀ  
InputꢀPin  
ꢀ
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀI/Oꢀbuffers.ꢀInꢀread  
ꢀ
ꢀ
mode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀ  
theꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀ  
goꢀtoꢀtheꢀHIGHꢀimpedanceꢀstateꢀwhenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcor-  
responds to OEꢀinꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀ  
theꢀinputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀen-  
abled,ꢀandꢀdataꢀcanꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀHIGH,ꢀinputꢀ  
data is masked and cannot be written to the device.  
RAS  
WE  
18ꢀ  
16ꢀ  
InputꢀPin  
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-  
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.  
ꢀInputꢀPin  
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-  
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ  
ꢀ
ꢀ
VD D q  
VD D  
3,ꢀ9,ꢀ43,ꢀ49ꢀ  
1,ꢀ14,ꢀ27ꢀ  
PowerꢀSupplyꢀPin  
PowerꢀSupplyꢀPin  
ꢀ
ꢀ
VD D q is the output buffer power supply.  
VD D is the device internal power supply.  
GNDq  
GND  
6,ꢀ12,ꢀ46,ꢀ52ꢀ  
28,ꢀ41,ꢀ54ꢀ  
PowerꢀSupplyꢀPin GNDq is the output buffer ground.  
PowerꢀSupplyꢀPin GND is the device internal ground.  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
3
Rev. C  
08/07/09  
IS42S16400E  
FUNCTION (InꢀDetail)  
READ  
A0-A11ꢀareꢀaddressꢀinputsꢀsampledꢀduringꢀtheꢀACTIVEꢀ  
(row-addressꢀA0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(A0-A7ꢀ  
withꢀA10ꢀdefiningꢀautoꢀPRECHARGE). A10 is sampled during  
aꢀPRECHARGEꢀcommandꢀtoꢀdetermineꢀifꢀallꢀbanksꢀareꢀtoꢀ  
beꢀPRECHARGEDꢀ(A10ꢀHIGH)ꢀorꢀbankꢀselectedꢀbyꢀBA0,ꢀ  
BA1ꢀ(LOW).ꢀꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀ  
duringꢀaꢀLOADꢀMODEꢀREGISTERꢀcommand.  
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ  
and starts a burst read access to an active row. Inputs  
A0-A7ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀꢀWhenꢀA10ꢀisꢀ  
HIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀPRECHARGEꢀ  
command. When the auto precharge is selected, the row  
beingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀtheꢀREADꢀ  
burst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccessesꢀ  
whenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀselected.ꢀꢀDQ’sꢀreadꢀ  
dataꢀisꢀsubjectꢀtoꢀtheꢀlogicꢀlevelꢀonꢀtheꢀDQMꢀinputsꢀtwoꢀ  
clocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀsignalꢀwasꢀregisteredꢀ  
HIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀbeꢀHigh-Zꢀtwoꢀclocksꢀ  
later.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀwhenꢀtheꢀDQMꢀsignalꢀ  
wasꢀregisteredꢀLOW.  
BankꢀSelectꢀAddressꢀ(BA0ꢀandꢀBA1) defines which bank  
theꢀACTIVE,ꢀREAD,ꢀWRITEꢀorꢀPRECHARGEꢀcommandꢀ  
is being applied.  
CAS,inconjunctionwiththeRASandWE,formsthedevice  
command.ꢀSeeꢀtheꢀ“CommandꢀTruthꢀTable”ꢀforꢀdetailsꢀonꢀ  
device commands.  
WRITE  
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀen-  
abled.ꢀTheꢀnextꢀrisingꢀedgeꢀofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀ  
whenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀisꢀ  
LOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀCLOCKꢀ  
SUSPENDꢀmode,ꢀorꢀSELF-REFRESHꢀmode.ꢀCKEꢀisꢀanꢀ  
asynchronous input.  
A burst write access to an active row is initiated with the  
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀ  
and the starting column location is provided by inputs  
A0-A7.ꢀWhetherꢀorꢀnotꢀAUTO-PRECHARGEꢀisꢀusedꢀisꢀ  
determined by A10.  
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀ  
CKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀareꢀacquiredꢀinꢀsynchroniza-  
tion with the rising edge of this pin.  
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ  
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ  
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ  
openꢀforꢀsubsequentꢀaccesses.  
TheꢀCS input determines whether command input is en-  
abled within the device. Command input is enabled when  
CS isꢀLOW,ꢀandꢀdisabledꢀwithꢀCS isꢀHIGH.ꢀTheꢀdeviceꢀ  
remains in the previous state when CS isꢀHIGH.ꢀDQ0ꢀtoꢀ  
DQ15ꢀareꢀDQꢀpins.ꢀDQꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀ  
inꢀbyteꢀunitsꢀusingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.  
A memory array is written with corresponding input data  
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ  
time.ꢀꢀDataꢀwillꢀbeꢀwrittenꢀtoꢀmemoryꢀwhenꢀDQMꢀsignalꢀisꢀ  
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ  
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ  
byte/column location.  
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀ  
theꢀDQꢀbuffers.ꢀInꢀreadꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀ  
theꢀ outputꢀ buffer.ꢀWhenꢀ LDQMꢀ orꢀ UDQMꢀ isꢀ LOW,ꢀ theꢀ  
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀ  
disabled.ꢀTheꢀoutputsꢀgoꢀtoꢀtheꢀHIGHꢀImpedanceꢀStateꢀ  
whenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀ  
to OE inꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀ  
UDQMꢀcontrolꢀtheꢀinputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀ  
LOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀdataꢀ  
canꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀ  
HIGH,ꢀinputꢀdataꢀisꢀmaskedꢀandꢀcannotꢀbeꢀwrittenꢀtoꢀtheꢀ  
device.  
PRECHARGE  
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀ  
open row in a particular bank or the open row in all banks.  
BA0,ꢀBA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀ  
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinedꢀ  
whetherꢀoneꢀorꢀallꢀbanksꢀareꢀprecharged.ꢀAfterꢀexecut-  
ingꢀ thisꢀ command,ꢀ theꢀ nextꢀ commandꢀ forꢀ theꢀ selectedꢀ  
banks(s)ꢀisꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtRP, which  
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ  
has been precharged, it is in the idle state and must be  
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ  
issued to that bank.  
RAS, in conjunction with CAS and WE , forms the device  
command.ꢀSeeꢀtheꢀ“CommandꢀTruthꢀTable”ꢀitemꢀforꢀdetailsꢀ  
on device commands.  
AUTO PRECHARGE  
WE , in conjunction with RAS and CAS , forms the device  
command.ꢀSeeꢀtheꢀ“CommandꢀTruthꢀTable”ꢀitemꢀforꢀdetailsꢀ  
on device commands.  
TheꢀAUTOꢀPRECHARGEꢀfunctionꢀensuresꢀthatꢀtheꢀpre-  
charge is initiated at the earliest valid stage within a burst.  
Thisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀwithoutꢀ  
requiringꢀanꢀexplicitꢀcommand.ꢀꢀA10ꢀtoꢀenablesꢀtheꢀAUTOꢀ  
PRECHARGEꢀfunctionꢀinꢀconjunctionꢀwithꢀaꢀspecificꢀREADꢀ  
orꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀindividualꢀREADꢀorꢀWRITEꢀ  
command, auto precharge is either enabled or disabled.  
VDDq is the output buffer power supply.  
VDD is the device internal power supply.  
GNDq is the output buffer ground.  
GNDꢀisꢀtheꢀdeviceꢀinternalꢀground.  
4ꢀ  
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IS42S16400E  
BURST TERMINATE  
AUTOꢀPRECHARGEꢀdoesꢀnotꢀapplyꢀexceptꢀinꢀfull-pageꢀ  
burstꢀ mode.ꢀ Uponꢀ completionꢀ ofꢀ theꢀ READꢀ orꢀWRITEꢀ  
burst, a precharge of the bank/row that is addressed is  
automatically performed.  
TheꢀBURSTꢀTERMINATEꢀcommandꢀforciblyꢀterminatesꢀ  
the burst read and write operations by truncating either  
fixed-lengthꢀ orꢀ full-pageꢀ burstsꢀ andꢀ theꢀ mostꢀ recentlyꢀ  
registeredꢀREADꢀorꢀWRITEꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀ  
TERMINATE.  
AUTO REFRESH COMMAND  
COMMAND INHIBIT  
COMMANDꢀINHIBITꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀ  
executed.ꢀOperationsꢀinꢀprogressꢀareꢀnotꢀaffected,ꢀapartꢀ  
fromꢀwhetherꢀtheꢀCLKꢀsignalꢀisꢀenabled  
ThisꢀcommandꢀexecutesꢀtheꢀAUTOꢀREFRESHꢀoperation.ꢀ  
Theꢀrowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ  
generatedꢀduringꢀthisꢀoperation.ꢀ Theꢀstipulatedꢀperiodꢀ(tr c )ꢀisꢀ  
requiredꢀforꢀaꢀsingleꢀrefreshꢀoperation,ꢀandꢀnoꢀotherꢀcom-  
mandsꢀcanꢀbeꢀexecutedꢀduringꢀthisꢀperiod.ꢀ Thisꢀcommandꢀisꢀ  
executedꢀatꢀleastꢀ4096ꢀtimesꢀeveryꢀ64ms.ꢀDuringꢀanꢀAUTOꢀ  
REFRESHꢀcommand,ꢀaddressꢀbitsꢀareꢀ“Don’tꢀCare”.ꢀꢀThisꢀ  
commandꢀcorrespondsꢀtoꢀCBRꢀAuto-refresh.  
NO OPERATION  
When CSꢀisꢀlow,ꢀtheꢀNOPꢀcommandꢀpreventsꢀunwantedꢀ  
commands from being registered during idle or wait  
states.  
SELF REFRESH  
LOAD MODE REGISTER  
DuringꢀtheꢀSELFꢀREFRESHꢀoperation,ꢀtheꢀrowꢀaddressꢀtoꢀ  
be refreshed, the bank, and the refresh interval are gen-  
eratedꢀautomaticallyꢀinternally.ꢀꢀSELFꢀREFRESHꢀcanꢀbeꢀ  
usedꢀtoꢀretainꢀdataꢀinꢀtheꢀSDRAMꢀwithoutꢀexternalꢀclocking,ꢀ  
evenꢀifꢀtheꢀrestꢀofꢀtheꢀsystemꢀisꢀpoweredꢀdown.ꢀTheꢀSELFꢀ  
REFRESHꢀoperationꢀisꢀstartedꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀ  
fromꢀHIGHꢀtoꢀLOW.ꢀDuringꢀtheꢀSELFꢀREFRESHꢀoperationꢀ  
allꢀotherꢀinputsꢀtoꢀtheꢀSDRAMꢀbecomeꢀ“Don’tꢀCare”.ꢀTheꢀ  
device must remain in self refresh mode for a minimum  
periodꢀequalꢀtoꢀtr a s or may remain in self refresh mode  
forꢀanꢀindefiniteꢀperiodꢀbeyondꢀthat.ꢀTheꢀSELF-REFRESHꢀ  
operationꢀcontinuesꢀasꢀlongꢀasꢀtheꢀCKEꢀpinꢀremainsꢀLOWꢀ  
andꢀthereꢀisꢀnoꢀneedꢀforꢀexternalꢀcontrolꢀofꢀanyꢀotherꢀpins.ꢀ  
Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀdeviceꢀ  
internal recovery period (tr c )ꢀ hasꢀ elapsed.ꢀ Onceꢀ CKEꢀ  
goesꢀHIGH,ꢀtheꢀNOPꢀcommandꢀmustꢀbeꢀissuedꢀ(minimum  
ofꢀ twoꢀclocks) to provide time for the completion of any  
internalꢀrefreshꢀinꢀprogress.ꢀAfterꢀtheꢀself-refresh,ꢀsinceꢀitꢀ  
is impossible to determine the address of the last row to  
beꢀrefreshed,ꢀanꢀAUTO-REFRESHꢀshouldꢀimmediatelyꢀbeꢀ  
performed for all addresses.  
DuringꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀtheꢀmodeꢀ  
registerꢀisꢀloadedꢀfromꢀA0-A11.ꢀꢀThisꢀcommandꢀcanꢀonlyꢀ  
be issued when all banks are idle.  
ACTIVE COMMAND  
Whenꢀ theꢀ ACTIVEꢀ COMMANDꢀ isꢀ activated,ꢀ BA0,ꢀ BA1ꢀ  
inputs selects a bank to be accessed, and the address  
inputsꢀonꢀA0-A11ꢀselectsꢀtheꢀrow.ꢀꢀꢀUntilꢀaꢀPRECHARGEꢀ  
command is issued to the bank, the row remains open  
for accesses.  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
5
Rev. C  
08/07/09  
                                           
                                                
                                                      
                                                            
                                                                             
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
Active  
High-Z  
                                           
                                                
                                                      
                                                            
Hꢀ  
                                                                             
—ꢀ  
IS42S16400E  
TRUTH TABLE – COMMANDS AND DQM OPERATION(1)  
FUNCTION  
CS  
Hꢀ  
Lꢀ  
RAS CAS  
WE DQM  
ADDR  
Xꢀ  
DQs  
COMMANDꢀINHIBITꢀ(NOP)ꢀ  
Xꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Xꢀ  
X
X
NOꢀOPERATIONꢀ(NOP)ꢀ  
Xꢀ  
ACTIVEꢀ(Selectꢀbankꢀandꢀactivateꢀrow)(3)ꢀ  
READꢀ(Selectꢀbank/column,ꢀstartꢀREADꢀburst)(4)  
WRITEꢀ(Selectꢀbank/column,ꢀstartꢀWRITEꢀburst)(4)ꢀ Lꢀ  
BURSTꢀTERMINATEꢀ Lꢀ  
PRECHARGEꢀ(Deactivateꢀrowꢀinꢀbankꢀorꢀbanks)(5)ꢀ Lꢀ  
Lꢀ  
Xꢀ  
Bank/Rowꢀ  
Bank/Colꢀ  
Bank/Colꢀ  
Xꢀ  
X
ꢀ
Lꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
L/H(8)ꢀ  
L/H(8)ꢀ  
Xꢀ  
X
Lꢀ  
Valid  
Active  
X
Hꢀ  
Hꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Codeꢀ  
Xꢀ  
AUTOꢀREFRESHꢀorꢀSELFꢀREFRESH(6,7)  
ꢀ
Lꢀ  
Lꢀ  
Hꢀ  
Xꢀ  
X
(Enterꢀselfꢀrefreshꢀmode)  
LOADꢀMODEꢀREGISTER(2)ꢀ  
WriteꢀEnable/OutputꢀEnable(8)ꢀ  
WriteꢀInhibit/OutputꢀHigh-Z(8)ꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Lꢀ  
Op-Codeꢀ  
—ꢀ  
X
NOTES:  
1.ꢀ CKEꢀisꢀHIGHꢀforꢀallꢀcommandsꢀexceptꢀSELFꢀREFRESH.  
2.ꢀ A0-A11ꢀdefineꢀtheꢀop-codeꢀwrittenꢀtoꢀtheꢀmodeꢀregister.  
3.ꢀ A0-A11ꢀprovideꢀrowꢀaddress,ꢀandꢀBA0,ꢀBA1ꢀdetermineꢀwhichꢀbankꢀisꢀmadeꢀactive.  
4.ꢀ A0-A7ꢀ(x16)ꢀprovideꢀcolumnꢀaddress;ꢀA10ꢀHIGHꢀenablesꢀtheꢀautoꢀprechargeꢀfeatureꢀ(nonpersistent),ꢀwhileꢀA10ꢀLOWꢀdisablesꢀ  
autoꢀprecharge;ꢀBA0,ꢀBA1ꢀdetermineꢀwhichꢀbankꢀisꢀbeingꢀreadꢀfromꢀorꢀwrittenꢀto.  
5.ꢀ A10ꢀLOW:ꢀBA0,ꢀBA1ꢀdetermineꢀtheꢀbankꢀbeingꢀprecharged.ꢀA10ꢀHIGH:ꢀAllꢀbanksꢀprechargedꢀandꢀBA0,ꢀBA1ꢀareꢀ“Don’tꢀCare.”  
6.ꢀ AUTOꢀREFRESHꢀifꢀCKEꢀisꢀHIGH,ꢀSELFꢀREFRESHꢀifꢀCKEꢀisꢀLOW.  
7.ꢀ Internalꢀrefreshꢀcounterꢀcontrolsꢀrowꢀaddressing;ꢀallꢀinputsꢀandꢀI/Osꢀareꢀ“Don’tꢀCare”ꢀexceptꢀforꢀCKE.  
8.ꢀ ActivatesꢀorꢀdeactivatesꢀtheꢀDQsꢀduringꢀWRITEsꢀ(zero-clockꢀdelay)ꢀandꢀREADsꢀ(two-clockꢀdelay).  
6
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
TRUTH TABLE – CKE (1-4)  
CURRENT STATE  
COMMANDn  
ACTIONn  
CKEn-1  
CKEn  
Power-Downꢀ  
Xꢀ  
MaintainꢀPower-Downꢀ  
MaintainꢀSelfꢀRefreshꢀ  
MaintainꢀClockꢀSuspendꢀ  
ExitꢀPower-Downꢀ  
ExitꢀSelfꢀRefreshꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Hꢀ  
Hꢀ  
Hꢀ  
L
L
SelfꢀRefreshꢀ  
Xꢀ  
ClockꢀSuspendꢀ  
Power-Down(5)ꢀ  
SelfꢀRefresh(6)ꢀ  
Clock Suspend(7)ꢀ  
AllꢀBanksꢀIdleꢀ  
AllꢀBanksꢀIdleꢀ  
ReadingꢀorꢀWritingꢀ  
Xꢀ  
L
COMMANDꢀINHIBITꢀorꢀNOPꢀ  
COMMANDꢀINHIBITꢀorꢀNOPꢀ  
Xꢀ  
H
H
H
L
ExitꢀClockꢀSuspendꢀ  
Power-DownꢀEntryꢀ  
SelfꢀRefreshꢀEntryꢀ  
ClockꢀSuspendꢀEntryꢀ  
COMMANDꢀINHIBITꢀorꢀNOPꢀ  
AUTOꢀREFRESHꢀ  
VALIDꢀ  
L
L
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n  
ꢀ
Hꢀ  
H
NOTES:  
1.ꢀ CKEnꢀisꢀtheꢀlogicꢀstateꢀofꢀCKEꢀatꢀclockꢀedgeꢀn;ꢀCKEn-1 wasꢀtheꢀstateꢀofꢀCKEꢀatꢀtheꢀpreviousꢀclockꢀedge.ꢀ  
2.ꢀ CurrentꢀstateꢀisꢀtheꢀstateꢀofꢀtheꢀSDRAMꢀimmediatelyꢀpriorꢀtoꢀclockꢀedgeꢀn.  
3.ꢀ COMMANDnꢀisꢀtheꢀcommandꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀACTONnꢀisꢀaꢀresultꢀofꢀCOMMANDn.  
4.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.  
5.ꢀ Exitingꢀpower-downꢀatꢀclockꢀedgeꢀn will put the device in the all banks idle state in time for clock edge n+1 (provided that tc k s is  
met)  
.
6.ꢀ Exitingꢀselfꢀrefreshꢀatꢀclockꢀedgeꢀn will put the device in all banks idle state once tx s r ꢀisꢀmet.ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀ  
commands should be issued on clock edges occurring during the tx s r ꢀperiod.ꢀAꢀminimumꢀofꢀtwoꢀNOPꢀcommandsꢀmustꢀbeꢀsentꢀ  
during tx s r period.  
7.ꢀ Afterꢀexitingꢀclockꢀsuspendꢀatꢀclockꢀedgeꢀn,ꢀtheꢀdeviceꢀwillꢀresumeꢀoperationꢀandꢀrecognizeꢀtheꢀnextꢀcommandꢀatꢀclockꢀedgeꢀ  
n+1.  
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)  
CURRENTꢀSTATE  
ꢀ
COMMANDꢀ(ACTION)  
CS RAS CAS WE  
Anyꢀ  
COMMANDꢀINHIBITꢀ(NOP/Continueꢀpreviousꢀoperation)  
ꢀ
Hꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
X
H
H
H
L
ꢀ
NOꢀOPERATIONꢀ(NOP/Continueꢀpreviousꢀoperation)  
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ  
ꢀAUTOꢀREFRESH(7)ꢀ  
ꢀ
Idleꢀ  
ꢀ
Lꢀ  
ꢀ
LOADꢀMODEꢀREGISTER(7)ꢀ  
PRECHARGE(11)ꢀ  
Lꢀ  
Lꢀ  
ꢀ
Lꢀ  
Hꢀ  
Lꢀ  
L
RowꢀActiveꢀ  
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(10)ꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(10)ꢀ  
PRECHARGEꢀ(Deactivateꢀrowꢀinꢀbankꢀorꢀbanks)(8)ꢀ  
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(10)ꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(10)ꢀ  
PRECHARGEꢀ(TruncateꢀREADꢀburst,ꢀstartꢀPRECHARGE)(8)ꢀ  
BURSTꢀTERMINATE(9)ꢀ  
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(10)ꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(10)ꢀ  
PRECHARGEꢀ(TruncateꢀWRITEꢀburst,ꢀstartꢀPRECHARGE)(8)ꢀ  
BURSTꢀTERMINATE(9)ꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
H
L
Lꢀ  
ꢀ
Hꢀ  
Lꢀ  
L
Readꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
H
L
(Autoꢀ  
Lꢀ  
Prechargeꢀ  
Disabled)ꢀ  
Writeꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
L
Hꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
L
H
L
(Autoꢀ  
Lꢀ  
Prechargeꢀ  
Hꢀ  
Hꢀ  
L
Disabled)ꢀ  
Hꢀ  
L
NOTE:  
ꢀ 1.ꢀThisꢀtableꢀappliesꢀwhenꢀCKEꢀn-1ꢀwasꢀHIGHꢀandꢀCKEꢀnꢀisꢀHIGHꢀ(seeꢀTruthꢀTableꢀ-ꢀCKE)ꢀandꢀafterꢀtx s r has been met (if the  
previous state was SELFꢀREFRESH).  
ꢀ 2.ꢀThisꢀtableꢀisꢀbank-specific,ꢀexceptꢀwhereꢀnoted;ꢀi.e.,ꢀtheꢀcurrentꢀstateꢀisꢀforꢀaꢀspecificꢀbankꢀandꢀtheꢀcommandsꢀshownꢀareꢀthoseꢀ  
allowedꢀtoꢀbeꢀissuedꢀtoꢀthatꢀbankꢀwhenꢀinꢀthatꢀstate.ꢀExceptionsꢀareꢀcoveredꢀinꢀtheꢀnotesꢀbelow.  
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7
Rev. C  
08/07/09  
IS42S16400E  
ꢀ 3.ꢀCurrentꢀstateꢀdefinitions:  
ꢀ
ꢀ
Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtr p has been met.  
RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtr c D has been met. No data bursts/accesses and no register  
accesses are in progress.  
ꢀ
ꢀ
Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-  
nated.  
Write:ꢀAꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-  
nated.  
ꢀ 4.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀaꢀcommandꢀissuedꢀtoꢀtheꢀsameꢀbank.ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommands,ꢀ  
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-  
mandsꢀtoꢀtheꢀotherꢀbankꢀareꢀdeterminedꢀbyꢀitsꢀcurrentꢀstateꢀandꢀCURRENTꢀSTATEꢀBANKꢀnꢀtruthꢀtables.  
ꢀ
ꢀ
ꢀ
Precharging:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀcommandꢀandꢀendsꢀwhenꢀtr p ꢀisꢀmet.ꢀOnceꢀtr p is met, the bank  
will be in the idle state.  
RowꢀActivating:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀACTIVEꢀcommandꢀandꢀendsꢀwhenꢀtr c D ꢀisꢀmet.ꢀOnceꢀtr c D is met, the bank will  
be in the row active state.  
Readꢀw/Auto  
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀREADꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtr p has been  
met.ꢀOnceꢀtr p is met, the bank will be in the idle state.  
Write w/Auto  
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtr p has been  
met.ꢀOnceꢀtr p is met, the bank will be in the idle state.  
ꢀ 5.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀanyꢀexecutableꢀcommand;ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandsꢀmustꢀbeꢀ  
applied on each positive clock edge during these states.  
ꢀ
Refreshing:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀAUTOꢀREFRESHꢀcommandꢀandꢀendsꢀwhenꢀtr c ꢀisꢀmet.ꢀOnceꢀtr c is met, the  
SDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.  
AccessingꢀMode  
ꢀ
Register:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀLOADꢀMODEꢀREGISTERꢀcommandꢀandꢀendsꢀwhenꢀtm r D ꢀhasꢀbeenꢀmet.ꢀOnceꢀ  
tm r D ꢀisꢀmet,ꢀtheꢀSDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.  
PrechargingꢀAll:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀALLꢀcommandꢀandꢀendsꢀwhenꢀtr p ꢀisꢀmet.ꢀOnceꢀtr p is met, all  
banks will be in the idle state.  
ꢀ 6.ꢀAllꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.  
ꢀ 7.ꢀNotꢀbank-specific;ꢀrequiresꢀthatꢀallꢀbanksꢀareꢀidle.  
ꢀ 8.ꢀMayꢀorꢀmayꢀnotꢀbeꢀbank-specific;ꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀallꢀmustꢀbeꢀinꢀaꢀvalidꢀstateꢀforꢀprecharging.  
ꢀ 9.ꢀNotꢀbank-specific;ꢀBURSTꢀTERMINATEꢀaffectsꢀtheꢀmostꢀrecentꢀREADꢀorꢀWRITEꢀburst,ꢀregardlessꢀofꢀbank.  
ꢀ10.ꢀREADsꢀorꢀWRITEsꢀlistedꢀinꢀtheꢀCommandꢀ(Action)ꢀcolumnꢀincludeꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀ  
READsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀdisabled.  
ꢀ11.ꢀDoesꢀnotꢀaffectꢀtheꢀstateꢀofꢀtheꢀbankꢀandꢀactsꢀasꢀaꢀNOPꢀtoꢀthatꢀbank.  
8
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Rev. C  
08/07/09  
IS42S16400E  
(1-6)  
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m  
CURRENTꢀSTATE  
ꢀ
COMMANDꢀ(ACTION)  
CS RAS CAS WE  
Anyꢀ  
COMMANDꢀINHIBITꢀ(NOP/Continueꢀpreviousꢀoperation)ꢀ  
NOꢀOPERATIONꢀ(NOP/Continueꢀpreviousꢀoperation)ꢀ  
AnyꢀCommandꢀOtherwiseꢀAllowedꢀtoꢀBankꢀm  
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ  
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7)ꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7)ꢀ  
PRECHARGEꢀ  
Hꢀ  
Lꢀ  
Xꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Lꢀ  
Xꢀ  
Hꢀ  
Xꢀ  
Hꢀ  
Lꢀ  
X
H
X
H
H
L
ꢀ
Idleꢀ  
Rowꢀ  
Activating,ꢀ  
Active,ꢀorꢀ  
Prechargingꢀ  
Readꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
Lꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ  
Lꢀ  
H
H
L
(Autoꢀ  
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(7,10)  
ꢀ
Hꢀ  
Hꢀ  
Lꢀ  
Prechargeꢀ  
Disabled)ꢀ  
Writeꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7,11)  
PRECHARGE(9)ꢀ  
ꢀ
Lꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ  
Lꢀ  
H
H
L
(Autoꢀ  
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7,12)  
ꢀ
Hꢀ  
Hꢀ  
Lꢀ  
Prechargeꢀ  
Disabled)ꢀ  
Readꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(7,13)  
PRECHARGE(9)ꢀ  
ꢀ
Lꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ  
Lꢀ  
H
H
L
(WithꢀAutoꢀ  
Precharge)ꢀ  
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(7,8,14)  
ꢀ
Hꢀ  
Hꢀ  
Lꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7,8,15)  
PRECHARGE(9)ꢀ  
ꢀ
Lꢀ  
Hꢀ  
Hꢀ  
Lꢀ  
L
Writeꢀ  
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ  
Lꢀ  
H
H
L
(WithꢀAutoꢀ  
Precharge)ꢀ  
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7,8,16)  
ꢀ
Hꢀ  
Hꢀ  
Lꢀ  
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(7,8,17)  
PRECHARGE(9)ꢀ  
ꢀ
Lꢀ  
Hꢀ  
L
NOTE:ꢀ  
ꢀ 1.ꢀThisꢀtableꢀappliesꢀwhenꢀCKEꢀn-1ꢀwasꢀHIGHꢀandꢀCKEꢀnꢀisꢀHIGHꢀ(TruthꢀTableꢀ-ꢀCKE)ꢀandꢀafterꢀtx s r has been met (if the previ-  
ousꢀstateꢀwasꢀselfꢀrefresh).  
ꢀ 2.ꢀThisꢀtableꢀdescribesꢀalternateꢀbankꢀoperation,ꢀexceptꢀwhereꢀnoted;ꢀi.e.,ꢀtheꢀcurrentꢀstateꢀisꢀforꢀbankꢀn and the commands  
shown are those allowed to be issued to bank m (assuming that bank m isꢀinꢀsuchꢀaꢀstateꢀthatꢀtheꢀgivenꢀcommandꢀisꢀallowable).ꢀExcep-  
tions are covered in the notes below.  
ꢀ 3.ꢀCurrentꢀstateꢀdefinitions:  
ꢀ
ꢀ
Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtr p has been met.  
RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtr c D has been met. No data bursts/accesses and no register  
accesses are in progress.  
ꢀ
ꢀ
ꢀ
Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-  
nated.  
Write:ꢀAꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-  
nated.  
Readꢀw/Auto  
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀREADꢀcommandꢀwithꢀautoꢀprechargeꢀenabled,ꢀandꢀendsꢀwhenꢀtr p has been  
met.ꢀOnceꢀtr p is met, the bank will be in the idle state.  
Write w/Auto  
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀautoꢀprechargeꢀenabled,ꢀandꢀendsꢀwhenꢀtr p has been  
met.ꢀOnceꢀtr p is met, the bank will be in the idle state.  
ꢀ 4.ꢀAUTOꢀREFRESH,ꢀSELFꢀREFRESHꢀandꢀLOADꢀMODEꢀREGISTERꢀcommandsꢀmayꢀonlyꢀbeꢀissuedꢀwhenꢀallꢀbanksꢀareꢀidle.  
ꢀ 5.ꢀAꢀBURSTꢀTERMINATEꢀcommandꢀcannotꢀbeꢀissuedꢀtoꢀanotherꢀbank;ꢀitꢀappliesꢀtoꢀtheꢀbankꢀrepresentedꢀbyꢀtheꢀcurrentꢀstateꢀ  
only.  
ꢀ 6.ꢀAllꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.  
ꢀ 7.ꢀREADsꢀorꢀWRITEsꢀtoꢀbankꢀmꢀlistedꢀinꢀtheꢀCommandꢀ(Action)ꢀcolumnꢀincludeꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀenabledꢀ  
andꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀdisabled.  
ꢀ 8.ꢀCONCURRENTꢀAUTOꢀPRECHARGE:ꢀBankꢀnꢀwillꢀinitiateꢀtheꢀAUTOꢀPRECHARGEꢀcommandꢀwhenꢀitsꢀburstꢀhasꢀbeenꢀinter-  
ruptedꢀbyꢀbankꢀm’sꢀburst.  
Integrated Silicon Solution, Inc. — www.issi.com  
9
Rev. C  
08/07/09  
IS42S16400E  
ꢀ 9.ꢀBurstꢀinꢀbankꢀnꢀcontinuesꢀasꢀinitiated.  
ꢀ10.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ  
theꢀREADꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlaterꢀ(ConsecutiveꢀREADꢀBursts).  
ꢀ11.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-  
ruptꢀtheꢀREADꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(READꢀtoꢀWRITE).ꢀDQMꢀshouldꢀbeꢀusedꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀ  
prevent bus contention.  
ꢀ12.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ  
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀREAD),ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀlastꢀvalidꢀWRITEꢀ  
toꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.  
ꢀ13.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-  
ruptꢀtheꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀWRITE).ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀ  
clockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.  
ꢀ14.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀtheꢀ  
READꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ  
1).  
ꢀ15.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ  
theꢀREADꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀtwoꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀ  
TheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ2).  
ꢀ16.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ  
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered,ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀ  
after tWR is met, where tw r ꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregis-  
teredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀmꢀ(FigꢀCAPꢀ3).  
ꢀ17.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ  
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtw r ꢀisꢀmet,ꢀwhereꢀtꢀWRꢀbeginsꢀwhenꢀtheꢀ  
WRITEꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀtoꢀbankꢀmꢀ  
(FigꢀCAPꢀ4).  
10  
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Rev. C  
08/07/09  
IS42S16400E  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
VDD m a x ꢀ  
VDDq m a x  
ViNꢀ  
Parameters  
Rating  
–1.0ꢀtoꢀ+4.6ꢀ  
–1.0ꢀtoꢀ+4.6ꢀ  
–1.0ꢀtoꢀVD D q +ꢀ0.5ꢀ  
–1.0ꢀtoꢀVD D q +ꢀ0.5ꢀ  
1ꢀ  
Unit  
V
V
V
V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ  
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ  
InputꢀVoltageꢀ  
OutputꢀVoltageꢀ  
AllowableꢀPowerꢀDissipationꢀ  
outputꢀShortedꢀCurrentꢀ  
Vo u t ꢀ  
PD m a x  
Ic s  
W
mA  
50ꢀ  
ꢀ
ꢀ
To p r  
operatingꢀTemperatureꢀ  
Com.ꢀ  
Ind.ꢀ  
0ꢀtoꢀ+70ꢀ  
-40ꢀtoꢀ+85ꢀ  
–65ꢀtoꢀ+150ꢀ  
°Cꢀ  
°C  
°C  
Ts t g ꢀ  
StorageꢀTemperatureꢀ  
ꢀ
DC RECOMMENDED OPERATING CONDITIONS(2) (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+70°C)  
Symbol  
VDD, VDDqꢀ  
Vihꢀ  
Parameter  
Min.  
3.0ꢀ  
2.0ꢀ  
-0.3ꢀ  
Typ.  
3.3ꢀ  
—ꢀ  
Max.  
3.6ꢀ  
VD D +ꢀ0.3ꢀ  
+0.8ꢀ  
Unit  
V
V
ꢀ
ꢀ
ꢀ
SupplyꢀVoltageꢀ  
InputꢀHighꢀVoltage(3)ꢀ  
InputꢀLowꢀVoltage(4)ꢀ  
Vilꢀ  
—ꢀ  
V
CAPACITANCE CHARACTERISTICS(1,2) (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVD D ꢀ=ꢀVD D q ꢀ=ꢀ3.3ꢀ±ꢀ0.3V,ꢀfꢀ=ꢀ1ꢀMHz)  
Symbol  
CiNꢀ  
Parameter  
Typ.  
—ꢀ  
—ꢀ  
Max.  
3.8ꢀ  
3.5ꢀ  
6.5ꢀ  
Unit  
pF  
pF  
InputꢀCapacitance:ꢀAddressꢀandꢀControlꢀ  
InputꢀCapacitance:ꢀ(CLK)ꢀ  
DataꢀInput/OutputꢀCapacitance:ꢀI/O0-I/O15ꢀ  
Cc l k ꢀ  
CI/Oꢀ  
ꢀ
—ꢀ  
pF  
Notes:  
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ  
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational  
sectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀ  
reliability.  
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀGND.  
3.ꢀꢀVih(max)ꢀ=ꢀVD D q ꢀ+ꢀ2.0Vꢀwithꢀaꢀpulseꢀwidthꢀ<ꢀ3ns.  
4.ꢀꢀVil(min)ꢀ=ꢀGNDꢀ-ꢀ2.0Vꢀwithꢀaꢀpulseꢀwidthꢀ<ꢀ3ns.  
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11  
Rev. C  
08/07/09  
i
Self-RefreshꢀCurrentꢀ  
CKEꢀ≤ꢀ0.2Vꢀ  
ꢀ
ꢀ
—ꢀ  
                                                                                      
—ꢀ  
2ꢀ  
mA  
IS42S16400E  
DC ELECTRICAL CHARACTERISTICS (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)  
Symbol Parameter  
Test Condition  
Speed Min.  
Max.  
Unit  
i
ꢀꢀ  
ilꢀ  
InputꢀLeakageꢀCurrentꢀ  
ꢀ
0Vꢀ≤ꢀViN ≤ꢀVD D ,ꢀwithꢀpinsꢀotherꢀthanꢀ  
theꢀtestedꢀpinꢀatꢀ0V  
ꢀ
ꢀ
–5ꢀ  
5ꢀ  
µA  
i
o l  
ꢀ
OutputꢀLeakageꢀCurrentꢀ  
OutputꢀHighꢀVoltageꢀLevelꢀ  
OutputꢀLowꢀVoltageꢀLevelꢀ  
Outputꢀisꢀdisabled,ꢀ0Vꢀ≤ Vo u t ≤ꢀVD D  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–5ꢀ  
2.4ꢀ  
—ꢀ  
5ꢀ  
µAꢀ  
V
V
o h  
ꢀ
ꢀ
i
o u t ꢀ=ꢀ–2ꢀmAꢀ  
o u t ꢀ=ꢀ+2ꢀmAꢀ  
ꢀ
ꢀ
—ꢀ  
0.4ꢀ  
V
o l  
ꢀ
i
V
ic c 1  
OperatingꢀCurrent(1,2)  
ꢀ
OneꢀBankꢀOperation,ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCASꢀlatencyꢀ=ꢀ3ꢀꢀꢀCom.ꢀ  
-6ꢀ  
-7ꢀ  
-7ꢀ  
-6ꢀ  
—ꢀ  
—ꢀ  
—
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—
95ꢀ  
85ꢀ  
145ꢀ  
155  
2ꢀ  
4ꢀ  
2
3ꢀ  
mA  
mA  
mA  
ꢀꢀ  
ꢀ
BurstꢀLength=1ꢀ  
ꢀ
ꢀ
ꢀ
t
ꢀ
t
ꢀ
Com.ꢀ  
Ind.ꢀ  
Ind.ꢀ  
Com.ꢀ  
Ind.ꢀ  
Com.  
Ind.ꢀ  
t
I
r c ≥ tr c ꢀ(min.)ꢀ  
o u t ꢀ=ꢀ0mAꢀ  
i
ꢀꢀ  
I
c c 2p  
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ Vil  
ꢀ
(InꢀPower-DownꢀMode)  
ꢀ
(m a x )ꢀ  
c k ꢀ=ꢀ15nsꢀ  
c k = ∞  
mA  
mA  
mA  
mA  
ꢀ
c c 2p s  
ꢀꢀ  
ꢀ
—ꢀ  
—ꢀ  
i
I
c c 2N(3)ꢀ  
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≥ Vih  
(InꢀNonꢀPower-DownꢀMode)  
ꢀ
(
m iN )ꢀ  
t
t
ꢀ
c k ꢀ=ꢀ15nsꢀ  
c k = ∞ꢀ  
ꢀ
Com.ꢀ  
Ind.ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
20ꢀ  
15ꢀ  
15ꢀ  
mA  
mA  
mA  
c c 2N s  
ꢀꢀ  
ꢀ
i
c c 3p  
ꢀ
ActiveꢀStandbyꢀCurrentꢀ  
CKEꢀ≤ Vil  
(m a x )ꢀ  
t
c k = 10ns  
Com.  
Ind.  
Com.ꢀ  
Ind.ꢀ  
—
—
—ꢀ  
—ꢀ  
—
—
—ꢀ  
—ꢀ  
7
7
5ꢀ  
5ꢀ  
mA  
mA  
mA  
mA  
ic c 3p s  
ꢀ
(InꢀPower-DownꢀMode)ꢀ  
ꢀ
ꢀ
ꢀ
tc k = ∞ꢀ  
ꢀ
ꢀꢀ  
i
I
ꢀꢀ  
c c 3N(3)ꢀ  
c c 3N s  
ActiveꢀStandbyꢀCurrentꢀ  
(InꢀNonꢀPower-DownꢀMode)  
ꢀ
CKEꢀ≥ Vih  
(
m iN )ꢀ  
t
t
ꢀ
c k ꢀ=ꢀ15nsꢀ  
c k = ∞ꢀ  
ꢀ
Com.ꢀ  
Ind.ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
30ꢀ  
25ꢀ  
25ꢀ  
mA  
mA  
mA  
ꢀ
i
ꢀꢀ  
ꢀꢀ  
ꢀꢀ  
c c 4  
c c 5  
c c 6  
ꢀ
ꢀ
ꢀ
OperatingꢀCurrentꢀ  
t
c k = tc k  
(
m iN )ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCASꢀlatencyꢀ=ꢀ3ꢀ Com.ꢀ  
-6ꢀ  
-7ꢀ  
-7ꢀ  
-6ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
130ꢀ  
100ꢀ  
110ꢀ  
140  
mAꢀ  
mAꢀ  
mAꢀ  
(InꢀBurstꢀMode)(1)ꢀ  
I
o u t =ꢀ0mAꢀ  
ꢀ
ꢀ
ꢀ
Com.ꢀ  
Ind.ꢀ  
Ind.ꢀꢀ  
ꢀ
ꢀ
BLꢀ=ꢀ4;ꢀ4ꢀbanksꢀactivatedꢀ  
ꢀ
i
Auto-RefreshꢀCurrentꢀ  
t
t
ꢀ
ꢀ
r c = tr c  
c l k = tc l k  
(
m iN )ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCASꢀlatencyꢀ=ꢀ3ꢀ Com.ꢀ  
-6ꢀ  
-7ꢀ  
-7ꢀ  
-6ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
—ꢀ  
150ꢀ  
130ꢀ  
150ꢀ  
170  
mAꢀ  
mAꢀ  
mAꢀ  
(m iN )ꢀꢀ  
ꢀ
ꢀ
ꢀ
Com.ꢀ  
Ind.ꢀ  
Ind.ꢀ  
ꢀꢀ  
ꢀꢀ  
ꢀ
ꢀ
Notes:  
1.ꢀ Theseꢀareꢀtheꢀvaluesꢀatꢀtheꢀminimumꢀcycleꢀtime.ꢀSinceꢀtheꢀcurrentsꢀareꢀtransient,ꢀtheseꢀvaluesꢀdecreaseꢀasꢀtheꢀcycleꢀtimeꢀin-  
creases.ꢀAlsoꢀnoteꢀthatꢀaꢀbypassꢀcapacitorꢀofꢀꢀatꢀꢀleastꢀꢀ0.01ꢀµFꢀshouldꢀbeꢀinsertedꢀbetweenꢀVD D ꢀandꢀGNDꢀforꢀeachꢀmemoryꢀchipꢀ  
toꢀsuppressꢀpowerꢀsupplyꢀvoltageꢀnoiseꢀ(voltageꢀdrops)ꢀdueꢀtoꢀtheseꢀtransientꢀcurrents.  
2. Icc1 and Icc4ꢀdependꢀonꢀtheꢀoutputꢀload.ꢀTheꢀmaximumꢀvaluesꢀforꢀIcc1 and Icc4 are obtained with the output open state.  
3.ꢀꢀInputꢀsignalꢀchnageꢀonceꢀperꢀ30ns.  
12  
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Rev. C  
08/07/09  
IS42S16400E  
AC ELECTRICAL CHARACTERISTICS (1,2,3)  
-6  
-7  
Symbol Parameter  
Min.  
Max.  
Min.  
Max.  
Units  
tc k 3ꢀ  
tc k 2  
ClockꢀCycleꢀTimeꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
6ꢀ  
7.5ꢀ  
—ꢀ  
—ꢀ  
7ꢀ  
7.5ꢀ  
—ꢀ  
—ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
ta c 3ꢀ  
ta c 2  
AccessꢀTimeꢀFromꢀCLK(4,6)  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
—ꢀ  
—ꢀ  
5ꢀ  
6ꢀ  
—ꢀ  
—ꢀ  
5.4ꢀ  
6ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
tc h iꢀ  
tc l ꢀ  
CLKꢀHIGHꢀLevelꢀWidthꢀ  
CLKꢀLOWꢀLevelꢀWidthꢀ  
OutputꢀDataꢀHoldꢀTime(6)  
ꢀ
ꢀ
2ꢀ  
2ꢀ  
—ꢀ  
—ꢀ  
2.5ꢀ  
2.5ꢀ  
—ꢀ  
—ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
to h 3ꢀ  
to h 2  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CAS Latencyꢀ=ꢀ2ꢀ  
2.5ꢀ  
2.5ꢀ  
—ꢀ  
—ꢀ  
2.7ꢀ  
3ꢀ  
—ꢀ  
—ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
tl z ꢀ  
OutputꢀLOWꢀImpedanceꢀTimeꢀ  
OutputꢀHIGHꢀImpedanceꢀTime(5) CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
ꢀ
0ꢀ  
—ꢀ  
0ꢀ  
—ꢀ  
ꢀ
ꢀ
ns  
th z 3ꢀ  
th z 2  
—ꢀ  
—ꢀ  
5ꢀ  
6ꢀ  
—ꢀ  
—ꢀ  
5.4ꢀ  
6ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
tD s ꢀ  
InputꢀDataꢀSetupꢀTimeꢀ  
InputꢀDataꢀHoldꢀTimeꢀ  
AddressꢀSetupꢀTimeꢀ  
AddressꢀHoldꢀTimeꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ  
1ꢀ  
2ꢀ  
1ꢀ  
2ꢀ  
1ꢀ  
—ꢀ  
—ꢀ  
2ꢀ  
1ꢀ  
2ꢀ  
1ꢀ  
2ꢀ  
1ꢀ  
—ꢀ  
—ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tD h ꢀ  
ta s ꢀ  
—ꢀ  
—ꢀ  
ta h ꢀ  
—ꢀ  
—ꢀ  
tc k s ꢀ  
tc k h ꢀ  
tc k a ꢀ  
tc s ꢀ  
CKEꢀSetupꢀTimeꢀ  
—ꢀ  
—ꢀ  
CKEꢀHoldꢀTimeꢀ  
—ꢀ  
—ꢀ  
CKEꢀtoꢀCLKꢀRecoveryꢀDelayꢀTimeꢀ  
1CLK+3  
2ꢀ  
—
1CLK+3  
2.0ꢀ  
1ꢀ  
—
CommandꢀSetupꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)ꢀ ꢀ  
—ꢀ  
—ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tc h ꢀ  
CommandꢀHoldꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)ꢀ  
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ  
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
1ꢀ  
—ꢀ  
—ꢀ  
tr c ꢀ  
60ꢀ  
—ꢀ  
63ꢀ  
—ꢀ  
tr a s ꢀ  
tr p ꢀ  
42ꢀ  
100,000  
—ꢀ  
ꢀ
42ꢀ  
100,000  
—ꢀ  
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ  
18ꢀ  
20ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tr c D ꢀ  
tr r D ꢀ  
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ  
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ  
18ꢀ  
—ꢀ  
20ꢀ  
—ꢀ  
ꢀ
12ꢀ  
—ꢀ  
14ꢀ  
—ꢀ  
tD p l orꢀ  
tw r ꢀ  
InputꢀDataꢀToꢀPrechargeꢀ  
CommandꢀDelayꢀtime  
CASꢀLatencyꢀ=ꢀ3ꢀ  
2CLKꢀ  
—ꢀ  
2CLKꢀ  
—ꢀ  
CAS Latencyꢀ=ꢀ2ꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
2CLKꢀ  
—ꢀ  
2CLKꢀ  
—ꢀ  
ꢀ
ꢀ
ns  
tD a l ꢀ  
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ  
2CLK+tr p  
—
2CLK+tr p  
—
ns  
ꢀ ꢀ ꢀ  
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)  
CAS Latencyꢀ=ꢀ2ꢀ  
2CLK+tr p  
—
2CLK+tr p  
—
ns  
ns  
ttꢀ  
TransitionꢀTimeꢀ  
ꢀ
ꢀ
1ꢀ  
10ꢀ  
64ꢀ  
1ꢀ  
10ꢀ  
64ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
tr e f ꢀ  
RefreshꢀCycleꢀTimeꢀ(4096)ꢀ  
—ꢀ  
—ꢀ  
ms  
Notes:  
1.ꢀ Whenꢀpowerꢀisꢀfirstꢀapplied,ꢀmemoryꢀoperationꢀshouldꢀbeꢀstartedꢀ200ꢀµsꢀafterꢀVD D ꢀandꢀVD D q reach their stipulated voltages. Also  
noteꢀthatꢀtheꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.  
2. measured with tt = 1 ns.  
3.ꢀ Theꢀreferenceꢀlevelꢀisꢀ1.4ꢀVꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih (min.)ꢀandꢀVil  
(max.).  
4.ꢀ Accessꢀtimeꢀisꢀmeasuredꢀatꢀ1.4Vꢀwithꢀtheꢀloadꢀshownꢀinꢀtheꢀfigureꢀbelow.  
5.ꢀ Theꢀtimeꢀth z (max.)ꢀisꢀdefinedꢀasꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀoutputꢀvoltageꢀtoꢀtransitionꢀbyꢀ±ꢀ200ꢀmVꢀfromꢀVo h (min.)ꢀorꢀVo l ꢀ(max.)ꢀ  
when the output is in the high impedance state.  
6. If clock rising time is longer than 1ns, tr/2ꢀ-ꢀ0.5nsꢀshouldꢀbeꢀaddedꢀtoꢀtheꢀparameter.  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
13  
Rev. C  
08/07/09  
IS42S16400E  
OPERATING FREQUENCY / LATENCY RELATIONSHIPS  
SYMBOL PARAMETER  
-6  
-7  
UNITS  
ꢀ
ꢀ
—ꢀ  
ꢀ
ClockꢀCycleꢀTimeꢀ  
ꢀ
ꢀ
ꢀ
CLꢀ=ꢀ3ꢀ  
CLꢀ=ꢀ2ꢀ  
6ꢀ  
7.5ꢀ  
7ꢀ  
7.5ꢀ  
nsꢀꢀ  
ns  
ꢀ
ꢀ
—ꢀ  
ꢀ
OperatingꢀFrequencyꢀ  
ꢀ
ꢀ
ꢀ
CLꢀ=ꢀ3ꢀ  
CLꢀ=ꢀ2ꢀ  
166ꢀ  
133ꢀ  
143ꢀ  
133ꢀ  
MHzꢀ  
MHz  
tc c D ꢀ  
tc k e D ꢀ  
tp e D ꢀ  
tD q D ꢀ  
tD q m ꢀ  
tD q z ꢀ  
tD w D ꢀ  
READ/WRITEꢀcommandꢀtoꢀREAD/WRITEꢀcommandꢀ  
CKEꢀtoꢀclockꢀdisableꢀorꢀpower-downꢀentryꢀmodeꢀ  
CKEꢀtoꢀclockꢀenableꢀorꢀpower-downꢀexitꢀsetupꢀmodeꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1ꢀ  
1ꢀ  
1ꢀ  
0ꢀ  
0ꢀ  
2ꢀ  
0ꢀ  
1ꢀ  
1ꢀ  
1ꢀ  
0ꢀ  
0ꢀ  
2ꢀ  
0ꢀ  
cycle  
cycle  
cycle  
cycle  
cycle  
cycle  
cycle  
DQMꢀtoꢀinputꢀdataꢀdelayꢀ  
ꢀ
ꢀ
DQMꢀtoꢀdataꢀmaskꢀduringꢀWRITEsꢀ  
DQMꢀtoꢀdataꢀhigh-impedanceꢀduringꢀREADsꢀ ꢀ  
WRITEꢀcommandꢀtoꢀinputꢀdataꢀdelayꢀ  
ꢀ
tD a l ꢀ  
ꢀ
Data-inꢀtoꢀACTIVEꢀcommandꢀ  
ꢀ
ꢀ
ꢀ
CLꢀ=ꢀ3ꢀ  
CLꢀ=ꢀ2ꢀ  
5ꢀ  
5ꢀ  
5ꢀ  
5ꢀ  
cycleꢀ  
cycle  
ꢀ
tD p l ꢀ  
tb D l ꢀ  
tc D l ꢀ  
tr D l ꢀ  
Data-inꢀtoꢀPRECHARGEꢀcommandꢀ  
Lastꢀdata-inꢀtoꢀburstꢀSTOPꢀcommandꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ  
1ꢀ  
1ꢀ  
2ꢀ  
2ꢀ  
2ꢀ  
1ꢀ  
1ꢀ  
2ꢀ  
2ꢀ  
cycle  
cycle  
cycle  
cycle  
cycle  
Lastꢀdata-inꢀtoꢀnewꢀREAD/WRITEꢀcommandꢀ ꢀ  
Lastꢀdata-inꢀtoꢀPRECHARGEꢀcommandꢀ  
ꢀ
ꢀ
tm r D ꢀ  
ꢀ
LOADꢀMODEꢀREGISTERꢀcommandꢀ  
toꢀACTIVEꢀorꢀREFRESHꢀcommand  
ꢀ
ꢀ
tr o h ꢀ  
ꢀ
Data-outꢀtoꢀhigh-impedanceꢀfromꢀ  
PRECHARGEꢀcommandꢀ  
ꢀ
ꢀ
CLꢀ=ꢀ3ꢀ  
CLꢀ=ꢀ2ꢀ  
3ꢀ  
2ꢀ  
3ꢀ  
2ꢀ  
cycle  
cycle  
AC TEST CONDITIONS (Input/OutputꢀReferenceꢀLevel:ꢀ1.4V)  
Input Load  
Output Load  
tCK  
tCHI  
t
CL  
3.0V  
50 Ω  
1.4V  
0V  
CLK  
I/O  
+1.4V  
tCS  
tCH  
50 pF  
3.0V  
1.4V  
INPUT  
0V  
tAC  
t
OH  
OUTPUT  
1.4V  
1.4V  
14  
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Rev. C  
08/07/09  
            
TIVEꢀcommandꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorWRITEꢀ  
                                             
IS42S16400E  
FUNCTIONAL DESCRIPTION  
Initialization  
Theꢀ64MbꢀSDRAMsꢀ(1ꢀMegꢀxꢀ16ꢀxꢀ4ꢀbanks)ꢀareꢀquad-bankꢀ  
DRAMsꢀwhichꢀoperateꢀatꢀ3.3Vꢀandꢀincludeꢀaꢀsynchronousꢀ  
interface (all signals are registered on the positive edge of  
theꢀclockꢀsignal,ꢀCLK).ꢀEachꢀofꢀtheꢀ16,777,216-bitꢀbanksꢀisꢀ  
organizedꢀasꢀ4,096ꢀrowsꢀbyꢀ256ꢀcolumnsꢀbyꢀ16ꢀbits.  
SDRAMsꢀ mustꢀ beꢀ poweredꢀ upꢀ andꢀ initializedꢀ inꢀ aꢀ  
predefined manner.  
Theꢀ64MꢀSDRAMꢀisꢀinitializedꢀafterꢀtheꢀpowerꢀisꢀappliedꢀ  
toꢀVD D ꢀandꢀVD D q ꢀ(simultaneously),ꢀandꢀtheꢀclockꢀisꢀstableꢀ  
withꢀDQMꢀHighꢀandꢀCKEꢀHigh.ꢀ  
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented;ꢀ  
accesses start at a selected location and continue for  
a programmed number of locations in a programmed  
sequence.ꢀAccessesꢀbeginꢀwithꢀtheꢀregistrationꢀofꢀanꢀAC-  
Aꢀ100µsꢀdelayꢀisꢀrequiredꢀpriorꢀtoꢀissuingꢀanyꢀcommandꢀ  
other than a COMMANDꢀINHIBIT or a NOP.ꢀTheꢀCOMMANDꢀ  
INHIBITꢀorꢀNOPꢀmayꢀbeꢀappliedꢀduringꢀtheꢀ100µsꢀperiodꢀandꢀ  
continue should at least through the end of the period.  
WithꢀatꢀleastꢀoneꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandꢀ  
havingꢀbeenꢀapplied,ꢀaꢀPRECHARGEꢀcommandꢀshouldꢀ  
beꢀappliedꢀonceꢀtheꢀ100µsꢀdelayꢀhasꢀbeenꢀsatisfied.ꢀꢀAllꢀ  
banksꢀmustꢀbeꢀprecharged.ꢀꢀThisꢀwillꢀleaveꢀallꢀbanksꢀinꢀ  
an idle state, afterꢀwhichꢀatꢀleastꢀtwoꢀAUTOꢀREFRESH cycles  
must be performed. After the AUTOꢀREFRESH cycles are  
complete,ꢀ theꢀ SDRAMꢀ isꢀ thenꢀ readyꢀ forꢀ modeꢀ registerꢀ  
programming.  
command.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀ  
ACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀ  
be accessed (BA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀA0-A11ꢀselectꢀtheꢀ  
row).Theꢀaddressꢀbitsꢀ(A0-A7) registeredcoincidentwiththe  
READꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀ  
column location for the burst access.  
Priorꢀ toꢀ normalꢀ operation,ꢀ theꢀ SDRAMꢀ mustꢀ beꢀ initial-  
ized.ꢀTheꢀfollowingꢀsectionsꢀprovideꢀdetailedꢀinformationꢀ  
coveringꢀdeviceꢀinitialization,ꢀregisterꢀdefinition,ꢀcommandꢀ  
descriptions and device operation.  
Theꢀ modeꢀ registerꢀ shouldꢀ beꢀ loadedꢀ priorꢀ toꢀ applyingꢀ  
any operational command because it will power up in an  
unknownꢀstate.ꢀAfterꢀtheꢀLoadꢀModeꢀRegisterꢀcommand,ꢀ  
atꢀleastꢀoneꢀNOPꢀcommandꢀmustꢀbeꢀassertedꢀpriorꢀtoꢀ  
any command.  
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initiatingꢀtheꢀsubsequentꢀoperation.  
                                                                            
Violatingꢀeitherꢀofꢀtheseꢀ  
IS42S16400E  
REGISTER DEFINITION  
Mode Register  
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ  
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ  
selection of a burst length, a burst type, a CAS latency,  
an operating mode and a write burst mode, as shown in  
MODEꢀREGISTERꢀDEFINITION.ꢀ  
ModeꢀregisterꢀbitsꢀM0-M2ꢀspecifyꢀtheꢀburstꢀlength,ꢀM3ꢀ  
specifiesthetypeofburst(sequentialꢀorꢀinterleaved),ꢀM4-ꢀM6ꢀ  
specifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀ  
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10ꢀandꢀ  
M11ꢀareꢀreservedꢀforꢀfutureꢀuse.  
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ  
idle, and the controller must wait the specified time before  
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ  
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ  
until it is programmed again or the device loses power.  
requirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.  
MODE REGISTER DEFINITION  
Address Bus  
A11 A10 A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Mode Register (Mx)  
Reserved(1)  
Burst Length  
M2 M1 M0  
M3=0  
M3=1  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved  
Reserved Reserved  
Reserved Reserved  
Full Page Reserved  
Burst Type  
M3  
Type  
0
1
Sequential  
Interleaved  
Latency Mode  
M6 M5 M4  
CAS Latency  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
Reserved  
2
3
Reserved  
Reserved  
Reserved  
Reserved  
Operating Mode  
M8 M7 M6-M0 Mode  
0
—
0
—
Defined Standard Operation  
All Other States Reserved  
—
Write Burst Mode  
M9  
0
Mode  
Programmed Burst Length  
Single Location Access  
1. To ensure compatibility with future devices,  
should program M11, M10 = "0, 0"  
1
16  
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Burst Length  
ing that the burst will wrap within the block if a boundary  
isꢀreached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-A7ꢀ(x16)ꢀ  
whenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo;ꢀbyꢀA2-A7ꢀ(x16)ꢀwhenꢀ  
theꢀburstꢀlengthꢀisꢀsetꢀtoꢀfour;ꢀandꢀbyꢀA3-A7ꢀ(x16)ꢀwhenꢀtheꢀ  
burstꢀlengthꢀisꢀsetꢀtoꢀeight.ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀ  
addressꢀbit(s)ꢀisꢀ(are)ꢀusedꢀtoꢀselectꢀtheꢀstartingꢀlocationꢀ  
withinꢀtheꢀblock.ꢀFull-pageꢀburstsꢀwrapꢀwithinꢀtheꢀpageꢀifꢀ  
the boundary is reached.  
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented,ꢀ  
with the burst length being programmable, as shown in  
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeter-  
minesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀ  
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀ  
lengthsꢀofꢀ1,ꢀ2,ꢀ4ꢀorꢀ8ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀ  
sequentialꢀandꢀtheꢀinterleavedꢀburstꢀtypes,ꢀandꢀaꢀfull-pageꢀ  
burstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀ  
burstꢀisꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀ  
command to generate arbitrary burst lengths.  
Burst Type  
Accesses within a given burst may be programmed to be  
eitherꢀsequentialꢀorꢀinterleaved;ꢀthisꢀisꢀreferredꢀtoꢀasꢀtheꢀ  
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀM3.  
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀ  
or incompatibility with future versions may result.  
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀ  
columnsꢀequalꢀtoꢀtheꢀburstꢀlengthꢀisꢀeffectivelyꢀselected.ꢀAllꢀ  
accesses for that burst take place within this block, mean-  
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀ  
the burst length, the burst type and the starting column  
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.  
BURST DEFINITION  
Burst  
Starting Column  
Address  
Order of Accesses Within a Burst  
Length  
Type = Sequential  
Type = Interleaved  
A0  
ꢀ
ꢀ
2ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ  
1ꢀ  
ꢀ
ꢀ
0-1ꢀ  
1-0ꢀ  
ꢀ
ꢀ
0-1  
1-0  
A1  
0ꢀ  
0ꢀ  
1ꢀ  
1ꢀ  
A1  
0ꢀ  
0ꢀ  
1ꢀ  
ꢀ1ꢀ  
0ꢀ  
0ꢀ  
1ꢀ  
1ꢀ  
A0  
0ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3ꢀ  
1-2-3-0ꢀ  
2-3-0-1ꢀ  
3-0-1-2ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3  
1-0-3-2  
2-3-0-1  
3-2-1-0  
1ꢀ  
ꢀ
0ꢀ  
ꢀ
ꢀ
1ꢀ  
A2  
0ꢀ  
0ꢀ  
0ꢀ  
0ꢀ  
1ꢀ  
1ꢀ  
1ꢀ  
1ꢀ  
A0  
0ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7ꢀ  
1-2-3-4-5-6-7-0ꢀ  
ꢀ2-3-4-5-6-7-0-1ꢀ  
ꢀ3-4-5-6-7-0-1-2ꢀ  
4-5-6-7-0-1-2-3ꢀ  
5-6-7-0-1-2-3-4ꢀ  
6-7-0-1-2-3-4-5ꢀ  
7-0-1-2-3-4-5-6ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7  
ꢀ1-0-3-2-5-4-7-6  
2-3-0-1-6-7-4-5  
3-2-1-0-7-6-5-4  
4-5-6-7-0-1-2-3  
5-4-7-6-1-0-3-2  
6-7-4-5-2-3-0-1  
7-6-5-4-3-2-1-0  
NotꢀSupportedꢀ  
1ꢀ  
ꢀ
ꢀ0ꢀ  
1ꢀ  
8ꢀ  
ꢀ
0ꢀ  
ꢀ
1ꢀ  
ꢀ
0ꢀ  
ꢀ
1ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
Fullꢀ  
Pageꢀ  
(y)ꢀ  
nꢀ=ꢀA0-A7ꢀ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ  
Cnꢀ+ꢀ3,ꢀCnꢀ+ꢀ4...  
…Cnꢀ-ꢀ1,  
ꢀ
(locationꢀ0-y)ꢀ  
ꢀ
ꢀ
Cn…  
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IS42S16400E  
Operating Mode  
CAS Latency  
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀ  
toꢀzero;ꢀtheꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀM7ꢀandꢀM8ꢀareꢀ  
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ  
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.  
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀ  
the registrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ  
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ  
three clocks.  
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-  
cause unknown operation or incompatibility with future  
versions may result.  
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀ  
the latency is m clocks, the data will be available by clock  
edge n + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ  
clock edge one cycle earlier (n + m -ꢀ1),ꢀandꢀprovidedꢀthatꢀ  
the relevant access times are met, the data will be valid by  
clock edge n + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ  
cycle time is such that all relevant access times are met,  
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ  
isꢀprogrammedꢀtoꢀtwoꢀclocks,ꢀtheꢀDQsꢀwillꢀstartꢀdrivingꢀ  
afterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ  
Latencyꢀdiagrams.ꢀTheꢀAllowable Operating Frequency  
tableꢀindicatesꢀtheꢀoperatingꢀfrequenciesꢀatꢀwhichꢀeachꢀ  
CAS latency setting can be used.  
Write Burst Mode  
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀ  
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ  
theꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀ  
writeꢀaccessesꢀareꢀsingle-locationꢀ(nonburst)ꢀaccesses.  
CAS Latency  
Allowable Operating Frequency (MHz)  
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀ  
or incompatibility with future versions may result.  
Speed  
CAS Latency = 2  
CAS Latency = 3  
6
7
133  
133  
166  
143  
CAS Latency  
T0  
T1  
T2  
T3  
CLK  
READ  
NOP  
NOP  
COMMAND  
DQ  
t
AC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 2  
T0  
T1  
T2  
T3  
T4  
CLK  
READ  
NOP  
NOP  
NOP  
COMMAND  
DQ  
t
AC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 3  
DON'T CARE  
UNDEFINED  
18  
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IS42S16400E  
OPERATION  
Activating Specific Row Within Specific Bank  
BANK/ROW ACTIVATION  
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀ  
toꢀaꢀbankꢀwithinꢀtheꢀSDRAM,ꢀaꢀrowꢀinꢀthatꢀbankꢀmustꢀbeꢀ  
“opened.”ꢀThisꢀisꢀaccomplishedꢀviaꢀtheꢀACTIVEꢀcommand,ꢀ  
which selects both the bank and the row to be activated  
(see ActivatingꢀSpecificꢀRowꢀWithinꢀSpecificꢀBank).  
CLK  
HIGH - Z  
CKE  
CS  
RAS  
CAS  
WE  
After opening a row (issuingꢀanꢀACTIVEꢀcommand),ꢀaꢀREADꢀ  
orꢀWRITEꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀ  
the tr c D ꢀspecification.ꢀMinimumꢀtr c D should be divided by  
theꢀclockꢀperiodꢀandꢀroundedꢀupꢀtoꢀtheꢀnextꢀwholeꢀnumberꢀ  
toꢀ determineꢀ theꢀ earliestꢀ clockꢀ edgeꢀ afterꢀ theꢀ ACTIVEꢀ  
commandꢀonꢀwhichꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcanꢀbeꢀ  
entered.ꢀForꢀexample,ꢀaꢀtr c D specification of 20ns with a  
125ꢀMHzꢀclockꢀ(8nsꢀperiod)ꢀresultsꢀinꢀ2.5ꢀclocks,ꢀroundedꢀ  
toꢀ3.ꢀThisꢀisꢀreflectedꢀinꢀtheꢀfollowingꢀexample,ꢀwhichꢀcov-  
ersꢀanyꢀcaseꢀwhereꢀ2ꢀ<ꢀ[tr c D ꢀ(MIN)/tc k ] ≤ꢀ3.ꢀ(Theꢀsameꢀ  
procedure is used to convert other specification limits from  
timeꢀunitsꢀtoꢀclockꢀcycles).  
A0-A11  
BA0, BA1  
ROW ADDRESS  
BANK ADDRESS  
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀaꢀdifferentꢀrowꢀinꢀtheꢀ  
same bank can only be issued after the previous active  
rowꢀhasꢀbeenꢀ“closed”ꢀ(precharged).ꢀTheꢀminimumꢀtimeꢀ  
intervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀtheꢀ  
same bank is defined by tr c .  
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀ  
issuedwhilethefirstbankisbeingaccessed, whichresults  
inꢀaꢀreductionꢀofꢀtotalꢀrow-accessꢀoverhead.ꢀTheꢀminimumꢀ  
timeꢀintervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀ  
different banks is defined by tr r D .  
Example: Meeting tR C D (MIN) when 2 < [tR C D (min)/tC K ] ≤ 3  
T0  
T1  
T2  
T3  
T4  
CLK  
READ or  
WRITE  
ACTIVE  
NOP  
NOP  
COMMAND  
t
RCD  
DON'T CARE  
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sameꢀbank.TheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀ  
                                                            
IS42S16400E  
READS  
READ COMMAND  
READꢀ burstsꢀ areꢀ initiatedꢀ withꢀ aꢀ READꢀ command,ꢀ asꢀ  
shownꢀinꢀtheꢀREADꢀCOMMANDꢀdiagram.  
CLK  
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ  
theꢀREADꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀorꢀ  
disabled for that burst access. If auto precharge is enabled,  
the row being accessed is precharged at the completion of  
theꢀburst.ꢀForꢀtheꢀgenericꢀREADꢀcommandsꢀusedꢀinꢀtheꢀfol-  
lowing illustrations, auto precharge is disabled.  
HIGH-Z  
CKE  
CS  
RAS  
DuringꢀREADꢀbursts,ꢀtheꢀvalidꢀdata-outꢀelementꢀfromꢀtheꢀ  
starting column address will be available following the  
CASꢀlatencyꢀafterꢀtheꢀREADꢀcommand.ꢀEachꢀsubsequentꢀ  
data-outꢀelementꢀwillꢀbeꢀvalidꢀbyꢀtheꢀnextꢀpositiveꢀclockꢀ  
edge.ꢀTheꢀCASꢀLatencyꢀdiagramꢀshowsꢀgeneralꢀtiming  
for each possible CAS latency setting.  
CAS  
WE  
COLUMN ADDRESS  
AUTO PRECHARGE  
Uponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀotherꢀcommandsꢀ  
haveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Z.ꢀAꢀfull-pageꢀburstꢀ  
will continue until terminated. (At the end of the page, it will  
wrapꢀtoꢀcolumnꢀ0ꢀandꢀcontinue.)  
A0-A7  
A8, A9, A11  
A10  
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-  
sequentꢀREADꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ  
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ  
READꢀcommand.ꢀInꢀeitherꢀcase,ꢀaꢀcontinuousꢀflowꢀofꢀdataꢀ  
canꢀbeꢀmaintained.ꢀTheꢀfirstꢀdataꢀelementꢀfromꢀtheꢀnewꢀ  
burst follows either the last element of a completed burst  
or the last desired data element of a longer burst which  
is being truncated.  
NO PRECHARGE  
BANK ADDRESS  
BA0, BA1  
TheꢀDQMꢀinputꢀisꢀusedꢀtoꢀavoidꢀI/Oꢀcontention,ꢀasꢀshownꢀ  
inꢀFiguresꢀRW1ꢀandꢀRW2.ꢀTheꢀDQMꢀsignalꢀmustꢀbeꢀas-  
sertedꢀ(HIGH)ꢀatꢀleastꢀthreeꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀ  
commandꢀ(DQMꢀlatencyꢀisꢀtwoꢀclocksꢀforꢀoutputꢀbuffers)ꢀ  
toꢀsuppressꢀdata-outꢀfromꢀtheꢀREAD.ꢀOnceꢀtheꢀWRITEꢀ  
commandꢀisꢀregistered,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Zꢀ(orꢀremainꢀ  
High-Z),ꢀregardlessꢀofꢀtheꢀstateꢀofꢀtheꢀDQMꢀsignal,ꢀprovidedꢀ  
theꢀDQMꢀwasꢀactiveꢀonꢀtheꢀclockꢀjustꢀpriorꢀtoꢀtheꢀWRITEꢀ  
commandꢀthatꢀtruncatedꢀtheꢀREADꢀcommand.ꢀIfꢀnot,ꢀtheꢀ  
secondꢀWRITEꢀwillꢀbeꢀanꢀinvalidꢀWRITE.ꢀForꢀexample,ꢀifꢀ  
DQMꢀwasꢀLOWꢀduringꢀT4ꢀinꢀFigureꢀRW2,ꢀthenꢀtheꢀWRITEsꢀ  
atꢀT5ꢀandꢀT7ꢀwouldꢀbeꢀvalid,ꢀwhileꢀtheꢀWRITEꢀatꢀT6ꢀwouldꢀ  
be invalid.  
TheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀxcyclesbefore  
the clock edge at which the last desired data element is  
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ  
shownꢀinꢀConsecutiveꢀREADꢀBurstsꢀforꢀCASꢀlatenciesꢀofꢀ  
twoꢀandꢀthree;ꢀdataꢀelementꢀn +ꢀ3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀ  
burstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀTheꢀ64Mbꢀ  
SDRAMꢀusesꢀaꢀpipelinedꢀarchitectureꢀandꢀthereforeꢀdoesꢀ  
notꢀrequireꢀtheꢀ2n rule associated with a prefetch architec-  
ture.ꢀAꢀREADꢀcommandꢀcanꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀ  
followingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀ  
read accesses can be performed to the same bank, as  
shownꢀinꢀRandomꢀREADꢀAccesses,ꢀorꢀeachꢀsubsequentꢀ  
READꢀmayꢀbeꢀperformedꢀtoꢀaꢀdifferentꢀbank.  
TheꢀDQMꢀsignalꢀmustꢀbeꢀde-assertedꢀpriorꢀtoꢀtheꢀWRITEꢀ  
commandꢀ(DQMꢀlatencyꢀisꢀzeroꢀclocksꢀforꢀinputꢀbuffers)ꢀ  
to ensure that the written data is not masked.  
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-  
sequentꢀWRITEꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ  
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ  
WRITEꢀcommandꢀ(subjectꢀtoꢀbusꢀturnaroundꢀlimitations).ꢀ  
TheꢀWRITEꢀburstꢀmayꢀbeꢀinitiatedꢀonꢀtheꢀclockꢀedgeꢀim-  
mediatelyꢀfollowingꢀtheꢀlastꢀ(orꢀlastꢀdesired)ꢀdataꢀelementꢀ  
fromꢀtheꢀREADꢀburst,ꢀprovidedꢀthatꢀI/Oꢀcontentionꢀcanꢀbeꢀ  
avoided. In a given system design, there may be a pos-  
sibilityꢀthatꢀtheꢀdeviceꢀdrivingꢀtheꢀinputꢀdataꢀwillꢀgoꢀLow-Zꢀ  
beforeꢀtheꢀSDRAMꢀDQsꢀgoꢀHigh-Z.ꢀInꢀthisꢀcase,ꢀatꢀleastꢀ  
aꢀsingle-cycleꢀdelayꢀshouldꢀoccurꢀbetweenꢀtheꢀlastꢀreadꢀ  
dataꢀandꢀtheꢀWRITEꢀcommand.  
Aꢀfixed-lengthꢀREADꢀburstꢀmayꢀbeꢀfollowedꢀby,ꢀorꢀtruncatedꢀ  
with, aPRECHARGE commandtothesamebank(provided  
thatꢀautoꢀprechargeꢀwasꢀnotꢀactivated),ꢀandꢀaꢀfull-pageꢀburstꢀ  
mayꢀbeꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ  
x cycles before the clock edge at which the last desired  
data element is valid, where x equalsꢀtheꢀCASꢀlatencyꢀ  
minusꢀone.ꢀThisꢀisꢀshownꢀinꢀtheꢀREADꢀtoꢀPRECHARGEꢀ  
20  
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08/07/09  
providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.TheꢀBURSTꢀ  
                                                                                       
IS42S16400E  
diagramꢀforꢀeachꢀpossibleꢀCASꢀlatency;ꢀdataꢀelementꢀn +ꢀ  
3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀ  
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ  
subsequentꢀcommandꢀtoꢀtheꢀsameꢀbankꢀcannotꢀbeꢀissuedꢀ  
until tr p is met. Note that part of the row precharge time is  
hiddenꢀduringꢀtheꢀaccessꢀofꢀtheꢀlastꢀdataꢀelement(s).  
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ  
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ  
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ  
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cycles before  
the clock edge at which the last desired data element is  
valid, where x equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ  
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ  
possibleꢀCASꢀlatency;ꢀdataꢀelementꢀn+ꢀ3ꢀisꢀtheꢀlastꢀdesiredꢀ  
data element of a longer burst.  
Inꢀ theꢀ caseꢀ ofꢀ aꢀ fixed-lengthꢀ burstꢀ beingꢀ executedꢀ toꢀ  
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ  
optimumꢀtimeꢀ(asꢀdescribedꢀabove)ꢀprovidesꢀtheꢀsameꢀ  
operationꢀ thatꢀ wouldꢀ resultꢀ fromꢀ theꢀ sameꢀ fixed-lengthꢀ  
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-  
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ  
and address buses be available at the appropriate time to  
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ  
commandꢀisꢀthatꢀitꢀcanꢀbeꢀusedꢀtoꢀtruncateꢀfixed-lengthꢀ  
orꢀfull-pageꢀbursts.  
CAS Latency  
T0  
T1  
T2  
T3  
CLK  
READ  
NOP  
NOP  
COMMAND  
DQ  
t
AC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 2  
T0  
T1  
T2  
T3  
T4  
CLK  
READ  
NOP  
NOP  
NOP  
COMMAND  
DQ  
tAC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 3  
DON'T CARE  
UNDEFINED  
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IS42S16400E  
Consecutive READ Bursts  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
READ  
NOP  
NOP  
x=1 cycle  
BANK,  
COL n  
BANK,  
COL b  
D
OUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
D
OUT  
b
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
READ  
NOP  
NOP  
NOP  
READ  
NOP  
x = 2 cycles  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
ADDRESS  
DQ  
DOUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
D
OUT  
b
CAS Latency - 3  
DON'T CARE  
22  
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IS42S16400E  
Random READ Accesses  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
COMMAND  
ADDRESS  
DQ  
READ  
READ  
READ  
READ  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
BANK,  
COL m  
BANK,  
COL x  
D
OUT  
n
DOUT  
b
DOUT  
m
DOUT  
x
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
COMMAND  
ADDRESS  
DQ  
READ  
READ  
READ  
READ  
NOP  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
BANK,  
COL m  
BANK,  
COL x  
DOUT  
n
DOUT  
b
DOUT  
m
DOUT  
x
CAS Latency - 3  
DON'T CARE  
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IS42S16400E  
RW1 - READ to WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
DQM  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
t
HZ  
DOUT n+1  
DOUT n+2  
D
OUT  
n
DIN b  
CAS Latency - 2  
t
DS  
DON'T CARE  
RW2 - READ to WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
DQM  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
t
HZ  
DOUT  
n
DIN  
b
CAS Latency - 3  
t
DS  
DON'T CARE  
24  
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IS42S16400E  
READ to PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
t
RP  
PRECHARGE  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
x = 1 cycle  
BANK a,  
COL n  
BANK  
BANK a,  
ROW  
(a or all)  
D
OUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
ADDRESS  
DQ  
t
RP  
PRECHARGE  
READ  
NOP  
NOP  
NOP  
NOP  
x = 2 cycles  
NOP  
ACTIVE  
BANK,  
COL n  
BANK,  
COL b  
BANK a,  
ROW  
DOUT  
n
DOUT n+1  
D
OUT n+2  
DOUT n+3  
CAS Latency - 3  
DON'T CARE  
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IS42S16400E  
READ Burst Termination  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
BURST  
TERMINATE  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
x = 1 cycle  
BANK a,  
COL n  
D
OUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
CAS Latency - 2  
DON'T CARE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
ADDRESS  
DQ  
BURST  
TERMINATE  
READ  
NOP  
NOP  
NOP  
NOP  
x = 2 cycles  
NOP  
NOP  
BANK,  
COL n  
DOUT  
n
DOUT n+1  
DOUT n+2  
DOUT n+3  
CAS Latency - 3  
DON'T CARE  
26  
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precharge.TheꢀdisadvantageꢀofꢀtheꢀPRECHARGEcommand  
                                                              
IS42S16400E  
AnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀWRITEꢀdiagram.ꢀDataꢀ  
n +ꢀ1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀ  
ofꢀaꢀlongerꢀburst.ꢀTheꢀ64MbꢀSDRAMꢀ usesꢀ aꢀ pipelinedꢀ  
architectureꢀandꢀthereforeꢀdoesꢀnotꢀrequireꢀtheꢀ2n rule as-  
sociatedꢀwithꢀaꢀprefetchꢀarchitecture.ꢀAꢀWRITEꢀcommandꢀ  
can be initiated on any clock cycle following a previous  
WRITEꢀcommand.ꢀFull-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀ  
a page can be performed to the same bank, as shown in  
RandomꢀWRITEꢀCycles,ꢀorꢀeachꢀsubsequentꢀWRITEꢀmayꢀ  
be performed to a different bank.  
WRITEs  
WRITEꢀburstsꢀareꢀinitiatedꢀwithꢀaꢀWRITEꢀcommand,ꢀasꢀ  
shownꢀinꢀWRITEꢀCommandꢀdiagram.  
WRITE Command  
CLK  
HIGH - Z  
CKE  
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-  
quentꢀREADꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ  
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀaꢀsubsequentꢀREADꢀ  
command.ꢀOnceꢀtheꢀREADꢀcommandꢀisꢀregistered,ꢀtheꢀ  
dataꢀinputsꢀwillꢀbeꢀignored,ꢀandꢀWRITEsꢀwillꢀnotꢀbeꢀex-  
ecuted.ꢀAnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀREAD.ꢀDataꢀn  
+ꢀ1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀ  
of a longer burst.  
CS  
RAS  
CAS  
WE  
Dataꢀ forꢀ aꢀ fixed-lengthꢀ WRITEꢀ burstꢀ mayꢀ beꢀ followedꢀ  
by,ꢀorꢀtruncatedꢀwith,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ  
same bank (provided that auto precharge was not acti-  
vated),ꢀandꢀaꢀfull-pageꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀ  
withꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀ  
PRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀtw r after the  
clock edge at which the last desired input data element  
isꢀregistered.ꢀTheꢀautoꢀprechargeꢀmodeꢀrequiresꢀaꢀtw r of  
atꢀleastꢀoneꢀclockꢀplusꢀtime,ꢀregardlessꢀofꢀfrequency.ꢀInꢀ  
addition,ꢀwhenꢀtruncatingꢀaꢀWRITEꢀburst,ꢀtheꢀDQMꢀsignalꢀ  
must be used to mask input data for the clock edge prior  
to,ꢀandꢀtheꢀclockꢀedgeꢀcoincidentꢀwith,ꢀtheꢀPRECHARGEꢀ  
command.ꢀAnꢀexampleꢀisꢀshownꢀinꢀtheꢀWRITEꢀtoꢀPRE-  
CHARGEꢀdiagram.ꢀDataꢀn+1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀ  
ofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀFollowingꢀtheꢀ  
PRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀ  
same bank cannot be issued until tr p is met.  
COLUMN ADDRESS  
AUTO PRECHARGE  
A0-A7  
A8, A9, A11  
A10  
NO PRECHARGE  
BANK ADDRESS  
BA0, BA1  
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ  
theꢀWRITEꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀ  
or disabled for that access. If auto precharge is enabled,  
the row being accessed is precharged at the completion of  
theꢀburst.ꢀForꢀtheꢀgenericꢀWRITEꢀcommandsꢀusedꢀinꢀtheꢀ  
following illustrations, auto precharge is disabled.  
Inꢀtheꢀcaseꢀofꢀaꢀfixed-lengthꢀburstꢀbeingꢀexecutedꢀtoꢀcomple-  
tion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀ  
time (asꢀdescribedꢀabove) provides the same operation that  
wouldꢀresultꢀfromꢀtheꢀsameꢀfixed-lengthꢀburstꢀwithꢀautoꢀ  
DuringꢀWRITEꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-in element will be  
registeredcoincidentwiththeWRITEꢀcommand.ꢀSubsequentꢀ  
data elements will be registered on each successive posi-  
tiveꢀclockꢀedge.ꢀUponꢀcompletionꢀofꢀaꢀfixed-lengthꢀburst,ꢀ  
assuming no other commands have been initiated, the  
DQsꢀwillꢀremainꢀHigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀ  
beꢀignoredꢀ(seeꢀWRITEꢀBurst).ꢀAꢀfull-pageꢀburstꢀwillꢀcon-  
tinue until terminated. (At the end of the page, it will wrap  
toꢀcolumnꢀ0ꢀandꢀcontinue.)  
isꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀandꢀaddressꢀbusesꢀbeꢀ  
availableꢀatꢀtheꢀappropriateꢀtimeꢀtoꢀissueꢀtheꢀcommand;ꢀtheꢀ  
advantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀ  
usedꢀtoꢀtruncateꢀfixed-lengthꢀorꢀfull-pageꢀbursts.  
Fixed-lengthꢀorꢀfull-pageꢀWRITEꢀburstsꢀcanꢀbeꢀtruncatedꢀ  
withꢀtheꢀBURSTꢀTERMINATEꢀcommand.ꢀWhenꢀtruncat-  
ingꢀaꢀWRITEꢀburst,ꢀtheꢀinputꢀdataꢀappliedꢀcoincidentꢀwithꢀ  
theꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀignored.ꢀTheꢀ  
lastꢀdataꢀwrittenꢀ(providedꢀthatꢀDQMꢀisꢀLOWꢀatꢀthatꢀtime)ꢀ  
will be the input data applied one clock previous to the  
BURSTꢀTERMINATEꢀcommand.ꢀThisꢀisꢀshownꢀinꢀWRITEꢀ  
BurstꢀTermination,ꢀwhereꢀdataꢀn is the last desired data  
element of a longer burst.  
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-  
quentꢀWRITEꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ  
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀforꢀaꢀWRITEꢀ  
command.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀ  
anyꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand,ꢀandꢀtheꢀ  
data provided coincident with the new command applies to  
the new command.  
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IS42S16400E  
WRITE Burst  
T0  
T1  
T2  
T3  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
NOP  
NOP  
BANK,  
COL n  
DIN  
n
DIN n+1  
DON'T CARE  
WRITE to WRITE  
T0  
T1  
T2  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
DIN  
n
DIN n+1  
DIN b  
DON'T CARE  
Random WRITE Cycles  
T0  
T1  
T2  
T3  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
WRITE  
WRITE  
WRITE  
BANK,  
COL n  
BANK,  
COL b  
BANK,  
COL m  
BANK,  
COL x  
DIN  
n
DIN  
b
DIN  
m
DIN x  
28  
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WRITE to READ  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
READ  
NOP  
NOP  
NOP  
BANK,  
COL n  
BANK,  
COL b  
DIN  
n
DIN n+1  
D
OUT  
b
DOUT b+1  
CAS Latency - 2  
DON'T CARE  
WP1 - WRITE to PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
DQM  
t
RP  
PRECHARGE  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
NOP  
ACTIVE  
NOP  
NOP  
BANK a,  
COL n  
BANK  
BANK a,  
ROW  
(a or all)  
t
WR  
DIN  
n
DIN n+1  
CAS Latency - 2  
DON'T CARE  
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29  
Rev. C  
08/07/09  
IS42S16400E  
WP2 - WRITE to PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
DQM  
tRP  
PRECHARGE  
COMMAND  
ADDRESS  
DQ  
WRITE  
NOP  
NOP  
NOP  
ACTIVE  
NOP  
BANK a,  
COL n  
BANK  
BANK a,  
ROW  
(a or all)  
t
WR  
DIN  
n
D
IN n+1  
CAS Latency - 3  
DON'T CARE  
WRITE Burst Termination  
T0  
T1  
T2  
CLK  
BURST  
TERMINATE  
NEXT  
COMMAND  
ADDRESS  
DQ  
WRITE  
COMMAND  
BANK,  
COL n  
(ADDRESS)  
DIN  
n
(DATA)  
DON'T CARE  
30  
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08/07/09  
allꢀbanks.Theꢀbank(s)ꢀwillꢀbeꢀavailableꢀforꢀaꢀsubsequentꢀrowꢀ  
                
IS42S16400E  
PRECHARGE  
PRECHARGE Command  
TheꢀPRECHARGEꢀcommandꢀ(seeꢀfigure)ꢀisꢀusedꢀtoꢀdeac-  
tivate the open row in a particular bank or the open row in  
CLK  
HIGH - Z  
access some specified time (tr p )ꢀafterꢀtheꢀPRECHARGEꢀ  
command is issued.Input A10 determines whether one or  
all banks are to be precharged, and in the case where only  
oneꢀbankꢀisꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀBA1ꢀselectꢀtheꢀ  
bank.ꢀWhenꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀ  
BA1ꢀareꢀtreatedꢀasꢀ“Don’tꢀCare.”ꢀOnceꢀaꢀbankꢀhasꢀbeenꢀ  
precharged, it is in the idle state and must be activated  
priorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀissuedꢀtoꢀ  
that bank.  
CKE  
CS  
RAS  
CAS  
WE  
POWER-DOWN  
A0-A9, A11  
ALL BANKS  
Power-downꢀoccursꢀifꢀCKEꢀisꢀregisteredꢀLOWꢀcoincidentꢀ  
withꢀaꢀNOPꢀorꢀCOMMANDꢀINHIBITꢀwhenꢀnoꢀaccessesꢀ  
areꢀinꢀprogress.ꢀIfꢀpower-downꢀoccursꢀwhenꢀallꢀbanksꢀareꢀ  
idle,ꢀthisꢀmodeꢀisꢀreferredꢀtoꢀasꢀprechargeꢀpower-down;ꢀ  
ifꢀpower-downꢀoccursꢀwhenꢀthereꢀisꢀaꢀrowꢀactiveꢀinꢀeitherꢀ  
bank,ꢀ thisꢀ modeꢀ isꢀ referredꢀ toꢀ asꢀ activeꢀ power-down.ꢀ  
Enteringꢀ power-downꢀ deactivatesꢀ theꢀ inputꢀ andꢀ outputꢀ  
buffers,ꢀexcludingꢀCKE,ꢀforꢀmaximumꢀpowerꢀsavingsꢀwhileꢀ  
inꢀstandby.ꢀTheꢀdeviceꢀmayꢀnotꢀremainꢀinꢀtheꢀpower-downꢀ  
stateꢀlongerꢀthanꢀtheꢀrefreshꢀperiodꢀ(64ms)ꢀsinceꢀnoꢀrefreshꢀ  
operations are performed in this mode.  
A10  
BANK SELECT  
BANK ADDRESS  
BA0, BA1  
Theꢀpower-downꢀstateꢀisꢀexitedꢀbyꢀregisteringꢀaꢀNOPꢀorꢀ  
COMMANDꢀINHIBITꢀandꢀCKEꢀHIGHꢀatꢀtheꢀdesiredꢀclockꢀ  
edge (meeting tc k s ).ꢀSeeꢀfigureꢀbelow.  
POWER-DOWN  
CLK  
t
CKS  
≥ tCKS  
CKE  
COMMAND  
NOP  
NOP  
ACTIVE  
tRCD  
tRAS  
t
RC  
All banks idle  
Input buffers gated off  
Enter power-down mode  
Exit power-down mode  
DON'T CARE  
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31  
Rev. C  
08/07/09  
IS42S16400E  
CLOCK SUSPEND  
ofꢀaꢀsuspendedꢀinternalꢀclockꢀedgeꢀisꢀignored;ꢀanyꢀdataꢀ  
presentꢀonꢀtheꢀDQꢀpinsꢀremainsꢀdriven;ꢀandꢀburstꢀcountersꢀ  
are not incremented, as long as the clock is suspended.  
(Seeꢀfollowingꢀexamples.)  
Clock suspend mode occurs when a column access/burst  
isꢀinꢀprogressꢀandꢀCKEꢀisꢀregisteredꢀLOW.ꢀInꢀtheꢀclockꢀ  
suspendꢀmode,ꢀtheꢀinternalꢀclockꢀisꢀdeactivated,ꢀ“freezing”ꢀ  
the synchronous logic.  
ClockꢀsuspendꢀmodeꢀisꢀexitedꢀbyꢀregisteringꢀCKEꢀHIGH;ꢀ  
the internal clock and related operation will resume on the  
subsequentꢀpositiveꢀclockꢀedge.  
ForꢀeachꢀpositiveꢀclockꢀedgeꢀonꢀwhichꢀCKEꢀisꢀsampledꢀ  
LOW,ꢀtheꢀnextꢀinternalꢀpositiveꢀclockꢀedgeꢀisꢀsuspended.ꢀ  
Any command or data present on the input pins at the time  
Clock Suspend During WRITE Burst  
T0  
T1  
T2  
T3  
T4  
T5  
CLK  
CKE  
INTERNAL  
CLOCK  
COMMAND  
ADDRESS  
DQ  
NOP  
WRITE  
NOP  
NOP  
BANK a,  
COL n  
DIN  
n
DIN n+1  
DIN n+2  
DON'T CARE  
Clock Suspend During READ Burst  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
CLK  
CKE  
INTERNAL  
CLOCK  
COMMAND  
ADDRESS  
DQ  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
BANK a,  
COL n  
DOUT  
n
D
OUT n+1  
DOUT n+2  
DOUT n+3  
DON'T CARE  
32  
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IS42S16400E  
BURST READ/SINGLE WRITE  
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ  
the write burst mode bit (M9) in the mode register to a logic  
1. In this mode, all WRITE commands result in the access  
ofꢀaꢀsingleꢀcolumnꢀlocationꢀ(burstꢀofꢀone),ꢀregardlessꢀofꢀ  
theꢀprogrammedꢀburstꢀlength.ꢀREADꢀcommandsꢀaccess  
columns according to the programmed burst length and  
sequence,ꢀjustꢀasꢀinꢀtheꢀnormalꢀmodeꢀofꢀoperationꢀ(M9ꢀ  
=ꢀ0).  
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ  
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ  
occurs are defined below.  
READ with Auto Precharge  
1.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ  
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀn,ꢀ  
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ  
beginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.  
CONCURRENT AUTO PRECHARGE  
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ  
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ  
whenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀtwoꢀclocksꢀpriorꢀ  
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ  
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ  
bank m is registered.  
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ  
while an access command with auto precharge enabled is  
executingꢀisꢀnotꢀallowedꢀbyꢀSDRAMs,ꢀunlessꢀtheꢀSDRAMꢀ  
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSI  
Fig CAP 1 - READ With Auto Precharge interrupted by a READ  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
READ - AP  
BANK n  
READ - AP  
BANK m  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Idle  
COMMAND  
BANK n  
Page Active  
READ with Burst of 4  
Page Active  
Interrupt Burst, Precharge  
t
RP - BANK n  
tRP - BANK m  
Internal States  
BANK m  
READ with Burst of 4  
Precharge  
BANK n,  
COL a  
BANK m,  
COL b  
ADDRESS  
DQ  
D
OUT  
a
DOUT a+1  
DOUT  
b
DOUT b+1  
CAS Latency - 3 (BANK n)  
CAS Latency - 3 (BANK m)  
DON'T CARE  
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
WRITE - AP  
BANK n  
WRITE - AP  
BANK m  
COMMAND  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Idle  
BANK n  
READ with Burst of 4  
Page Active  
Interrupt Burst, Precharge  
Page Active  
tRP - BANK n  
tRP - BANK m  
Internal States  
BANK m  
WRITE with Burst of 4  
Write-Back  
BANK n,  
COL a  
BANK m,  
COL b  
ADDRESS  
DQM  
DQ  
D
OUT  
a
DIN  
b
DIN b+1  
DIN b+2  
DIN b+3  
CAS Latency - 3 (BANK n)  
DON'T CARE  
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33  
Rev. C  
08/07/09  
IS42S16400E  
WRITE with Auto Precharge  
4.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ  
WRITE tobankmwillinterruptaWRITE onbanknwhen  
3.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ  
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀ  
whenꢀregistered,ꢀwithꢀtheꢀdata-outꢀappearingꢀCASlatency  
later.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtw r  
is met, where tw r ꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀ  
registered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀ  
registeredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.  
A
registered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀ  
tw r is met, where tw r ꢀbeginsꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀ  
mꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀdataꢀWRITEꢀtoꢀbankꢀnꢀ  
willꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀaꢀWRITEꢀtoꢀ  
bank m.  
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
BANK n  
WRITE - AP  
BANK n  
READ - AP  
BANK m  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Page Active  
WRITE with Burst of 4 Interrupt Burst, Write-Back  
WR - BANK n  
Precharge  
t
tRP - BANK n  
Internal States  
tRP - BANK m  
BANK m  
Page Active  
READ with Burst of 4  
Precharge  
BANK n,  
COL a  
BANK m,  
COL b  
ADDRESS  
DQ  
DIN  
a
DIN a+1  
DOUT  
b
DOUT b+1  
CAS Latency - 3 (BANK m)  
DON'T CARE  
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
CLK  
COMMAND  
BANK n  
WRITE - AP  
BANK n  
WRITE - AP  
BANK m  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Page Active  
WRITE with Burst of 4  
Interrupt Burst, Write-Back  
WR - BANK n  
Precharge  
t
t
RP - BANK n  
Internal States  
tRP - BANK m  
BANK m  
Page Active  
WRITE with Burst of 4  
Write-Back  
BANK n,  
COL a  
BANK m,  
COL b  
ADDRESS  
DQ  
DIN  
a
DIN a+1  
DIN a+2  
D
IN  
b
DIN b+1  
DIN b+2  
DIN b+3  
DON'T CARE  
34  
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Rev. C  
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IS42S16400E  
INITIALIꢀE AND LOAD MODE REGISTER(1)  
T0  
T1  
Tn+1  
To+1  
t
CL  
Tp+1  
Tp+2  
Tp+3  
tCK  
t
CH  
CLK  
CKE  
tCKS t  
CKH  
t
CMH  
tCMS  
t
CMH  
tCMS  
tCMH tCMS  
AUTO  
REFRESH  
AUTO  
Load MODE  
REGISTER  
COMMAND  
NOP  
PRECHARGE  
NOP  
NOP  
NOP  
ACTIVE  
REFRESH  
DQM/  
DQML, DQMH  
t
t
AS  
tAH  
A0-A9, A11  
A10  
ROW  
ROW  
BANK  
CODE  
AS  
tAH  
ALL BANKS  
CODE  
SINGLE BANK  
ALL BANKS  
BA0, BA1  
DQ  
t
RP  
t
RC  
t
RC  
tMRD  
T
Power-up: VCC  
Precharge AUTO REFRESH  
AUTO REFRESH  
Program MODE REGISTER(2, 3, 4)  
and CLK stable all banks  
At least 2 Auto-Refresh Commands  
DON'T CARE  
T = 100µs Min.  
Notes:  
1. If CSꢀisꢀHighꢀatꢀclockꢀHighꢀtime,ꢀallꢀcommandsꢀappliedꢀareꢀNOP.  
2.ꢀꢀTheꢀModeꢀregisterꢀmayꢀbeꢀloadedꢀpriorꢀtoꢀtheꢀAuto-Refreshꢀcyclesꢀifꢀdesired.  
3.ꢀꢀJEDECꢀandꢀPC100ꢀspecifyꢀthreeꢀclocks.  
4.ꢀꢀOutputsꢀareꢀguaranteedꢀHigh-Zꢀafterꢀtheꢀcommandꢀisꢀissued.  
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IS42S16400E  
POWER-DOWN MODE CYCLE  
T0  
T1  
T2  
Tn+1  
Tn+2  
tCK  
t
CL  
t
CH  
CLK  
t
CKS  
t
CKH  
t
CKS  
tCKS  
CKE  
tCMS  
tCMH  
COMMAND  
PRECHARGE  
NOP  
NOP  
NOP  
ACTIVE  
DQM/  
DQML, DQMH  
A0-A9, A11  
A10  
ROW  
ROW  
ALL BANKS  
SINGLE BANK  
tAS  
tAH  
BA0, BA1  
DQ  
BANK  
BANK  
High-Z  
Two clock cycles  
Input buffers gated  
All banks idle  
off while in  
power-down mode  
Precharge all  
active banks  
All banks idle, enter  
power-down mode  
DON'T CARE  
Exit power-down mode  
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3  
36  
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Rev. C  
08/07/09  
IS42S16400E  
CLOCK SUSPEND MODE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
t
CK  
tCL  
tCH  
CLK  
CKE  
tCKS  
t
CKH  
t
CKS  
t
CKH  
t
CMS  
tCMH  
COMMAND  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
WRITE  
NOP  
t
CMS tCMH  
DQM/  
DQML, DQMH  
tAS  
tAH  
COLUMN n(2)  
A0-A9, A11  
A10  
COLUMN m(2)  
tAS  
t
AH  
tAS  
t
AH  
BA0, BA1  
BANK  
BANK  
tDS  
tDH  
tAC  
t
AC  
tHZ  
DQ  
D
OUT  
m
DOUT m+1  
DOUT e  
D
OUT e+1  
tLZ  
tOH  
DON'T CARE  
UNDEFINED  
Notes:  
1. CASꢀꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
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Rev. C  
08/07/09  
IS42S16400E  
AUTO-REFRESH CYCLE  
T0  
T1  
T2  
Tn+1  
To+1  
tCK  
t
CL  
t
CH  
CLK  
t
CKS CKH  
t
CKE  
t
CMS  
tCMH  
Auto  
Refresh  
Auto  
COMMAND  
PRECHARGE  
NOP  
NOP  
NOP  
ACTIVE  
Refresh  
DQM/  
DQML, DQMH  
A0-A9, A11  
A10  
ROW  
ROW  
BANK  
ALL BANKS  
SINGLE BANK  
BANK(s)  
BA0, BA1  
DQ  
tAS  
tAH  
High-Z  
t
RP  
t
RC  
t
RC  
DON'T CARE  
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3  
38  
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Rev. C  
08/07/09  
IS42S16400E  
SELF-REFRESH CYCLE  
T0  
T1  
T2  
Tn+1  
To+1  
To+2  
t
CK  
tCH  
t
CL  
CLK  
CKE  
t
CKS  
t
CKH  
t
CKS  
≥ tRAS  
t
CKS  
tCMS  
tCMH  
Auto  
Auto  
COMMAND  
PRECHARGE  
NOP  
NOP  
NOP  
Refresh  
Refresh  
DQM/  
DQML, DQMH  
A0-A9, A11  
A10  
ALL BANKS  
SINGLE BANK  
t
AS  
tAH  
BA0, BA1  
DQ  
BANK  
High-Z  
tXSR  
tRP  
Precharge all  
active banks  
Enter self  
refresh mode  
CLK stable prior to exiting  
self refresh mode  
Exit self refresh mode  
(Restart refresh time base)  
DON'T CARE  
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3  
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Rev. C  
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IS42S16400E  
READ WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
t
CL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
NOP  
PRECHARGE  
ALL BANKS  
NOP  
ACTIVE  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
t
AH  
ROW  
AS  
t
AH  
DISABLE AUTO PRECHARGE  
SINGLE BANK  
BANK  
BA0, BA1  
DQ  
BANK  
BANK  
t
AC  
t
AC  
tAC  
tAC  
tHZ  
DOUT  
m
D
OUT m+1  
D
OUT m+2  
D
OUT m+3  
t
LZ  
tOH  
tOH  
tOH  
tOH  
tRCD  
tRAS  
t
RC  
CAS Latency  
DON'T CARE  
t
RP  
UNDEFINED  
Notes:  
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
40  
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IS42S16400E  
READ WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
tCL  
tCH  
CLK  
CKE  
t
CKS tCKH  
tCMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
t
AH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
t
AH  
BA0, BA1  
DQ  
BANK  
BANK  
tAC  
t
AC  
t
AC  
t
AC  
tHZ  
D
OUT  
m
D
OUT m+1  
D
OUT m+2  
D
OUT m+3  
t
LZ  
t
OH  
t
OH  
tOH  
tOH  
tRCD  
tRAS  
t
RC  
CAS Latency  
DON'T CARE  
tRP  
UNDEFINED  
Notes:  
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
41  
Rev. C  
08/07/09  
IS42S16400E  
SINGLE READ WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
PRECHARGE  
NOP  
ACTIVE  
NOP  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
t
AH  
ALL BANKS  
ROW  
SINGLE BANK  
BANK  
AS  
t
AH  
DISABLE AUTO PRECHARGE  
BA0, BA1  
DQ  
BANK  
BANK  
t
OH  
tAC  
D
OUT m  
t
LZ  
tHZ  
DON'T CARE  
UNDEFINED  
tRCD  
tRAS  
t
RC  
CAS Latency  
tRP  
Notes:  
1. CAS latency = 2, burst length = 1  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
42  
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
SINGLE READ WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
NOP  
NOP  
READ  
NOP  
NOP  
ACTIVE  
NOP  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
ROW  
ROW  
BANK  
AS  
t
AH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
t
AH  
BA0, BA1  
BANK  
BANK  
tOH  
tAC  
DOUT m  
DQ  
t
HZ  
DON'T CARE  
UNDEFINED  
tRCD  
tRAS  
t
RC  
CAS Latency  
tRP  
Notes:  
1. CAS latency = 2, burst length = 1  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
43  
Rev. C  
08/07/09  
IS42S16400E  
ALTERNATING BANK READ ACCESSES  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
tCK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
tCMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
ACTIVE  
NOP  
READ  
NOP  
ACTIVE  
tCMS tCMH  
DQM/  
DQML, DQMH  
tAS tAH  
COLUMN m(2)  
ROW  
ROW  
COLUMN b(2)  
ROW  
ROW  
A0-A9, A11  
A10  
ROW  
tAS tAH  
ENABLE AUTO PRECHARGE  
ENABLE AUTO PRECHARGE  
ROW  
tAS tAH  
BANK 0  
BANK 3  
BANK 3  
BANK 0  
BA0, BA1  
BANK 0  
t
LZ  
t
OH  
t
OH  
tOH  
tOH  
t
OH  
DQ  
D
OUT  
m
D
OUT m+  
1
D
OUT m+  
2
D
OUT m+  
3
D
OUT  
b
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tRCD - BANK 0  
tRRD  
CAS Latency - BANK 0  
tRP - BANK 0  
tRCD - BANK 0  
tRCD - BANK 3  
CAS Latency - BANK 3  
tRAS - BANK 0  
tRC - BANK 0  
DON'T CARE  
Notes:  
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
44  
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
READ - FULL-PAGE BURST  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
Tn+1  
Tn+2  
Tn+3  
Tn+4  
t
CK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
t
CMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
CMS CMH  
NOP  
NOP  
NOP  
NOP  
NOP  
BURST TERM  
NOP  
NOP  
t
t
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
AS  
t
AH  
ROW  
AS  
t
AH  
BA0, BA1  
BANK  
BANK  
tAC  
tAC  
tAC  
tAC  
tAC  
tAC  
tHZ  
D
OUT  
m
D
OUT m+  
1
D
OUT m+  
2
D
OUT m-  
1
D
OUT  
m
D
OUT m+1  
DQ  
t
LZ  
t
OH  
tOH  
t
OH  
tOH  
t
OH  
tOH  
tRCD  
CAS Latency  
each row (x4) has  
1,024 locations  
DON'T CARE  
UNDEFINED  
Full page Full-page burst not self-terminating.  
completion Use BURST TERMINATE command.  
Notes:  
1. CAS latency = 2, burst length = full page  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
45  
Rev. C  
08/07/09  
IS42S16400E  
READ - DQM OPERATION  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
t
CK  
t
CL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS tCMH  
COMMAND  
ACTIVE  
NOP  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ROW  
DISABLE AUTO PRECHARGE  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
t
OH  
tOH  
tOH  
t
AC  
tAC  
D
OUT  
m
D
OUT m+  
2
D
OUT m+  
3
DQ  
t
LZ  
tLZ  
t
HZ  
tAC  
t
HZ  
DON'T CARE  
UNDEFINED  
t
RCD  
CAS Latency  
Notes:  
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
46  
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
WRITE - WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
t
CK  
t
CL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
PRECHARGE  
NOP  
ACTIVE  
t
CMS tCMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
ROW  
ROW  
BANK  
A0-A9, A11  
A10  
ROW  
AS  
t
AH  
ALL BANKS  
ROW  
AS  
t
AH  
SINGLE BANK  
BANK  
DISABLE AUTO PRECHARGE  
BANK  
BA0, BA1  
BANK  
tDS  
t
DH  
t
DS  
t
DH  
t
DS  
tDH  
tDS  
tDH  
DQ  
DIN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+3  
tRCD  
tRAS  
t
RC  
t
WR(3)  
t
RP  
DON'T CARE  
Notes:  
1. burstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
3.ꢀtr a s must not be violated  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
47  
Rev. C  
08/07/09  
IS42S16400E  
WRITE - WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
t
CK  
tCL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
ACTIVE  
t
CMS tCMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
ROW  
ROW  
BANK  
A0-A9, A11  
A10  
ROW  
AS  
t
AH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
t
AH  
BA0, BA1  
BANK  
BANK  
tDS  
t
DH  
t
DS  
t
DH  
t
DS  
tDH  
t
DS  
tDH  
DQ  
DIN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+3  
tRCD  
tRAS  
t
RC  
t
WR  
tRP  
DON'T CARE  
Notes:  
1. burstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
48  
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
SINGLE WRITE - WITHOUT AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
t
CK  
tCL  
tCH  
CLK  
CKE  
tCKS tCKH  
t
CMS tCMH  
NOP(4)  
NOP(4)  
PRECHARGE  
NOP  
ACTIVE  
NOP  
COMMAND  
ACTIVE  
NOP  
WRITE  
tCMS tCMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
ROW  
A0-A9, A11  
A10  
ROW  
AS  
t
AH  
ALL BANKS  
ROW  
ROW  
SINGLE BANK  
AS  
t
AH  
DISABLE AUTO PRECHARGE  
BANK  
BA0, BA1  
BANK  
BANK  
BANK  
t
DS  
t
DH  
DQ  
DIN  
m
t
t
t
RCD  
RAS  
RC  
t
WR(3)  
tRP  
DON'T CARE  
Notes:  
1. burst length = 1  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
3.ꢀtr a s must not be violated  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
49  
Rev. C  
08/07/09  
IS42S16400E  
SINGLE WRITE - WITH AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
t
CK  
tCL  
tCH  
CLK  
CKE  
t
CKS tCKH  
t
CMS tCMH  
NOP(3)  
NOP(3)  
NOP(3)  
WRITE  
NOP  
NOP  
NOP  
ACTIVE  
NOP  
COMMAND  
ACTIVE  
tCMS tCMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
ROW  
ROW  
BANK  
A0-A9, A11  
A10  
ROW  
AS  
t
AH  
ENABLE AUTO PRECHARGE  
ROW  
AS  
t
AH  
BA0, BA1  
BANK  
BANK  
tDS  
t
DH  
DQ  
DIN  
m
tRCD  
tRAS  
t
RC  
t
WR  
tRP  
DON'T CARE  
Notes:  
1. burst length = 1  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
50  
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
ALTERNATING BANK WRITE ACCESS  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
tCK  
tCL  
tCH  
CLK  
CKE  
t
CKS tCKH  
tCMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
ACTIVE  
t
CMS tCMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
tAH  
COLUMN m(2)  
ROW  
ROW  
COLUMN b(2)  
ROW  
ROW  
A0-A9, A11  
A10  
ROW  
AS  
t
AH  
ENABLE AUTO PRECHARGE  
ENABLE AUTO PRECHARGE  
ROW  
AS  
tAH  
BANK 0  
BANK 1  
BANK 1  
BANK 0  
BA0, BA1  
BANK 0  
tDS  
t
DH  
t
DS  
t
DH  
tDS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
tDS  
t
DH  
tDS  
tDH  
t
DS  
tDH  
DQ  
DIN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+  
3
D
IN  
b
D
IN b+  
1
D
IN b+  
2
DIN b+3  
t
t
t
t
RCD - BANK 0  
RRD  
t
WR - BANK 0  
t
RP - BANK 0  
t
RCD - BANK 0  
t
RCD - BANK 1  
tWR - BANK 1  
RAS - BANK 0  
RC - BANK 0  
DON'T CARE  
Notes:  
1. burstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
51  
Rev. C  
08/07/09  
IS42S16400E  
WRITE - FULL PAGE BURST  
T0  
T1  
T2  
T3  
T4  
T5  
Tn+1  
Tn+2  
t
CK  
t
CL  
tCH  
CLK  
CKE  
t
CKS CKH  
t
t
CMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
NOP  
BURST TERM  
NOP  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
t
AH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ROW  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
t
DS  
t
DH  
t
DS  
t
DH  
tDS  
t
DH  
tDS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
D
IN  
m
D
IN m+  
1
D
IN m+  
2
D
IN m+  
3
DIN m-1  
DQ  
t
RCD  
Full page completed  
DON'T CARE  
Notes:  
1. burst length = full page  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
52  
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
WRITE - DQM OPERATION  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
t
CK  
t
CL  
tCH  
CLK  
CKE  
t
CKS CKH  
t
tCMS  
tCMH  
COMMAND  
ACTIVE  
NOP  
WRITE  
NOP  
NOP  
NOP  
NOP  
NOP  
t
CMS  
t
CMH  
DQM/  
DQML, DQMH  
t
t
t
AS  
t
AH  
COLUMN m(2)  
A0-A9, A11  
A10  
ROW  
AS  
tAH  
ENABLE AUTO PRECHARGE  
ROW  
DISABLE AUTO PRECHARGE  
AS  
tAH  
BA0, BA1  
BANK  
BANK  
t
DS  
t
DH  
t
DS  
t
DH  
t
DS  
t
DH  
D
IN  
m
D
IN m+  
2
DIN m+3  
DQ  
t
RCD  
DON'T CARE  
Notes:  
1. burstꢀlengthꢀ=ꢀ4  
2. A8, A9, and A11ꢀ=ꢀ"Don'tꢀCare"  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
53  
Rev. C  
08/07/09  
IS42S16400E  
ORDERING INFORMATION  
Commercial Range: 0°C to +70°C  
Frequency  
ꢀ166ꢀMHzꢀ  
ꢀ166ꢀMHzꢀ  
ꢀ143ꢀMHzꢀ  
ꢀ143ꢀMHzꢀ  
Speed (ns)  
Order Part No.  
Package  
6ꢀ  
6ꢀ  
7ꢀ  
7ꢀ  
IS42S16400E-6Tꢀ  
IS42S16400E-6TLꢀ  
IS42S16400E-7Tꢀ  
IS42S16400E-7TLꢀ  
400-milꢀTSOPꢀII  
400-milꢀTSOPꢀII,ꢀLead-free  
400-milꢀTSOPꢀII  
400-milꢀTSOPꢀII,ꢀLead-freeꢀ  
Industrial Range: -40°C to +85°C  
Frequency  
ꢀ166ꢀMHzꢀ  
ꢀ143ꢀMHzꢀ  
Speed (ns)  
Order Part No.  
Package  
6ꢀ  
7ꢀ  
IS42S16400E-6TLIꢀ  
IS42S16400E-7TLIꢀ  
400-milꢀTSOPꢀII,ꢀLead-free  
400-milꢀTSOPꢀII,ꢀLead-freeꢀ  
54  
www.issi.com — Integrated Silicon Solution, Inc.  
Rev. C  
08/07/09  
IS42S16400E  
Integrated Silicon Solution, Inc. — www.issi.comꢀ  
55  
Rev. C  
08/07/09  

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