IS42S16400F-5BLI [ISSI]
Synchronous DRAM, 4MX16, 5ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-54;
| 型号： | IS42S16400F-5BLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Synchronous DRAM, 4MX16, 5ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-54 时钟 动态存储器 内存集成电路 |
| 文件： | 总59页 (文件大小：1324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS42S16400F
IS45S16400F
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
DECEMBER 2011
FEATURES
OVERVIEW
ISSI'sꢀ64MbꢀSynchronousꢀDRAMꢀisꢀorganizedꢀasꢀ1,048,576ꢀ
bitsꢀ xꢀ 16-bitꢀ xꢀ 4-bankꢀ forꢀ improvedꢀ performance.ꢀ Theꢀ
synchronousꢀ DRAMsꢀ achieveꢀ high-speedꢀ dataꢀ transferꢀ
usingꢀpipelineꢀarchitecture.ꢀAllꢀinputsꢀandꢀoutputsꢀsignalsꢀ
referꢀtoꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.
•ꢀ Clockꢀfrequency:ꢀ200,ꢀ166,ꢀ143,ꢀ133ꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positiveꢀclockꢀedge
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Singleꢀ3.3Vꢀpowerꢀsupply
•ꢀ LVTTLꢀinterface
•ꢀ Programmableꢀburstꢀlengthꢀꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
KEY TIMING PARAMETERS
•ꢀ Programmableꢀburstꢀsequence:ꢀꢀ
Sequential/Interleave
Parameter
-5
-6
-7
Unit
ClkꢀCycleꢀTimeꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
5ꢀ
7.5ꢀ
ꢀ
6ꢀ
7.5ꢀ
ꢀ
7ꢀ
7.5ꢀ
ꢀ
nsꢀ
ns
•ꢀ Selfꢀrefreshꢀmodes
•ꢀ Autoꢀrefreshꢀ(CBR)
ClkꢀFrequencyꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
200ꢀ
133ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ64ꢀmsꢀ(Com,ꢀInd,ꢀA1ꢀ
grade)ꢀorꢀ16msꢀ(A2ꢀgrade)
166ꢀ
133ꢀ
143ꢀ
133ꢀ
Mhzꢀ
Mhz
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
AccessꢀTimeꢀꢀfromꢀClockꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
5ꢀ
6ꢀ
ꢀ
ꢀ
ꢀ
5.4ꢀ
6ꢀ
5.4ꢀ
6ꢀ
nsꢀ
ns
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀꢀ
operationsꢀcapability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
command
ADDRESS TABLE
OPTIONS
Parameter
4M x 16
•ꢀ Package:ꢀꢀ
Configuration
1M x 16 x 4
banks
54-pinꢀTSOPꢀIIꢀ
54-ballꢀFBGAꢀ(8mmꢀxꢀ8mm)
Refresh Count
•ꢀ OperatingꢀTemperatureꢀRangeꢀ
Commercialꢀ(0oCꢀtoꢀ+70oC)
Industrialꢀ(-40oCꢀtoꢀ+85oC)
AutomotiveꢀGradeꢀA1ꢀ(-40oCꢀtoꢀ+85oC)
AutomotiveꢀGradeꢀA2ꢀ(-40oCꢀtoꢀ+105oC)
ꢀ
Com./Ind. 4K/64ms
A1 4K/64ms
A2 4K/16ms
Row Addresses
A0-A11
Column Addresses
Bank Address Pins
Auto Precharge Pins
A0-A7
BA0, BA1
A10/AP
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀ
liabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀ
anyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreasonablyꢀbeꢀex-
pectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀunlessꢀIntegratedꢀSiliconꢀ
Solution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
1
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
GENERAL DESCRIPTION
Theꢀ 64Mbꢀ SDRAMꢀ isꢀ aꢀ highꢀ speedꢀ CMOS,ꢀ dynamicꢀ
random-accessꢀ memoryꢀ designedꢀ toꢀ operateꢀ inꢀ 3.3Vꢀ
memoryꢀsystemsꢀcontainingꢀ67,108,864ꢀbits.ꢀꢀInternallyꢀ
configuredꢀasꢀaꢀquad-bankꢀDRAMꢀwithꢀaꢀsynchronousꢀ
interface.ꢀꢀEachꢀ16,777,216-bitꢀbankꢀisꢀorganizedꢀasꢀ4,096ꢀ
rowsꢀbyꢀ256ꢀcolumnsꢀbyꢀ16ꢀbits.
otherꢀthreeꢀbanksꢀwillꢀhideꢀtheꢀprechargeꢀcyclesꢀandꢀprovideꢀ
seamless,ꢀhigh-speed,ꢀrandom-accessꢀoperation.
SDRAMꢀreadꢀandꢀwriteꢀaccessesꢀareꢀburstꢀorientedꢀstartingꢀ
atꢀaꢀselectedꢀlocationꢀandꢀcontinuingꢀforꢀaꢀprogrammedꢀ
numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ sequence.ꢀ ꢀTheꢀ
registrationꢀ ofꢀ anꢀ ACTIVEꢀ commandꢀ beginsꢀ accesses,ꢀ
followedꢀbyꢀaꢀREADꢀorꢀWRITEꢀcommand.ꢀTheꢀACTIVEꢀ
commandꢀinꢀconjunctionꢀwithꢀaddressꢀbitsꢀregisteredꢀareꢀ
usedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀbeꢀaccessedꢀ(BA0,ꢀ
BA1ꢀselectꢀtheꢀbank;ꢀA0-A11ꢀselectꢀtheꢀrow).ꢀꢀTheꢀREADꢀ
orꢀWRITEꢀ commandsꢀ inꢀ conjunctionꢀ withꢀ addressꢀ bitsꢀ
registeredꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀcolumnꢀlocationꢀ
forꢀtheꢀburstꢀaccess.
Theꢀ64MbꢀSDRAMꢀincludesꢀanꢀAUTOꢀREFRESHꢀMODE,ꢀ
andꢀaꢀpower-saving,ꢀpower-downꢀmode.ꢀAllꢀsignalsꢀareꢀ
registeredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀtheꢀclockꢀsignal,ꢀCLK.ꢀ
AllꢀinputsꢀandꢀoutputsꢀareꢀLVTTLꢀcompatible.
Theꢀ64MbꢀSDRAMꢀhasꢀtheꢀabilityꢀtoꢀsynchronouslyꢀburstꢀ
dataꢀatꢀaꢀhighꢀdataꢀrateꢀwithꢀautomaticꢀcolumn-addressꢀ
generation,ꢀtheꢀabilityꢀtoꢀinterleaveꢀbetweenꢀinternalꢀbanksꢀ
toꢀ hideꢀ prechargeꢀ timeꢀ andꢀ theꢀ capabilityꢀ toꢀ randomlyꢀ
changeꢀ columnꢀ addressesꢀ onꢀ eachꢀ clockꢀ cycleꢀ duringꢀ
burstꢀaccess.
ProgrammableꢀREADꢀorꢀWRITEꢀburstꢀlengthsꢀconsistꢀofꢀ
1,ꢀ2,ꢀ4ꢀandꢀ8ꢀlocations,ꢀorꢀfullꢀpage,ꢀwithꢀaꢀburstꢀterminateꢀ
option.ꢀ
Aꢀself-timedꢀrowꢀprechargeꢀinitiatedꢀatꢀtheꢀendꢀofꢀtheꢀburstꢀ
sequenceꢀisꢀavailableꢀwithꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀ
enabled.ꢀ Prechargeꢀoneꢀbankꢀwhileꢀaccessingꢀoneꢀofꢀtheꢀ
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
DQM
DATA IN
BUFFER
COMMAND
DECODER
&
CLOCK
GENERATOR
16
16
REFRESH
CONTROLLER
MODE
REGISTER
DQ 0-15
A10
12
V
DD/VDDQ
SELF
DATA OUT
BUFFER
REFRESH
GND/GNDQ
A11
CONTROLLER
16
16
A9
A8
A7
A6
REFRESH
COUNTER
A5
A4
4096
A3
A2
A1
A0
BA0
BA1
4096
MEMORY CELL
ARRAY
4096
4096
12
BANK 0
ROW
ADDRESS
LATCH
ROW
ADDRESS
BUFFER
12
12
SENSE AMP I/O GATE
256K
(x 16)
COLUMN
ADDRESS LATCH
BANK CONTROL LOGIC
8
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
PIN CONFIGURATION
PACKAꢀꢁ Cꢂꢃꢁ: B 54 BALL ꢄBꢀA (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
GND DQ15 GNDQ
DQ14 DQ13 VDDQ
DQ12 DQ11 GNDQ
DQ10 DQ9 VDDQ
VDDQ DQ0 VDD
GNDQ DQ2 DQ1
VDDQ DQ4 DQ3
GNDQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
B
C
D
E
F
DQ8
NC GND
DQMH CLK CKE
G
H
J
NC
A8
A11
A7
A9
A6
A4
BA0 BA1
CS
A10
VDD
A0
A3
A1
A2
GND
A5
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
ꢃQ0 to ꢃQ15
CLK
Row Address Input
Column Address Input
Bank Select Addresses
ꢃata I/ꢂ
WE
Write ꢁnable
LꢃQM, UꢃQM
Vdd
x16 Input/ꢂutput Mask
Power
ꢀNꢃ
ꢀround
System Clock Input
Clock ꢁnable
Vddq
Power Supply for I/ꢂ Pin
ꢀround for I/ꢂ Pin
No Connection
CKꢁ
ꢀNꢃQ
NC
CS
Chip Select
RAS
Row Address Strobe Command
CASꢀ
ꢀ
Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.comꢀ
3
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
PIN CONFIGURATIONS
54 pin TSOP - Type II
V
DD
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ0
2
DQ15
GNDQ
DQ14
DQ13
V
DD
Q
3
DQ1
DQ2
4
5
GNDQ
DQ3
6
VDDQ
7
DQ12
DQ11
GNDQ
DQ10
DQ9
DQ4
8
V
DD
Q
9
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
GNDQ
DQ7
VDDQ
DQ8
GND
NC
VDD
LDQM
WE
CAS
RAS
CS
UDQM
CLK
CKE
NC
BA0
BA1
A10
A0
A11
A9
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
GND
PIN DESCRIPTIONS
A0-A11ꢀ ꢀ
RowꢀAddressꢀInput
WEꢀ
WriteꢀEnable
A0-A7ꢀ
ꢀ
ColumnꢀAddressꢀInput
BankꢀSelectꢀAddress
DataꢀI/O
LDQMꢀ x16ꢀLowerꢀByte,ꢀInput/OutputꢀMask
UDQMꢀ x16ꢀUpperꢀByte,ꢀInput/OutputꢀMask
BA0,ꢀBA1ꢀ
DQ0ꢀtoꢀDQ15ꢀ
Vddꢀ
Power
CLKꢀ
CKEꢀ
CSꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
SystemꢀClockꢀInput
ClockꢀEnable
GNDꢀ
Vddqꢀ
Ground
PowerꢀSupplyꢀforꢀI/OꢀPin
ChipꢀSelect
GNDqꢀ GroundꢀforꢀI/OꢀPin
NCꢀ NoꢀConnection
RASꢀ
CASꢀ
RowꢀAddressꢀStrobeꢀCommand
ColumnꢀAddressꢀStrobeꢀCommand
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
PIN FUNCTIONS
Symbol
TSOP Pin No.
23ꢀtoꢀ26ꢀ
29ꢀtoꢀ34
22,ꢀ35
Type
Function (In Detail)
ꢀ
ꢀ
ꢀ
A0-A11ꢀ
InputꢀPin
ꢀ
AddressꢀInputs:ꢀA0-A11ꢀareꢀsampledꢀduringꢀtheꢀACTIVE
commandꢀ(row-addressꢀA0-A11)ꢀandꢀREAD/WRITEꢀcommandꢀ(A0-A7
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
withꢀA10ꢀdefiningꢀautoꢀprecharge)ꢀtoꢀselectꢀoneꢀlocationꢀoutꢀofꢀtheꢀmemoryꢀarray
inꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀcommandꢀtoꢀdeter-
mineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀselectedꢀbyꢀ
BA0,ꢀBA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀLOADꢀ
MODEꢀREGISTERꢀcommand.
ꢀ
ꢀ
ꢀ
BA0,ꢀBA1
ꢀ
20,ꢀ21ꢀ
17ꢀ
InputꢀPin
InputꢀPin
InputꢀPin
ꢀ
ꢀ
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
CASꢀ
CAS,ꢀinꢀconjunctionꢀwithꢀtheꢀRASꢀandꢀꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
CKEꢀ
37ꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ
refreshꢀmode.ꢀCKEꢀisꢀanꢀasynchronousꢀinput.
ꢀ
ꢀ
CLKꢀ
38ꢀ
19ꢀ
InputꢀPin
ꢀ
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ
areꢀacquiredꢀinꢀsynchronizationꢀwithꢀtheꢀrisingꢀedgeꢀofꢀthisꢀpin.
CSꢀ
InputꢀPin
TheꢀCSꢀinputꢀdeterminesꢀwhetherꢀcommandꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀ
CommandꢀinputꢀisꢀenabledꢀwhenꢀCSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ
deviceꢀremainsꢀinꢀtheꢀpreviousꢀstateꢀwhenꢀCSꢀisꢀHIGH.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DQ0ꢀtoꢀ
DQ15ꢀ
ꢀ
2,ꢀ4,ꢀ5,ꢀ7,ꢀ8,ꢀ10,ꢀ
11,13,ꢀ42,ꢀ44,ꢀ45,
47,ꢀ48,ꢀ50,ꢀ51,ꢀ53
15,ꢀ39ꢀ
DQꢀPin
ꢀ
ꢀ
DQ0ꢀtoꢀDQ15ꢀareꢀI/Oꢀpins.ꢀI/Oꢀthroughꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀinꢀbyteꢀunits
usingꢀtheꢀLDQMꢀandꢀUDQMꢀpins.
ꢀ
LDQM,ꢀ
UDQMꢀ
InputꢀPin
ꢀ
LDQMꢀandꢀUDQMꢀcontrolꢀtheꢀlowerꢀandꢀupperꢀbytesꢀofꢀtheꢀI/Oꢀbuffers.ꢀInꢀread
ꢀ
ꢀ
mode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀ
theꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀ
goꢀtoꢀtheꢀHIGHꢀimpedanceꢀstateꢀwhenꢀLDQM/UDQMꢀisꢀHIGH.ꢀThisꢀfunctionꢀcor-
respondsꢀtoꢀOEꢀinꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀLDQMꢀandꢀUDQMꢀcontrolꢀ
theꢀinputꢀbuffer.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀen-
abled,ꢀandꢀdataꢀcanꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀLDQMꢀorꢀUDQMꢀisꢀHIGH,ꢀinputꢀ
dataꢀisꢀmaskedꢀandꢀcannotꢀbeꢀwrittenꢀtoꢀtheꢀdevice.
ꢀ
ꢀ
RASꢀ
WEꢀ
18ꢀ
16ꢀ
InputꢀPin
ꢀ
RAS,ꢀinꢀconjunctionꢀwithꢀCASꢀandꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ"Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
ꢀInputꢀPin
ꢀ
WE,ꢀinꢀconjunctionꢀwithꢀRASꢀandꢀCAS,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ"Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddqꢀ
Vddꢀ
3,ꢀ9,ꢀ43,ꢀ49ꢀ
1,ꢀ14,ꢀ27ꢀ
PowerꢀSupplyꢀPin
PowerꢀSupplyꢀPin
PowerꢀSupplyꢀPin
PowerꢀSupplyꢀPin
ꢀ
ꢀ
ꢀ
ꢀ
Vddqꢀisꢀtheꢀoutputꢀbufferꢀpowerꢀsupply.
Vddꢀisꢀtheꢀdeviceꢀinternalꢀpowerꢀsupply.
GNdqꢀisꢀtheꢀoutputꢀbufferꢀground.
GNdꢀisꢀtheꢀdeviceꢀinternalꢀground.
GNdqꢀ
GNdꢀ
6,ꢀ12,ꢀ46,ꢀ52ꢀ
28,ꢀ41,ꢀ54ꢀ
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eitherꢀenabledꢀorꢀdisabled.ꢀAUTOꢀPRECHARGEꢀdoesꢀnotꢀ
applyꢀexceptꢀinꢀfull-pageꢀburstꢀmode.ꢀUponꢀcompletionꢀofꢀ
theꢀREADꢀorꢀWRITEꢀburst,ꢀaꢀprechargeꢀofꢀtheꢀbank/rowꢀ
thatꢀisꢀaddressedꢀisꢀautomaticallyꢀperformed.
READ
TheꢀREADꢀcommandꢀselectsꢀtheꢀbankꢀfromꢀBA0,ꢀBA1ꢀinputsꢀ
andꢀstartsꢀaꢀburstꢀreadꢀaccessꢀtoꢀanꢀactiveꢀrow.ꢀꢀInputsꢀ
A0-A7ꢀprovidesꢀtheꢀstartingꢀcolumnꢀlocation.ꢀꢀWhenꢀA10ꢀisꢀ
HIGH,ꢀthisꢀcommandꢀfunctionsꢀasꢀanꢀAUTOꢀPRECHARGEꢀ
command.ꢀꢀWhenꢀtheꢀautoꢀprechargeꢀisꢀselected,ꢀtheꢀrowꢀ
beingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀtheꢀREADꢀ
burst.ꢀTheꢀrowꢀwillꢀremainꢀopenꢀforꢀsubsequentꢀaccessesꢀ
whenꢀAUTOꢀPRECHARGEꢀisꢀnotꢀselected.ꢀꢀDQ’sꢀreadꢀ
dataꢀisꢀsubjectꢀtoꢀtheꢀlogicꢀlevelꢀonꢀtheꢀDQMꢀinputsꢀtwoꢀ
clocksꢀearlier.ꢀWhenꢀaꢀgivenꢀDQMꢀsignalꢀwasꢀregisteredꢀ
HIGH,ꢀtheꢀcorrespondingꢀDQ’sꢀwillꢀbeꢀHigh-Zꢀtwoꢀclocksꢀ
later.ꢀDQ’sꢀwillꢀprovideꢀvalidꢀdataꢀwhenꢀtheꢀDQMꢀsignalꢀ
wasꢀregisteredꢀLOW.
AUTO REFRESH COMMAND
ThisꢀcommandꢀexecutesꢀtheꢀAUTOꢀREFRESHꢀoperation.ꢀ
Theꢀrowꢀaddressꢀandꢀbankꢀtoꢀbeꢀrefreshedꢀareꢀautomaticallyꢀ
generatedꢀduringꢀthisꢀoperation.ꢀ Theꢀstipulatedꢀperiodꢀ(trc)ꢀisꢀ
requiredꢀforꢀaꢀsingleꢀrefreshꢀoperation,ꢀandꢀnoꢀotherꢀcom-
mandsꢀcanꢀbeꢀexecutedꢀduringꢀthisꢀperiod.ꢀ Thisꢀcommandꢀ
isꢀexecutedꢀatꢀleastꢀ4096ꢀtimesꢀeveryꢀTref.ꢀDuringꢀanꢀAUTOꢀ
REFRESHꢀcommand,ꢀaddressꢀbitsꢀareꢀ“Don’tꢀCare”.ꢀꢀThisꢀ
commandꢀcorrespondsꢀtoꢀCBRꢀAuto-refresh.
SELF REFRESH
WRITE
DuringꢀtheꢀSELFꢀREFRESHꢀoperation,ꢀtheꢀrowꢀaddressꢀtoꢀ
beꢀrefreshed,ꢀtheꢀbank,ꢀandꢀtheꢀrefreshꢀintervalꢀareꢀgen-
eratedꢀautomaticallyꢀinternally.ꢀꢀSELFꢀREFRESHꢀcanꢀbeꢀ
usedꢀtoꢀretainꢀdataꢀinꢀtheꢀSDRAMꢀwithoutꢀexternalꢀclocking,ꢀ
evenꢀifꢀtheꢀrestꢀofꢀtheꢀsystemꢀisꢀpoweredꢀdown.ꢀTheꢀSELFꢀ
REFRESHꢀoperationꢀisꢀstartedꢀbyꢀdroppingꢀtheꢀCKEꢀpinꢀ
fromꢀHIGHꢀtoꢀLOW.ꢀDuringꢀtheꢀSELFꢀREFRESHꢀoperationꢀ
allꢀotherꢀinputsꢀtoꢀtheꢀSDRAMꢀbecomeꢀ“Don’tꢀCare”.ꢀTheꢀ
deviceꢀmustꢀremainꢀinꢀselfꢀrefreshꢀmodeꢀforꢀaꢀminimumꢀ
periodꢀequalꢀtoꢀtrasꢀorꢀmayꢀremainꢀinꢀselfꢀrefreshꢀmodeꢀ
forꢀanꢀindefiniteꢀperiodꢀbeyondꢀthat.ꢀTheꢀSELF-REFRESHꢀ
operationꢀcontinuesꢀasꢀlongꢀasꢀtheꢀCKEꢀpinꢀremainsꢀLOWꢀ
andꢀthereꢀisꢀnoꢀneedꢀforꢀexternalꢀcontrolꢀofꢀanyꢀotherꢀpins.ꢀ
Theꢀnextꢀcommandꢀcannotꢀbeꢀexecutedꢀuntilꢀtheꢀdeviceꢀ
internalꢀ recoveryꢀ periodꢀ (trc)ꢀ hasꢀ elapsed.ꢀ Onceꢀ CKEꢀ
goesꢀHIGH,ꢀtheꢀNOPꢀcommandꢀmustꢀbeꢀissuedꢀ(minimumꢀ
ofꢀtwoꢀclocks)ꢀtoꢀprovideꢀ timeꢀforꢀtheꢀcompletionꢀofꢀanyꢀ
internalꢀrefreshꢀinꢀprogress.ꢀAfterꢀtheꢀself-refresh,ꢀsinceꢀitꢀ
isꢀimpossibleꢀtoꢀdetermineꢀtheꢀaddressꢀofꢀtheꢀlastꢀrowꢀtoꢀ
beꢀrefreshed,ꢀanꢀAUTO-REFRESHꢀshouldꢀimmediatelyꢀbeꢀ
performedꢀforꢀallꢀaddresses.
Aꢀburstꢀwriteꢀaccessꢀtoꢀanꢀactiveꢀrowꢀisꢀinitiatedꢀwithꢀtheꢀ
WRITEꢀcommand.ꢀꢀBA0,ꢀBA1ꢀinputsꢀselectsꢀtheꢀbank,ꢀ
andꢀ theꢀ startingꢀ columnꢀ locationꢀ isꢀ providedꢀ byꢀ inputsꢀ
A0-A7.ꢀWhetherꢀorꢀnotꢀAUTO-PRECHARGEꢀisꢀusedꢀisꢀ
determinedꢀbyꢀA10.
Theꢀrowꢀbeingꢀaccessedꢀwillꢀbeꢀprechargedꢀatꢀtheꢀendꢀofꢀ
theꢀWRITEꢀburst,ꢀifꢀAUTOꢀPRECHARGEꢀisꢀselected.ꢀIfꢀ
AUTOꢀPRECHARGEꢀisꢀnotꢀselected,ꢀtheꢀrowꢀwillꢀremainꢀ
openꢀforꢀsubsequentꢀaccesses.
Aꢀmemoryꢀarrayꢀisꢀwrittenꢀwithꢀcorrespondingꢀinputꢀdataꢀ
onꢀDQ’sꢀandꢀDQMꢀinputꢀlogicꢀlevelꢀappearingꢀatꢀtheꢀsameꢀ
time.ꢀꢀDataꢀwillꢀbeꢀwrittenꢀtoꢀmemoryꢀwhenꢀDQMꢀsignalꢀisꢀ
LOW.ꢀꢀWhenꢀDQMꢀisꢀHIGH,ꢀtheꢀcorrespondingꢀdataꢀinputsꢀ
willꢀbeꢀignored,ꢀandꢀaꢀWRITEꢀwillꢀnotꢀbeꢀexecutedꢀtoꢀthatꢀ
byte/columnꢀlocation.
PRECHARGE
TheꢀPRECHARGEꢀcommandꢀisꢀusedꢀtoꢀdeactivateꢀtheꢀ
openꢀrowꢀinꢀaꢀparticularꢀbankꢀorꢀtheꢀopenꢀrowꢀinꢀallꢀbanks.ꢀ
BA0,ꢀBA1ꢀcanꢀbeꢀusedꢀtoꢀselectꢀwhichꢀbankꢀisꢀprechargedꢀ
orꢀ theyꢀ areꢀ treatedꢀ asꢀ “Don’tꢀ Care”.ꢀ ꢀ A10ꢀ determinesꢀ
whetherꢀoneꢀorꢀallꢀbanksꢀareꢀprecharged.ꢀAfterꢀexecut-
ingꢀ thisꢀ command,ꢀ theꢀ nextꢀ commandꢀ forꢀ theꢀ selectedꢀ
bank(s)ꢀisꢀexecutedꢀafterꢀpassageꢀofꢀtheꢀperiodꢀtRP,ꢀwhichꢀ
isꢀtheꢀperiodꢀrequiredꢀforꢀbankꢀprecharging.ꢀꢀꢀOnceꢀaꢀbankꢀ
hasꢀbeenꢀprecharged,ꢀitꢀisꢀinꢀtheꢀidleꢀstateꢀandꢀmustꢀbeꢀ
activatedꢀpriorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀ
issuedꢀtoꢀthatꢀbank.
BURST TERMINATE
TheꢀBURSTꢀTERMINATEꢀcommandꢀforciblyꢀterminatesꢀ
theꢀburstꢀreadꢀandꢀwriteꢀoperationsꢀbyꢀtruncatingꢀeitherꢀ
fixed-lengthꢀ orꢀ full-pageꢀ burstsꢀ andꢀ theꢀ mostꢀ recentlyꢀ
registeredꢀREADꢀorꢀWRITEꢀcommandꢀpriorꢀtoꢀtheꢀBURSTꢀ
TERMINATE.
COMMAND INHIBIT
COMMANDꢀINHIBITꢀpreventsꢀnewꢀcommandsꢀfromꢀbeingꢀ
executed.ꢀOperationsꢀinꢀprogressꢀareꢀnotꢀaffected,ꢀapartꢀ
fromꢀwhetherꢀtheꢀCLKꢀsignalꢀisꢀenabled
AUTO PRECHARGE
Theꢀ AUTOꢀ PRECHARGEꢀ functionꢀ ensuresꢀ thatꢀ theꢀ
prechargeꢀisꢀinitiatedꢀatꢀtheꢀearliestꢀvalidꢀstageꢀwithinꢀaꢀ
burst.ꢀꢀThisꢀfunctionꢀallowsꢀforꢀindividual-bankꢀprechargeꢀ
withoutꢀrequiringꢀanꢀexplicitꢀcommand.ꢀꢀA10ꢀcanꢀbeꢀusedꢀ
toꢀenableꢀtheꢀAUTOꢀPRECHARGEꢀfunctionꢀinꢀconjunc-
tionꢀwithꢀaꢀspecificꢀREADꢀorꢀWRITEꢀcommand.ꢀꢀForꢀeachꢀ
individualꢀREADꢀorꢀWRITEꢀcommand,ꢀautoꢀprechargeꢀisꢀ
NO OPERATION
WhenꢀCSꢀisꢀlow,ꢀtheꢀNOPꢀcommandꢀpreventsꢀunwantedꢀ
commandsꢀ fromꢀ beingꢀ registeredꢀ duringꢀ idleꢀ orꢀ waitꢀ
states.
6ꢀ
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LOAD MODE REGISTER
DuringꢀtheꢀLOADꢀMODEꢀREGISTERꢀcommandꢀtheꢀmodeꢀ
registerꢀisꢀloadedꢀfromꢀA0-A11.ꢀꢀThisꢀcommandꢀcanꢀonlyꢀ
beꢀissuedꢀwhenꢀallꢀbanksꢀareꢀidle.ꢀ
ACTIVE COMMAND
Whenꢀ theꢀ ACTIVEꢀ COMMANDꢀ isꢀ activated,ꢀ BA0,ꢀ BA1ꢀ
inputsꢀselectsꢀaꢀbankꢀtoꢀbeꢀaccessed,ꢀandꢀtheꢀaddressꢀ
inputsꢀonꢀA0-A11ꢀselectsꢀtheꢀrow.ꢀꢀꢀUntilꢀaꢀPRECHARGEꢀ
commandꢀisꢀissuedꢀtoꢀtheꢀbank,ꢀtheꢀrowꢀremainsꢀopenꢀ
forꢀaccesses.
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—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
Active
High-Z
Hꢀ
—ꢀ
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TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION
CS
Hꢀ
Lꢀ
RAS CAS
WE DQM
ADDR
Xꢀ
DQs
COMMANDꢀINHIBITꢀ(NOP)ꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
X
X
NOꢀOPERATIONꢀ(NOP)ꢀ
Xꢀ
ACTIVEꢀ(Selectꢀbankꢀandꢀactivateꢀrow)(3)ꢀ
READꢀ(Selectꢀbank/column,ꢀstartꢀREADꢀburst)(4)
WRITEꢀ(Selectꢀbank/column,ꢀstartꢀWRITEꢀburst)(4)ꢀ Lꢀ
BURSTꢀTERMINATEꢀ Lꢀ
PRECHARGEꢀ(Deactivateꢀrowꢀinꢀbankꢀorꢀbanks)(5)ꢀ Lꢀ
Lꢀ
Xꢀ
Bank/Rowꢀ
Bank/Colꢀ
Bank/Colꢀ
Xꢀ
X
ꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
L/H(8)ꢀ
L/H(8)ꢀ
Xꢀ
X
Lꢀ
Valid
Active
X
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Codeꢀ
Xꢀ
AUTOꢀREFRESHꢀorꢀSELFꢀREFRESH(6,7)
ꢀ
Lꢀ
Lꢀ
Hꢀ
Xꢀ
X
(Enterꢀselfꢀrefreshꢀmode)
LOADꢀMODEꢀREGISTER(2)ꢀ
WriteꢀEnable/OutputꢀEnable(8)ꢀ
WriteꢀInhibit/OutputꢀHigh-Z(8)ꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Lꢀ
Op-Codeꢀ
—ꢀ
X
NOTES:
1.ꢀ CKEꢀisꢀHIGHꢀforꢀallꢀcommandsꢀexceptꢀSELFꢀREFRESH.
2.ꢀ A0-A11ꢀdefineꢀtheꢀop-codeꢀwrittenꢀtoꢀtheꢀmodeꢀregister.
3.ꢀ A0-A11ꢀprovideꢀrowꢀaddress,ꢀandꢀBA0,ꢀBA1ꢀdetermineꢀwhichꢀbankꢀisꢀmadeꢀactive.
4.ꢀ A0-A7ꢀ(x16)ꢀprovideꢀcolumnꢀaddress;ꢀA10ꢀHIGHꢀenablesꢀtheꢀautoꢀprechargeꢀfeatureꢀ(nonpersistent),ꢀwhileꢀA10ꢀLOWꢀdisablesꢀꢀ
autoꢀprecharge;ꢀBA0,ꢀBA1ꢀdetermineꢀwhichꢀbankꢀisꢀbeingꢀreadꢀfromꢀorꢀwrittenꢀto.
5.ꢀ A10ꢀLOW:ꢀBA0,ꢀBA1ꢀdetermineꢀtheꢀbankꢀbeingꢀprecharged.ꢀA10ꢀHIGH:ꢀAllꢀbanksꢀprechargedꢀandꢀBA0,ꢀBA1ꢀareꢀ“Don’tꢀCare.”
6.ꢀ AUTOꢀREFRESHꢀifꢀCKEꢀisꢀHIGH,ꢀSELFꢀREFRESHꢀifꢀCKEꢀisꢀLOW.
7.ꢀ Internalꢀrefreshꢀcounterꢀcontrolsꢀrowꢀaddressing;ꢀallꢀinputsꢀandꢀI/Osꢀareꢀ“Don’tꢀCare”ꢀexceptꢀforꢀCKE.
8.ꢀ ActivatesꢀorꢀdeactivatesꢀtheꢀDQsꢀduringꢀWRITEsꢀ(zero-clockꢀdelay)ꢀandꢀREADsꢀ(two-clockꢀdelay).
8ꢀ
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IS42S16400F
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TRUTH TABLE – CKE (1-4)
CURRENT STATE
COMMANDn
ACTIONn
CKEn-1
CKEn
Power-Downꢀ
Xꢀ
MaintainꢀPower-Downꢀ
MaintainꢀSelfꢀRefreshꢀ
MaintainꢀClockꢀSuspendꢀ
ExitꢀPower-Downꢀ
ExitꢀSelfꢀRefreshꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
L
L
SelfꢀRefreshꢀ
Xꢀ
ClockꢀSuspendꢀ
Power-Down(5)ꢀ
SelfꢀRefresh(6)ꢀ
ClockꢀSuspend(7)ꢀ
AllꢀBanksꢀIdleꢀ
AllꢀBanksꢀIdleꢀ
ReadingꢀorꢀWritingꢀ
Xꢀ
L
COMMANDꢀINHIBITꢀorꢀNOPꢀ
COMMANDꢀINHIBITꢀorꢀNOPꢀ
Xꢀ
H
H
H
L
ExitꢀClockꢀSuspendꢀ
Power-DownꢀEntryꢀ
SelfꢀRefreshꢀEntryꢀ
ClockꢀSuspendꢀEntryꢀ
COMMANDꢀINHIBITꢀorꢀNOPꢀ
AUTOꢀREFRESHꢀ
VALIDꢀ
L
L
ꢀ
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
ꢀ
Hꢀ
H
NOTES:
1.ꢀ CKEnꢀisꢀtheꢀlogicꢀstateꢀofꢀCKEꢀatꢀclockꢀedgeꢀn;ꢀCKEn-1 wasꢀtheꢀstateꢀofꢀCKEꢀatꢀtheꢀpreviousꢀclockꢀedge.ꢀ
2.ꢀ CurrentꢀstateꢀisꢀtheꢀstateꢀofꢀtheꢀSDRAMꢀimmediatelyꢀpriorꢀtoꢀclockꢀedgeꢀn.
3.ꢀ COMMANDnꢀisꢀtheꢀcommandꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀACTONnꢀisꢀaꢀresultꢀofꢀCOMMANDn.
4.ꢀ Allꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
5.ꢀ Exitingꢀpower-downꢀatꢀclockꢀedgeꢀnꢀwillꢀputꢀtheꢀdeviceꢀinꢀtheꢀallꢀbanksꢀidleꢀstateꢀinꢀtimeꢀforꢀclockꢀedgeꢀn+1 (providedꢀthatꢀtcksꢀisꢀ
met)
.
6.ꢀ Exitingꢀselfꢀrefreshꢀatꢀclockꢀedgeꢀnꢀwillꢀputꢀtheꢀdeviceꢀinꢀallꢀbanksꢀidleꢀstateꢀonceꢀtxsrꢀisꢀmet.ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀ
commandsꢀshouldꢀbeꢀissuedꢀonꢀclockꢀedgesꢀoccurringꢀduringꢀtheꢀtxsrꢀperiod.ꢀAꢀminimumꢀofꢀtwoꢀNOPꢀcommandsꢀmustꢀbeꢀsentꢀ
duringꢀtxsrꢀperiod.
7.ꢀ Afterꢀexitingꢀclockꢀsuspendꢀatꢀclockꢀedgeꢀn,ꢀtheꢀdeviceꢀwillꢀresumeꢀoperationꢀandꢀrecognizeꢀtheꢀnextꢀcommandꢀatꢀclockꢀedgeꢀ
n+1.
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENTꢀSTATE
ꢀ
COMMANDꢀ(ACTION)ꢀ
CSꢀ RASꢀ CASꢀ WE
Anyꢀ
COMMANDꢀINHIBITꢀ(NOP/Continueꢀpreviousꢀoperation)
ꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Lꢀ
Xꢀ
Hꢀ
Hꢀ
Lꢀ
X
H
H
H
L
ꢀ
NOꢀOPERATIONꢀ(NOP/Continueꢀpreviousꢀoperation)
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
ꢀAUTOꢀREFRESH(7)ꢀ
ꢀ
Idleꢀ
ꢀ
Lꢀ
ꢀ
LOADꢀMODEꢀREGISTER(7)ꢀ
PRECHARGE(11)ꢀ
Lꢀ
Lꢀ
ꢀ
Lꢀ
Hꢀ
Lꢀ
L
RowꢀActiveꢀ
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(10)ꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(10)ꢀ
PRECHARGEꢀ(Deactivateꢀrowꢀinꢀbankꢀorꢀbanks)(8)ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(10)ꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(10)ꢀ
PRECHARGEꢀ(TruncateꢀREADꢀburst,ꢀstartꢀPRECHARGE)(8)ꢀ
BURSTꢀTERMINATE(9)ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(10)ꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(10)ꢀ
PRECHARGEꢀ(TruncateꢀWRITEꢀburst,ꢀstartꢀPRECHARGE)(8)ꢀ
BURSTꢀTERMINATE(9)ꢀ
Hꢀ
Hꢀ
Lꢀ
H
L
Lꢀ
ꢀ
Hꢀ
Lꢀ
L
Readꢀ
Hꢀ
Hꢀ
Lꢀ
H
L
(Autoꢀ
Lꢀ
Prechargeꢀ
Disabled)ꢀ
Writeꢀ
Hꢀ
Hꢀ
Lꢀ
L
Hꢀ
Hꢀ
Hꢀ
Lꢀ
L
H
L
(Autoꢀ
Lꢀ
Prechargeꢀ
Hꢀ
Hꢀ
L
Disabled)ꢀ
Hꢀ
L
NOTE:
ꢀ 1.ꢀThisꢀtableꢀappliesꢀwhenꢀCKEꢀn-1ꢀwasꢀHIGHꢀandꢀCKEꢀnꢀisꢀHIGHꢀ(seeꢀTruthꢀTableꢀ-ꢀCKE)ꢀandꢀafterꢀtxsrꢀhasꢀbeenꢀmetꢀ(ifꢀtheꢀ
previousꢀstateꢀwasꢀSELFꢀREFRESH).
ꢀ 2.ꢀThisꢀtableꢀisꢀbank-specific,ꢀexceptꢀwhereꢀnoted;ꢀi.e.,ꢀtheꢀcurrentꢀstateꢀisꢀforꢀaꢀspecificꢀbankꢀandꢀtheꢀcommandsꢀshownꢀareꢀthoseꢀ
allowedꢀtoꢀbeꢀissuedꢀtoꢀthatꢀbankꢀwhenꢀinꢀthatꢀstate.ꢀExceptionsꢀareꢀcoveredꢀinꢀtheꢀnotesꢀbelow.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
ꢀ 3.ꢀCurrentꢀstateꢀdefinitions:
ꢀ
ꢀ
Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtrpꢀhasꢀbeenꢀmet.
RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtrcdꢀhasꢀbeenꢀmet.ꢀNoꢀdataꢀbursts/accessesꢀandꢀnoꢀregisterꢀ
accessesꢀareꢀinꢀprogress.
ꢀ
ꢀ
Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
Write:ꢀAꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
ꢀ 4.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀaꢀcommandꢀissuedꢀtoꢀtheꢀsameꢀbank.ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommands,ꢀ
orꢀallowableꢀcommandsꢀtoꢀtheꢀotherꢀbankꢀshouldꢀbeꢀissuedꢀonꢀanyꢀclockꢀedgeꢀoccurringꢀduringꢀtheseꢀstates.ꢀAllowableꢀcom-
mandsꢀtoꢀtheꢀotherꢀbankꢀareꢀdeterminedꢀbyꢀitsꢀcurrentꢀstateꢀandꢀCURRENTꢀSTATEꢀBANKꢀnꢀtruthꢀtables.
ꢀ
Precharging:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀcommandꢀandꢀendsꢀwhenꢀtrpꢀisꢀmet.ꢀOnceꢀtrpꢀisꢀmet,ꢀtheꢀbankꢀ
willꢀbeꢀinꢀtheꢀidleꢀstate.
ꢀ
RowꢀActivating:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀACTIVEꢀcommandꢀandꢀendsꢀwhenꢀtrcdꢀisꢀmet.ꢀOnceꢀtrcdꢀisꢀmet,ꢀtheꢀbankꢀwillꢀ
beꢀinꢀtheꢀrowꢀactiveꢀstate.
ꢀ
ꢀ
Readꢀw/Auto
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀREADꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtrpꢀhasꢀbeenꢀ
met.ꢀOnceꢀtrpꢀisꢀmet,ꢀtheꢀbankꢀwillꢀbeꢀinꢀtheꢀidleꢀstate.
ꢀ
ꢀ
Writeꢀw/Auto
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀendsꢀwhenꢀtrpꢀhasꢀbeenꢀ
met.ꢀOnceꢀtrpꢀisꢀmet,ꢀtheꢀbankꢀwillꢀbeꢀinꢀtheꢀidleꢀstate.
ꢀ 5.ꢀTheꢀfollowingꢀstatesꢀmustꢀnotꢀbeꢀinterruptedꢀbyꢀanyꢀexecutableꢀcommand;ꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandsꢀmustꢀbeꢀ
appliedꢀonꢀeachꢀpositiveꢀclockꢀedgeꢀduringꢀtheseꢀstates.
ꢀ
Refreshing:ꢀStartsꢀwithꢀregistrationꢀofꢀanꢀAUTOꢀREFRESHꢀcommandꢀandꢀendsꢀwhenꢀtrcꢀisꢀmet.ꢀOnceꢀtrcꢀisꢀmet,ꢀtheꢀ
SDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.
ꢀ
ꢀ
AccessingꢀMode
Register:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀLOADꢀMODEꢀREGISTERꢀcommandꢀandꢀendsꢀwhenꢀtmrdꢀhasꢀbeenꢀmet.ꢀOnceꢀ
tmrdꢀisꢀmet,ꢀtheꢀSDRAMꢀwillꢀbeꢀinꢀtheꢀallꢀbanksꢀidleꢀstate.
ꢀ
PrechargingꢀAll:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀPRECHARGEꢀALLꢀcommandꢀandꢀendsꢀwhenꢀtrpꢀisꢀmet.ꢀOnceꢀtrpꢀisꢀmet,ꢀallꢀ
banksꢀwillꢀbeꢀinꢀtheꢀidleꢀstate.
ꢀ 6.ꢀAllꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
ꢀ 7.ꢀNotꢀbank-specific;ꢀrequiresꢀthatꢀallꢀbanksꢀareꢀidle.
ꢀ 8.ꢀMayꢀorꢀmayꢀnotꢀbeꢀbank-specific;ꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀallꢀmustꢀbeꢀinꢀaꢀvalidꢀstateꢀforꢀprecharging.
ꢀ 9.ꢀNotꢀbank-specific;ꢀBURSTꢀTERMINATEꢀaffectsꢀtheꢀmostꢀrecentꢀREADꢀorꢀWRITEꢀburst,ꢀregardlessꢀofꢀbank.
ꢀ10.ꢀREADsꢀorꢀWRITEsꢀlistedꢀinꢀtheꢀCommandꢀ(Action)ꢀcolumnꢀincludeꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀenabledꢀandꢀ
READsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀdisabled.
ꢀ11.ꢀDoesꢀnotꢀaffectꢀtheꢀstateꢀofꢀtheꢀbankꢀandꢀactsꢀasꢀaꢀNOPꢀtoꢀthatꢀbank.
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
(1-6)
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m
CURRENTꢀSTATE
ꢀ
COMMANDꢀ(ACTION)ꢀ
CSꢀ RASꢀ CASꢀ WEꢀ
Anyꢀ
COMMANDꢀINHIBITꢀ(NOP/Continueꢀpreviousꢀoperation)ꢀ
NOꢀOPERATIONꢀ(NOP/Continueꢀpreviousꢀoperation)ꢀ
AnyꢀCommandꢀOtherwiseꢀAllowedꢀtoꢀBankꢀm
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7)ꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7)ꢀ
PRECHARGEꢀ
Hꢀ
Lꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Lꢀ
X
H
X
H
H
L
ꢀ
Idleꢀ
Rowꢀ
Activating,ꢀ
Active,ꢀorꢀ
Prechargingꢀ
Readꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(Autoꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(7,10)
ꢀ
Hꢀ
Hꢀ
Lꢀ
Prechargeꢀ
Disabled)ꢀ
Writeꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7,11)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(Autoꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7,12)
ꢀ
Hꢀ
Hꢀ
Lꢀ
Prechargeꢀ
Disabled)ꢀ
Readꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(7,13)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(WithꢀAutoꢀ
Precharge)ꢀ
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀREADꢀburst)(7,8,14)
ꢀ
Hꢀ
Hꢀ
Lꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀWRITEꢀburst)(7,8,15)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
L
Writeꢀ
ACTIVEꢀ(Selectꢀandꢀactivateꢀrow)ꢀ
Lꢀ
H
H
L
(WithꢀAutoꢀ
Precharge)ꢀ
ꢀ
READꢀ(SelectꢀcolumnꢀandꢀstartꢀREADꢀburst)(7,8,16)
ꢀ
Hꢀ
Hꢀ
Lꢀ
WRITEꢀ(SelectꢀcolumnꢀandꢀstartꢀnewꢀWRITEꢀburst)(7,8,17)
PRECHARGE(9)ꢀ
ꢀ
Lꢀ
Hꢀ
L
NOTE:ꢀ
ꢀ 1.ꢀThisꢀtableꢀappliesꢀwhenꢀCKEꢀn-1ꢀwasꢀHIGHꢀandꢀCKEꢀnꢀisꢀHIGHꢀ(TruthꢀTableꢀ-ꢀCKE)ꢀandꢀafterꢀtxsrꢀhasꢀbeenꢀmetꢀ(ifꢀtheꢀprevi-
ousꢀstateꢀwasꢀselfꢀrefresh).
ꢀ 2.ꢀThisꢀtableꢀdescribesꢀalternateꢀbankꢀoperation,ꢀexceptꢀwhereꢀnoted;ꢀi.e.,ꢀtheꢀcurrentꢀstateꢀisꢀforꢀbankꢀn andꢀtheꢀcommandsꢀ
shownꢀareꢀthoseꢀallowedꢀtoꢀbeꢀissuedꢀtoꢀbankꢀm (assumingꢀthatꢀbankꢀm isꢀinꢀsuchꢀaꢀstateꢀthatꢀtheꢀgivenꢀcommandꢀisꢀallowable).ꢀExcep-
tionsꢀareꢀcoveredꢀinꢀtheꢀnotesꢀbelow.
ꢀ 3.ꢀCurrentꢀstateꢀdefinitions:
ꢀ
ꢀ
Idle:ꢀTheꢀbankꢀhasꢀbeenꢀprecharged,ꢀandꢀtrpꢀhasꢀbeenꢀmet.
RowꢀActive:ꢀAꢀrowꢀinꢀtheꢀbankꢀhasꢀbeenꢀactivated,ꢀandꢀtrcdꢀhasꢀbeenꢀmet.ꢀNoꢀdataꢀbursts/accessesꢀandꢀnoꢀregisterꢀ
accessesꢀareꢀinꢀprogress.
ꢀ
ꢀ
Read:ꢀAꢀREADꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
Write:ꢀAꢀWRITEꢀburstꢀhasꢀbeenꢀinitiated,ꢀwithꢀautoꢀprechargeꢀdisabled,ꢀandꢀhasꢀnotꢀyetꢀterminatedꢀorꢀbeenꢀtermi-
nated.
ꢀ
ꢀ
Readꢀw/Auto
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀREADꢀcommandꢀwithꢀautoꢀprechargeꢀenabled,ꢀandꢀendsꢀwhenꢀtrpꢀhasꢀbeenꢀ
met.ꢀOnceꢀtrpꢀisꢀmet,ꢀtheꢀbankꢀwillꢀbeꢀinꢀtheꢀidleꢀstate.
ꢀ
ꢀ
Writeꢀw/Auto
PrechargeꢀEnabled:ꢀStartsꢀwithꢀregistrationꢀofꢀaꢀWRITEꢀcommandꢀwithꢀautoꢀprechargeꢀenabled,ꢀandꢀendsꢀwhenꢀtrpꢀhasꢀbeenꢀ
met.ꢀOnceꢀtrpꢀisꢀmet,ꢀtheꢀbankꢀwillꢀbeꢀinꢀtheꢀidleꢀstate.
ꢀ 4.ꢀAUTOꢀREFRESH,ꢀSELFꢀREFRESHꢀandꢀLOADꢀMODEꢀREGISTERꢀcommandsꢀmayꢀonlyꢀbeꢀissuedꢀwhenꢀallꢀbanksꢀareꢀidle.
ꢀ 5.ꢀAꢀBURSTꢀTERMINATEꢀcommandꢀcannotꢀbeꢀissuedꢀtoꢀanotherꢀbank;ꢀitꢀappliesꢀtoꢀtheꢀbankꢀrepresentedꢀbyꢀtheꢀcurrentꢀstateꢀ
only.
ꢀ 6.ꢀAllꢀstatesꢀandꢀsequencesꢀnotꢀshownꢀareꢀillegalꢀorꢀreserved.
ꢀ 7.ꢀREADsꢀorꢀWRITEsꢀtoꢀbankꢀmꢀlistedꢀinꢀtheꢀCommandꢀ(Action)ꢀcolumnꢀincludeꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀenabledꢀ
andꢀREADsꢀorꢀWRITEsꢀwithꢀautoꢀprechargeꢀdisabled.
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11
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
ꢀ 8.ꢀCONCURRENTꢀAUTOꢀPRECHARGE:ꢀBankꢀnꢀwillꢀinitiateꢀtheꢀAUTOꢀPRECHARGEꢀcommandꢀwhenꢀitsꢀburstꢀhasꢀbeenꢀinter-
ruptedꢀbyꢀbankꢀm’sꢀburst.
ꢀ 9.ꢀBurstꢀinꢀbankꢀnꢀcontinuesꢀasꢀinitiated.
ꢀ10.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀREADꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlaterꢀ(ConsecutiveꢀREADꢀBursts).
ꢀ11.ꢀForꢀaꢀREADꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-
ruptꢀtheꢀREADꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(READꢀtoꢀWRITE).ꢀDQMꢀshouldꢀbeꢀusedꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀ
preventꢀbusꢀcontention.
ꢀ12.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀREAD),ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀlastꢀvalidꢀWRITEꢀ
toꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
ꢀ13.ꢀForꢀaꢀWRITEꢀwithoutꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinter-
ruptꢀtheꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregisteredꢀ(WRITEꢀtoꢀWRITE).ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregisteredꢀoneꢀ
clockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
ꢀ14.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀtheꢀ
READꢀonꢀbankꢀn,ꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ
1).
ꢀ15.ꢀForꢀaꢀREADꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀREADꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀtwoꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀ
TheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀmꢀisꢀregisteredꢀ(FigꢀCAPꢀ2).
ꢀ16.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered,ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀ
afterꢀtWRꢀisꢀmet,ꢀwhereꢀtwrꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀregis-
teredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀmꢀ(FigꢀCAPꢀ3).
ꢀ17.ꢀForꢀaꢀWRITEꢀwithꢀautoꢀprechargeꢀinterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge),ꢀtheꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀ
theꢀWRITEꢀonꢀbankꢀnꢀwhenꢀregistered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtwrꢀisꢀmet,ꢀwhereꢀtꢀWRꢀbeginsꢀwhenꢀtheꢀ
WRITEꢀtoꢀbankꢀmꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀWRITEꢀtoꢀbankꢀmꢀ
(FigꢀCAPꢀ4).
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vdd maxꢀ
Vddqꢀꢀmax
ViNꢀ
Parameters
Rating
–1.0ꢀtoꢀ+4.6ꢀ
–1.0ꢀtoꢀ+4.6ꢀ
–1.0ꢀtoꢀVddq +ꢀ0.5ꢀ
–1.0ꢀtoꢀVddq +ꢀ0.5ꢀ
1ꢀ
Unit
V
V
V
V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
MaximumꢀSupplyꢀVoltageꢀ
MaximumꢀSupplyꢀVoltageꢀforꢀOutputꢀBufferꢀ
InputꢀVoltageꢀ
OutputꢀVoltageꢀ
AllowableꢀPowerꢀDissipationꢀ
outputꢀShortedꢀCurrentꢀ
Voutꢀ
Pd max
Ics
W
mA
50ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Topr
operatingꢀTemperatureꢀ
Com.ꢀ
Ind.ꢀ
A1ꢀ
0ꢀtoꢀ+70ꢀ
-40ꢀtoꢀ+85ꢀ
-40ꢀtoꢀ+85ꢀ
-40ꢀtoꢀ+105ꢀ
°Cꢀ
°Cꢀ
°Cꢀ
°C
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
A2ꢀ
ꢀ
Tstgꢀ
StorageꢀTemperatureꢀ
ꢀ
–65ꢀtoꢀ+150ꢀ
°C
DC RECOMMENDED OPERATING CONDITIONS(2)
(AtꢀTaꢀ=ꢀ0ꢀtoꢀ+70°Cꢀforꢀcommercialꢀgrade.ꢀTaꢀ=ꢀ-40ꢀtoꢀ+85°CꢀforꢀindustrialꢀandꢀA1ꢀgrade.ꢀꢀTaꢀ=ꢀ-40ꢀtoꢀ+105°CꢀforꢀA2ꢀgrade)
Symbol
Vdd, Vddqꢀ
Vihꢀ
Parameter
Min.
3.0ꢀ
2.0ꢀ
-0.3ꢀ
Typ.
3.3ꢀ
—ꢀ
Max.
3.6ꢀ
Vdd +ꢀ0.3ꢀ
+0.8ꢀ
Unit
V
V
ꢀ
ꢀ
ꢀ
SupplyꢀVoltageꢀ
InputꢀHighꢀVoltage(3)ꢀ
InputꢀLowꢀVoltage(4)ꢀ
Vilꢀ
—ꢀ
V
CAPACITANCE CHARACTERISTICS(1,2) (AtꢀTaꢀ=ꢀ0ꢀtoꢀ+25°C,ꢀVddꢀ=ꢀVddqꢀ=ꢀ3.3ꢀ ꢀ0.3V,ꢀfꢀ=ꢀ1ꢀMHz)
Symbol
CiNꢀ
Parameter
Typ.
—ꢀ
—ꢀ
Max.
3.8ꢀ
3.5ꢀ
6.5ꢀ
Unit
pF
pF
ꢀ
ꢀ
ꢀ
InputꢀCapacitance:ꢀAddressꢀandꢀControlꢀ
InputꢀCapacitance:ꢀ(CLK)ꢀ
DataꢀInput/OutputꢀCapacitance:ꢀI/O0-I/O15ꢀ
Cclkꢀ
CI/Oꢀ
—ꢀ
pF
Notes:
1.ꢀ StressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀ
stressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀ
sectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀ
reliability.
2.ꢀ AllꢀvoltagesꢀareꢀreferencedꢀtoꢀGND.
3.ꢀꢀVih(max)ꢀ=ꢀVddqꢀ+ꢀ1.2Vꢀwithꢀaꢀpulseꢀwidthꢀ<ꢀ3ns.
4.ꢀꢀVil(min)ꢀ=ꢀGNDꢀ-ꢀ1.2Vꢀwithꢀaꢀpulseꢀwidthꢀ<ꢀ3ns.
5.ꢀThisꢀparameterꢀisꢀcharacterized.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev. I
12/01/2011
ꢀicc6
Self-RefreshꢀCurrentꢀ
CKEꢀ≤ꢀ0.2Vꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
2ꢀ
mA
IS42S16400F
IS45S16400F
DC ELECTRICAL CHARACTERISTICS (RecommendedꢀOperationꢀConditionsꢀunlessꢀotherwiseꢀnoted.)
Symbolꢀ Parameterꢀ
Test Conditionꢀ
Speed Min.ꢀ
Max.
Unit
ꢀiil
ꢀꢀ
ꢀ
InputꢀLeakageꢀCurrentꢀ
ꢀ
0Vꢀ≤ꢀViNꢀ≤ꢀVdd,ꢀwithꢀpinsꢀotherꢀthanꢀ
theꢀtestedꢀpinꢀatꢀ0V
ꢀ
ꢀ
–5ꢀ
5ꢀ
µA
ꢀiol
ꢀ
OutputꢀLeakageꢀCurrentꢀ
OutputꢀHighꢀVoltageꢀLevelꢀ
OutputꢀLowꢀVoltageꢀLevelꢀ
Outputꢀisꢀdisabled,ꢀ0Vꢀ≤ꢀVoutꢀ≤ꢀVdd
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–5ꢀ
2.4ꢀ
—ꢀ
5ꢀ
µAꢀ
V
ꢀVoh
ꢀ
ꢀ
i
i
outꢀ=ꢀ–2ꢀmAꢀ
outꢀ=ꢀ+2ꢀmAꢀ
ꢀ
ꢀ
—ꢀ
0.4ꢀ
ꢀVol
ꢀ
V
ꢀicc1
OperatingꢀCurrent(1,2)
ꢀ
OneꢀBankꢀOperation,ꢀ
BurstꢀLength=1ꢀ
CASꢀlatencyꢀ=ꢀ3ꢀꢀꢀ Com.ꢀ
-5ꢀ
-6ꢀ
-7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
110ꢀ
95ꢀ
85ꢀ
155ꢀ
145ꢀ
2ꢀ
4ꢀ
2ꢀ
3ꢀ
mA
mA
mA
mA
mA
mA
mAꢀ
mA
mA
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
t
ꢀ
t
ꢀ
Com.ꢀ
Com.ꢀ
A1,ꢀInd.ꢀ -5/-6ꢀ
t
I
ꢀ
rcꢀ≥ꢀtrcꢀ(min.)ꢀ
outꢀ=ꢀ0mAꢀ
A1,ꢀA2,ꢀInd.ꢀ
-7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀicc2p
ꢀꢀ
ꢀIcc2ps
ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≤ꢀVilꢀꢀ(max)ꢀ
ꢀ
(InꢀPower-DownꢀMode)
ꢀ
ckꢀ=ꢀ15nsꢀ
ck = ∞ꢀ
Com.ꢀ
A1,ꢀA2,ꢀInd.ꢀ
Com.ꢀ
ꢀ
ꢀꢀ
ꢀ
A1,ꢀA2,ꢀInd.ꢀ
i
cc2N(3)ꢀ
PrechargeꢀStandbyꢀCurrentꢀ CKEꢀ≥ꢀVihꢀ(miN)ꢀ
(InꢀNonꢀPower-DownꢀMode)
ꢀ
t
t
ꢀ
ckꢀ=ꢀ15nsꢀ
ck = ∞ꢀ
ꢀ
Com.ꢀ
A1,ꢀA2,ꢀInd.ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
20ꢀ
15ꢀ
15ꢀ
mA
mA
mA
ꢀIcc2Ns
ꢀꢀ
ꢀ
ꢀicc3p
ꢀꢀ
ꢀicc3ps
ꢀ
ActiveꢀStandbyꢀCurrentꢀ
ꢀ
(InꢀPower-DownꢀMode)ꢀ
ꢀ
CKEꢀ≤ꢀVilꢀ(max)ꢀ
t
ꢀ
t
ꢀ
ckꢀ=ꢀ15nsꢀ
Com.ꢀ
A1,ꢀA2,ꢀInd.ꢀ
Com.ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
7ꢀ
7ꢀ
5ꢀ
5ꢀ
mA
mAꢀ
mA
mA
ꢀ
ꢀ
ꢀ
ꢀ
ck = ∞ꢀ
ꢀꢀ
A1,ꢀA2,ꢀInd.ꢀ
i
cc3N(3)ꢀ
ActiveꢀStandbyꢀCurrentꢀ
(InꢀNonꢀPower-DownꢀMode)
ꢀ
CKEꢀ≥ꢀVihꢀ(miN)ꢀ
t
t
ꢀ
ckꢀ=ꢀ15nsꢀ
ck = ∞ꢀ
ꢀ
Com.ꢀ
A1,ꢀA2,ꢀInd.ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
30ꢀ
25ꢀ
25ꢀ
mA
mA
mA
ꢀIcc3Ns
ꢀꢀ
ꢀ
ꢀicc4
ꢀ
ꢀ
ꢀ
OperatingꢀCurrentꢀ
t
ckꢀ=ꢀtckꢀ(miN)ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
CASꢀlatencyꢀ=ꢀ3ꢀ Com.ꢀ
-5ꢀ
—ꢀ
140ꢀ
mA
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
(InꢀBurstꢀMode)(1)ꢀ
I
out =ꢀ0mAꢀ
ꢀ
Com.ꢀ
Com.ꢀ
-6ꢀ
-7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
130ꢀ
100ꢀ
140ꢀ
110ꢀ
mAꢀ
mAꢀ
mAꢀ
mA
ꢀ
BLꢀ=ꢀ4;ꢀ4ꢀbanksꢀactivatedꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
A1,ꢀInd.ꢀ -5/-6ꢀ
A1,ꢀA2,ꢀInd.ꢀ
-7ꢀ
ꢀicc5
Auto-RefreshꢀCurrentꢀ
trcꢀ=ꢀtrc
(miN)ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ CASꢀlatencyꢀ=ꢀ3ꢀ Com.ꢀ
-5ꢀ
—ꢀ
160ꢀ
mA
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tclkꢀ=ꢀtclk
(miN)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Com.ꢀ
Com.ꢀ
A1,ꢀInd.ꢀ -5/-6ꢀ
-6ꢀ
-7ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
150ꢀ
130ꢀ
170ꢀ
150ꢀ
mAꢀ
mAꢀ
mAꢀ
mA
ꢀꢀ
ꢀ
ꢀ
A1,ꢀA2,ꢀInd.ꢀ
-7ꢀ
Notes:
1.ꢀ Theseꢀareꢀtheꢀvaluesꢀatꢀtheꢀminimumꢀcycleꢀtime.ꢀSinceꢀtheꢀcurrentsꢀareꢀtransient,ꢀtheseꢀvaluesꢀdecreaseꢀasꢀtheꢀcycleꢀtimeꢀin-
creases.ꢀAlsoꢀnoteꢀthatꢀaꢀbypassꢀcapacitorꢀofꢀꢀatꢀꢀleastꢀꢀ0.01ꢀµFꢀshouldꢀbeꢀinsertedꢀbetweenꢀVddꢀandꢀGNDꢀforꢀeachꢀmemoryꢀchipꢀ
toꢀsuppressꢀpowerꢀsupplyꢀvoltageꢀnoiseꢀ(voltageꢀdrops)ꢀdueꢀtoꢀtheseꢀtransientꢀcurrents.
2.ꢀ Icc1ꢀandꢀIcc4ꢀdependꢀonꢀtheꢀoutputꢀload.ꢀTheꢀmaximumꢀvaluesꢀforꢀIcc1ꢀandꢀIcc4ꢀareꢀobtainedꢀwithꢀtheꢀoutputꢀopenꢀstate.
3.ꢀꢀInputꢀsignalꢀchnageꢀonceꢀperꢀ30ns.
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5
-6
-7
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
ꢀ tck3ꢀ
ꢀ tck2ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
AccessꢀTimeꢀFromꢀCLK(4,6)
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
5ꢀ
7.5ꢀ
—ꢀ
—ꢀ
6ꢀ
7.5ꢀ
—ꢀ
—ꢀ
7ꢀ
7.5ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ tac3ꢀ
ꢀ tac2ꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6ꢀ
ns
ns
ꢀ tchꢀ
ꢀ tclꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
OutputꢀDataꢀHoldꢀTime(6)
ꢀ
ꢀ
ꢀ
2ꢀ
2ꢀ
—ꢀ
—ꢀ
2ꢀ
2ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ toh3ꢀ
ꢀ toh2ꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.7ꢀ
2.7ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ tlzꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
OutputꢀHIGHꢀImpedanceꢀTime(5)
ꢀ
ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
ns
ꢀ thz3ꢀ
ꢀ thz2ꢀ
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6ꢀ
ns
ns
ꢀ tdsꢀ
InputꢀDataꢀSetupꢀTimeꢀ
InputꢀDataꢀHoldꢀTimeꢀ
AddressꢀSetupꢀTimeꢀ
AddressꢀHoldꢀTimeꢀ
CKEꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ tdhꢀ
ꢀ tasꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ tahꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ tcksꢀ
ꢀ tckhꢀ
ꢀ tckaꢀ
ꢀ tcmsꢀ
ꢀ tcmhꢀ
ꢀ trcꢀ
—ꢀ
—ꢀ
—ꢀ
CKEꢀHoldꢀTimeꢀ
—ꢀ
—ꢀ
—ꢀ
CKEꢀtoꢀCLKꢀRecoveryꢀDelayꢀTimeꢀ
1CLK+3
1.5ꢀ
0.8ꢀ
55ꢀ
ꢀ
—ꢀ
1CLK+3
1.5ꢀ
0.8ꢀ
60ꢀ
ꢀ
—ꢀ
1CLK+3ꢀ
1.5ꢀ
0.8ꢀ
63ꢀ
—ꢀ
CommandꢀSetupꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)ꢀ ꢀ
—ꢀ
—ꢀ
—ꢀ
CommandꢀHoldꢀTimeꢀ(CS,ꢀRAS,ꢀCAS,ꢀWE,ꢀDQM)ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ trasꢀ
ꢀ trpꢀ
40ꢀ
100,000
—ꢀ
ꢀ
42ꢀ
100,000
—ꢀ
ꢀ
42ꢀ
100,000
—ꢀ
ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
15ꢀ
18ꢀ
20ꢀ
ꢀ trcdꢀ
ꢀ trrdꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ
15ꢀ
—ꢀ
18ꢀ
—ꢀ
20ꢀ
—ꢀ
ꢀ
10ꢀ
—ꢀ
12ꢀ
—ꢀ
14ꢀ
—ꢀ
ꢀ tdpl orꢀ
ꢀ twrꢀ
ꢀ ꢀ ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtime
ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ
—ꢀ
—ꢀ
2CLKꢀ
—ꢀ
—ꢀ
2CLKꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ tdalꢀ
ꢀ ꢀ ꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
CommandꢀDelayꢀtimeꢀ
2CLK+trp
2CLK+trp
2CLK+trp
ꢀ
ꢀ ꢀ ꢀ
(DuringꢀAuto-Precharge)ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
2CLK+trp
0.3ꢀ
—ꢀ
1.2ꢀ
—ꢀ
2CLK+trp
0.3ꢀ
—ꢀ
1.2ꢀ
—ꢀ
2CLK+trp
0.3ꢀ
ꢀ
—ꢀ
1.2ꢀ
—ꢀ
ns
ns
ns
ꢀ ttꢀ
TransitionꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ txsrꢀ
ExitꢀtoꢀSelf-RefreshꢀtoꢀActiveꢀTimeꢀ
RefreshꢀCycleꢀTimeꢀ(4096)ꢀ
60ꢀ
66ꢀ
70ꢀ
ꢀ trefꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Taꢀꢀ≤ꢀ70oCꢀꢀꢀꢀCom.,ꢀInd.,ꢀA1,ꢀA2ꢀ
Taꢀꢀ≤ꢀ85oCꢀꢀꢀꢀInd.,ꢀA1,ꢀA2ꢀ
Taꢀꢀ>ꢀ85oCꢀꢀꢀꢀꢀA2ꢀ
—ꢀ
—ꢀ
—ꢀ
64ꢀ
64ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
64ꢀ
64ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
64ꢀ
64ꢀ
16ꢀ
msꢀ
msꢀ
ms
ꢀ ꢀ ꢀ
Notes:
1.ꢀ Whenꢀpowerꢀisꢀfirstꢀapplied,ꢀmemoryꢀoperationꢀshouldꢀbeꢀstartedꢀ200ꢀµsꢀafterꢀVddꢀandꢀVddqꢀreachꢀtheirꢀstipulatedꢀvoltages.ꢀAlsoꢀ
noteꢀthatꢀtheꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2.ꢀ measuredꢀwithꢀtt =ꢀ1ꢀns.
3.ꢀ Theꢀreferenceꢀlevelꢀisꢀ1.4ꢀVꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih (min.)ꢀandꢀVil
(max.).
4.ꢀ Accessꢀtimeꢀisꢀmeasuredꢀatꢀ1.4Vꢀwithꢀtheꢀloadꢀshownꢀinꢀtheꢀfigureꢀbelow.
5.ꢀ Theꢀtimeꢀthz (max.)ꢀisꢀdefinedꢀasꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀoutputꢀvoltageꢀtoꢀtransitionꢀbyꢀ ꢀ200ꢀmVꢀfromꢀVoh (min.)ꢀorꢀVolꢀ(max.)ꢀ
whenꢀtheꢀoutputꢀisꢀinꢀtheꢀhighꢀimpedanceꢀstate.
6.ꢀꢀIfꢀclockꢀrisingꢀtimeꢀisꢀlongerꢀthanꢀ1ns,ꢀtt/2ꢀ-ꢀ0.5nsꢀshouldꢀbeꢀaddedꢀtoꢀtheꢀparameter.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
15
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER
-5
-6
-7
UNITS
ꢀ
ꢀ
—ꢀ
ꢀ
ClockꢀCycleꢀTimeꢀ
ꢀ
CL=3ꢀ
CL=2ꢀ
5ꢀ
7.5ꢀ
6ꢀ
7.5ꢀ
7ꢀ
7.5ꢀ
nsꢀꢀ
ns
ꢀ
ꢀ
—ꢀ
ꢀ
OperatingꢀFrequencyꢀ
ꢀ
CL=3ꢀ
CL=2ꢀ
200ꢀ 166ꢀ
133ꢀ 133ꢀ
143ꢀ
133ꢀ
MHzꢀ
MHꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tccdꢀ
tckedꢀ
tpedꢀ
tdqdꢀ
tdqmꢀ
tdqzꢀ
tdwdꢀ
READ/WRITEꢀcommandꢀtoꢀREAD/WRITEꢀcommandꢀ
CKEꢀtoꢀclockꢀdisableꢀorꢀpower-downꢀentryꢀmodeꢀꢀ
CKEꢀtoꢀclockꢀenableꢀorꢀpower-downꢀexitꢀsetupꢀmodeꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
2ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
2ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
0ꢀ
0ꢀ
2ꢀ
0ꢀ
cycle
cycle
cycle
cycle
cycle
cycle
cycle
DQMꢀtoꢀinputꢀdataꢀdelayꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DQMꢀtoꢀdataꢀmaskꢀduringꢀWRITEsꢀ
DQMꢀtoꢀdataꢀhigh-impedanceꢀduringꢀREADsꢀ
WRITEꢀcommandꢀtoꢀinputꢀdataꢀdelayꢀ
ꢀ
ꢀ
tdalꢀ
ꢀ
Data-inꢀtoꢀACTIVEꢀcommandꢀ
ꢀ
CL=3ꢀ
CL=2ꢀ
5ꢀ
4ꢀ
5ꢀ
5ꢀ
5ꢀ
5ꢀ
cycleꢀ
cycle
ꢀ
ꢀ
ꢀ
ꢀ
tdplꢀ
tbdlꢀ
tcdlꢀ
trdlꢀ
Data-inꢀtoꢀPRECHARGEꢀcommandꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2ꢀ
1ꢀ
1ꢀ
2ꢀ
2ꢀ
2ꢀ
1ꢀ
1ꢀ
2ꢀ
2ꢀ
2ꢀ
1ꢀ
1ꢀ
2ꢀ
2ꢀ
cycle
cycle
cycle
cycle
cycle
Lastꢀdata-inꢀtoꢀburstꢀSTOPꢀcommandꢀ
Lastꢀdata-inꢀtoꢀnewꢀREAD/WRITEꢀcommandꢀ
Lastꢀdata-inꢀtoꢀPRECHARGEꢀcommandꢀ
ꢀ
ꢀ
tmrdꢀ
ꢀ
LOADꢀMODEꢀREGISTERꢀcommandꢀ
toꢀACTIVEꢀorꢀREFRESHꢀcommand
ꢀ
ꢀ
trohꢀ
ꢀ
Data-outꢀtoꢀhigh-impedanceꢀfromꢀ
PRECHARGEꢀcommandꢀ
CL=3ꢀ
CL=2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
3ꢀ
2ꢀ
cycle
cycle
AC TEST CONDITIONS (Input/OutputꢀReferenceꢀLevel:ꢀ1.4V)
Input Load
Output Load
tCK
t
CH
t
CL
3.0V
50 Ω
1.4V
0V
CLK
I/O
+1.4V
t
CMS
t
CMH
50 pF
3.0V
1.4V
INPUT
0V
tAC
t
OH
OUTPUT
1.4V
1.4V
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
TIVEꢀcommandꢀwhichꢀisꢀthenꢀfollowedꢀbyꢀaꢀREADꢀorWRITEꢀ
IS42S16400F
IS45S16400F
FUNCTIONAL DESCRIPTION
Initialization
Theꢀ64MbꢀSDRAMsꢀ(1ꢀMegꢀxꢀ16ꢀxꢀ4ꢀbanks)ꢀareꢀquad-bankꢀ
DRAMsꢀwhichꢀoperateꢀatꢀ3.3Vꢀandꢀincludeꢀaꢀsynchronousꢀ
interfaceꢀ(allꢀsignalsꢀareꢀregisteredꢀonꢀtheꢀpositiveꢀedgeꢀofꢀ
theꢀclockꢀsignal,ꢀCLK).ꢀEachꢀofꢀtheꢀ16,777,216-bitꢀbanksꢀisꢀ
organizedꢀasꢀ4,096ꢀrowsꢀbyꢀ256ꢀcolumnsꢀbyꢀ16ꢀbits.
SDRAMsꢀ mustꢀ beꢀ poweredꢀ upꢀ andꢀ initializedꢀ inꢀ aꢀ
predefinedꢀmanner.
Theꢀ64MbꢀSDRAMꢀisꢀinitializedꢀafterꢀtheꢀpowerꢀisꢀappliedꢀ
toꢀVddꢀandꢀVddqꢀ(simultaneously),ꢀandꢀtheꢀclockꢀisꢀstableꢀ
withꢀDQMꢀHighꢀandꢀCKEꢀHigh.ꢀ
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented;ꢀ
accessesꢀ startꢀ atꢀ aꢀ selectedꢀ locationꢀ andꢀ continueꢀ forꢀ
aꢀ programmedꢀ numberꢀ ofꢀ locationsꢀ inꢀ aꢀ programmedꢀ
sequence.ꢀAccessesꢀbeginꢀwithꢀtheꢀregistrationꢀofꢀanꢀAC-
Aꢀ100µsꢀdelayꢀisꢀrequiredꢀpriorꢀtoꢀissuingꢀanyꢀcommandꢀ
otherꢀthanꢀaꢀCOMMANDꢀINHIBITꢀorꢀaꢀNOP.ꢀTheꢀCOMMANDꢀ
INHIBITꢀorꢀNOPꢀmayꢀbeꢀappliedꢀduringꢀtheꢀ100µsꢀperiodꢀandꢀ
continueꢀshouldꢀatꢀleastꢀthroughꢀtheꢀendꢀofꢀtheꢀperiod.ꢀ
WithꢀatꢀleastꢀoneꢀCOMMANDꢀINHIBITꢀorꢀNOPꢀcommandꢀ
havingꢀbeenꢀapplied,ꢀaꢀPRECHARGEꢀcommandꢀshouldꢀ
beꢀappliedꢀonceꢀtheꢀ100µsꢀdelayꢀhasꢀbeenꢀsatisfied.ꢀꢀAllꢀ
banksꢀmustꢀbeꢀprecharged.ꢀꢀThisꢀwillꢀleaveꢀallꢀbanksꢀinꢀ
anꢀidleꢀstate,ꢀafterꢀwhichꢀatꢀleastꢀtwoꢀAUTOꢀREFRESHꢀcyclesꢀ
mustꢀbeꢀperformed.ꢀ AfterꢀtheꢀAUTOꢀREFRESHꢀcyclesꢀareꢀ
complete,ꢀ theꢀ SDRAMꢀ isꢀ thenꢀ readyꢀ forꢀ modeꢀ registerꢀ
programming.
command.ꢀTheꢀaddressꢀbitsꢀregisteredꢀcoincidentꢀwithꢀtheꢀ
ACTIVEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀbankꢀandꢀrowꢀtoꢀ
beꢀaccessedꢀ(BA0ꢀandꢀBA1ꢀselectꢀtheꢀbank,ꢀA0-A11ꢀselectꢀtheꢀ
row).Theꢀaddressꢀbitsꢀ(A0-A7)ꢀregisteredꢀcoincidentꢀwithꢀtheꢀ
READꢀorꢀWRITEꢀcommandꢀareꢀusedꢀtoꢀselectꢀtheꢀstartingꢀ
columnꢀlocationꢀforꢀtheꢀburstꢀaccess.ꢀ
Priorꢀ toꢀ normalꢀ operation,ꢀ theꢀ SDRAMꢀ mustꢀ beꢀ initial-
ized.ꢀTheꢀfollowingꢀsectionsꢀprovideꢀdetailedꢀinformationꢀ
coveringꢀdeviceꢀinitialization,ꢀregisterꢀdefinition,ꢀcommandꢀ
descriptionsꢀandꢀdeviceꢀoperation.ꢀ
Theꢀ modeꢀ registerꢀ shouldꢀ beꢀ loadedꢀ priorꢀ toꢀ applyingꢀ
anyꢀoperationalꢀcommandꢀbecauseꢀitꢀwillꢀpowerꢀupꢀinꢀanꢀ
unknownꢀstate.ꢀAfterꢀtheꢀLoadꢀModeꢀRegisterꢀcommand,ꢀ
atꢀleastꢀoneꢀNOPꢀcommandꢀmustꢀbeꢀassertedꢀpriorꢀtoꢀ
anyꢀcommand.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
17
Rev. I
12/01/2011
initiatingꢀtheꢀsubsequentꢀoperation.
Violatingꢀeitherꢀofꢀtheseꢀ
IS42S16400F
IS45S16400F
REGISTER DEFINITION
Mode Register
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ
selectionꢀofꢀaꢀburstꢀlength,ꢀaꢀburstꢀtype,ꢀaꢀCASꢀlatency,ꢀ
anꢀoperatingꢀmodeꢀandꢀaꢀwriteꢀburstꢀmode,ꢀasꢀshownꢀinꢀ
MODEꢀREGISTERꢀDEFINITION.ꢀ
ModeꢀregisterꢀbitsꢀM0-M2ꢀspecifyꢀtheꢀburstꢀlength,ꢀM3ꢀ
specifiesꢀtheꢀtypeꢀofꢀburstꢀ(sequentialꢀorꢀinterleaved),ꢀM4-ꢀM6ꢀ
specifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀ
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10ꢀandꢀ
M11ꢀareꢀreservedꢀforꢀfutureꢀuse.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idle,ꢀandꢀtheꢀcontrollerꢀmustꢀwaitꢀtheꢀspecifiedꢀtimeꢀbeforeꢀ
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
untilꢀitꢀisꢀprogrammedꢀagainꢀorꢀtheꢀdeviceꢀlosesꢀpower.
requirementsꢀwillꢀresultꢀinꢀunspecifiedꢀoperation.
MODE REGISTER DEFINITION
Address Bus
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
AllOtherStatesReserved
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
1
18ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
Burst Length
ingꢀthatꢀtheꢀburstꢀwillꢀwrapꢀwithinꢀtheꢀblockꢀifꢀaꢀboundaryꢀ
isꢀreached.ꢀTheꢀblockꢀisꢀuniquelyꢀselectedꢀbyꢀA1-A7ꢀ(x16)ꢀ
whenꢀtheꢀburstꢀlengthꢀisꢀsetꢀtoꢀtwo;ꢀbyꢀA2-A7ꢀ(x16)ꢀwhenꢀ
theꢀburstꢀlengthꢀisꢀsetꢀtoꢀfour;ꢀandꢀbyꢀA3-A7ꢀ(x16)ꢀwhenꢀtheꢀ
burstꢀlengthꢀisꢀsetꢀtoꢀeight.ꢀTheꢀremainingꢀ(leastꢀsignificant)ꢀ
addressꢀbit(s)ꢀisꢀ(are)ꢀusedꢀtoꢀselectꢀtheꢀstartingꢀlocationꢀ
withinꢀtheꢀblock.ꢀFull-pageꢀburstsꢀwrapꢀwithinꢀtheꢀpageꢀifꢀ
theꢀboundaryꢀisꢀreached.
ReadꢀandꢀwriteꢀaccessesꢀtoꢀtheꢀSDRAMꢀareꢀburstꢀoriented,ꢀ
withꢀtheꢀburstꢀlengthꢀbeingꢀprogrammable,ꢀasꢀshownꢀinꢀ
MODEꢀREGISTERꢀDEFINITION.ꢀTheꢀburstꢀlengthꢀdeter-
minesꢀtheꢀmaximumꢀnumberꢀofꢀcolumnꢀlocationsꢀthatꢀcanꢀ
beꢀaccessedꢀforꢀaꢀgivenꢀREADꢀorꢀWRITEꢀcommand.ꢀBurstꢀ
lengthsꢀofꢀ1,ꢀ2,ꢀ4ꢀorꢀ8ꢀlocationsꢀareꢀavailableꢀforꢀbothꢀtheꢀ
sequentialꢀandꢀtheꢀinterleavedꢀburstꢀtypes,ꢀandꢀaꢀfull-pageꢀ
burstꢀisꢀavailableꢀforꢀtheꢀsequentialꢀtype.ꢀTheꢀfull-pageꢀ
burstꢀisꢀusedꢀinꢀconjunctionꢀwithꢀtheꢀBURSTꢀTERMINATEꢀ
commandꢀtoꢀgenerateꢀarbitraryꢀburstꢀlengths.
Burst Type
Accessesꢀwithinꢀaꢀgivenꢀburstꢀmayꢀbeꢀprogrammedꢀtoꢀbeꢀ
eitherꢀsequentialꢀorꢀinterleaved;ꢀthisꢀisꢀreferredꢀtoꢀasꢀtheꢀ
burstꢀtypeꢀandꢀisꢀselectedꢀviaꢀbitꢀM3.
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀused,ꢀasꢀunknownꢀoperationꢀ
orꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
WhenꢀaꢀREADꢀorꢀWRITEꢀcommandꢀisꢀissued,ꢀaꢀblockꢀofꢀ
columnsꢀequalꢀtoꢀtheꢀburstꢀlengthꢀisꢀeffectivelyꢀselected.ꢀAllꢀ
accessesꢀforꢀthatꢀburstꢀtakeꢀplaceꢀwithinꢀthisꢀblock,ꢀmean-
Theꢀorderingꢀofꢀaccessesꢀwithinꢀaꢀburstꢀisꢀdeterminedꢀbyꢀ
theꢀburstꢀlength,ꢀtheꢀburstꢀtypeꢀandꢀtheꢀstartingꢀcolumnꢀ
address,ꢀasꢀshownꢀinꢀBURSTꢀDEFINITIONꢀtable.
BURST DEFINITION
Burst
Starting Column
Address
Order of Accesses Within a Burst
Length
Type = Sequential
Type = Interleaved
A0
ꢀ
ꢀ
2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
1ꢀ
ꢀ
ꢀ
0-1ꢀ
1-0ꢀ
ꢀ
ꢀ
0-1
1-0
A1
0ꢀ
0ꢀ
1ꢀ
1ꢀ
A1
0ꢀ
0ꢀ
1ꢀ
ꢀ1ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
A0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3ꢀ
1-2-3-0ꢀ
2-3-0-1ꢀ
3-0-1-2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
1ꢀ
ꢀ
0ꢀ
ꢀ
ꢀ
1ꢀ
A2
0ꢀ
0ꢀ
0ꢀ
0ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
A0
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7ꢀ
1-2-3-4-5-6-7-0ꢀ
ꢀ2-3-4-5-6-7-0-1ꢀ
ꢀ3-4-5-6-7-0-1-2ꢀ
4-5-6-7-0-1-2-3ꢀ
5-6-7-0-1-2-3-4ꢀ
6-7-0-1-2-3-4-5ꢀ
7-0-1-2-3-4-5-6ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0-1-2-3-4-5-6-7
ꢀ1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NotꢀSupportedꢀ
1ꢀ
ꢀ
ꢀ0ꢀ
1ꢀ
8ꢀ
ꢀ
0ꢀ
ꢀ
1ꢀ
ꢀ
0ꢀ
ꢀ
1ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Fullꢀ
Pageꢀ
(y)ꢀ
nꢀ=ꢀA0-A7ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Cn,ꢀCnꢀ+ꢀ1,ꢀCnꢀ+ꢀ2ꢀ
Cnꢀ+ꢀ3,ꢀCnꢀ+ꢀ4...
…Cnꢀ-ꢀ1,
ꢀ
(locationꢀ0-y)ꢀ
ꢀ
ꢀ
Cn…
Integrated Silicon Solution, Inc. — www.issi.comꢀ
19
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
CAS Latency
Operating Mode
TheꢀCASꢀlatencyꢀisꢀtheꢀdelay,ꢀinꢀclockꢀcycles,ꢀbetweenꢀ
theꢀregistrationꢀofꢀaꢀREADꢀcommandꢀandꢀtheꢀavailabilityꢀofꢀ
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ
threeꢀclocks.
TheꢀnormalꢀoperatingꢀmodeꢀisꢀselectedꢀbyꢀsettingꢀM7ꢀandꢀM8ꢀ
toꢀzero;ꢀtheꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀM7ꢀandꢀM8ꢀareꢀ
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀ
theꢀlatencyꢀisꢀm clocks,ꢀtheꢀdataꢀwillꢀbeꢀavailableꢀbyꢀclockꢀ
edgeꢀn + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ
clockꢀedgeꢀoneꢀcycleꢀearlierꢀ(n + m -ꢀ1),ꢀandꢀprovidedꢀthatꢀ
theꢀrelevantꢀaccessꢀtimesꢀareꢀmet,ꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀ
clockꢀedgeꢀn + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ
cycleꢀtimeꢀisꢀsuchꢀthatꢀallꢀrelevantꢀaccessꢀtimesꢀareꢀmet,ꢀ
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ
isꢀprogrammedꢀtoꢀtwoꢀclocks,ꢀtheꢀDQsꢀwillꢀstartꢀdrivingꢀ
afterꢀT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ
Latencyꢀdiagrams.ꢀTheꢀAllowable Operating Frequencyꢀ
tableꢀindicatesꢀtheꢀoperatingꢀfrequenciesꢀatꢀwhichꢀeachꢀ
CASꢀlatencyꢀsettingꢀcanꢀbeꢀused.
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-
causeꢀ unknownꢀ operationꢀ orꢀ incompatibilityꢀ withꢀ futureꢀ
versionsꢀmayꢀresult.
Write Burst Mode
WhenꢀM9ꢀ=ꢀ0,ꢀtheꢀburstꢀlengthꢀprogrammedꢀviaꢀM0-M2ꢀ
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ
theꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀ
writeꢀaccessesꢀareꢀsingle-locationꢀ(nonburst)ꢀaccesses.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀ
orꢀincompatibilityꢀwithꢀfutureꢀversionsꢀmayꢀresult.
5
6
7
133
133
133
200
166
143
CAS Latency
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 3
DON'T CARE
UNDEFINED
20ꢀ
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OPERATION
Activating Specific Row Within Specific Bank
BANK/ROW ACTIVATION
BeforeꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀcanꢀbeꢀissuedꢀ
toꢀaꢀbankꢀwithinꢀtheꢀSDRAM,ꢀaꢀrowꢀinꢀthatꢀbankꢀmustꢀbeꢀ
“opened.”ꢀThisꢀisꢀaccomplishedꢀviaꢀtheꢀACTIVEꢀcommand,ꢀ
whichꢀselectsꢀbothꢀtheꢀbankꢀandꢀtheꢀrowꢀtoꢀbeꢀactivatedꢀ
(seeꢀActivatingꢀSpecificꢀRowꢀWithinꢀSpecificꢀBank).
CLK
HIGH
CKE
CS
RAS
CAS
WE
Afterꢀopeningꢀaꢀrowꢀ(issuingꢀanꢀACTIVEꢀcommand),ꢀaꢀREADꢀ
orꢀWRITEꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀthatꢀrow,ꢀsubjectꢀtoꢀ
theꢀtrcdꢀspecification.ꢀMinimumꢀtrcdꢀshouldꢀbeꢀdividedꢀbyꢀ
theꢀclockꢀperiodꢀandꢀroundedꢀupꢀtoꢀtheꢀnextꢀwholeꢀnumberꢀ
toꢀ determineꢀ theꢀ earliestꢀ clockꢀ edgeꢀ afterꢀ theꢀ ACTIVEꢀ
commandꢀonꢀwhichꢀaꢀREADꢀorꢀWRITEꢀcommandꢀcanꢀbeꢀ
entered.ꢀForꢀexample,ꢀaꢀtrcdꢀspecificationꢀofꢀ20nsꢀwithꢀaꢀ
125ꢀMHzꢀclockꢀ(8nsꢀperiod)ꢀresultsꢀinꢀ2.5ꢀclocks,ꢀroundedꢀ
toꢀ3.ꢀThisꢀisꢀreflectedꢀinꢀtheꢀfollowingꢀexample,ꢀwhichꢀcov-
ersꢀanyꢀcaseꢀwhereꢀ2ꢀ<ꢀ[trcdꢀ(MIN)/tck]ꢀ≤ꢀ3.ꢀ(Theꢀsameꢀ
procedureꢀisꢀusedꢀtoꢀconvertꢀotherꢀspecificationꢀlimitsꢀfromꢀ
timeꢀunitsꢀtoꢀclockꢀcycles).
A0-A11
BA0,BA1
ROW ADDRESS
BANK ADDRESS
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀaꢀdifferentꢀrowꢀinꢀtheꢀ
sameꢀbankꢀcanꢀonlyꢀbeꢀissuedꢀafterꢀtheꢀpreviousꢀactiveꢀ
rowꢀhasꢀbeenꢀ“closed”ꢀ(precharged).ꢀTheꢀminimumꢀtimeꢀ
intervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀtheꢀ
sameꢀbankꢀisꢀdefinedꢀbyꢀtrc.
AꢀsubsequentꢀACTIVEꢀcommandꢀtoꢀanotherꢀbankꢀcanꢀbeꢀ
issuedꢀwhileꢀtheꢀfirstꢀbankꢀisꢀbeingꢀaccessed,ꢀwhichꢀresultsꢀ
inꢀaꢀreductionꢀofꢀtotalꢀrow-accessꢀoverhead.ꢀTheꢀminimumꢀ
timeꢀintervalꢀbetweenꢀsuccessiveꢀACTIVEꢀcommandsꢀtoꢀ
differentꢀbanksꢀisꢀdefinedꢀbyꢀtrrd.
Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] ≤ 3
T0
T1
T2
T3
T4
CLK
READ or
WRITE
ACTIVE
NOP
NOP
COMMAND
t
RCD
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21
Rev. I
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sameꢀbank.TheꢀPRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀ
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READS
READ COMMAND
READꢀ burstsꢀ areꢀ initiatedꢀ withꢀ aꢀ READꢀ command,ꢀ asꢀ
shownꢀinꢀtheꢀREADꢀCOMMANDꢀdiagram.
CLK
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀREADꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀorꢀ
disabledꢀforꢀthatꢀburstꢀaccess.ꢀIfꢀautoꢀprechargeꢀisꢀenabled,ꢀ
theꢀrowꢀbeingꢀaccessedꢀisꢀprechargedꢀatꢀtheꢀcompletionꢀofꢀ
theꢀburst.ꢀForꢀtheꢀgenericꢀREADꢀcommandsꢀusedꢀinꢀtheꢀfol-
lowingꢀillustrations,ꢀautoꢀprechargeꢀisꢀdisabled.
HIGH
CKE
CS
RAS
DuringꢀREADꢀbursts,ꢀtheꢀvalidꢀdata-outꢀelementꢀfromꢀtheꢀ
startingꢀ columnꢀ addressꢀ willꢀ beꢀ availableꢀ followingꢀ theꢀ
CASꢀlatencyꢀafterꢀtheꢀREADꢀcommand.ꢀEachꢀsubsequentꢀ
data-outꢀelementꢀwillꢀbeꢀvalidꢀbyꢀtheꢀnextꢀpositiveꢀclockꢀ
edge.ꢀTheꢀCASꢀLatencyꢀdiagramꢀshowsꢀgeneralꢀtimingꢀ
forꢀeachꢀpossibleꢀCASꢀlatencyꢀsetting.
CAS
WE
COLUMN ADDRESS
AUTO PRECHARGE
Uponꢀcompletionꢀofꢀaꢀburst,ꢀassumingꢀnoꢀotherꢀcommandsꢀ
haveꢀbeenꢀinitiated,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Z.ꢀAꢀfull-pageꢀburstꢀ
willꢀcontinueꢀuntilꢀterminated.ꢀ(Atꢀtheꢀendꢀofꢀtheꢀpage,ꢀitꢀwillꢀ
wrapꢀtoꢀcolumnꢀ0ꢀandꢀcontinue.)
A0-A7
A8,A9,A11
A10
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀREADꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
READꢀcommand.ꢀInꢀeitherꢀcase,ꢀaꢀcontinuousꢀflowꢀofꢀdataꢀ
canꢀbeꢀmaintained.ꢀTheꢀfirstꢀdataꢀelementꢀfromꢀtheꢀnewꢀ
burstꢀfollowsꢀeitherꢀtheꢀlastꢀelementꢀofꢀaꢀcompletedꢀburstꢀ
orꢀtheꢀlastꢀdesiredꢀdataꢀelementꢀofꢀaꢀlongerꢀburstꢀwhichꢀ
isꢀbeingꢀtruncated.
NO PRECHARGE
BANK ADDRESS
BA0, BA1
TheꢀDQMꢀinputꢀisꢀusedꢀtoꢀavoidꢀI/Oꢀcontention,ꢀasꢀshownꢀ
inꢀFiguresꢀRW1ꢀandꢀRW2.ꢀTheꢀDQMꢀsignalꢀmustꢀbeꢀas-
sertedꢀ(HIGH)ꢀatꢀleastꢀthreeꢀclocksꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀtwoꢀclocksꢀforꢀoutputꢀbuffers)ꢀ
toꢀsuppressꢀdata-outꢀfromꢀtheꢀREAD.ꢀOnceꢀtheꢀWRITEꢀ
commandꢀisꢀregistered,ꢀtheꢀDQsꢀwillꢀgoꢀHigh-Zꢀ(orꢀremainꢀ
High-Z),ꢀregardlessꢀofꢀtheꢀstateꢀofꢀtheꢀDQMꢀsignal,ꢀprovidedꢀ
theꢀDQMꢀwasꢀactiveꢀonꢀtheꢀclockꢀjustꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀthatꢀtruncatedꢀtheꢀREADꢀcommand.ꢀIfꢀnot,ꢀtheꢀ
secondꢀWRITEꢀwillꢀbeꢀanꢀinvalidꢀWRITE.ꢀForꢀexample,ꢀifꢀ
DQMꢀwasꢀLOWꢀduringꢀT4ꢀinꢀFigureꢀRW2,ꢀthenꢀtheꢀWRITEsꢀ
atꢀT5ꢀandꢀT7ꢀwouldꢀbeꢀvalid,ꢀwhileꢀtheꢀWRITEꢀatꢀT6ꢀwouldꢀ
beꢀinvalid.
TheꢀnewꢀREADꢀcommandꢀshouldꢀbeꢀissuedꢀxcyclesꢀbeforeꢀ
theꢀclockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀdataꢀelementꢀisꢀ
valid,ꢀwhereꢀx equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀConsecutiveꢀREADꢀBurstsꢀforꢀCASꢀlatenciesꢀofꢀ
twoꢀandꢀthree;ꢀdataꢀelementꢀn +ꢀ3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀ
burstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀTheꢀ64Mbꢀ
SDRAMꢀusesꢀaꢀpipelinedꢀarchitectureꢀandꢀthereforeꢀdoesꢀ
notꢀrequireꢀtheꢀ2n ruleꢀassociatedꢀwithꢀaꢀprefetchꢀarchitec-
ture.ꢀAꢀREADꢀcommandꢀcanꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀ
followingꢀaꢀpreviousꢀREADꢀcommand.ꢀFull-speedꢀrandomꢀ
readꢀaccessesꢀcanꢀbeꢀperformedꢀtoꢀtheꢀsameꢀbank,ꢀasꢀ
shownꢀinꢀRandomꢀREADꢀAccesses,ꢀorꢀeachꢀsubsequentꢀ
READꢀmayꢀbeꢀperformedꢀtoꢀaꢀdifferentꢀbank.
TheꢀDQMꢀsignalꢀmustꢀbeꢀde-assertedꢀpriorꢀtoꢀtheꢀWRITEꢀ
commandꢀ(DQMꢀlatencyꢀisꢀzeroꢀclocksꢀforꢀinputꢀbuffers)ꢀ
toꢀensureꢀthatꢀtheꢀwrittenꢀdataꢀisꢀnotꢀmasked.ꢀ
DataꢀfromꢀanyꢀREADꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsub-
sequentꢀWRITEꢀcommand,ꢀandꢀdataꢀfromꢀaꢀfixed-lengthꢀ
READꢀburstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀfromꢀaꢀ
WRITEꢀcommandꢀ(subjectꢀtoꢀbusꢀturnaroundꢀlimitations).ꢀ
TheꢀWRITEꢀburstꢀmayꢀbeꢀinitiatedꢀonꢀtheꢀclockꢀedgeꢀim-
mediatelyꢀfollowingꢀtheꢀlastꢀ(orꢀlastꢀdesired)ꢀdataꢀelementꢀ
fromꢀtheꢀREADꢀburst,ꢀprovidedꢀthatꢀI/Oꢀcontentionꢀcanꢀbeꢀ
avoided.ꢀInꢀaꢀgivenꢀsystemꢀdesign,ꢀthereꢀmayꢀbeꢀaꢀpos-
sibilityꢀthatꢀtheꢀdeviceꢀdrivingꢀtheꢀinputꢀdataꢀwillꢀgoꢀLow-Zꢀ
beforeꢀtheꢀSDRAMꢀDQsꢀgoꢀHigh-Z.ꢀInꢀthisꢀcase,ꢀatꢀleastꢀ
aꢀsingle-cycleꢀdelayꢀshouldꢀoccurꢀbetweenꢀtheꢀlastꢀreadꢀ
dataꢀandꢀtheꢀWRITEꢀcommand.
Aꢀfixed-lengthꢀREADꢀburstꢀmayꢀbeꢀfollowedꢀby,ꢀorꢀtruncatedꢀ
with,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbankꢀ(providedꢀ
thatꢀautoꢀprechargeꢀwasꢀnotꢀactivated),ꢀandꢀaꢀfull-pageꢀburstꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
x cyclesꢀbeforeꢀtheꢀclockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀ
dataꢀelementꢀisꢀvalid,ꢀwhereꢀx equalsꢀtheꢀCASꢀlatencyꢀ
minusꢀone.ꢀThisꢀisꢀshownꢀinꢀtheꢀREADꢀtoꢀPRECHARGEꢀ
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providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀactivated.TheꢀBURSTꢀ
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diagramꢀforꢀeachꢀpossibleꢀCASꢀlatency;ꢀdataꢀelementꢀn +ꢀ
3ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀfourꢀorꢀtheꢀlastꢀdesiredꢀofꢀ
aꢀlongerꢀburst.ꢀFollowingꢀtheꢀPRECHARGEꢀcommand,ꢀaꢀ
subsequentꢀcommandꢀtoꢀtheꢀsameꢀbankꢀcannotꢀbeꢀissuedꢀ
untilꢀtrpꢀisꢀmet.ꢀNoteꢀthatꢀpartꢀofꢀtheꢀrowꢀprechargeꢀtimeꢀisꢀ
hiddenꢀduringꢀtheꢀaccessꢀofꢀtheꢀlastꢀdataꢀelement(s).
Full-pageꢀREADꢀburstsꢀcanꢀbeꢀtruncatedꢀwithꢀtheꢀBURSTꢀ
TERMINATEꢀ command,ꢀ andꢀ fixed-lengthꢀ READꢀ burstsꢀ
mayꢀbeꢀtruncatedꢀwithꢀaꢀBURSTꢀTERMINATEꢀcommand,ꢀ
TERMINATEꢀcommandꢀshouldꢀbeꢀissuedꢀx cyclesꢀbeforeꢀ
theꢀclockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀdataꢀelementꢀisꢀ
valid,ꢀwhereꢀx equalsꢀtheꢀCASꢀlatencyꢀminusꢀone.ꢀThisꢀisꢀ
shownꢀinꢀtheꢀREADꢀBurstꢀTerminationꢀdiagramꢀforꢀeachꢀ
possibleꢀCASꢀlatency;ꢀdataꢀelementꢀn+ꢀ3ꢀisꢀtheꢀlastꢀdesiredꢀ
dataꢀelementꢀofꢀaꢀlongerꢀburst.
Inꢀ theꢀ caseꢀ ofꢀ aꢀ fixed-lengthꢀ burstꢀ beingꢀ executedꢀ toꢀ
completion,ꢀ aꢀ PRECHARGEꢀ commandꢀ issuedꢀ atꢀ theꢀ
optimumꢀtimeꢀ(asꢀdescribedꢀabove)ꢀprovidesꢀtheꢀsameꢀ
operationꢀ thatꢀ wouldꢀ resultꢀ fromꢀ theꢀ sameꢀ fixed-lengthꢀ
burstꢀwithꢀautoꢀprecharge.ꢀTheꢀdisadvantageꢀofꢀtheꢀPRE-
CHARGEꢀcommandꢀisꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀ
andꢀaddressꢀbusesꢀbeꢀavailableꢀatꢀtheꢀappropriateꢀtimeꢀtoꢀ
issueꢀtheꢀcommand;ꢀtheꢀadvantageꢀofꢀtheꢀPRECHARGEꢀ
commandꢀisꢀthatꢀitꢀcanꢀbeꢀusedꢀtoꢀtruncateꢀfixed-lengthꢀ
orꢀfull-pageꢀbursts.
CAS Latency
T0
T1
T2
T3
CLK
READ
NOP
NOP
COMMAND
DQ
t
AC
D
OUT
OH
t
LZ
t
CAS Latency - 2
T0
T1
T2
T3
T4
CLK
READ
NOP
NOP
NOP
COMMAND
DQ
tAC
D
OUT
OH
t
LZ
t
CAS Latency - 3
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Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
READ
NOP
NOP
x=1cycle
BANK,
COL n
BANK,
COL b
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
D
OUT
b
CAS Latency - 3
DON'T CARE
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Rev. I
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Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
D
OUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DOUT
n
DOUT
b
DOUT
m
DOUT
x
CAS Latency - 3
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RW1 - READ to WRITE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT n+1
DOUT n+2
D
OUT
n
DIN b
CAS Latency - 2
t
DS
DON'T CARE
RW2 - READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
WRITE
BANK,
COL n
BANK,
COL b
t
HZ
DOUT
n
DIN
b
CAS Latency - 3
t
DS
DON'T CARE
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READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
x=1cycle
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
t
RP
PRECHARGE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
ACTIVE
BANK,
COL n
BANK,
COL b
BANK a,
ROW
DOUT
n
DOUT n+1
D
OUT n+2
DOUT n+3
CAS Latency - 3
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READ Burst Termination
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
x=1cycle
BANK a,
COL n
D
OUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 2
DON'T CARE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
x = 2 cycles
NOP
NOP
BANK,
COL n
DOUT
n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency - 3
DON'T CARE
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precharge.TheꢀdisadvantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀ
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AnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀWRITEꢀdiagram.ꢀDataꢀ
n +ꢀ1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀ
ofꢀaꢀlongerꢀburst.ꢀTheꢀ64MbꢀSDRAMꢀ usesꢀ aꢀ pipelinedꢀ
architectureꢀandꢀthereforeꢀdoesꢀnotꢀrequireꢀtheꢀ2n ruleꢀas-
sociatedꢀwithꢀaꢀprefetchꢀarchitecture.ꢀAꢀWRITEꢀcommandꢀ
canꢀbeꢀinitiatedꢀonꢀanyꢀclockꢀcycleꢀfollowingꢀaꢀpreviousꢀ
WRITEꢀcommand.ꢀFull-speedꢀrandomꢀwriteꢀaccessesꢀwithinꢀ
aꢀpageꢀcanꢀbeꢀperformedꢀtoꢀtheꢀsameꢀbank,ꢀasꢀshownꢀinꢀ
RandomꢀWRITEꢀCycles,ꢀorꢀeachꢀsubsequentꢀWRITEꢀmayꢀ
beꢀperformedꢀtoꢀaꢀdifferentꢀbank.
WRITEs
WRITEꢀburstsꢀareꢀinitiatedꢀwithꢀaꢀWRITEꢀcommand,ꢀasꢀ
shownꢀinꢀWRITEꢀCommandꢀdiagram.
WRITE Command
CLK
HIGH
CKE
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀREADꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀaꢀsubsequentꢀREADꢀ
command.ꢀOnceꢀtheꢀREADꢀcommandꢀisꢀregistered,ꢀtheꢀ
dataꢀinputsꢀwillꢀbeꢀignored,ꢀandꢀWRITEsꢀwillꢀnotꢀbeꢀex-
ecuted.ꢀAnꢀexampleꢀisꢀshownꢀinꢀWRITEꢀtoꢀREAD.ꢀDataꢀn
+ꢀ1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀ
ofꢀaꢀlongerꢀburst.
CS
RAS
CAS
WE
Dataꢀ forꢀ aꢀ fixed-lengthꢀ WRITEꢀ burstꢀ mayꢀ beꢀ followedꢀ
by,ꢀorꢀtruncatedꢀwith,ꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀ
sameꢀbankꢀ(providedꢀthatꢀautoꢀprechargeꢀwasꢀnotꢀacti-
vated),ꢀandꢀaꢀfull-pageꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀ
withꢀaꢀPRECHARGEꢀcommandꢀtoꢀtheꢀsameꢀbank.ꢀTheꢀ
PRECHARGEꢀcommandꢀshouldꢀbeꢀissuedꢀtwrꢀafterꢀtheꢀ
clockꢀedgeꢀatꢀwhichꢀtheꢀlastꢀdesiredꢀinputꢀdataꢀelementꢀ
isꢀregistered.ꢀTheꢀautoꢀprechargeꢀmodeꢀrequiresꢀaꢀtwrꢀofꢀ
atꢀleastꢀoneꢀclockꢀplusꢀtime,ꢀregardlessꢀofꢀfrequency.ꢀInꢀ
addition,ꢀwhenꢀtruncatingꢀaꢀWRITEꢀburst,ꢀtheꢀDQMꢀsignalꢀ
mustꢀbeꢀusedꢀtoꢀmaskꢀinputꢀdataꢀforꢀtheꢀclockꢀedgeꢀpriorꢀ
to,ꢀandꢀtheꢀclockꢀedgeꢀcoincidentꢀwith,ꢀtheꢀPRECHARGEꢀ
command.ꢀAnꢀexampleꢀisꢀshownꢀinꢀtheꢀWRITEꢀtoꢀPRE-
CHARGEꢀdiagram.ꢀDataꢀn+1ꢀisꢀeitherꢀtheꢀlastꢀofꢀaꢀburstꢀ
ofꢀtwoꢀorꢀtheꢀlastꢀdesiredꢀofꢀaꢀlongerꢀburst.ꢀFollowingꢀtheꢀ
PRECHARGEꢀcommand,ꢀaꢀsubsequentꢀcommandꢀtoꢀtheꢀ
sameꢀbankꢀcannotꢀbeꢀissuedꢀuntilꢀtrpꢀisꢀmet.
COLUMN ADDRESS
AUTO PRECHARGE
A0-A7
A8,A9,A11
A10
NO PRECHARGE
BANK ADDRESS
BA0, BA1
Theꢀstartingꢀcolumnꢀandꢀbankꢀaddressesꢀareꢀprovidedꢀwithꢀ
theꢀWRITEꢀcommand,ꢀandꢀautoꢀprechargeꢀisꢀeitherꢀenabledꢀ
orꢀdisabledꢀforꢀthatꢀaccess.ꢀIfꢀautoꢀprechargeꢀisꢀenabled,ꢀ
theꢀrowꢀbeingꢀaccessedꢀisꢀprechargedꢀatꢀtheꢀcompletionꢀofꢀ
theꢀburst.ꢀForꢀtheꢀgenericꢀWRITEꢀcommandsꢀusedꢀinꢀtheꢀ
followingꢀillustrations,ꢀautoꢀprechargeꢀisꢀdisabled.
Inꢀtheꢀcaseꢀofꢀaꢀfixed-lengthꢀburstꢀbeingꢀexecutedꢀtoꢀcomple-
tion,ꢀaꢀPRECHARGEꢀcommandꢀissuedꢀatꢀtheꢀoptimumꢀ
timeꢀ(asꢀdescribedꢀabove)ꢀprovidesꢀtheꢀsameꢀoperationꢀthatꢀ
wouldꢀresultꢀfromꢀtheꢀsameꢀfixed-lengthꢀburstꢀwithꢀautoꢀ
DuringꢀWRITEꢀbursts,ꢀtheꢀfirstꢀvalidꢀdata-inꢀelementꢀwillꢀbeꢀ
registeredꢀcoincidentꢀwithꢀtheꢀWRITEꢀcommand.ꢀSubsequentꢀ
dataꢀelementsꢀwillꢀbeꢀregisteredꢀonꢀeachꢀsuccessiveꢀposi-
tiveꢀclockꢀedge.ꢀUponꢀcompletionꢀofꢀaꢀfixed-lengthꢀburst,ꢀ
assumingꢀnoꢀotherꢀcommandsꢀhaveꢀbeenꢀinitiated,ꢀtheꢀ
DQsꢀwillꢀremainꢀHigh-Zꢀandꢀanyꢀadditionalꢀinputꢀdataꢀwillꢀ
beꢀignoredꢀ(seeꢀWRITEꢀBurst).ꢀAꢀfull-pageꢀburstꢀwillꢀcon-
tinueꢀuntilꢀterminated.ꢀ(Atꢀtheꢀendꢀofꢀtheꢀpage,ꢀitꢀwillꢀwrapꢀ
toꢀcolumnꢀ0ꢀandꢀcontinue.)
isꢀthatꢀitꢀrequiresꢀthatꢀtheꢀcommandꢀandꢀaddressꢀbusesꢀbeꢀ
availableꢀatꢀtheꢀappropriateꢀtimeꢀtoꢀissueꢀtheꢀcommand;ꢀtheꢀ
advantageꢀofꢀtheꢀPRECHARGEꢀcommandꢀisꢀthatꢀitꢀcanꢀbeꢀ
usedꢀtoꢀtruncateꢀfixed-lengthꢀorꢀfull-pageꢀbursts.
Fixed-lengthꢀorꢀfull-pageꢀWRITEꢀburstsꢀcanꢀbeꢀtruncatedꢀ
withꢀtheꢀBURSTꢀTERMINATEꢀcommand.ꢀWhenꢀtruncat-
ingꢀaꢀWRITEꢀburst,ꢀtheꢀinputꢀdataꢀappliedꢀcoincidentꢀwithꢀ
theꢀBURSTꢀTERMINATEꢀcommandꢀwillꢀbeꢀignored.ꢀTheꢀ
lastꢀdataꢀwrittenꢀ(providedꢀthatꢀDQMꢀisꢀLOWꢀatꢀthatꢀtime)ꢀ
willꢀbeꢀtheꢀinputꢀdataꢀappliedꢀoneꢀclockꢀpreviousꢀtoꢀtheꢀ
BURSTꢀTERMINATEꢀcommand.ꢀThisꢀisꢀshownꢀinꢀWRITEꢀ
BurstꢀTermination,ꢀwhereꢀdataꢀn isꢀtheꢀlastꢀdesiredꢀdataꢀ
elementꢀofꢀaꢀlongerꢀburst.
DataꢀforꢀanyꢀWRITEꢀburstꢀmayꢀbeꢀtruncatedꢀwithꢀaꢀsubse-
quentꢀWRITEꢀcommand,ꢀandꢀdataꢀforꢀaꢀfixed-lengthꢀWRITEꢀ
burstꢀmayꢀbeꢀimmediatelyꢀfollowedꢀbyꢀdataꢀforꢀaꢀWRITEꢀ
command.ꢀTheꢀnewꢀWRITEꢀcommandꢀcanꢀbeꢀissuedꢀonꢀ
anyꢀclockꢀfollowingꢀtheꢀpreviousꢀWRITEꢀcommand,ꢀandꢀtheꢀ
dataꢀprovidedꢀcoincidentꢀwithꢀtheꢀnewꢀcommandꢀappliesꢀtoꢀ
theꢀnewꢀcommand.
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WRITE Burst
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
BANK,
COL n
DIN
n
DIN n+1
DON'T CARE
WRITE to WRITE
T0
T1
T2
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
DIN b
DON'T CARE
Random WRITE Cycles
T0
T1
T2
T3
CLK
COMMAND
ADDRESS
DQ
WRITE
WRITE
WRITE
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL m
BANK,
COL x
DIN
n
DIN
b
DIN
m
DIN x
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WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
WRITE
NOP
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL b
DIN
n
DIN n+1
D
OUT
b
DOUT b+1
CAS Latency - 2
DON'T CARE
WP1 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
t
RP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
ACTIVE
NOP
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
WR
DIN
n
DIN n+1
CAS Latency - 2
DON'T CARE
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WP2 - WRITE to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
tRP
PRECHARGE
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
ACTIVE
NOP
BANK a,
COL n
BANK
BANK a,
ROW
(a or all)
t
WR
DIN
n
D
IN n+1
CAS Latency - 3
DON'T CARE
WRITE Burst Termination
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
ADDRESS
DQ
WRITE
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
DON'T CARE
32ꢀ
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allꢀbanks.Theꢀbank(s)ꢀwillꢀbeꢀavailableꢀforꢀaꢀsubsequentꢀrowꢀ
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PRECHARGE
PRECHARGE Command
TheꢀPRECHARGEꢀcommandꢀ(seeꢀfigure)ꢀisꢀusedꢀtoꢀdeac-
tivateꢀtheꢀopenꢀrowꢀinꢀaꢀparticularꢀbankꢀorꢀtheꢀopenꢀrowꢀinꢀ
CLK
HIGH
accessꢀsomeꢀspecifiedꢀtimeꢀ(trp)ꢀafterꢀtheꢀPRECHARGEꢀ
commandꢀisꢀissued.ꢀInputꢀA10ꢀdeterminesꢀwhetherꢀoneꢀorꢀ
allꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀandꢀinꢀtheꢀcaseꢀwhereꢀonlyꢀ
oneꢀbankꢀisꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀBA1ꢀselectꢀtheꢀ
bank.ꢀWhenꢀallꢀbanksꢀareꢀtoꢀbeꢀprecharged,ꢀinputsꢀBA0,ꢀ
BA1ꢀareꢀtreatedꢀasꢀ“Don’tꢀCare.”ꢀOnceꢀaꢀbankꢀhasꢀbeenꢀ
precharged,ꢀitꢀisꢀinꢀtheꢀidleꢀstateꢀandꢀmustꢀbeꢀactivatedꢀ
priorꢀtoꢀanyꢀREADꢀorꢀWRITEꢀcommandsꢀbeingꢀissuedꢀtoꢀ
thatꢀbank.
CKE
CS
RAS
CAS
WE
POWER-DOWN
A0-A9,A11
ALL BANKS
Power-downꢀoccursꢀifꢀCKEꢀisꢀregisteredꢀLOWꢀcoincidentꢀ
withꢀaꢀNOPꢀorꢀCOMMANDꢀINHIBITꢀwhenꢀnoꢀaccessesꢀ
areꢀinꢀprogress.ꢀIfꢀpower-downꢀoccursꢀwhenꢀallꢀbanksꢀareꢀ
idle,ꢀthisꢀmodeꢀisꢀreferredꢀtoꢀasꢀprechargeꢀpower-down;ꢀ
ifꢀpower-downꢀoccursꢀwhenꢀthereꢀisꢀaꢀrowꢀactiveꢀinꢀeitherꢀ
bank,ꢀ thisꢀ modeꢀ isꢀ referredꢀ toꢀ asꢀ activeꢀ power-down.ꢀ
Enteringꢀ power-downꢀ deactivatesꢀ theꢀ inputꢀ andꢀ outputꢀ
buffers,ꢀexcludingꢀCKE,ꢀforꢀmaximumꢀpowerꢀsavingsꢀwhileꢀ
inꢀstandby.ꢀTheꢀdeviceꢀmayꢀnotꢀremainꢀinꢀtheꢀpower-downꢀ
stateꢀlongerꢀthanꢀtheꢀrefreshꢀperiodꢀ(64ms)ꢀsinceꢀnoꢀrefreshꢀ
operationsꢀareꢀperformedꢀinꢀthisꢀmode.
A10
BANK SELECT
BANK ADDRESS
BA0, BA1
Theꢀpower-downꢀstateꢀisꢀexitedꢀbyꢀregisteringꢀaꢀNOPꢀorꢀ
COMMANDꢀINHIBITꢀandꢀCKEꢀHIGHꢀatꢀtheꢀdesiredꢀclockꢀ
edgeꢀ(meetingꢀtcks).ꢀSeeꢀfigureꢀbelow.
POWER-DOWN
CLK
t
CKS
≥ tCKS
CKE
COMMAND
NOP
NOP
ACTIVE
tRCD
tRAS
t
RC
All banks idle
Input buffers gated off
Enter power-down mode
Exit power-down mode
DON'T CARE
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CLOCK SUSPEND
ofꢀaꢀsuspendedꢀinternalꢀclockꢀedgeꢀisꢀignored;ꢀanyꢀdataꢀ
presentꢀonꢀtheꢀDQꢀpinsꢀremainsꢀdriven;ꢀandꢀburstꢀcountersꢀ
areꢀnotꢀincremented,ꢀasꢀlongꢀasꢀtheꢀclockꢀisꢀsuspended.ꢀ
(Seeꢀfollowingꢀexamples.)
Clockꢀsuspendꢀmodeꢀoccursꢀwhenꢀaꢀcolumnꢀaccess/burstꢀ
isꢀinꢀprogressꢀandꢀCKEꢀisꢀregisteredꢀLOW.ꢀInꢀtheꢀclockꢀ
suspendꢀmode,ꢀtheꢀinternalꢀclockꢀisꢀdeactivated,ꢀ“freezing”ꢀ
theꢀsynchronousꢀlogic.
ClockꢀsuspendꢀmodeꢀisꢀexitedꢀbyꢀregisteringꢀCKEꢀHIGH;ꢀ
theꢀinternalꢀclockꢀandꢀrelatedꢀoperationꢀwillꢀresumeꢀonꢀtheꢀ
subsequentꢀpositiveꢀclockꢀedge.
ForꢀeachꢀpositiveꢀclockꢀedgeꢀonꢀwhichꢀCKEꢀisꢀsampledꢀ
LOW,ꢀtheꢀnextꢀinternalꢀpositiveꢀclockꢀedgeꢀisꢀsuspended.ꢀ
Anyꢀcommandꢀorꢀdataꢀpresentꢀonꢀtheꢀinputꢀpinsꢀatꢀtheꢀtimeꢀ
Clock Suspend During WRITE Burst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
BANK a,
COL n
DIN
n
DIN n+1
DIN n+2
DON'T CARE
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DQ
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
DOUT
n
D
OUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
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BURST READ/SINGLE WRITE
Theꢀburstꢀread/singleꢀwriteꢀmodeꢀisꢀenteredꢀbyꢀprogrammingꢀ
theꢀwriteꢀburstꢀmodeꢀbitꢀ(M9)ꢀinꢀtheꢀmodeꢀregisterꢀtoꢀaꢀlogicꢀ
1.ꢀInꢀthisꢀmode,ꢀallꢀWRITEꢀcommandsꢀresultꢀinꢀtheꢀaccessꢀ
ofꢀaꢀsingleꢀcolumnꢀlocationꢀ(burstꢀofꢀone),ꢀregardlessꢀofꢀ
theꢀprogrammedꢀburstꢀlength.ꢀREADꢀcommandsꢀaccessꢀ
columnsꢀaccordingꢀtoꢀtheꢀprogrammedꢀburstꢀlengthꢀandꢀ
sequence,ꢀjustꢀasꢀinꢀtheꢀnormalꢀmodeꢀofꢀoperationꢀ(M9ꢀ
=ꢀ0).
SDRAMsꢀsupportꢀCONCURRENTꢀAUTOꢀPRECHARGE.ꢀ
FourꢀcasesꢀwhereꢀCONCURRENTꢀAUTOꢀPRECHARGEꢀ
occursꢀareꢀdefinedꢀbelow.
READ with Auto Precharge
1.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀn,ꢀ
CASꢀlatencyꢀlater.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀ
beginꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀregistered.
CONCURRENT AUTO PRECHARGE
2.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀWRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀREADꢀonꢀbankꢀnꢀ
whenꢀregistered.ꢀDQMꢀshouldꢀbeꢀusedꢀtwoꢀclocksꢀpriorꢀ
toꢀtheꢀWRITEꢀcommandꢀtoꢀpreventꢀbusꢀcontention.ꢀTheꢀ
PRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀwhenꢀtheꢀWRITEꢀtoꢀ
bankꢀmꢀisꢀregistered.
Anꢀaccessꢀcommandꢀ(READꢀorꢀWRITE)ꢀtoꢀanotherꢀbankꢀ
whileꢀanꢀaccessꢀcommandꢀwithꢀautoꢀprechargeꢀenabledꢀisꢀ
executingꢀisꢀnotꢀallowedꢀbyꢀSDRAMs,ꢀunlessꢀtheꢀSDRAMꢀ
supportsꢀ CONCURRENTꢀ AUTOꢀ PRECHARGE.ꢀ ISSIꢀ
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
BANK n
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
RP - BANK n
tRP -BANKm
Internal States
BANK m
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
D
OUT
a
DOUT a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
Idle
BANK n
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
Page Active
tRP - BANK n
tRP -BANKm
Internal States
BANK m
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQM
DQ
D
OUT
a
DIN
b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
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WRITE with Auto Precharge
3.ꢀInterruptedꢀbyꢀaꢀREADꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
AꢀREADꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀ
4.ꢀInterruptedꢀbyꢀaꢀWRITEꢀ(withꢀorꢀwithoutꢀautoꢀprecharge):ꢀ
WRITEꢀtoꢀbankꢀmꢀwillꢀinterruptꢀaꢀWRITEꢀonꢀbankꢀnꢀwhenꢀ
A
registered.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀ
twrꢀisꢀmet,ꢀwhereꢀtwrꢀbeginsꢀwhenꢀtheꢀWRITEꢀtoꢀbankꢀ
mꢀisꢀregistered.ꢀTheꢀlastꢀvalidꢀdataꢀWRITEꢀtoꢀbankꢀnꢀ
willꢀbeꢀdataꢀregisteredꢀoneꢀclockꢀpriorꢀtoꢀaꢀWRITEꢀtoꢀ
bankꢀm.
whenꢀregistered,ꢀwithꢀtheꢀdata-outꢀappearingꢀCASꢀlatency
ꢀ
later.ꢀTheꢀPRECHARGEꢀtoꢀbankꢀnꢀwillꢀbeginꢀafterꢀtwrꢀ
isꢀmet,ꢀwhereꢀtwrꢀbeginsꢀwhenꢀtheꢀREADꢀtoꢀbankꢀmꢀisꢀ
registered.ꢀTheꢀlastꢀvalidꢀWRITEꢀtoꢀbankꢀnꢀwillꢀbeꢀdata-inꢀ
registeredꢀoneꢀclockꢀpriorꢀtoꢀtheꢀREADꢀtoꢀbankꢀm.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4 Interrupt Burst,Write-Back
WR - BANK n
Precharge
t
tRP - BANK n
Internal States
tRP -BANKm
BANK m
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DOUT
b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst,Write-Back
WR - BANK n
Precharge
t
t
RP - BANK n
Internal States
tRP -BANKm
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL b
ADDRESS
DQ
DIN
a
DIN a+1
DIN a+2
D
IN
b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
36ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
INITIALIꢀE AND LOAD MODE REGISTER(1)
T0
T1
Tn+1
tCH
To+1
tCL
Tp+1
Tp+2
Tp+3
tCK
CLK
CKE
tCKS tCKH
tCMS tCMH
tCMS tCMH
tCMS tCMH
AUTO
AUTO
Load MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVE
REFRESH
REFRESH
DQM/
DQML, DQMH
tAS tAH
A0-A9, A11
A10
ROW
ROW
BANK
CODE
tAS tAH
ALL BANKS
CODE
SINGLE BANK
ALLBANKS
BA0, BA1
DQ
tRP
tRC
tRC
tMRD
T
Power-up: VCC
Precharge AUTO REFRESH
AUTO REFRESH
Program MODE REGISTER(2, 3, 4)
and CLK stable all banks
At least 2 Auto-Refresh Commands
DON'T CARE
T = 100µs Min.
Notes:
1.ꢀꢀIfꢀCSꢀisꢀHighꢀatꢀclockꢀHighꢀtime,ꢀallꢀcommandsꢀappliedꢀareꢀNOP.
2.ꢀꢀTheꢀModeꢀregisterꢀmayꢀbeꢀloadedꢀpriorꢀtoꢀtheꢀAuto-Refreshꢀcyclesꢀifꢀdesired.
3.ꢀꢀJEDECꢀandꢀPC100ꢀspecifyꢀthreeꢀclocks.
4.ꢀꢀOutputsꢀareꢀguaranteedꢀHigh-Zꢀafterꢀtheꢀcommandꢀisꢀissued.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
37
Rev. I
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IS42S16400F
IS45S16400F
POWER-DOWN MODE CYCLE
T0
T1
T2
Tn+1
Tn+2
tCK
t
CL
t
CH
CLK
t
CKS
t
CKH
t
CKS
tCKS
CKE
tCMS
tCMH
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
ALL BANKS
SINGLE BANK
tAS
tAH
BA0, BA1
DQ
BANK
BANK
High-Z
Two clock cycles
Input buffers gated
All banks idle
off while in
power-down mode
Precharge all
active banks
All banks idle, enter
power-down mode
DON'T CARE
Exit power-down mode
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
38ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
CLOCK SUSPEND MODE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
tCKS
t
CKH
t
CKS
t
CKH
t
CMS
tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
CMS tCMH
DQM/
DQML, DQMH
tAS
tAH
COLUMN n(2)
A0-A9, A11
A10
COLUMN m(2)
tAS
t
AH
tAS
t
AH
BA0, BA1
BANK
BANK
tDS
tDH
tAC
t
AC
tHZ
DQ
D
OUT
m
DOUT m+1
DOUT e
D
OUT e+1
tLZ
tOH
DON'T CARE
UNDEFINED
Notes:
1.ꢀCASꢀꢀlatencyꢀ=ꢀ3,ꢀburstꢀlengthꢀ=ꢀ2
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
39
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
AUTO-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
tCK
t
CL
t
CH
CLK
t
CKS CKH
t
CKE
t
CMS
tCMH
Auto
Refresh
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ROW
ROW
BANK
ALL BANKS
SINGLE BANK
BANK(s)
BA0, BA1
DQ
tAS
tAH
High-Z
t
RP
t
RC
t
RC
DON'T CARE
CASꢀꢀlatencyꢀ=ꢀ2,ꢀ3
40ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
SELF-REFRESH CYCLE
T0
T1
T2
Tn+1
To+1
To+2
t
CK
tCH
t
CL
CLK
CKE
t
CKS
t
CKH
t
CKS
≥ tRAS
t
CKS
tCMS
tCMH
Auto
Auto
COMMAND
PRECHARGE
NOP
NOP
NOP
Refresh
Refresh
DQM/
DQML, DQMH
A0-A9, A11
A10
ALL BANKS
SINGLE BANK
t
AS
tAH
BA0, BA1
DQ
BANK
High-Z
tXSR
tRP
Precharge all
active banks
Enter self
refresh mode
CLK stable prior to exiting
Exit self refresh mode
(Restart refresh time base)
DON'T CARE
Note:
1.ꢀSelf-RefreshꢀModeꢀisꢀnotꢀsupportedꢀforꢀA2ꢀgradeꢀwithꢀTaꢀ>ꢀ85oC.ꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
41
Rev. I
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IS42S16400F
IS45S16400F
READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
t
CL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
ALL BANKS
NOP
ACTIVE
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ROW
AS
t
AH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BA0, BA1
DQ
BANK
BANK
t
AC
t
AC
tAC
tAC
tHZ
DOUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
tOH
tOH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
t
RP
UNDEFINED
Notes:
1.ꢀCASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
42ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
t
CKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
DQ
BANK
BANK
tAC
t
AC
t
AC
t
AC
tHZ
D
OUT
m
D
OUT m+1
D
OUT m+2
D
OUT m+3
t
LZ
t
OH
t
OH
tOH
tOH
tRCD
tRAS
t
RC
CAS Latency
DON'T CARE
tRP
UNDEFINED
Notes:
1.ꢀCASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
43
Rev. I
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IS42S16400F
IS45S16400F
SINGLE READ WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ALL BANKS
ROW
SINGLE BANK
BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BA0, BA1
DQ
BANK
BANK
t
OH
tAC
D
OUT m
t
LZ
tHZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1.ꢀCASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ1
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
44ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
SINGLE READ WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
NOP
NOP
READ
NOP
NOP
ACTIVE
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
ROW
ROW
BANK
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tOH
tAC
DOUT m
DQ
t
HZ
DON'T CARE
UNDEFINED
tRCD
tRAS
t
RC
CAS Latency
tRP
Notes:
1.ꢀCASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ1
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
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45
Rev. I
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IS42S16400F
IS45S16400F
ALTERNATING BANK READ ACCESSES
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCK
tCL
tCH
CLK
CKE
tCKS tCKH
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
tAS tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
tAS tAH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tAS tAH
BANK 0
BANK 3
BANK 3
BANK 0
BA0, BA1
BANK 0
t
LZ
t
OH
t
OH
tOH
tOH
t
OH
DQ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m+
3
D
OUT
b
tAC
tAC
tAC
tAC
tAC
tAC
tRCD - BANK 0
tRRD
CAS Latency - BANK 0
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 3
CAS Latency - BANK 3
tRAS - BANK 0
tRC - BANK 0
DON'T CARE
Notes:
1. CASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
46ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
READ - FULL-PAGE BURST
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
READ
CMS CMH
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
t
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
t
AH
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tAC
tAC
tAC
tAC
tAC
tAC
tHZ
D
OUT
m
D
OUT m+
1
D
OUT m+
2
D
OUT m-
1
D
OUT
m
D
OUT m+1
DQ
t
LZ
t
OH
tOH
t
OH
tOH
t
OH
tOH
tRCD
CAS Latency
each row (x4) has
1,024 locations
DON'T CARE
UNDEFINED
Full page Full-page burst not self-terminating.
completion Use BURST TERMINATE command.
Notes:
1.ꢀCASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀfullꢀpage
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
47
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
READ - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
OH
tOH
tOH
t
AC
tAC
D
OUT
m
D
OUT m+
2
D
OUT m+
3
DQ
t
LZ
tLZ
t
HZ
tAC
t
HZ
DON'T CARE
UNDEFINED
t
RCD
CAS Latency
Notes:
1.ꢀCASꢀꢀlatencyꢀ=ꢀ2,ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
48ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ALL BANKS
ROW
AS
t
AH
SINGLE BANK
BANK
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
tDS
t
DH
t
DS
t
DH
t
DS
tDH
tDS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
tRCD
tRAS
t
RC
t
WR(3)
t
RP
DON'T CARE
Notes:
1.ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
3.ꢀtrasꢀmustꢀnotꢀbeꢀviolated
Integrated Silicon Solution, Inc. — www.issi.comꢀ
49
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tDS
t
DH
t
DS
t
DH
t
DS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+3
tRCD
tRAS
t
RC
t
WR
tRP
DON'T CARE
Notes:
1.ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
50ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
SINGLE WRITE - WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
tCL
tCH
CLK
CKE
tCKS tCKH
t
CMS tCMH
NOP(4)
NOP(4)
PRECHARGE
NOP
ACTIVE
NOP
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ALL BANKS
ROW
ROW
SINGLE BANK
AS
t
AH
DISABLE AUTO PRECHARGE
BANK
BA0, BA1
BANK
BANK
BANK
t
DS
t
DH
DQ
DIN
m
t
t
t
RCD
RAS
RC
t
WR(3)
tRP
DON'T CARE
Notes:
1.ꢀburstꢀlengthꢀ=ꢀ1
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
3.ꢀtrasꢀmustꢀnotꢀbeꢀviolated
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51
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
SINGLE WRITE - WITH AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
tCL
tCH
CLK
CKE
t
CKS tCKH
t
CMS tCMH
NOP(3)
NOP(3)
NOP(3)
WRITE
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
ACTIVE
tCMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
BANK
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ROW
AS
t
AH
BA0, BA1
BANK
BANK
tDS
t
DH
DQ
DIN
m
tRCD
tRAS
t
RC
t
WR
tRP
DON'T CARE
Notes:
1.ꢀburstꢀlengthꢀ=ꢀ1
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
52ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
ALTERNATING BANK WRITE ACCESS
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
tCK
tCL
tCH
CLK
CKE
t
CKS tCKH
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
CMS tCMH
DQM/
DQML, DQMH
t
t
t
AS
tAH
COLUMN m(2)
ROW
ROW
COLUMN b(2)
ROW
ROW
A0-A9, A11
A10
ROW
AS
t
AH
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
AS
tAH
BANK 0
BANK 1
BANK 1
BANK 0
BA0, BA1
BANK 0
tDS
t
DH
t
DS
t
DH
tDS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
tDH
t
DS
tDH
DQ
DIN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
D
IN
b
D
IN b+
1
D
IN b+
2
DIN b+3
t
t
t
t
RCD - BANK 0
RRD
t
WR - BANK 0
t
RP - BANK 0
t
RCD - BANK 0
t
RCD - BANK 1
tWR - BANK 1
RAS - BANK 0
RC - BANK 0
DON'T CARE
Notes:
1.ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
53
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
WRITE - FULL PAGE BURST
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
t
CK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
t
CMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ROW
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
tDS
t
DH
tDS
t
DH
t
DS
t
DH
t
DS
t
DH
D
IN
m
D
IN m+
1
D
IN m+
2
D
IN m+
3
DIN m-1
DQ
t
RCD
Full page completed
DON'T CARE
Notes:
1.ꢀburstꢀlengthꢀ=ꢀfullꢀpage
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
54ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
WRITE - DQM OPERATION
T0
T1
T2
T3
T4
T5
T6
T7
t
CK
t
CL
tCH
CLK
CKE
t
CKS CKH
t
tCMS
tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
CMS
t
CMH
DQM/
DQML, DQMH
t
t
t
AS
t
AH
COLUMN m(2)
A0-A9, A11
A10
ROW
AS
tAH
ENABLE AUTO PRECHARGE
ROW
DISABLE AUTO PRECHARGE
AS
tAH
BA0, BA1
BANK
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D
IN
m
D
IN m+
2
DIN m+3
DQ
t
RCD
DON'T CARE
Notes:
1.ꢀburstꢀlengthꢀ=ꢀ4
2.ꢀA8,ꢀA9,ꢀandꢀA11ꢀ=ꢀ"Don'tꢀCare"
Integrated Silicon Solution, Inc. — www.issi.comꢀ
55
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Frequency
Speed (ns)
Order Part No.
Package
200ꢀMHzꢀ
200ꢀMHzꢀ
5ꢀ
5ꢀ
IS42S16400F-5TLꢀ
IS42S16400F-5BLꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
166ꢀMHzꢀ
166ꢀMHzꢀ
6ꢀ
6ꢀ
IS42S16400F-6TLꢀ
IS42S16400F-6BLꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
143ꢀMHzꢀ
143ꢀMHzꢀ
7ꢀ
7ꢀ
IS42S16400F-7TLꢀ
IS42S16400F-7BLꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
Industrial Range: -40°C to 85°C
Frequency
Speed (ns)
Order Part No.
Package
200ꢀMHzꢀ
200ꢀMHzꢀ
5ꢀ
5ꢀ
IS42S16400F-5TLIꢀ
IS42S16400F-5BLIꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
166ꢀMHzꢀ
166ꢀMHzꢀ
6ꢀ
6ꢀ
IS42S16400F-6TLIꢀ
IS42S16400F-6BLIꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
143ꢀMHzꢀ
143ꢀMHzꢀ
7ꢀ
7ꢀ
IS42S16400F-7TLIꢀ
IS42S16400F-7BLIꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
Automotive Range (A1): -40°C to 85°C
Frequency
Speed (ns)
Order Part No.
Package
200ꢀMHzꢀ
200ꢀMHzꢀ
5ꢀ
5ꢀ
IS45S16400F-5TLA1ꢀ
IS45S16400F-5BLA1ꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
166ꢀMHzꢀ
166ꢀMHzꢀ
166ꢀMHzꢀ
166ꢀMHzꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
IS45S16400F-6TLA1ꢀ
IS45S16400F-6CTLA1ꢀ 54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS45S16400F-6CTNA1ꢀ 54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀNiPdAuꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
IS45S16400F-6BLA1ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballs
143ꢀMHzꢀ
143ꢀMHzꢀ
143ꢀMHzꢀ
143ꢀMHzꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
IS45S16400F-7TLA1ꢀ
IS45S16400F-7CTLA1ꢀ 54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS45S16400F-7CTNA1ꢀ 54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀNiPdAuꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
IS45S16400F-7BLA1ꢀ
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
ꢀ
Automotive Range (A2): -40°C to 105°C
Frequency
Speed (ns)
Order Part No.
Package
143ꢀMHzꢀ
143ꢀMHzꢀ
143ꢀMHzꢀ
143ꢀMHzꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
IS45S16400F-7BLA2ꢀ
IS45S16400F-7TLA2ꢀ
IS45S16400F-7CTLA2ꢀ 54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
IS45S16400F-7CTNA2ꢀ 54-PinꢀTSOPII,ꢀCuꢀleadframeꢀplatedꢀwithꢀNiPdAu
54-ballꢀBGA,ꢀSnAgCuꢀballsꢀ
54-PinꢀTSOPII,ꢀAlloy42ꢀleadframeꢀplatedꢀwithꢀmatteꢀSnꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Notes:
1.ꢀContactꢀISSIꢀforꢀleadedꢀandꢀcopperꢀleadframeꢀpartsꢀsupport.
2.ꢀPartꢀnumbersꢀwithꢀ"L"ꢀorꢀ"N"ꢀareꢀleadfree,ꢀandꢀRoHSꢀcompliant.
56ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
ForꢀAlloy42ꢀandꢀCuꢀlead-framesꢀwithꢀmatteꢀSnꢀplating
Integrated Silicon Solution, Inc. — www.issi.comꢀ
57
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
58ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
12/01/2011
IS42S16400F
IS45S16400F
Integrated Silicon Solution, Inc. — www.issi.comꢀ
59
Rev. I
12/01/2011
相关型号：
IS42S16400F-6TLI-TR
Synchronous DRAM, 4MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, TSOP2-54
ISSI
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