IS24C64-P [ISSI]
EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, DIP-8;
| 型号： | IS24C64-P |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS24C64
65,552-BIT SERIAL ELECTRICALLY
ERASABLE PROM
ISSI
ADVANCE INFORMATION
OCTOBER 1997
FEATURES
OVERVIEW
• 400 KHz (5V) Compatibility
• Low power CMOS
The IS24C64 provides 65,536 bits of serial electrically
erasableandprogrammablereadonlymemory(EEPROM)
organized as 8197 words of 8 bits each. It is fabricated
using ISSI’s advanced CMOS EEPROM technology and
operates from a single supply.
– Active current less than 3.0 mA
– Standby current less than 35 µA
• Operating voltage: 4.5V to 5.5V
• Hardware write protection
– Write control pin
• Internally organized: 8192 x 8
• 32 byte page write mode (partial page writes
allowed)
The IS24C64 is internally organized as 256 pages of 32
bytes each. Random word addressing requires 12/13 bit
data word address bank. The IS24C64 cascadable fea-
ture allows up to 8 devices to share a common 2-wire bus.
Included is a bidirectional serial data bus synchronized by
a clock offering flexible byte write and a faster 32-byte
pagewrite.Awriteprotectpincanprotectdataintheupper
quadrant of memory.
• Two-wire serial interface
• Bidirectional data transfer protocol
• Self timed write cycles (10 ms max)
• High-reliability
– Endurance: 1 million cycles per byte
– Data retention: 100 years
• Industrial temperature available
• 8-pin PDIP or SOIC packages
PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to positive
edgeclockalldataintothedevice.IntheREADmode,data
is clocked out on the falling edge of SCL.
SerialData(SDA)-TheSDApinisabidirectionalpinused
to transfer data into and out of the device. Data may
change only when SCL is LOW. It is an open-drain output,
and may be wire-ORed with any number of open-drain or
open-collector outputs.
PIN CONFIGURATION
8-Pin DIP and SOIC
Device/Page Addresses (A0, A1, and A2):
The A2, A1 and A0 pins are device address inputs that are
hard wired or left not connected for hardware compatibility
with IS24C64. When the pins are hardwired, as many as
eight 64K devices may be addressed on a single bus
system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not
hardwired, the default A2, A1 and A0 are zero.
A0
A1
1
2
3
4
8
7
6
5
VCC
WC
A2
SCL
SDA
GND
PIN DESCRIPTIONS
Write Control (WC) - The Write Control input is used to
disable any attempt to write to the memory. When HIGH,
the upper quadrant (16K bits)of array is protected against
write operations; when LOW, the write function is normal.
The part can be read independent of the state of WC pin.
When not connected this pin will be pulled LOW.
A0-A2
SDA
SCL
WC
Address Inputs (No connection)
Serial Data I/O
Serial Clock Input
Write Control Input
Power
Vcc
GND
Ground
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
1
10/29/97
®
IS24C64
ISSI
BLOCK DIAGRAM
WP
Vcc
GND
SCL
SDA
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
EN
HV PUMP/TIMING
LOAD
COMP
DEVICE
ADDRESS
COMPARATOR
LOAD
INC
DATA RECOVERY
EEPROM
DATA
WORD
ADDRESS/
COUNTER
R/W
A2
A1
A0
SERIAL MUX
Y DEC
D
OUT/ACK
LOGIC
DIN
DOUT
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
10/29/97
®
IS24C64
ISSI
GENERAL DESCRIPTION
Acknowledge
All addresses and data words are serially transmitted to
andfromtheEEPROMin8bitwords.TheEEPROMsends
a zero during the ninth clock cycle to acknowledge that it
has received each word.
Device Addressing
The IS24C64 requires an 8 bit device address word
following a start condition to enable the chip for a read or
write operation (See Figure 4). The device address word
consists of a mandatory one, zero sequence for the first
four most significant bits as shown. This is common to all
2-wire EEPROM devices.
Standby Mode
The IS24C64 features a low power standby mode which is
enabled:
The IS24C64 uses the three device address bits A2, A1,
A0 to allow as many as eight devices on the same bus.
Thesebitsmustcomparetotheircorrespondinghardwired
input pins. The A2, A1, and A0 pins use an internal
proprietary circuit that biases them to a logic low condition
if the pins are allowed to float.
– upon power-up
– after the receipt of the STOP bit and the completion
of any internal operations
WRITE OPERATIONS
Byte Write
The eighth bit of the device address is the rea/write
operation select bit. A read operation is initiated if this bit
is HIGH and a write operation is initiated if this bit is LOW.
A write operation requires two 8 bit data word addresses
following the device address word and acknowledgment.
Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8 bit data
word.Followingreceiptofthe8bitdataword,theEEPROM
will output a zero and the addressing device, such as a
microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an inter-
nally-timed write cycle to the nonvolatile memory. All
inputsaredisabledduringthiswritecycleandtheEEPROM
will not respond until the write is complete (See Figure 5).
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not made, the device will
return to standby state.
Noise Protection
Special internal circuitry placed on the SDA and SCL pins
prevent small noise spikes from activating the device. A
low-VCC detector resets the device to prevent data corrup-
tion in a noisy environment.
Data Security
Page Write
The IS24C64 has a hardware data protection scheme that
allows the user to write protect the upper quadrant (16K
bits) of memory when the WP pin is at VCC.
The IS24C64 EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but
themicrocontrollerdoesnotsendastopconditionafterthe
first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
trollercantransmitupto31moredatawords.TheEEPROM
willrespondwithazeroaftereachdatawordreceived. The
microcontroller must terminate the page write sequence
with a stop condition (See Figure 6).
DEVICE OPERATION
CLOCK and DATA Transitions
The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL
low time periods (See Figure 3). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
The data word address lower 5 bits are internally
incremented following the receipt of each data word. The
higher data word address bits are not incremented, retain-
ing the memory page row location. If more than 32 data
words are transmitted to the EEPROM, the data word
address will "roll over" and previous data will be overwrit-
ten.
Start Condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command (See
Figure 2).
Stop Condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command will
place the EEPROM in a standby power mode (See
Figure 2).
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
3
10/29/97
®
IS24C64
ISSI
Sequential Read
Acknowledge Polling
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the micro-
controller receives a data word, it responds with an ac-
knowledge. AslongastheEEPROMreceivesanacknowl-
edge, it will continue to increment the data word address
and serially clock out sequential data words.
Once the internal write cycle has started and the
IS24C64 inputs are disabled, acknowledge polling can be
initiated. This involves sending a start condition followed
by the Device Address word. The read/write bit is repre-
sentative of the operation desired. Only if the internal write
cycle has been completed will the IS24C64 respond with
a zero allowing the read or write sequence to continue.
When memory address limit is reached, the data word
address will "roll over" and the sequential read will con-
tinue. The sequential read operation is terminated when
the microcontroller does not respond with a zero but does
generate a following stop condition (See Figure 9).
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
device address word is set to “1”. There are three READ
operation options: current address read, random address
read and sequential read.
Current Address Read
The IS24C64 contains an internal address counter which
maintains the address of the last data word accessed,
incremented by one. This address stays valid between
operations as long as the address stays valid between
operations as long as the chip power is maintained. The
address "roll over" during read is from the last byte of the
last memory page, to the first byte of the first page. The
address "roll over" during write is from the last byte of the
current page to the first byte of the same page.
Once the device address with the read/write select bit set
to one is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (See Figure 7).
Random Read
A random READ requires a "dummy" byte write sequence
to load in the data word address. Once the device address
word and data word address are clocked in and acknowl-
edgedbytheEEPROM,themicrocontrollermustgenerate
another start condition. The microcontroller now initiates a
currentaddressreadbysendingadeviceaddresswiththe
read/write select bit high. The EEPROM acknowledges
the device address and serially clocks out the data word.
The microcontroller does not respond with a zero but does
generate a following stop condition (See Figure 8).
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
10/29/97
®
IS24C64
ISSI
SCL
1
8
9
Data In
Data Out
START
ACKNOWLEDGE
Figure 1. Output Acknowledge
SDA
SCL
START
STOP
Figure 2. START and STOP Conditions
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
5
10/29/97
®
IS24C64
ISSI
Data Change
SCL
SDA
Data Stable
Data Stable
Figure 3. Data Validity Protocol
BIT 7
BIT 4 BIT 3
BIT 1 BIT 0
R
W
1
0
1
0
A2 A1 A0
LSB
MSB
Figure 4. Device Addressing
S
T
A
R
T
W
R
I
S
T
O
P
Device
Address
First
Second
Word Address
T
E
Data
Word Address
SDA
Bus
Activity
A
A
C
K
A
C
K
A
C
K
R C
W K
* * * *
M
S
B
L
S
B
M
S
B
Don't Care bits
*
Figure 5. Byte Write
S
T
W
R
I
S
T
O
P
A
R
First
Second
Device
Address
T
Data (n)
Data (n+1)
Word Address (n) Word Address (n)
A
T
E
SDA
Bus
Activity
A
R C
W K
A
C
K
A
C
K
A
C
K
C
K
* * *
M
S
B
L
S
B
M
S
B
Don't Care bits
*
Figure 6. Page Write
6
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
10/29/97
®
IS24C64
ISSI
S
T
A
R
T
R
E
A
D
R
W
S
T
O
P
Device
Address
Data
SDA
Bus
Activity
A
C
K
M
S
B
L
S
B
N
O
A
C
K
Figure 7. Current Access Read
S
T
A
R
T
W
S
T
A
R
T
R
R
E
A
D
R
E
A
D
1st, 2nd
Word
I
T
E
Device
Address
Device
Address
Address n
Data n
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
R
W
* * *
M
S
B
L
S
B
N
O
A
C
K
DUMMY WRITE
* Don't Care bits
Figure 8. Random Access Read
R
E
A
D
S
T
O
P
Device
Address
Data Byte
Data Byte n+1
Data Byte n+2
Data Byte n+3
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
A
C
K
N
O
R/W
A
C
K
Figure 9. Sequential Read
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
7
10/29/97
®
IS24C64
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
2.7 to +5.5
–0.5 to Vcc + 0.5
–40 to +85
–65 to +150
5
Unit
V
VS
Supply Voltage
VP
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
V
TBIAS
TSTG
IOUT
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
0°C to +70°C
VCC
Commercial
Industrial
5V ± 10%
5V ± 10%
–40°C to +85°C
CAPACITANCE(1,2)
Symbol Parameter
Conditions
Max.
Unit
pF
CIN
Input Capacitance (A0, A1, A2, SCL)
Output Capacitance (SDA)
VIN = 0V
5
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters and not
100% tested.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
8
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
10/29/97
®
IS24C64
ISSI
DC ELECTRICAL CHARACTERISTICS
TA = 0°C to +70°C for IS24C64 and –40°C to +85°C for IS24C64-I, Vcc = 4.5V to 5.5V. (Unless Otherwise Noted.)
Symbol Parameter
Test Conditions
Min.
—
Max.
Unit
V
VOL1
VOL2
VIH
VIL
Output LOW Voltage
VCC = 2.7V., IOL = 0.15 mA
VCC = 3.0V., IOL = 2.1 mA
0.25
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
—
0.4
V
—
VCC + 0.5
V
–1.0
—
—
3
V
ILI
Input Leakage Current
Output Leakage Current
VIN = VCC max.
µA
µA
ILO
—
3
POWER SUPPLY CHARACTERISTICS
TA = 0°C to +70°C for IS24C64 and –40°C to +85°C for IS24C64-I, Vcc = 4.5V to 5.5V.
Symbol Parameter
Test Conditions
Min. Max.
Unit
mA
mA
µA
ICC1
ICC2
ISB1
ISB2
Vcc Operating Current Vcc = 5.0V
READ at 100 KHz
—
—
—
—
1.0
3.0
20
Vcc Operating Current Vcc = 5.0V
Standby Current
WRITE at 100 KHz
Vcc = 4.5V, VIN = VCC or GND
Vcc = 5.5V, VIN = VCC or GND
Standby Current
35
µA
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
9
10/29/97
®
IS24C64
ISSI
AC ELECTRICAL CHARACTERISTICS
Applicable Over Recommended Operating Range From: T
(Unless Otherwise Noted)
A
= –40°C to +85°C, Vcc = 5.0 ± 10%, CL = ITTL Gate and 100pF
5.5V
Symbol Parameter
Test Conditions
Min. Max.
Unit
fSCL
SCL Clock Frequency
0
—
400
50
—
—
—
—
—
—
—
—
—
—
0.9
300
300
10
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ns
ms
tI
Noise Suppression Time(1)
tLOW
tHIGH
tBUF
Clock LOW Period
Clock HIGH Period
1.2
0.6
1.2
0.6
0.6
0.6
0.6
100
0
50
0.1
—
—
—
Bus Free Time Before New Transmission(1)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data In Setup Time
Data In Hold Time
Data Out Hold Time
Clock to Output
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
tDH
SCL LOW to SDA Data Out Change
SCL LOW to SDA Data Out Valid
tAA
tR
SCL and SDA Rise Time(1)
SCL and SDA Fall Time(1)
Write Cycle Time
tF
tWR
Note:
1. This parameter is characterized but not 100% tested.
AC WAVEFORMS
BUS TIMING
t
LOW
HIGH
t
F
t
t
LOW
tR
SCL
t
SU:STO
t
SU:STA
tHD:DAT
t
BUF
t
HD:STA
tSU:DAT
SDAIN
t
AA
tDH
SDAOUT
10
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
10/29/97
®
IS24C64
ISSI
WRITE CYCLE
SCL
SDA
8th BIT
ACK
t
WR
WORD n
STOP
START
Condition
Condition
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency Order Part Number
Package
300-mil Plastic DIP
Small Outline (JEDEC STD)
400 KHz
400 KHz
IS24C64-P
IS24C64-G
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Frequency Order Part Number
Package
400 KHz
400 KHz
IS24C64-PI
IS24C64-GI
300-mil Plastic DIP
Small Outline (JEDEC STD)
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
Toll Free: 1-800-379-4774
e-mail: sales@issiusa.com
http://www.issiusa.com
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE011-0A
11
10/29/97
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