IS24C64A-2GLI-TR [ISSI]
EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, LEAD FREE, PLASTIC, SOIC-8;
| 型号： | IS24C64A-2GLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, LEAD FREE, PLASTIC, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总17页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS24C32A/B
IS24C64A/B
ISSI
64K-bit/32K-bit
2-WIRE SERIAL CMOS EEPROM
APRIL2006
FEATURES
DESCRIPTION
• Two-Wire Serial Interface, I2CTM Compatible
–Bi-directional data transfer protocol
• Wide Voltage Operation
The IS24C32A/B and IS24C64A/B are electrically
erasable PROM devices that use the standard 2-
wire interface for communications. The IS24C32A/B
and IS24C64A/B contain a memory array of 32K-
bits (4K x 8) and 64K-bits (8K x 8), respectively.
Each device is organized into 32 byte pages for
page write mode.
–Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1MHz (5.0V) Compatible
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Hardware Data Protection
This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution.
The devices are available in 8-pin PDIP, 8-pin
SOIC, 8-pin TSSOP, and 8-pin MSOP packages.
–IS24C32A/64A: WP protects entire array
–IS24C32B/64B: WP protects top quarter of
array
• Sequential Read Feature
The IS24C32A/32B/64A/64B (IS24CXX) maintains
compatibility with the popular 2-wire bus protocol,
so it is easy to use in applications implementing
this bus type. The simple bus consists of the
Serial Clock wire (SCL) and the Serial Data wire
(SDA). Using the bus, a Master device such as a
microcontroller is usually connected to one or
more Slave devices such as this device. The bit
stream over the SDA line includes a series of
bytes, which identifies a particular Slave device,
an instruction, an address within that Slave device,
and a series of data, if appropriate. The IS24CXX
has a Write Protect pin (WP) to allow blocking of
any write instruction transmitted over the bus.
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max.@ 2.5V
• Organization:
–IS24C32A/B: 4Kx8 (128 pages of 32 bytes)
–IS24C64A/B: 8Kx8 (256 pages of 32 bytes)
• 32 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Automotive and Industrial temperature ranges
• 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, and 8-pin
MSOP packages
• Lead-free Available
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
8
Vcc
5
6
7
SDA
SCL
WP
CONTROL
LOGIC
EEPROM
ARRAY
SLAVE ADDRESS
REGISTER &
COMPARATOR
1
2
3
WORD ADDRESS
COUNTER
A0
A1
A2
Y
DECODER
ACK
Clock
DI/O
DATA
REGISTER
4
GND
>
nMOS
PIN DESCRIPTIONS
PIN CONFIGURATION
8-Pin DIP, SOIC, TSSOP, and MSOP
A0-A2
SDA
SCL
WP
Address Inputs
Serial Address/Data I/O
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Serial Clock Input
Write Protect Input
Power Supply
Ground
Vcc
A2
SCL
SDA
GND
GND
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
WP
WPistheWriteProtectpin.Theinputleveldeterminesifall,
partial,ornoneofthearrayisprotectedfrommodifications.
SDA
The SDA is a Bi-directional pin used to transfer addresses
anddataintoandoutofthedevice. TheSDApinisanopen
drain output and can be wire-Ored with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
WriteProtection
Array Addresses Protected
WP
IS24C32A/64A
None
IS24C32B
IS24C64B
A0, A1, A2
GND or floating
Vcc
None
None
Entire Array
C00h
-FFFh
1800h
-1FFFh
The A0, A1 and A2 are the device address inputs that are
hardwired or left not connected for hardware compatibility
withthe24C16.Whenpinsarehardwired,asmanyaseight
32K/64K devices may be addressed on a single bus
system.Whenthepinsarenothardwired,thedefaultvalues
of A0, A1, and A2 are zero.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
DEVICE OPERATION
Stop Condition
IS24CXXfeaturesserialcommunicationandsupportsabi-
directional 2-wire bus transmission protocol called I2CTM.
The Stop condition is defined as a Low to High transition of
SDAwhenSCLisHigh. AlloperationsmustendwithaStop
condition.
2-WIRE BUS
Acknowledge (ACK)
Thetwo-wirebusisdefinedasaSerialDataline(SDA),and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by a
Master device that generates the SCL, controls the bus
access, andgeneratestheStopandStartconditions. The
IS24CXX is the Slave device on the bus.
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24CXX contains a reset function in case the 2-
wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.)
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the SDA line must remain stable
whenevertheSCLlineishigh. AnychangesintheSDA
line while the SCL line is high will be interpreted as a
Start or Stop condition.
Standby Mode
ThestateoftheSDAlinerepresentsvaliddataafteraStart
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Power consumption is reduced in standby mode. The
IS24CXX will enter standby mode: a) At Power-up, and
remaininituntilSCLorSDAtoggles;b)FollowingtheStop
signal if a no write operation is initiated; or c) Following any
internalwriteoperation.
Start Condition
The Start condition precedes all commands to the device
andisdefinedasaHightoLowtransitionofSDAwhenSCL
isHigh.TheEEPROMmonitorstheSDAandSCLlinesand
will not respond until the Start condition is met.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
WRITE OPERATION
Byte Write
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave
device (Fig. 5) address is 8 bits.
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
settoZero)totheSlavedevice. AftertheSlavegenerates
an ACK, the Master sends the two byte address that is to
be written into the address pointer of the IS24CXX. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memorylocation. TheIS24CXXacknowledgesoncemore
andtheMastergeneratestheStopcondition,atwhichtime
the device begins its internal programming cycle. While
thisinternalcycleisinprogress,thedevicewillnotrespond
to any request from the Master device.
ThefourmostsignificantbitsoftheSlaveaddressarefixed
as 1010 for the IS24CXX.
The next three bits of the Slave address are A0, A1, and
A2, and are used in comparison with the hard-wired input
values on the A0, A1, and A2 pins. Up to eight IS24CXX
units may share the 2-wire bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to1,aReadoperationisselected,andwhensetto0,aWrite
operation is selected.
Page Write
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C64A)willrespondwithACKontheSDAline. The
Slave will pull down the SDA on the ninth clock cycle,
signalingthatitreceivedtheeightbitsofdata.Theselected
EEPROM then prepares for a Read or Write operation by
monitoring the bus.
TheIS24CXXiscapableof32-bytePage-Writeoperation.A
Page-Write is initiated in the same manner as a Byte Write,
but instead of terminating the internal Write cycle after the
firstdatawordistransferred,theMasterdevicecantransmit
upto31morebytes. Afterthereceiptofeachdataword,the
EEPROM responds immediately with an ACK on SDA line,
andthefivelowerorderdatawordaddressbitsareinternally
incremented by one, while the higher order bits of the data
word address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the
first byte of that page. If the Master device should transmit
more than 32 bytes prior to issuing the Stop condition, the
addresscounterwill“rollover,”andthepreviouslywrittendata
will be overwritten. Once all 32 bytes are received and the
Stop condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data is
written to the IS24CXX in a single Write cycle. All inputs are
disabled until completion of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24CXXinitiatestheinternalWritecycle. ACKpollingcan
be initiated immediately. This involves issuing the Start
conditionfollowedbytheSlaveaddressforaWriteoperation.
IftheEEPROMisstillbusywiththeWriteoperation,noACK
will be returned. If the IS24CXX has completed the Write
operation, an ACK will be returned and the host can then
proceed with the next Read or Write operation.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
READ OPERATION
Random Address Read
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
issetto“1”. TherearethreeReadoperationoptions:current
addressread, randomaddressreadandsequentialread.
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read.
After the IS24CXX acknowledges the byte address, the
Master device resends the Start condition and the Slave
address, this time with the R/W bit set to one. The
EEPROM then responds with its ACK and sends the data
requested. The Master device does not send an ACK but
willgenerateaStopcondition. (RefertoFigure9.Random
AddressReadDiagram.)
Current Address Read
The IS24CXX contains an internal address counter which
maintainstheaddressofthelastbyteaccessed,incremented
by one. For example, if the previous operation is either a
ReadorWriteoperationaddressedtotheaddresslocation
n,theinternaladdresscounterwouldincrementtoaddress
location n+1. When the EEPROM receives the Slave
AddressingBytewithaReadoperation(R/W bit set to “1”),
itwillrespondanACKandtransmitthe8-bitdatabytestored
ataddresslocationn+1. TheMastershouldnotacknowledge
the transfer but should generate a Stop condition so the
IS24CXX discontinues transmission. If 'n' is the last byte
ofthememory,thedatafromlocation'0'willbetransmitted.
(Refer to Figure 8. Current Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
AddressReadorRandomAddressRead. AftertheIS24CXX
sends the initial byte sequence, the Master device now
respondswithanACKindicatingitrequiresadditionaldata
fromtheIS24CXX.TheEEPROMcontinuestooutputdata
foreachACKreceived. TheMasterdeviceterminatesthe
sequential Read operation by pulling SDA High (no ACK)
indicating the last data word to be read, followed by a Stop
condition.
The data output is sequential, with the data from address
n followed by the data from address n+1, n+2 ... etc. The
addresscounterincrementsbyoneautomatically,allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundaryof8191forIS24C64A/Bor4095forIS24C32A/B
(dependingonthedevice)isreached,theaddresscounter
“rollsover”toaddress0,andthedevicecontinuestooutput
data. (Refer to Figure 10. Sequential Read Diagram).
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS24CXX
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
t
AA
tAA
Data Output
from
ACK
Receiver
Figure 3. START and STOP Conditions
SCL
SDA
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
Figure 4. Data Validity Protocol
Data Change
SCL
SDA
Data Stable
Data Stable
Figure 5. Slave Address
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2 A1 A0
R/W
Figure 6. Byte Write
S
W
R
I
S
T
T
A
Device
Address
O
P
R
T
T
E
Data
Word Address
Word Address
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
A
C
K
#
* * *
M
S
B
L
S
B
M
S
B
* = Don't care bits
# = Don't care bit for 24C32A/B
R/W
Figure 7. Page Write
S
T
A
R
T
W
R
I
S
T
Device
Address
O
T
E
Data (n)
Data (n+1)
Data (n+31)
Word Address (n) Word Address (n)
A
* * *
P
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
C
K
#
M
S
B
L
S
B
* = Don't care bits
# = Don't care bit for 24C32A/B
R/W
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
Figure 8. Current Address Read
S
T
A
R
T
R
E
A
D
S
T
O
P
Device
Address
Data
SDA
Bus
Activity
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Address Read
S
T
A
R
T
W
R
I
T
E
S
T
R
E
A
D
S
T
A
Device
Address
Device
Address
Word
Address (n)
Word
Address (n)
O
R
T
Data n
P
SDA
Bus
Activity
A
C
K
A
C
K
A
A
C
K
C
#
* * *
K
M
S
B
L
S
B
N
O
A
C
K
* = Don't care bits
# = Don't care bit for 24C32A/B
R/W
DUMMY WRITE
Figure 10. Sequential Read
R
E
A
D
S
T
Device
Address
O
P
Data Byte n
Data Byte n+1
Data Byte n+2
Data Byte n+X
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
R/W
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +6.5
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
5
Unit
V
VS
Supply Voltage
VP
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
V
TBIAS
TSTG
IOUT
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectreliability.
OPERATING RANGE (IS24C64A/B-2 and IS24C32A/B-2)
Range
AmbientTemperature
VCC
Industrial
–40°Cto+85°C
1.8V to 5.5V
Note: ISSI offers Industrial grade for Commerical applications (0oC to +70oC).
OPERATING RANGE (IS24C64A/B-3 and IS24C32A/B-3)
Range
Ambient Temperature
VCC
Automotive
–40°C to +125°C
2.5V to 5.5V
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Output Capacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
AC WAVEFORMS
Figure 11. Bus Timing
t
R
t
F
tHIGH
tLOW
tSU:STO
SCL
t
BUF
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDAIN
t
AA
tDH
SDAOUT
WP
t
SU:WP
t
HD:WP
Figure 12. Write Cycle Timing
SCL
ACK
SDA
t
WR
WORD n
STOP
Condition
START
Condition
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
DC ELECTRICAL CHARACTERISTICS Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol Parameter
Test Conditions
Min.
—
Max.
0.2
Unit
V
VOL1
VOL2
VIH
Output Low Voltage
VCC = 1.8V, IOL = 0.15 mA
VCC = 2.5V, IOL = 3 mA
Output Low Voltage
Input High Voltage
—
0.4
V
VCC X 0.7 VCC + 0.5
V
VIL
Input Low Voltage
–1.0
—
VCC X 0.3
V
ILI
Input Leakage Current
Output Leakage Current
VIN = VCC max.
3
3
µA
µA
ILO
—
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol Parameter
Test Conditions
Min.
—
Max.
2.0
3.0
1
Unit
mA
mA
µA
ICC1
ICC2
ISB1
ISB2
Vcc Operating Current
Read at 400 KHz (Vcc = 5V)
Write at 400 KHz (Vcc = 5V)
Vcc = 1.8V
Vcc Operating Current
Standby Current
—
—
Standby Current
Vcc = 2.5V
—
2
µA
ISB3
Standby Current
Vcc = 5.0V
—
6
µA
AC ELECTRICAL CHARACTERISTICS Industrial (TA = -40oC to +85oC)
1.8V
≤
Vcc < 2.5V
2.5V
≤
Vcc < 4.5V
4.5V
Min. Max.
≤ Vcc ≤
5.5V(1)
Symbol Parameter
Min.
0
Max.
100
100
—
Min.
0
Max.
400
50
—
Unit
KHz
ns
f
SCL
SCLClockFrequency
NoiseSuppressionTime(1)
ClockLowPeriod
0
1000
50
—
—
—
—
—
—
—
—
—
—
—
—
T
—
4.7
4
—
—
t
Low
High
BUF
SU:STA
SU:STO
HD:STA
HD:STO
SU:DAT
HD:DAT
SU WP
HD WP
DH
1.2
0.6
1.2
0.6
0.6
0.6
0.6
100
0
0.6
0.4
0.5
0.25
0.25
0.25
0.25
100
0
µs
t
ClockHighPeriod
—
—
µs
t
BusFreeTimeBeforeNewTransmission(1)
StartConditionSetupTime
StopConditionSetupTime
StartConditionHoldTime
StopConditionHoldTime
DataInSetupTime
4.7
4
—
—
µs
t
—
—
µs
t
4
—
—
µs
t
4
—
—
µs
t
4
—
—
µs
t
100
0
—
—
ns
t
DataInHoldTime
—
—
ns
t
:
WPpinSetupTime
4
—
0.6
1.2
50
—
0.6
1.2
50
µs
t
:
WPpinHoldTime
4.7
100
—
—
µs
t
DataOutHoldTime
—
—
ns
(SCLLowtoSDADataOutChange)
tAA
ClocktoOutput
100
3500
50
900
50
400
ns
(SCLLowtoSDADataOutValid)
t
R
F
SCLandSDARiseTime(1)
SCLandSDAFallTime(1)
WriteCycleTime
—
—
—
1000
300
5
—
—
—
300
300
5
—
—
—
300
100
5
ns
ns
t
tWR
ms
Note: 1. These parameters are characterized but not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
AC ELECTRICAL CHARACTERISTICS Automotive (TA = -40oC to +125oC)
2.5V
≤
Vcc < 4.5V
4.5V
≤
Vcc
≤
5.5V(1)
Symbol Parameter
Min.
0
Max.
400
50
Min.
0
Max.
1000
50
—
Unit
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ms
fSCL
SCL Clock Frequency
T
Noise Suppression Time(1)
—
—
tLow
Clock Low Period
1.2
0.6
1.2
0.6
0.6
0.6
0.6
100
0
—
0.6
0.4
0.5
0.25
0.25
0.25
0.25
100
0
tHigh
Clock High Period
—
—
tBUF
Bus Free Time Before New Transmission(1)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data In Setup Time
—
—
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
tSU:WP
tHD:WP
tDH
—
—
—
—
—
—
—
—
—
—
Data In Hold Time
—
—
WP pin Setup Time
0.6
1.2
50
—
0.6
1.2
50
—
WP pin Hold Time
—
—
Data Out Hold Time (SCL Low to SDA Data Out Change)
Clock to Output (SCL Low to SDA Data Out Valid)
SCL and SDA Rise Time(1)
SCL and SDA Fall Time(1)
Write Cycle Time
—
—
tAA
50
900
300
300
10
50
550
300
100
5
tR
—
—
tF
—
—
tWR
—
—
Note:
1. These parameters are characterized but not 100% tested.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/12/06
IS24C32A/B
IS24C64A/B
®
ISSI
ORDERING INFORMATION
Industrial Range: -40°C to +85°C, Lead-free
Voltage
Range
PartNumber
Package
1.8V
to 5.5V
IS24C32A-2PLI
IS24C32A-2GLI
IS24C32A-2ZLI
IS24C32A-2SLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
MSOP
1.8V
to 5.5V
IS24C32B-2PLI
IS24C32B-2GLI
IS24C32B-2ZLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C64A-2PLI
IS24C64A-2GLI
IS24C64A-2ZLI
IS24C64A-2SLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
MSOP
1.8V
to 5.5V
IS24C64B-2PLI
IS24C64B-2GLI
IS24C64B-2ZLI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage
Range
PartNumber
Package
1.8V
to 5.5V
IS24C32A-2PI
IS24C32A-2GI
IS24C32A-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C32B-2PI
IS24C32B-2GI
IS24C32B-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C64A-2PI
IS24C64A-2GI
IS24C64A-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
1.8V
to 5.5V
IS24C64B-2PI
IS24C64B-2GI
IS24C64B-2ZI
300-mil Plastic DIP
Small Outline (JEDEC STD)
TSSOP
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. A
04/12/06
®
ISSI
PACKAGING
INFORMATION
PlasticMSOP
Package Code: S
N
E1 E
1
D
SEATING PLANE
A
L
A1
α
e
C
B
Plastic MSOP (S)
Ref.Std.
JEDECMO187
No.Leads
8 (120 mil)
Inches
Millimeters
Notes:
Symbol Min
Max
Min
Max
1. Controlling dimension: inches, unless
otherwise specified.
A
A1
B
C
D
E
0.038 0.043
0.002 0.006
0.010 0.016
0.005 0.009
0.114 0.122
0.193BSC
0.97
0.05
0.25
0.13
2.90
1.10
0.15
0.40
0.23
3.10
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package
.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
4.90BSC
2.90 3.10
0.65BSC
E1
e
0.114 0.122
0.0256BSC
L
α
—
—
0.022
7°
—
—
0.55
7°
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 02/01/02
®
PACKAGING INFORMATION
300-mil Plastic DIP
Package Code: N,P
ISSI
N
E1
1
D
SEATING PLANE
E
S
B1
S
A
L
C
A1
FOR
32-PIN ONLY
e
B
B2
e
A
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should
bemeasuredfromthebottomofthepackage
4. Formed leads shall be planar with respect to one another within 0.004
inches at the seating plane.
Sym. Min.
Max.
Min.
Max.
.
N0.
Leads
8
A
3.68
0.38
0.36
1.14
0.81
0.20
9.12
7.62
6.20
4.57
—
0.145
0.015
0.014
0.045
0.032
0.008
0.359
0.300
0.244
0.180
—
A1
B
0.56
1.52
1.17
0.33
9.53
8.26
6.60
0.022
0.060
0.046
0.013
0.375
0.325
0.260
B1
B2
C
D
E
E1
e
A
8.13
9.65
0.320
0.380
e
2.54 BSC
0.100 BSC
—
—
L
3.18
0.64
0.125
0.025
S
0.762
0.030
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/14/03
®
PACKAGING INFORMATION
ISSI
150-mil Plastic SOP
Package Code: G, GR
N
E
H
1
D
SEATING PLANE
A
L
A1
α
e
C
B
150-milPlasticSOP(G,GR)
Max Min
Inches mm
Symbol
Min
Max
Ref. Std.
No.Leads
8
8
A
A1
B
C
D
E
H
e
L
—
0.068
0.009
0.020
0.010
0.197
0.157
0.245
—
0.1
1.73
0.23
0.51
0.25
5
0.004
0.013
0.007
0.189
0.150
0.228
0.33
0.18
4.8
3.81
5.79
3.99
6.22
0.050BSC
0.020 0.035
1.27 BSC
0.51
0.89
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be
measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the
seating plane.
Integrated Silicon Solution, Inc. — 1-800-379-4774
2
Rev. C
10/03/01
®
PACKAGING INFORMATION
ISSI
Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)
N
E1
E
1
α
N/2
L
A1
D
A
A2
C
e
B
TSSOP (Z)
TSSOP (Z)
Ref. Std.
No. Leads
JEDEC MO-153
Ref. Std.
No. Leads
JEDEC MO-153
14
8
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Symbol Min
Max
Min
Max
A
A1
A2
B
C
D
—
1.20
—
0.047
A
A1
A2
B
C
D
—
1.20
—
0.047
0.05 0.15
0.80 1.05
0.19 0.30
0.09 0.20
4.90 5.10
4.30 4.50
6.40 BSC
0.002 0.006
0.031 0.041
0.007 0.012
0.0035 0.008
0.193 0.201
0.170 0.177
0.252 BSC
0.05 0.15
0.80 1.05
0.19 0.30
0.09 0.20
2.90 3.10
4.30 4.50
6.40 BSC
0.002 0.006
0.032 0.041
0.007 0.012
0.004 0.008
0.114 0.122
0.169 0.177
0.252 BSC
E1
E
E1
E
e
0.65 BSC
0.026 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.0177 0.0295
L
0.45 0.75
0.018 0.030
α
—
8°
—
8°
α
—
8°
—
8°
SSIreservestherighttomakechangestoitsproductsatanytimewithoutnoticeinordertoimprovedesignandsupplythebestpossibleproduct. Weassumenoresponsibilityforanyerrorswhichmay
appearinthispublication. ©Copyright2002,IntegratedSiliconSolution,Inc.
Integrated Silicon Solution, Inc.
Rev B 02/01/02
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