IC61C1024L-25K [ISSI]
Standard SRAM, 128KX8, 25ns, CMOS, PDSO32, 0.400 INCH, SOJ-32;
| 型号： | IC61C1024L-25K |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 128KX8, 25ns, CMOS, PDSO32, 0.400 INCH, SOJ-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IC61C1024
IC61C1024L
Document Title
128K x 8 High-Speed SRAM
Revision History
Revision No
History
Draft Date
Remark
0A
0B
Initial Draft
Revise typo on page 6 and page 8
March 13,2001
October 18,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
1
IC61C1024
IC61C1024L
128K x 8 HIGH-SPEED
CMOS STATIC RAM
DESCRIPTION
FEATURES
The ICSI IC61C1024 and IC61C1024L are very high-speed,
low power, 131,072-word by 8-bit CMOS static RAMs. They
are fabricated using ICSI's high-performance CMOS
technology. This highly reliable process coupled with innovative
circuit design techniques, yields higher performance and low
power consumption devices.
• High-speed access time: 12, 15, 20, 25 ns
• Low active power: 600 mW (typical)
• Low standby power: 500 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
required
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
• Low power version available: IC61C1024L
The IC61C1024 and IC61C1024L are available in 32-pin
300mil SOJ, and 8*20mm TSOP-1, and 8*13.4mm TSOP-1
packages.
• Commercial and industrial temperature ranges
available
FUNCTIONAL BLOCK DIAGRAM
512 x 2048
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CE2
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
IC61C1024
IC61C1024L
PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOJ
32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
4
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
8
A3
9
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A2
A3
PIN DESCRIPTIONS
A0-A16
CE1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
CE2
OE
WE
I/O0-I/O7
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Commercial
Ambient Temperature
VCC
5V ± 10%
0°C to +70°C
Industrial
–40°C to +85°C
5V ± 10%
TRUTH TABLE
Mode
WE CE1 CE2 OE
I/O Operation
Vcc Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled H
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
Read
Write
H
L
X
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
3
IC61C1024
IC61C1024L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +7.0
–55 to +125
–65 to +150
1.5
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
°C
°C
W
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Input Capacitance
Conditions
VIN = 0V
Max.
5
Unit
pF
COUT
Notes:
Output Capacitance
VOUT = 0V
7
pF
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VCC = Min., IOH = –4.0 mA
Min.
2.4
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
VCC = Min., IOL = 8.0 mA
—
0.4
V
2.2
VCC + 0.5
0.8
V
–0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–2
–5
2
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC
Outputs Disabled
Com.
Ind.
–2
–5
2
5
µA
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
4
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
IC61C1024
IC61C1024L
IC61C1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-12 ns
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ICC1
ICC2
ISB1
Vcc Operating
Supply Current
VCC = VCC MAX., CE = VIL Com.
—
—
85
110
—
—
85
110
—
—
85
110
—
—
85
110
mA
IOUT = 0 mA, f = 0
Ind.
Vcc Dynamic Operating
Supply Current
VCC = VCC MAX., CE = VIL Com.
—
—
170
180
—
—
160
170
—
—
150
160
—
—
140
150
mA
mA
IOUT = 0 mA, f = fMAX
Ind.
TTL Standby Current
(TTL Inputs)
VCC = VCC MAX.,
VIN = VIH or VIL
Com.
Ind.
—
—
40
60
—
—
40
60
—
—
40
60
—
—
40
60
CE1
≥
≤
VIH, f = 0 or
VIL, f = 0
CE2
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = VCC MAX.,
Com.
Ind.
—
—
30
40
—
—
30
40
—
—
30
40
—
—
30
40
mA
CE1
≥
≤
VCC – 0.2V,
0.2V
CE2
VIN > VCC – 0.2V, or
VIN 0.2V, f = 0
≤
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC61C1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-15 ns
-20 ns
-25 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ICC1
ICC2
ISB1
Vcc Operating
Supply Current
VCC = VCC MAX., CE = VIL Com.
—
—
85
110
—
—
85
110
—
—
85
110
mA
IOUT = 0 mA, f = 0
Ind.
Vcc Dynamic Operating VCC = VCC MAX., CE = VIL Com.
—
—
160
170
—
—
150
160
—
—
140
150
mA
mA
Supply Current
IOUT = 0 mA, f = fMAX
Ind.
TTL Standby Current
(TTL Inputs)
VCC = VCC MAX,
VIN = VIH or VIL
Com.
Ind.
—
—
40
60
—
—
40
60
—
—
40
60
CE1
≥
≤
VIH, f = 0 or
VIL, f = 0
CE2
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = VCC MAX.,
Com.
Ind.
—
—
500
750
—
—
500
750
—
—
500
750
µA
CE1
≥
≤
VCC – 0.2V,
0.2V
CE2
VIN > VCC – 0.2V, or
VIN 0.2V, f = 0
≤
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
5
IC61C1024
IC61C1024L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
(2)
-12
-15 ns
-20 ns
-25 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
12
—
3
—
12
—
12
12
6
15
—
3
—
15
—
15
15
7
20
—
3
—
20
—
20
20
9
25
—
3
—
25
—
25
25
9
tAA
Address Access Time
Output Hold Time
CE1 Access Time
CE2 Access Time
OE Access Time
tOHA
tACE1
tACE2
tDOE
—
—
—
0
—
—
—
0
—
—
—
0
—
—
—
0
(3)
tLZOE
OE to Low-Z Output
OE to High-Z Output
—
6
—
6
—
7
—
10
—
—
10
—
20
(3)
tHZOE
0
0
0
0
tLZCE1(3) CE1 to Low-Z Output
tLZCE2(3) CE2 to Low-Z Output
2
—
—
7
2
—
—
8
3
—
—
9
3
2
2
3
3
(3)
tHZCE
CE1 or CE2 to High-Z Output
0
0
0
0
(4)
tPU
CE1 or CE2 to Power-Up
0
—
12
0
—
12
0
—
18
0
(4)
tPD
CE1 or CE2 to Power-Down
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. -12 ns device for IC61C1024 only.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
6
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
IC61C1024
IC61C1024L
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
7
IC61C1024
IC61C1024L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low
Power)
(3)
-12 ns
Min.
-15 ns
Min.
-20 ns
-25 ns
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
7
Max.
—
—
—
—
—
—
—
—
—
7
Min.
Max.
—
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
12
10
10
10
0
15
12
12
12
0
20
15
15
15
0
25
20
20
20
0
tSCE1
tSCE2
tAW
CE1 to Write End
—
—
CE2 to Write End
—
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
tHA
—
—
tSA
0
0
0
—
0
—
(4)
tPWE
tSD
WE Pulse Width
10
7
10
8
12
10
0
—
15
12
0
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
—
tHD
0
0
—
—
(5)
tHZWE
—
2
—
2
—
2
10
—
—
2
12
—
(5)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. -12 ns device for IC61C1024 only.
4. Tested with OE HIGH.
5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
IC61C1024
IC61C1024L
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
9
IC61C1024
IC61C1024L
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
IC61C1024 STANDARD VERSION
ORDERING INFORMATION
IC61C1024 STANDARD VERSION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
12
12
12
12
IC61C1024-12J
IC61C1024-12K
IC61C1024-12H
IC61C1024-12T
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
12
12
12
12
IC61C1024-12JI
IC61C1024-12KI
IC61C1024-12HI
IC61C1024-12TI
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
15
15
15
15
IC61C1024-15J
IC61C1024-15K
IC61C1024-15H
IC61C1024-15T
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
15
15
15
15
IC61C1024-15JI
IC61C1024-15KI
IC61C1024-15HI
IC61C1024-15TI
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
20
20
20
20
IC61C1024-20J
IC61C1024-20K
IC61C1024-20H
IC61C1024-20T
300mil SOJ
400mil SOJ
88*13.4mm TSOP-1
8*20mm TSOP-1
20
20
20
20
IC61C1024-20JI
IC61C1024-20KI
IC61C1024-20HI
IC61C1024-20TI
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
25
25
25
25
IC61C1024-25J
IC61C1024-25K
IC61C1024-25H
IC61C1024-25T
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
25
25
25
25
IC61C1024-25JI
IC61C1024-25KI
IC61C1024-25HI
IC61C1024-25TI
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
10
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
IC61C1024
IC61C1024L
IC61C1024L LOW POWER VERSION
ORDERING INFORMATION
IC61C1024L LOW POWER VERSION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
15
20
25
IC61C1024L-15J
IC61C1024L-15K
IC61C1024L-15H
IC61C1024L-15T
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
15
20
25
IC61C1024L-15JI
IC61C1024L-15KI 400mil SOJ
IC61C1024L-12HI 8*13.4mm TSOP-1
IC61C1024L-15TI
300mil SOJ
8*20mm TSOP-1
IC61C1024L-20J
IC61C1024L-20K
IC61C1024L-20H
IC61C1024L-20T
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
IC61C1024L-20JI
IC61C1024L-20KI 400mil SOJ
IC61C1024L-12HI 8*13.4mm TSOP-1
IC61C1024L-20TI
300mil SOJ
8*20mm TSOP-1
IC61C1024L-25J
IC61C1024L-25K
IC61C1024L-25H
IC61C1024L-25T
300mil SOJ
400mil SOJ
8*13.4mm TSOP-1
8*20mm TSOP-1
IC61C1024L-25JI
IC61C1024L-25KI 400mil SOJ
IC61C1024L-12HI 8*13.4mm TSOP-1
IC61C1024L-25TI
300mil SOJ
8*20mm TSOP-1
Integrated Circuit Solution Inc.
HEADQUARTER:
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HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
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BRANCH OFFICE:
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HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
11
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