ZL8801ALAFT7A [INTERSIL]
Dual Phase PMBus⢠ChargeMode⢠Control DC/DC Digital Controller;型号: | ZL8801ALAFT7A |
厂家: | Intersil |
描述: | Dual Phase PMBus⢠ChargeMode⢠Control DC/DC Digital Controller |
文件: | 总87页 (文件大小:2024K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
Dual Phase PMBus™ ChargeMode™ Control DC/DC
Digital Controller
ZL8801
Features
• Unique compensation-free design – always stable
• Output voltage range: 0.54V to 5.5V
• Input voltage range: 4.5V to 14V
The ZL8801 is a dual phase digital DC/DC controller. Up to four
ZL8801s (8 phases) can be operated in parallel to provide
additional output current.
The ZL8801 supports a wide range of output voltages
(0.54V to 5.5V) operating from input voltages as low as 4.5V
up to 14V.
• 1% output voltage accuracy over line, load and temperature
• Charge mode control achieves fast transient response,
reduced output capacitance and provides output stability
without compensation
With its fully digital ChargeMode™ Control loop the ZL8801
can respond to a transient load step within a single switching
cycle. This unique compensation-free modulation technique
allows designs to meet transient specifications with minimum
output capacitance, thus saving cost and board space.
• Single 2-phase output, up to 8 phases with multiple devices
• Switching frequency range 200kHz to 1.33MHz
• Proprietary single wire DDC (Digital-DC) serial bus enables
voltage sequencing and fault spreading with all other Intersil
digital power ICs
Intersil’s proprietary single wire DDC (Digital-DC™) serial bus
enables the ZL8801 to communicate between other Intersil
digital power ICs. By using the DDC, the ZL8801 achieves
complex functions such as inter-IC phase current balancing,
sequencing and fault spreading, eliminating complicated
power supply managers with numerous external discrete
components.
• Tracking of an external power supply in the single 2-phase
configuration
• Cycle-by-cycle inductor peak current protection
• Digital fault protection for output voltage UV/OV, input
voltage UV/OV, temperature and MOSFET driver voltage
The ZL8801 features cycle-by-cycle overcurrent protection and
protection for overvoltage, undervoltage, over-temperature and
MOSFET driver under and overvoltage protection. A snapshot
parametric capture feature allows users to take a snapshot of
operating and fault data during normal or fault conditions.
• 10-bit cycle-by-cycle average output current measurement
with adjustable gain settings for sensing with high current,
low DCR inductors
• 10-bit monitor ADC measures input voltage, input current,
output voltage, internal, external temperature, driver voltage
Integrated Low Drop-Out (LDO) regulators allow the ZL8801 to
be operated from a single input supply eliminating the need
for additional linear regulators. A dedicated 5V VDRV LDO
output can be used to power external drivers or DrMOS
devices.
• Configurable to use standalone MOSFET drivers or
integrated driver-MOSFET (DrMOS) devices
• Nonvolatile memory (NVRAM) for storing operating
parameters and fault events.
With full PMBus™ compliance, the ZL8801 is capable of
measuring and reporting input voltage, input current, output
voltage, output current as well as the device’s internal
temperature, an external temperature and an auxiliary voltage
input.
• PMBus™ compliant
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
Related Literature
• AN1948, “ZL8801-4PH-DEMO1Z Demonstration Board User
Guide”
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER DUAL OUTPUT DUAL PHASE DDC CURRENT SHARE
• UG005, “ZL8801-2PH-DEMO1Z Demonstration Board User
Guide”
ZL8800
ZL8801
Yes
No
Yes
Yes
No
• AN1900, “USB to PMBus™ Adapter User Guide”
Yes
March 27, 2015
FN8614.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design), ChargeMode and Digital-DC are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ZL8801
Table of Contents
Simplified Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ZL8801 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Digital-DC Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multi-mode Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Configurable Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Voltage and VOUT_MAX Selection (VSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Switching Frequency Setting (SYNC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Voltage Undervoltage Lockout Setting (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TON Delay and Rise Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Limit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Temperature Monitoring Using XTEMP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Nonvolatile Memory (NVRAM) and Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC/DC Converter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PMBus™ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PMBus™ User Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PMBus™ Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PMBus™ Command Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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ZL8801
Simplified Application
VIN
VDD
VIN
VDRV
4.5V TO 14V
EN
PWM BST
PWMH0
PWML0
CONTROL
AND
STATUS
EN
PG
Vsw
GND
ZL8801
VOUT
0.6V TO 5V
ISENA0
ISENB0
INTER-DEVICE
COMMUNICATION
DDC
VIN
VDRV
PWMH1
PWML1
PWM BST
EN
Vsw
SDA
GND
PMBus
SCL
SALRT
ISENA1
ISENB1
VSENP
VSENN
GND
FIGURE 1. SIMPLIFIED APPLICATION
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ZL8801
Block Diagram
PWMH0
PWML0
PWM+
DEAD
TIME
ASCR
ADC
ADC
DIGITAL PWM
MODULATOR
VSENP/N
ASCR
DIGITAL PWM
MODULATOR
PWM+
DEAD
TIME
PWMH1
PWML1
XTEMP1P/N
XTEMP0P/N
MONITOR
ADC
VTRKP/N
DIGITAL LOGIC
+
OV/UV/OC/UC
COMPARATORS
MGN
EN
VMON
VDD
PG
OSC
ISENA0
IPEAK/
IAVG
ADC
CLK
GEN
PLL
SYNC
DDC
ISENB0
ISENA1
DIGITAL-DC
MICRO-
INTER-DEVICE
CONTROLLER
AND
IPEAK/
IAVG
ADC
COMMUNICATIONS
NONVOLATILE
MEMORY
ISENB1
SDA
IIN
ADC
PMBUS
SERIAL
INTERFACE
SCL
SALRT
PIN-STRAP
RESISTOR
DETECTION
LDOs
VDD
GAIN
FIGURE 2. BLOCK DIAGRAM
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Schematic
VIN
10.8 TO 13.2V
RIN
CIN1
C6
1µF
1mΩ
(OPTIONAL)
IINN VDD
VDRV
IINP
C7
10µF
R8
100kΩ
V25
V5
C3
10µF
VMON
C4
10µF
R9
6.65kΩ
VIN
PVCC
VCC
V6
C5
10µF
L1
SW
C8
ISL99140
PHASE
1µF
C1
R1
AGND
C9
0.1µF
U1
SYNC
BOOT
PWM
EN
PWMH0
PWML0
THDN
SMOD
SA
R3
PGND
VSET0
UVLO
R4
VOUT
R5
ISENA0
ISENB0
COUT
64
VIN
U3
ZL8801
CIN2
R2
PVCC
VIN
CONTROL
AND
STATUS
EN
PG
L2
VCC
SW
ISL99140
C10
1µF
V5
PHASE
C2
AGND
C11
0.1µF
U2
BOOT
THDN
SMOD
PWMH1
PWML1
PWM
EN
R7
10kΩ
PGND
INTER-DEVICE
COORDINATION
(OPTIONAL)
DDC
ISENA1
SYNC
ISENB1
VSENN
VSENP
SDA
SCL
PMBus
(OPTIONAL)
DGND SGND
FIGURE 3. ZL8801 SCHEMATIC
ZL8801
Pin Configuration
ZL8801
(44 LD QFN)
TOP VIEW
33
32
31
30
VDD
SCL
SDA
1
2
VR5
VR6
3
SALRT
SG ND
SA
VDRV
4
29 ISENA1
5
EXPO SED PADDLE
CONNECT TO SGND
28
27
26
25
24
23
6
ISENB1
PWML1
PWMH1
PWMH0
PWML0
ISENB0
VMON
DGND
MGN
NC
7
8
9
VSET
NC
10
11
Pin Description
TYPE
PIN#
1
PIN NAME (Note 1)
DESCRIPTION
SCL
I/O
I/O
O
Serial clock. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V
(recommend VR5, do not use V25) source.
2
3
4
5
6
SDA
Serial data. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V
(recommend VR5, do not use V25) source.
SALRT
SGND
SA
Serial alert. Connect to external host if desired. Requires a pull-up resistor to a 2.5V to 5.5V (recommend VR5)
source. If not used this pin should be left floating.
PWR Connect to low impedance ground plane. Internal connection to SGND. All pin-strap resistors should be connected
to SGND. SGND must be connected to DGND and PGND using a single point connection.
M
Serial address select pin. Used to assign unique address for each individual device or to enable certain management
features. See Table 3 for SMBus address options. Connect resistor to SGND.
VMON
I
External voltage monitoring (can be used for external driver bias (VDRV) monitoring). Requires an external 16:1
resistor divider network. Connect bottom of resistor divider network to SGND. Connect divider network to VR5 if an
external voltage is not monitored.
7
8
DGND
MGN
VSET
PWR Digital ground. Must connect to SGND and PGND using a single point connection.
I
Margin pin. High = margin high, low = margin low, float = no margin.
Output voltage selection pin. Used to set V and V max. See Table 4 for V
10
M
pin-strap options. Default VOUT
setting, but this can be overridden via the PMBus interface with VOUT_MAX command. Connect
OUT OUT OUT
max is 115% of V
resistor to SGND.
OUT
12
13
14
15
PG
UVLO
O
M
I/O
I
Power-good output. Can be configured as open-drain or push-pull using the PMBus interface. Default setting is open
drain.
Undervoltage lockout selection. Sets the minimum value for V voltage to enable V . See Table 6 for UVLO setting
DD OUT
options. Pin-strapped (configured) values can be overridden by the PMBus interface. Connect resistor to SGND.
DDC
Single wire DDC bus (Current sharing and interdevice communication). Requires a pull-up resistor to a 2.5 to 5.5V
(recommend VR5, do not use V25) source. Pull-up voltage must be present when the device is powered.
XTEMP0P
External temperature sensor input. Connect to external 2N3904 (Base Emitter junction) or equivalent embedded
thermal diode. If not used connect to SGND.
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ZL8801
Pin Description (Continued)
TYPE
PIN#
16
PIN NAME (Note 1)
DESCRIPTION
XTEMP0N
VTRKP
I
I
External temperature sensor input return. If not used connect to SGND.
17
Tracking sense positive input. Used to track an external voltage source. If not used, this pin can be left floating.
Tracking is only possible in 2-phase operation. Tracking is disabled in 4-, 6- and 8-phase operation.
18
19
20
21
VTRKN
VSENP
VSENN
VDRVEN
I
I
I
I
Tracking sense negative input (return). If not used, this pin can be left floating.
Differential voltage sense feedback. Connect to positive output regulation point.
Differential voltage sense feedback. Connect to negative output regulation point.
VDRV (MOSFET Driver Bias Supply) Enable. Leave unconnected (float) or pull-up to VR5 to enable, tie to ground to
disable.
22
23
24
ISENA0
ISENB0
PWML0
I
I
Positive differential voltage input for phase 0 DCR current sensing. Should be routed as a pair with ISENB0. Should
connect to resistor located close to output inductor. See “Current Sensing Components” on page 17.
Negative differential voltage input for phase 0 DCR current sensing. Should be routed as a pair with ISENA0. Should
be connected to output inductor terminal. See “Current Sensing Components” on page 17.
O
PWM0 Gate low signal/DrMOS enable. Configured using Bit 10 of USER_CONFIG command. Default is DrMOS
operation.
25
26
27
PWMH0
PWMH1
PWML1
O
O
O
PWM0 Gate high signal.
PWM1 Gate high signal.
PWM1 Gate low signal/DrMOS enable. Configure using Bit 10 of USER_CONFIG command. Default is DrMOS
operation.
28
29
30
31
32
ISENB1
ISENA1
VDRV
VR6
I
I
Negative differential voltage input for phase 1 DCR current sensing. Should be routed as a pair with ISENA1. Should
be connected to output inductor terminal. See “Current Sensing Components” on page 17.
Positive differential voltage input for phase 1 DCR current sensing. Should be routed as a pair with ISENB1. Should
connect to resistor located close to output inductor. See “Current Sensing Components” on page 17.
PWR MOSFET driver bias supply regulator output. If disabled, this pin can be left floating. Decouple with a high quality
4.7µF X7R or better ceramic capacitor placed close to this pin.
PWR Bypass for internal 6V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better
ceramic capacitor placed close to this pin. Keep this net as small as possible. Do not route near switching signals.
VR5
PWR Bypass for internal 5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better
ceramic capacitor placed close to this pin.
33
34
35
36
VDD
IINN
IINP
V25
PWR Supply voltage. Decouple with a high quality 1µF X7R or better ceramic capacitor placed close to this pin.
I
I
Input current monitor negative input. If not used connect to VDD.
Input current monitor positive input. If not used connect to VDD
PWR Bypass for internal 2.5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better
ceramic capacitor placed close to this pin
9, 11, 37,
38, 39, 43
NC
Not Connected. Leave pin floating.
40
XTEMP1N
I
External temperature sensor input for phase1. Connect to external 2N3904 (Base Emitter junction) or equivalent
embedded thermal diode. If not used connect to SGND.
41
42
XTEMP1P
EN
I
I
External temperature sensor input for phase 1 return. If not used connect to SGND.
Enable input. Active signal enables PWM0 and PWM1 switching. Recommended to be tied low during device
configuration. Refer to “Enable” on page 16 for additional information.
44
SYNC
SGND
M/I/O Clock synchronization input. Used to set the frequency of the internal clock to sync to an external clock or to output
internal clock. When configured as an output, this pin is push-pull and does not require a pull-up. See “Switching
Frequency Setting (SYNC)” on page 14 for additional information.
PAD
PWR Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.
NOTE:
1. I = Input, O = Output, PWR = Power or Ground, M = Multi-mode pins.
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ZL8801
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
PART
MARKING
TEMP. RANGE
(°C)
PACK
METHOD
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ZL8801ALAFTK
8801
8801
-40 to +85
-40 to +85
Tape and Reel 1k
Tape and Reel 250pc
44 Ld QFN
44 Ld QFN
L44.7x7B
L44.7x7B
ZL8801ALAFT7A
ZL8801-2PH-DEMO1Z
ZL8801-4PH-DEMO1Z
NOTES:
2-phase Demonstration board.
4-phase Demonstration board.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ZL8801. For more information on MSL, please see tech brief TB363
ZL8801
A L A F T
Product Designator
Shipping Option
TK = Tape and Reel - 1000 pcs
T7A = 7 inch Tape and Reel - 250 pcs
Lead Finish
F = Lead-free matte tin
Firmware Revision
Alpha character
Operating Temperature Range
L = -40°C to +85°C
Package Designator
A = QFN package
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ZL8801
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage: VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic I/O Voltage: DDC, EN, MGN, PG,
Thermal Resistance (Typical)
44 Ld QFN Package (Notes 6, 7) . . . . . . . .
(°C/W)
25
(°C/W)
1.5
JA
JC
SA, VDRVEN, SALRT, SCL, SDA, SYNC, UVLO,
VMON, VSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Analog Input Voltages:
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
VSENP, VSENN, VTRKP, VTRKN, ISENA0, ISENA1,
ISENB0, ISENB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
XTEMP0P, XTEMP1P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
XTEMP0N, XTEMP1N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
IINN, IINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V
Logic Reference: V25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
Bias Supplies: VR5, VR6, VDRV. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
PWM Logic Outputs, PWMH0, PWMH1, PWML0, PWML1 . . . .-0.3V to 6.5V
Ground Voltage Differential (VDGND, VSGND). . . . . . . . . . . . . . . .-0.3V to +0.3V
ESD Ratings
Recommended Operating Conditions
Input Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
Output Voltage Range, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V
Operating Junction Temperature Range, T . . . . . . . . . . . .-40°C to +125°C
J
Ambient Temperature Range, T . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
A
5V (VR5) Supply Total Supplied Current (Note 8) . . . . . . . . . . . . . . . . . 5mA
5V LDO Supply (VDRV) (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 80mA
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C1010-D) . . . . . . . . . . . . 1kV
Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. Output current is limited by device thermal dissipation.
6. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
7. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
8. Total of current used by pull-ups to SDA, SCL, SALRT, DDC, EN, PG (including Push-pull configuration).
Electrical Specifications
V
= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature
DD A
range, T -40°C to +85°C.
A
MIN
MAX
PARAMETER
IC INPUT AND BIAS SUPPLY CHARACTERISTICS
TEST CONDITIONS
(Note 14)
TYP
(Note 14) UNITS
I
Supply Current
f
f
= 200kHz
26
50
50
80
mA
mA
mA
V
DD
SW
= 1.33MHz
SW
I
Device Disabled Current
EN = 0V, SMBus inactive, V = 12V, f
DD SW
= 1.33MHz
20
30
DD
VR5 Reference Output Voltage
V
> 6V, I < 5mA
4.5
2.25
5.5
5.0
2.5
6.1
5.25
5.5
2.75
6.6
5.5
DD
For reference only, VR > 3V
For reference only, V = 12V
V25 Reference Output Voltage
V
VR6 Reference Output Voltage
V
DD
> 5.5V; 0 to 80mA
VDRV 5V Output Voltage (Note 9)
OUTPUT CHARACTERISTICS
V
4.5
V
DD
Output Voltage Adjustment Range
Output Voltage Set-point Accuracy (Note 11)
Output Voltage Set-point Resolution (Note 10)
Output Voltage Positive Sensing Bias Current
Output Voltage Negative Sensing Bias Current
Logic Input/Output Characteristics
Logic Input Leakage Current
V
> V
OUT
+ 1.1V
0.54
-1
5.5
1
V
IN
Across line, load, temperature variation
Set using PMBus™ command
VSENP = 4V (negative = sinking)
VSENN = 0V
% V
OUT
±0.025
20
% V
OUT
-100
100
µA
20
µA
Logic I/O - multi-mode pins
-100
2
100
0.8
nA
V
Logic Input Low, V
IL
Logic Input High, V
V
IH
Logic Output Low, V
2mA sinking
0.5
V
OL
Logic Output High, V
2mA sourcing
2.25
V
OH
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ZL8801
Electrical Specifications
V
= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature
A
DD
range, T -40°C to +85°C. (Continued)
A
MIN
MAX
PARAMETER
PWM INPUT/OUTPUT CHARACTERISTICS
PWM Output Low
TEST CONDITIONS
(Note 14)
TYP
(Note 14) UNITS
2mA sinking
0.5
V
V
PWM Output High
2mA sourcing
4.25
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
200
-5
1334
5
kHz
%
Switching Frequency Set-point Accuracy
Minimum SYNC Pulse Width
50% to 50%
150
-10
100
ns
Input Clock Frequency Drift Tolerance
PMBus™ Clock Frequency (Note 12)
Maximum allowed drift of external clock
10
%
400
kHz
POWER MANAGEMENT
SOFT-START/RAMP CHARACTERISTICS
t
t
t
t
t
t
Delay/t
Delay/t
Delay
Factory default
5
ms
ms
ms
ms
ms
µs
ON
ON
ON
ON
ON
ON
OFF
OFF
Delay Range
Set using PMBus™ command
Turn on, Turn off delay
4
5
5000
100
Delay/T
Ramp/t
Ramp/t
Ramp/t
Delay Accuracy
Ramp Duration
Ramp Duration Range
Ramp Duration Accuracy
-0/+2
5
OFF
OFF
OFF
OFF
Factory default (2-phase only)
Set using PMBus™ command (2-phase only)
(2-phase only)
±250
70
TRACKING
VTRK Input Bias Current
VTRK Regulation Accuracy
POWER-GOOD
VTRK = 5V
200
2
µA
100% Tracking, V
– VTRK (2-phase only)
-2
% V
OUT
OUT
Power-good V
Power-good V
Threshold
Hysteresis
Factory default
Factory default
Factory default
90
5
% V
OUT
OUT
%
OUT
Power-good Delay
Applies to turn-on only (Low-to-high transition)
1
ms
ms
Set using PMBus™ command
0
5000
16
MONITORING AND FAULT MANAGEMENT
INPUT VOLTAGE MONITOR AND FAULT DETECTION
VDD/VIN UVLO Threshold Range
VDD/VIN Monitor Accuracy
2.85
V
% FS
%
Full Scale (FS) = 14V
Full Scale (FS) = 14V
±2
VDD/VIN Monitor Resolution
±0.15
100
VIN UV/OV Fault Response Delay
INPUT CURRENT
µs
Input Current Sense Differential Input Voltage
Input Current Sense Input Offset Voltage
Input Current Sense Accuracy
V
V
to V
to V
0
20
2
mV
µV
IINP
IINN
IINN
±100
±5
IINP
% of Full Scale (20mV)
% FS
OUTPUT VOLTAGE MONITOR AND FAULT DETECTION
VOUT Monitor Accuracy
FS = VSET voltage (V
FS = VSET voltage (V
)
)
-2
% FS
% FS
µs
OUT
VOUT Monitor Resolution
± 0.15
10
OUT
VOUT UV/OV Fault Response Delay
OUTPUT CURRENT
OUTPUT CURRENT SENSE INPUT RESOLUTION
Low Range
±25mV Full Scale
37.5
56.25
75
µV
µV
µV
Medium Range
High Range
±35mV Full Scale
±50mV Full Scale
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ZL8801
Electrical Specifications
V
= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature
A
DD
range, T -40°C to +85°C. (Continued)
A
MIN
MAX
PARAMETER
TEST CONDITIONS
(Note 14)
TYP
(Note 14) UNITS
OUTPUT CURRENT SENSE INPUT BIAS CURRENT
VOUT Referenced
ISENA0 or ISENA1
ISENB0 or ISENB1
OUTPUT CURRENT SENSE MONITOR AND FAULT DETECTION
-100
-25
100
25
nA
µA
IOUT Monitor Temperature Compensation
Factory default
3900
ppm/°C
Configurable via PMBus™
100
12700 ppm/°C
VMON BIAS MONITOR AND FAULT DETECTION
VMON UVLO Threshold Range
VMON Accuracy (Note 13)
Using VMON pin with 16:1 resistor divider
Full Scale (FS) = 1.15V
2.85
-2
5
2
V
% FS
% FS
µs
VMON Resolution
Full Scale (FS) = 1.15V
±0.15
200
VMON UV/OV Fault Response Delay
TEMPERATURE SENSING
Tested at +100°C
INTERNAL TEMPERATURE SENSOR
Internal Temperature Accuracy
Internal Temperature Resolution
-5
5
°C
°C
°C
°C
°C
1
Thermal Protection Threshold
(junction temperature)
Factory default
125
Configurable via PMBus™
-40
125
Thermal Protection Hysteresis
15
EXTERNAL TEMPERATURE SENSOR: XTEMP0 and XTEMP1
External Temperature Accuracy
±5
1
°C
°C
°C
°C
°C
External Temperature Resolution
Thermal Protection Threshold
Factory default
Configurable via PMBus™
125
-40
125
Thermal Protection Hysteresis
NOTES:
15
9. Output current is limited by device thermal dissipation.
10. Percentage of Full Scale (FS) with temperature compensation applied.
11. V
OUT
measured at the termination of the VSENP and VSENN sense points.
12. For operation at 400kHz, see PMBus™ Power System Management Protocol Specification Part 1, Section 5.2.6.2 for timing parameter limits.
13. Does not include errors due to resistor divider tolerances.
14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ZL8801
All power management functions can be configured using either
ZL8801 Overview
Digital-DC Architecture Overview
The ZL8801 is an innovative mixed-signal power conversion and
power management IC based on Intersil patented Digital-DC
technology that provides an integrated, high performance
step-down converter for a wide variety of power supply
applications.
pin configuration techniques described in this document or via
the SMBus interface using PMBus™ commands. Monitoring
parameters can also be preconfigured to provide alerts for
specific conditions. “PMBus™ Command Detail” starting on
page 30, contains a listing of all the PMBus™ commands
supported by the ZL8801 and a detailed description of the use of
each of these commands.
Multi-mode Pins
The ZL8801 DC/DC controller is a dual phase controller based on
an architecture that does not require loop compensation. Adaptive
algorithms enable the power converter to automatically change
the operating state to increase efficiency and overall performance
with no user interaction needed.
In order to simplify circuit design, the ZL8801 incorporates
patented multi-mode pins that allow the user to easily configure
many aspects of the device with no programming. Most power
management features can be configured using these pins. The
multi-mode pins can respond to four different connections as
shown in Table 2. These pins are sampled when power is applied.
The ZL8801 is a full digital loop that achieves precise control of
the entire power conversion process with no software required
resulting in a very flexible device that is also very easy to use. The
ChargeMode control algorithm is implemented that responds to
output current changes within a single PWM switching cycle,
achieving a smaller total output voltage variation with less output
capacitance than traditional PWM controllers. An extensive set of
power management functions are fully integrated and can be
configured using simple pin connections. The user configuration
can be saved in an internal nonvolatile memory (NVRAM).
Additionally, all functions can be configured and monitored via
the SMBus hardware interface using standard PMBus™
commands, allowing ultimate flexibility. The ZL8801 is compliant
with the PMBus™ Power System Management Protocol
Specification Part I and II version 1.2.
Pin-strap Settings: This is the simplest implementation method,
as no external components are required. Using this method, each
pin can take on one of three possible states: LOW, OPEN, or
HIGH. These pins can be connected to the V25 pin for logic HIGH
settings (excluding VDRVEN which should be left floating or tied
to VR5). Using a single pin, one of three settings can be selected.
TABLE 2. MULTI-MODE PIN CONFIGURATION
PIN TIED TO
VALUE
LOW (Logic LOW)
<0.8 VDC
OPEN (N/C)
No connection
>2.0 VDC
HIGH (Logic HIGH)
Resistor to SGND
Once enabled, the ZL8801 is immediately ready to regulate
power and perform power management tasks with no
programming required. Advanced configuration options and
real-time configuration changes are available via PMBus™
commands if desired and continuous monitoring of multiple
operating parameters is possible with minimal interaction from a
host controller. Integrated subregulation circuitry enables single
supply operation from any supply between 4.5V and 14V with no
bias supplies needed.
Set by resistor value
V25
LOGIC
HIGH
OPEN
The ZL8801 can be configured by simply connecting its pins
according to the tables provided in the following sections.
Additionally, a comprehensive set of online tools and application
notes are available to help simplify the design process. An
evaluation board is also available to help the user become
familiar with the device. This board can be evaluated as a
standalone platform using pin configuration settings. A
Windows™ based GUI is also provided to enable full configuration
and monitoring capability via the SMBus interface and the
included USB cable.
MULTI-MODE
PIN
MULTI-MODE
PIN
LOGIC
LOW
PIN-STRAP
SETTINGS
RESISTOR
SETTINGS
FIGURE 4. PIN-STRAP AND RESISTOR SETTING
Power Management Overview
The ZL8801 incorporates a wide range of configurable power
management features that are simple to implement with no
external components. Additionally, the ZL8801 includes circuit
protection features that continuously safeguard the device and load
from damage due to unexpected system faults. The ZL8801 can
continuously monitor input voltage and current, output voltage and
current, internal temperature and the temperature of an external
thermal diode. A power-good output signal is also included to enable
power-on reset functionality for an external processor.
Resistor Settings: This method allows a greater range of
adjustability when connecting a finite value resistor
(in a specified range) between the multi-mode pin and SGND.
Standard 1% resistor values are used and only every fourth E96
resistor value is used so the device can reliably recognize the
value of resistance connected to the pin while eliminating the
error associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
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ZL8801
SMBus: Almost any ZL8801 function can be configured via the
Output Voltage and VOUT_MAX Selection
(VSET)
The output voltage may be set to any voltage between 0.54V and
5.5V provided that the input voltage is higher than the desired
output voltage by at least 1.1V. Using the pin-strap method, V
can be set to any of the voltages shown in Table 4. The V
OUT
SMBus interface using standard PMBus™ commands.
Additionally, any value that has been configured using the
pin-strap or resistor setting methods can also be reconfigured
and/or verified via the SMBus. The “PMBus™ Command Detail”
section, starting on page 30, explains the use of the PMBus™
commands in detail.
OUT
can
also be set using a PMBus™ command. VOUT_MAX is also
determined by this pin-strap setting and is 10% greater than the
VSET voltage setting. VOUT_MAX can be set higher than this
pin-strap setting using the VOUT_MAX PMBus command.
Configurable Pins
Four operating parameters can be set using the pin-strap or
resistor setting method: The SMBus address (pin 5, SA), output
voltage (pin 10, VSET), switching frequency (pin 44, SYNC) and
input voltage undervoltage lockout (pin 13, UVLO).
TABLE 4.
RVSET
V
RVSET
V
OUT
OUT
(kΩ)
(V)
(kΩ)
(V)
The SMBus device address and the output voltage are the only
parameters that must be set by external pins. All other device
parameters can be set via the SMBus. The device address is set
using the SA pin. The output voltage is set using the VSET pin.
LOW (SGND)
OPEN
HIGH (>2.0V)
10
1.00
1.20
2.50
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.50
2.80
3.00
3.30
4.00
5.00
SMBus Device Address Selection (SA)
When communicating with multiple SMBus devices using the
SMBus interface, each device must have its own unique address
so the host can distinguish between the devices. The device
address can be set according to the pin-strap options listed in
Table 3. The SMBus address cannot be changed with a PMBus™
command.
11
12.1
13.3
14.7
16.2
82.5
90.9
100
110
121
133
147
162
178
TABLE 3. SMBus DEVICE ADDRESS SELECTION
17.8
RSA
SMBus
RSA
SMBus
(kΩ)
ADDRESS
(kΩ)
ADDRESS
19.6
LOW (SGND)
OPEN
10
26h
28h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
42.2
46.4
51.1
56.2
61.9
68.1
75
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
21.5
23.7
26.1
11
28.7
12.1
13.3
14.7
16.2
17.8
31.6
34.8
82.5
90.9
100
110
121
133
147
162
178
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
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ZL8801
limits given in the “Logic Input/Output Characteristics” on page 9.
The SYNC pin will not be checked for an incoming clock signal
while in this mode.
Switching Frequency Setting (SYNC)
The device’s switching frequency is set from 200kHz to 1333kHz
using the pin-strap method as shown in Table 5, or by using a
PMBus™ command. The ZL8801 generates the device switching
frequency by dividing an internal precision 16MHz clock by
integers from 12 to 80. 500kHz (n = 32) and 1000kHz (n = 16)
are not recommended operating frequencies; use 533kHz
(or 516kHz if setting the frequency with PMBus) and 1067kHz
instead.
The switching frequency can be set to any value between 200kHz
and 1.33MHz using a PMBus™ command. The available
frequencies below 1.33MHz are defined by f
= 16MHz/N,
SW
where 12 ≤ N ≤ 80.
If a value other than f
SW
= 16MHz/N is entered using a PMBus™
command, the internal circuitry will select the switching
frequency value using N as a whole number to achieve a value
close to the entered value. For example, if 810kHz is entered, the
device will select 800kHz (N = 20).
TABLE 5.
RSYNC
(kΩ)
FREQ
(kHz)
RSYNC
kΩ
FREQ
(kHz)
Input Voltage Undervoltage Lockout Setting
(UVLO)
The input undervoltage lockout (UVLO) prevents the ZL8801 from
operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The input
voltage undervoltage lockout threshold can be set between
2.85V and 16V using the pin-strap method as shown in Table 6.
The UVLO can also be set or changed using the
LOW (SGND)
OPEN
HIGH (>2.0V)
10
200
400
1067
200
222
242
267
296
320
364
400
421
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
471
533
571
615
11
727
12.1
800
VIN_UV_FAULT_LIMIT command.
13.3
842
14.7
889
TABLE 6.
16.2
1067
1143
1231
1333
RUVLO
(kΩ)
UVLO
(V)
RUVLO
(kΩ)
UVLO
(V)
17.8
LOW (SGND)
OPEN
Not used
4.5
46.4
51.1
56.2
61.9
68.1
75
7.42
8.18
19.6
21.5
HIGH (>2.0V)
26.1
10.8
4.18
4.59
5.06
5.57
6.13
6.75
8.99
9.90
The ZL8801 incorporates an internal phase-locked loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin. When using the internal
oscillator, the SYNC pin can be configured as a clock source for
other Intersil digital power devices.
28.7
10.90
12.00
13.20
14.54
16.00
31.6
34.8
82.5
90.9
100
38.3
The SYNC pin can also be configured as an input. When
configured as an input, the device will automatically check for a
clock signal on the SYNC pin each time EN is asserted. The
ZL8801’s oscillator will then synchronize with the rising edge of
the external clock.
42.2
Once an input undervoltage fault condition occurs, the user may
determine the desired response to the fault condition. The
following input undervoltage protection response options are
available:
The incoming clock signal must be in the range of 200kHz to
1.33MHz, meet the limits given in the “Logic Input/Output
Characteristics” on page 9 and must be stable when the enable
pin (EN) is asserted. When using an external clock, the
frequencies are not limited to discrete values as when using the
internal clock. The external clock signal must not vary more than
10% from its initial value and should have a minimum pulse
width of 150ns. In the event of a loss of the external clock signal,
the output voltage may show transient overshoot or undershoot.
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The default response from an undervoltage fault is to shut down
and stay off until the fault has cleared and the device has been
disabled and reenabled (see option 1).
Refer to “PMBus™ Command Detail”, starting on page 30 of this
document, for details on how to select specific undervoltage fault
response options using the VIN_UV_FAULT_RESPONSE
command.
If loss of synchronization occurs, the ZL8801 will automatically
switch to its internal oscillator and switch at its configured
frequency. For this reason, it is important to configure the
ZL8801 to a frequency close to the expected external clock
frequency.
When controlling the ZL8801 exclusively through the PMBus™, a
high voltage setting for UVLO can be used to prevent the ZL8801
from being enabled until a lower voltage for UVLO is set using the
VIN_UV_FAULT_LIMIT command.
The SYNC pin can also be configured as an output. The device will
run from its internal oscillator and will drive the SYNC pin so other
devices can be synchronized to it. The output will conform to the
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ZL8801
Internal Bias Regulators and Input Supply
Connections
The ZL8801 employs internal low dropout (LDO) regulators to
supply bias voltages for internal circuitry, allowing it to operate
from a single input supply. The internal bias regulators are as
follows:
VIN
VIN
VDD
VR6
VDD
VR6
VR6: The VR6 LDO provides a regulated 6.1V bias supply for
internal circuitry. It is powered from the VDD pin. A 4.7µF
ceramic X7R filter capacitor to SGND is required at the VR6 pin.
Keep this net as small as possible and avoid routing this net near
any switching signals.
VR5
VR5
VR5: The VR5 LDO provides a regulated 5.1V bias supply for
internal circuitry. It is powered from the VDD pin. A 4.7µF
ceramic X7R filter capacitor to SGND is required at the VR5 pin.
This supply may be used for to provide a pull-up supply as long as
load current does not exceed 5mA.
4.5V < VIN < 5.5V
5.5V < VIN < 14V
FIGURE 5.
Start-up Procedure
The ZL8801 follows a specific internal start-up procedure after
power is applied to the VDD pin, as shown in Figure 6.
V25: The V25 LDO provides a regulated 2.5V bias supply for the
main controller circuitry. It is powered from an internal 5V node.
A 4.7µF ceramic X7R filter capacitor to SGND is required at the
V25 pin. The V25 supply is used to power internal IC circuitry. It
should only be used externally to set pin-strap pins to the HIGH
state.
The device requires approximately 30ms to check for specific
values stored in its internal memory. If the user has stored values
in memory, those values will be loaded.
VDRV: The VDRV LDO provides a regulated 5.25V bias supply for
external MOSFET driver ICs or DrMOS integrated drivers/FETs. A
4.7µF ceramic X7R filter capacitor to PGND is required, however,
additional capacitance will be needed as specified by the
MOSFET driver or DrMOS device selected. The maximum rated
output current is 80mA, but device thermal limits must be
considered. The power dissipated by the VDRV supply, as shown
by Equation 1.
Once this process is completed, the device is ready to accept
commands via the serial interface and the device is ready to be
enabled. If the device is to be synchronized to an external clock
source, the clock frequency must be stable prior to asserting the
EN pin. Once enabled, the device requires approximately 2ms
before its output voltage may be allowed to start its ramp-up
process.
After the TON_DELAY period has expired, the output will begin to
ramp towards its target voltage according to the preconfigured
ton-rise time.
(EQ. 1)
VIN – 5.25Vx IDRV
where IDRV is the current supplied by the VDRV bias supply. The
VDRV is enabled by leaving the VDRVEN unconnected (floating)
or connecting it to VR5 and is disabled by connecting VDRVEN to
ground.
INTERNAL MEMORY
CHECK
20ms TO 30ms
DEVICE WILL IGNORE AN
INPUT POWER APPLIED
ENABLE SIGNAL OR
PMBUS COMMANDS
NOTE: The internal bias regulators, VR6, VR5 and V25, are not
designed to be outputs for powering other circuitry. The
multi-mode pins may be connected to the V25 pin for logic HIGH
settings and the VR5 supply should be used to provide up to 5mA
of pull-up current for the SDA, SCL, SALRT, DDC and PG pins.
PRE-RAMP DELAY
MINIMUM 2ms
DELAY BETWEEN ENABLE
SIGNAL AND START OF
DEVICE READY
Operation with 5V VDD: When operating the ZL8801 at voltages
below 5.5V, the VR6 and VR5 supplies should be connected
OUTPUT RAMP.
ADDITIONAL DELAY MAY
BE ADDED WITH PMBUS
COMMAND
directly to V for best performance. The VDRV supply should not
DD
be used; the 5V VDD supply should be used instead for powering
DrMOS and MOSFET driver ICs.
FIGURE 6. ZL8801 INTERNAL START-UP PROCEDURE
The V should be above the ZL8801’s UVLO limit
IN
(VIN_UV_FAULT_LIMIT) before the Enable pin is driven high.
Following this sequence will result in the most consistent turn-on
delays. When V is first applied to the ZL8801, for example
IN
during initial PCB turn-on and test, the Enable pin must be held
low by some means until the ZL8801 configuration file can be
loaded. If the Enable pin is not held low, then the ZL8801 may
attempt to turn-on with incorrect configuration settings, possibly
causing circuit failure.
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ZL8801
In those cases where the Enable pin cannot be held low during
the initial application of power, two options are available:
circuit. When the ZL8801 is used in a self-enabled mode, for
example, when EN is tied to VR5, or to a resistor divider to V
,
IN
the user must consider the ZL8801's default factory settings.
1. Limit V to 3.0V during initial testing. The ZL8801
IN
When a configuration file is used to configure the ZL8801, the
factory default settings are restored to both the user and default
stores in order to set the ZL8801 to an initialized state. Since the
default state of the ZL8801 is to be enabled when the enable pin
is high, it is possible for the ZL8801 to be enabled while the
PMBus™ commands are sent to the ZL8801 during the
configuration process. For this reason self-enabled mode is not
recommended for the ZL8801.
configuration file can be loaded when V is as low as 3V.
IN
Once the configuration file is loaded V can be increased to
IN
the normal input voltage range.
2. Use a 100kΩ resistor to set UVLO to 16V. This will keep the
ZL8801 disabled while the configuration file is loaded. Ensure
that the VIN_UV_FAULT_LIMIT command is the last command
in the configuration file.
TON Delay and Rise Times
Power-good
In some applications, it may be necessary to set a delay from
when an enable signal is received until the output voltage starts
to ramp to its target value. In addition, the designer may wish to
The ZL8801 provides a power-good (PG) signal that indicates the
output voltage is within a specified tolerance of its target level
and no fault condition exists. By default, the PG pin will assert if
the output is within 10% of the target voltage. These limits may
be changed using PMBus™ commands.
precisely set the time required for V
to ramp to its target
OUT
value after the delay period has expired. The ZL8801 gives the
system designer the ability to independently control both the
delay and ramp time periods.
A PG delay period is defined as the time from when all conditions
within the ZL8801 for asserting PG are met to when the PG pin is
actually asserted. This feature is commonly used instead of using
an external reset controller to control external digital logic. By
default, the ZL8801 PG delay is set equal to 1ms. The PG delay
may be set using a PMBus™ command as described in the
“PMBus™ Command Summary” on page 25.
The TON_DELAY time begins when the EN pin is asserted. The
TON_DELAY time is set using the PMBus™ command TON_DELAY.
The TON-RISE time enables a precisely controlled ramp to the
nominal V
value that begins once the TON_DELAY time has
OUT
expired. The ramp-up is monotonic and its slope may be precisely
set using the PMBus™ command TON_RISE.
Power Management Functional
Description
The TON_DELAY and TON_RAMP times can be set using
PMBus™ commands TON_DELAY and TON_RISE over the serial
bus interface. When the TON_DELAY time is set to 0ms, the
device will begin its ramp after the internal circuitry has
initialized.
Output Overvoltage Protection
The ZL8801 offers an internal output overvoltage protection
circuit that can be used to protect sensitive load circuitry from
being subjected to a voltage higher than its prescribed limits. A
hardware comparator is used to compare the actual output
voltage (seen at the VSEN pins) to a programmable threshold set
to 10% higher than the target output voltage (the default setting).
If the VSEN voltage exceeds this threshold, the PG pin will
deassert and the device can then respond to the following
options:
The TON_DELAY and TON_RAMP times can be set using PMBus™
commands TON_DELAY and TON_RISE over the serial bus
interface. When the TON_DELAY time is set to 0ms, the device
will begin its ramp after the internal circuitry has initialized which
takes approximately 2ms to complete. The TON_RISE time may
be set to values less than 2ms, however the TON_RISE time
should be set to a value greater than 500µs to prevent
inadvertent fault conditions due to excessive inrush current. A
lower TON_RISE time limit can be estimated using the formula
as shown by Equation 2.
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
(EQ. 2)
2. Shut down and restart continuously after a delay.
TON_RISE = C
*V
OUT OUT
The default response from an overvoltage fault is to shut down
and stay off until the fault has cleared and the device has been
disabled and reenabled (see option 1).
Where C
is the total output capacitance, V is the output
OUT
OUT
voltage and limit is the current limit setting for the ZL8801.
When interdevice current sharing is used (4-, 6- or 8- phases), the
output voltage rise time will vary by application. The rise time in
this case can be adjusted using the PMBus command
MULTI_PHASE_RAMP_GAIN. Higher gain values produce faster
turn-on ramps. Typical MULTI_PHASE_RAMP_GAIN values range
between 1 and 10; the default value is 3.
Refer to the “PMBus™ Command Detail” section, starting on
page 30, for details on how to select specific overvoltage fault
response options using the VOUT_OV_FAULT_RESPONSE
command.
Output Prebias Protection
The ZL8801 provides prebiased start-up operation. An output
prebias condition exists when an externally applied voltage is
present on a power supply's output before the power supply's
control IC is enabled. Certain applications require that the
converter not be allowed to sink current during start-up if a
prebias condition exists at the output. The ZL8801 provides
Enable
The enable pin (EN) is used to enable and disable the ZL8801.
The enable pin should be held low whenever a configuration file
or script is used to configure the ZL8801, or a PMBus™
command is sent that could potentially damage the application
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ZL8801
prebias protection by sampling the output voltage prior to
initiating an output ramp. If a prebias voltage lower than the
desired output voltage is present after the TON_DELAY time, the
ZL8801 starts switching with a duty cycle that matches the
prebias voltage. This ensures that the ramp-up from the prebias
voltage is monotonic. The output voltage is then ramped to the
desired output voltage at the ramp rate set by the TON_RISE
command. The resulting output voltage rise time will vary
depending on the prebias voltage, but the total time elapsed
from the end of the TON_DELAY time to when the TON-RISE time
is complete and the output is at the desired value will match the
preconfigured ramp time (see Figure 7).
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
The default response from an overcurrent voltage fault is to shut
down and stay off until the fault has cleared and the device has
been disabled and reenabled (see option 1).
Refer to the “PMBus™ Command Detail” section, starting on
page 30, for details on how to select specific overcurrent fault
response options using the IOUT_OC_FAULT_RESPONSE
command.
CURRENT SENSING COMPONENTS
VOUT
The ZL8801 uses the inductor DCR current sensing technique.
Current sensing is achieved by selecting an R/C network as
shown in Figure 8.
DESIRED
OUTPUT
VOLTAGE
VIN
PREBIAS
VOLTAGE
VDRV
VDD
GH
L
VOUT
PWMH
PWML
BST
GL
TIME
tON
tON
DELAY
RISE
R1
ZL8801
C1
VPREBIAS < VTARGET
ISENA
ISENB
VOUT
PREBIAS
VOLTAGE
FIGURE 8. DCR CURRENT SENSING (ONLY 1 PHASE SHOWN)
DESIRED
OUTPUT
VOLTAGE
For the voltage across C to reflect the voltage across the DCR of
1
the inductor, the time constant of the inductor must match the
time constant of the RC network, as shown in Equation 3:
RC L / DCR
(EQ. 3)
TIME
L
tON
DELAY
R1 C1
tON
RISE
DCR
For L, use the average of the nominal value and the minimum
value. Include the effects of tolerance, DC bias and switching
frequency on the inductance when determining the minimum
value of L. Use the typical room temperature value for DCR.
VPREBIAS > VTARGET
FIGURE 7. OUTPUT RESPONSES TO PREBIAS VOLTAGES
If a prebias voltage higher than the target voltage exists after the
preconfigured TON-DELAY time and TON-RISE time have
completed, the ZL8801 starts switching with a duty cycle that
matches the prebias voltage. This ensures that the ramp down
from the prebias voltage is monotonic. The output voltage is then
ramped down to the desired output voltage.
The value of R should be as small as feasible and no greater
1
than 5kΩ for best signal-to-noise ratio. The designer should make
sure the resistor package size is appropriate for the power
dissipated and include this loss in efficiency calculations. In
calculating the minimum value of R , the average voltage across
1
C (which is the average I , DCR product) is small and can be
1
OUT
If a prebias voltage higher than the overvoltage limit exists, the
device will not initiate a turn on sequence and will stay off with
an output OV fault recorded.
neglected. Therefore, the minimum value of R may be
1
approximated by Equation 4:
V – V
V
OUT
IN
OUT
(EQ. 4)
----------------------------------------------------------
R1
=
Output Overcurrent Protection
min
P
R1
The ZL8801 can protect the power supply from damage if the
output is shorted to ground or if an overload condition is imposed
on the output. Once the current limit threshold has been selected
(see “Current Limit Configuration” on page 18), the user may
determine the desired response to the fault condition. The
following overcurrent protection response options are available:
where P is the maximum power dissipation specification for
R1
the resistor. Once R1
has been calculated, solve for the
min
maximum value of C1 from Equation 5:
L
(EQ. 5)
C1max
R1min DCR
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ZL8801
Choose the next lowest readily available value (e.g., for
C1 = 1.86µF, C = 1.5µF is a good choice). Then substitute
current sense resistor. Using the IIN_SCALE command, set the
current sense resistor value. Select the current sense resistor
value such that the maximum expected input current times the
current sense resistor value does not exceed the maximum
current sensing input voltage of 20mV. If this feature is not used,
IINN and IINP should be tied to VDD.
max
the chosen value into the same equation and recalculate the
value of R . Choose the 1% resistor standard value closest to this
1
1
recalculated value of R .
1
Current Limit Configuration
Thermal Overload Protection
The ZL8801 includes an on-chip thermal sensor that continuously
measures the internal temperature of the die. This thermal
sensor is used to provide both over-temperature and
The ZL8801 gives the power supply designer several choices for
the fault response during over or undercurrent condition. The
user can select the number of violations allowed before declaring
fault, a blanking time and the action taken when a fault is
detected. These parameters are configured using the
ISENSE_CONFIG command.
under-temperature protection. If the over-temperature limit is
exceeded, or the temperature falls below the under-temperature
limit, the ZL8801 is shut down. The over-temperature and
under-temperature limits are set by the OT_FAULT_LIMIT and
UT_FAULT_LIMIT respectively. The ZL8801 will not attempt to
restart until the temperature has fallen below the
OT_WARN_LIMIT for over-temperature faults or has risen above
the UT_WARN_LIMIT for under-temperature faults. The default
temperature limits are +125°C and -45°C, but the user may set
the limits to different values if desired. Note that setting a higher
over-temperature or under-temperature limit may result in
permanent damage to the device. Once the device has been
disabled due to an internal temperature fault, the user may
select one of the fault response options as follows:
The blanking time represents the time when no current
measurement is taken. This is to avoid taking a reading just after
a switching transition (less accuracy due to potential ringing). It is
a configurable parameter from 0 to 832ns.
The ZL8801 provides an adjustable maximum full scale sensing
range. Three ranges are available: ±25mV, ±35mV and ±50mV
maximum input voltage.
By default, current sensing is enabled during the inductor current
down slope period of the switching period (D). In applications
where the steady state duty cycle is >0.5, for example a 5V to
3.3V converter, the ZL8801 can be configured to sense current
during the inductor up slope period of the switching cycle (D).
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
The user has the option of selecting how many consecutive
overcurrent readings must occur before an overcurrent fault and
subsequent shutdown are initiated. Either 1, 3, 5, 7, 9, 11, 13 or
15 consecutive faults can be selected.
2. Shut down and restart continuously after a delay.
The default response from an over-temperature or
under-temperature fault is to shut down and stay off until the
fault has cleared and the device has been disabled and
reenabled (see option 1).
Once the ISENSE_CONFIG parameters have been selected, the
user must select the desired current limit thresholds and the
resistance of the sensing element.
Refer to the “PMBus™ Command Detail” section, starting on
page 30, for details on how to select specific over-temperature or
under-temperature fault response options using the
The current limit thresholds are set with 4 commands:
OT_FAULT_RESPONSE and UT_FAULT_ RESPONSE commands.
1. IOUT_OC_FAULT_LIMIT – this sets the overcurrent threshold
that must be exceeded by the number of consecutive times
chosen in ISENSE_CONFIG.
Voltage Tracking
Numerous high performance systems place stringent demands
on the order in which the power supply voltages are turned on.
This is particularly true when powering FPGAs, ASICs and other
advanced processor devices that require multiple supply voltages
to power a single die. In most cases, the I/O interface operates at
a higher voltage than the core and therefore the core supply
voltage must not exceed the I/O supply voltage according to the
manufacturers' specifications.
2. IOUT_UC_FAULT_LIMIT – this is the same as
IOUT_OC_FAULT_LIMIT, but represents the negative current
that flows in the lower FET during the D’ interval. Large
negative currents can flow during faults such as when a
higher voltage rail is shorted to a lower voltage rail.
3. IOUT_AVG_OC_FAULT_LIMIT – this limit is similar to
IOUT_OC_FAULT_LIMIT, but the limit represents an average
reading over several switching cycles. Since it is an average,
the response time is slower, but the limit can be set closer to
the maximum average expected output current.
The ZL8801 integrates a tracking scheme that allows its output
to track a voltage that is applied to the VTRK pin with no external
components required. The VTRK pin is an analog input that,
when tracking mode is enabled, configures the voltage applied to
the VTRK pin to act as a reference for the device’s output
regulation. Tracking can only be used when operating as a
2-phase controller, i.e.; when the device is not part of a current
sharing group.
4. IOUT_AVG_UC_FAULT_LIMIT – this limit is similar to
IOUT_AVG_OC_FAULT_LIMIT, but represents the negative
current that flows in the lower FET during the D’ interval.
Input Current Monitor
The input current can be monitored through the IINN and IINP
pins. The input current monitor input should be connected across
a current sensing resistor in series with the input supply. The IINP
pin is connected to the input supply side of the current sense
resistor, the IINN pin is connected to the ZL8801 VDD side of the
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ZL8801
Figure 9 illustrates the typical connection and the two tracking
Default margin limits of V ±5% are preloaded in the factory,
OUT
modes:
but the margin limits can be modified through to be as high as
5.5V or as low as 0V.
Coincident: This mode configures the ZL8801 to ramp its output
voltage at the same rate as the voltage applied to the VTRK pin.
Additionally, the transition rate between the nominal output
voltage and either margin limit can be configured using the
VOUT_TRANSITION_RATE command.
Ratiometric. This mode configures the ZL8801 to ramp its output
voltage at a rate that is a percentage of the voltage applied to the
VTRK pin. The default setting is 50%, but an external resistor
string may be used to configure a different tracking ratio. The
device that is tracking another output voltage (slave) must be set
to its desired steady-state output voltage.
External Voltage Monitoring
The voltage monitoring (VMON) pin is available to monitor the
voltage supply for the external driver IC. The VMON input must be
scaled by a 16:1 ratio in order to read-back the VMON voltage
correctly. A 100kΩ and 6.65kΩ resistor divider is recommended.
Overvoltage and undervoltage fault thresholds can be set using
MFR_VMON_OV_FAULT_LIMIT and MFR_ VMON_UV_FAULT_LIMIT
commands. The response to these limits are set using the
VMON_OV_FAULT_RESPONSE and VMON_ UV_FAULT_RESPONSE
commands.
The master ZL8801 device in a tracking group is defined as the
device that has the highest target output voltage within the
group. This master device will control the ramp rate of all
tracking devices and is not configured for tracking mode.
The maximum tracking rise-time is 1V/ms. The slave device
must be enabled before the master.
Once the device has been disabled due to VMON fault, the user
may select one of the following fault response option:
Any device that is configured for tracking mode will ignore its
TON_DELAY and TON_RISE settings and its output will take on
the turn-on/turn-off characteristics of the reference voltage
present at the VTRK pin.
1. Shut down and stay off until the fault has cleared and the
device has been disabled and reenabled.
2. Shut down and restart continuously after a delay.
Tracking mode can be configured by using the TRACK_CONFIG
command.
The default response from an overvoltage or undervoltage VMON
fault is to shut down and stay off until the fault has cleared and
the device has been disabled and reenabled (see option 1).
VOUT
VTRACK
SMBus Communications
The ZL8801 provides a SMBus digital interface. The ZL8801 can
be used with any standard 2-wire SMBus host device. In addition,
the device is compatible with SMBus version 2.0 and includes an
SALRT line to help mitigate bandwidth limitations related to
continuous fault monitoring. Pull-up resistors are required on the
SMBus. The pull-up resistor may be tied to VR5 or to an external
3.3V or 5V supply as long as this voltage is present prior to or
during device power-up. The ideal design will use a central pull-up
resistor that is well-matched to the total load capacitance. The
minimum pull-up resistance should be limited to a value that
enables any device to assert the bus to a voltage that will ensure
a logic 0 (typically 0.8V at the device monitoring point) given the
pull-up voltage (5V if tied to VR5) and the pull-down current
capability of the ZL8801 (nominally 4mA). A pull-up resistor of
10kΩ is a good value for most applications.
VOUT
TIME
COINCIDENT
VOUT
VTRACK
VOUT
The SMBus Data and Clock lines should be routed with a closely
coupled return or ground plane to minimize coupled interference
(noise). Excessive noise on the data and clock lines that cause
the voltage on these lines to cross the high and low logic
thresholds of 2.0V and 0.8V respectively, will cause command
transmissions to be interrupted and result in slow bus operation
or missed commands. For less than 10 devices on an SMBus, a
10kΩ resistor on each line provides good performance.
TIME
RATIOMETRIC
FIGURE 9. TRACKING MODES
Voltage Margining
The ZL8801 offers a simple means to vary its output higher or
lower than its nominal voltage setting in order to determine
whether the load device is capable of operating over its specified
supply voltage range. Margining is controlled through the
OPERATION command.
The ZL8801 accepts most standard PMBus™ commands. When
enabling the device with ON_OFF_CONFIG command, it is
recommended that the enable pin is tied to SGND.
In addition to bus noise considerations, it is important to ensure
that user connections to the SMBus are compliant to the
PMBus™ command standards. Any device that can malfunction
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ZL8801
in a way that permanently shorts SMBus lines will disable
In order to enable phase spreading, all converters must be
synchronized to the same switching clock. Configuring the SYNC
pin is described in the Configuration Pin on page 6 The ZL8801
will automatically offset the phase of parallel connected
ZL8801s in a current sharing group. Selecting the phase offset
for the device is accomplished by selecting a device address
according to Equation 7:
PMBus™ communications. Incomplete PMBus™ commands can
also cause the ZL8801 to halt PMBus™ communications. This
can be corrected by disabling, then reenabling the device.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to communicate
between Intersil digital power Digital-DC devices. This dedicated bus
provides the communication channel between devices for features
such as sequencing, fault spreading and current sharing. The DDC
pin must be pulled up to an external 3.3V or 5.0V supply, even if the
ZL8801 is operating standalone. If the ZL8801 is used in a
standalone circuit and will not have its DDC pin connected to any
other devices, the ZL8801 DDC pin can be configured as a push-pull
output using the MFR_USER_CONFIG command and the pull-up
resistor can be eliminated. In addition, the DDC pin must be
pulled up (or configured as a push-pull output, with the limitations
listed previously) before the Enable pin is set high. The DDC pin on
all Digital-DC devices that utilize sequencing, fault spreading or
current sharing must be connected together. The DDC pin on all
Digital-DC devices in an application should be connected together. A
pull-up resistor is required on the DDC bus in order to guarantee the
rise time as shown by Equation 6:
(EQ. 7)
Phase offset = device address 45
This behavior is illustrated in Table 7.
:
TABLE 7.
PHASE OFFSET
(°)
PHASE OFFSET
(°)
ADDRESS LSB
ADDRESS LSB
0
1
2
3
4
5
6
7
0
8
9
A
B
C
D
E
F
0
45
45
90
90
135
180
225
270
315
135
180
225
270
315
(EQ. 6)
Rise Time = R
C
1s
LOAD
PU
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments using the
INTERLEAVE PMBus™ command.
Where R is the DDC bus pull-up resistance and C
PU
is the
LOAD
bus loading. The pull-up resistor may be tied to VR5 or to an
external 3.3V or 5V supply as long as this voltage is present prior
to or during device power-up. As a rule of thumb, each device
connected to the DDC bus presents approximately 12pF of
capacitive loading. The ideal design will use a central pull-up
resistor that is well matched to the total load capacitance. In
power module applications, the user should consider whether to
place the pull-up resistor on the module or on the PCB of the end
application. The minimum pull-up resistance should be limited to
a value that enables any device to assert the bus to a voltage that
will ensure a logic 0 (typically 0.8V at the device monitoring
point) given the pull-up voltage (5V if tied to VR5) and the
pull-down current capability of the ZL8801 (nominally 4mA). As
with SMBus data and clock lines, the DDC data line should be
routed with a closely coupled return or ground plane to minimize
coupled interference (noise). Excessive noise on the DDC signal
can cause the voltage on this line to cross the high and low logic
thresholds of 2.0V and 0.8V respectively and will cause
Output Sequencing
A group of Intersil digital power devices may be configured to
power-up in a predetermined sequence. This feature is especially
useful when powering advanced processors, FPGAs and ASICs
that require one supply to reach its operating voltage prior to
another supply reaching its operating voltage in order to avoid
latch-up from occurring. Multi-device sequencing can be
achieved by configuring each device using the SEQUENCE
PMBus™ command.
Multiple device sequencing is achieved by issuing PMBus™
commands to assign the preceding device in the sequencing
chain as well as the device that will follow in the sequencing
chain.
The enable (EN) pins of all devices in a sequencing group must be
tied together and driven high to initiate a sequenced turn on of
the group. Enable must be driven low to initiate a sequenced
turn off of the group. The DDC pins of all devices in a sequencing
group must be connected together to ensure accurate
sequencing.
command transmissions to be interrupted and result in slow bus
operation or missed commands. For less than 10 devices on the
DDC bus, a 10kΩ resistor provides good performance.
Phase Spreading
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices have coincident rising
edges. Setting each converter to start its switching cycle at a
different point in time can dramatically reduce input capacitance
requirements. Since the peak current drawn from the input
supply is effectively spread out over a period of time, the peak
Sequencing can also be accomplished by connecting the enable
pin of a sequel device to the power-good pin of a prequel device.
Sequencing is also achieved by using the TON_DELAY and
TON_RISE commands and choosing appropriate delay and rise
durations such that sequel devices start after their associated
prequel devices. The drawback to this method is that if a prequel
device fails to start properly, its sequel device will still start and
ramp on according to its delay and rise time settings. The best
sequencing performance is achieved by using the SEQUENCE
command and tying the Enable and DDC pins of the sequencing
current drawn at any given moment is reduced and the power
2
losses proportional to I
are reduced.
RMS
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ZL8801
group devices together. If the DDC pins of the devices are not
connected together and the user depends on TON_DELAY and
TOFF_DELAY values alone to ensure device sequencing, timing
accuracy will suffer. This is due to the 0ms to 4ms delay
variability between ZL8801 devices.
VREFERENCE
-R
VMEMBER
-R
Fault Spreading
Digital-DC devices can be configured to broadcast a fault event
over the DDC bus to the other devices in the group. When a fault
occurs and the device is configured to shut down on a fault, the
device will shut down and broadcast the fault event over the DDC
bus. The other devices on the DDC bus will shut down together if
configured to do so, and will attempt to restart in their prescribed
order if configured to do so.
IMEMBER
IOUT
IREFERENCE
FIGURE 11. ACTIVE CURRENT SHARING
When current sharing up to 4 sets of ZL8801s (8 phases total),
the ZL8801 uses a low-bandwidth, first-order digital current
sharing technique to balance the unequal device output loading
by aligning the load lines of member devices to a reference
device.
Active Current Sharing
The PWM outputs of the ZL8801 are used in parallel to create a
dual phase power rail. The device outputs will share the current
equally within a few percent, assuming all external sensing
element variations and tolerances are negligible. Current sensing
element tolerances must be taken into account, or adjusted for
using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands in
any application.
Upon system start-up, the lowest numbered phase is defined as
the reference phase and all other phases are member phases.
The reference phase broadcasts its current over the DDC bus. The
member phases use the reference current information to trim
their reference voltages (V
loading of each device in the system.
) to balance the current
MEMBER
Figure 10 shows a typical connection for a dual phase converter.
The ZL8801 will current share between phases without utilizing
output voltage droop.
Figure 11 shows that, for load lines with identical slopes, the
member reference voltage is increased towards the reference
voltage, which closes the gap between the inductor currents.
Droop resistance is used in 4-, 6- and 8-phase current sharing to
add artificial resistance in the output voltage path to control the
slope of the load line curve, calibrating out the physical parasitic
mismatches due to power train components and PCB layout.
The relation between reference and member current and voltage
is given by Equation 8:
VIN
(EQ. 8)
VMEMBER VOUT R
IREFERENCE IMEMBER
Where R is the value of the droop resistance.
The ISHARE_CONFIG command is used to configure the device
for active current sharing. The default setting is a standalone non
current sharing, two-phase device. A current sharing rail can be
part of a system sequencing group.
VOUT
A 4-, 6- or 8-phase current sharing group must have their DDC
and SYNC pins tied together in order to achieve current sensing
and accurate phase offsets between current sharing phases.
ZL8801
VI
N
Temperature Monitoring Using XTEMP Pin
The ZL8801 supports measurement of an external device
temperature using either a thermal diode integrated in a
processor, FPGA or ASIC, or using a discrete diode-connected
2N3904 NPN transistor. Figure 12 illustrates the typical
connections required. A noise filtering capacitor, not exceeding
100pF, may be connected close to the ZL8801 XTEMP pins for
long or noisy trace runs. The external temperature sensors can
be used to provide the temperature reading for over-temperature
and under-temperature faults. The external sensors can also be
used to provide more accurate temperature compensation for
inductor DCR current sensing by being placed close to the
inductor. When routing the XTEMP signals between the inductor
and the ZL8801, these PCB traces should be kept away from the
switch node; (node connected the inductor to the MOSFET
switches).
FIGURE 10. DUAL PHASE SIMPLIFIED CIRCUIT
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ZL8801
DUAL OUTPUT PWM PER PHASE
The ZL8801 has been designed to provide independent upper
and lower FET drive signals to a 2 input MOSFET driver such as
the ZL1505.
XTEMPxP
XTEMPxN
100pF
2N3904
ZL
The ZL8801 utilizes adaptive deadtime control to improve the
power conversion efficiency. The ZL8801 monitors the power
converter’s operating conditions and continuously adjusts the
turn-on and turn-off timing of the high-side and low-side driver
input signals to optimize the overall efficiency of the power supply.
DISCRETE NPN
The ZL8801 can also be used with single-ended DrMOS
integrated driver and MOSFET devices. The DrMOS device or
single-ended MOSFET driver must have a fast-acting enable pin.
Power supplies using DrMOS devices can be made smaller than
discrete solutions utilizing separate drivers and MOSFETs, but at
a slightly lower efficiency. The option to use DrMOS or drivers and
discrete MOSFETs is set using the USER_CONFIG command.
XTEMPxP
µP
FPGA
DSP
ASIC
100pF
ZL
XTEMPxN
EMBEDDED THERMAL DIODE
Power Train Component Selection
FIGURE 12. EXTERNAL TEMPERATURE MONITORING
The ZL8801 is a dual phase synchronous buck converter that
uses external Drivers, MOSFETs, inductors and capacitors to
perform the power conversion process. The proper selection of
the external components is critical for optimized performance.
Nonvolatile Memory (NVRAM) and Security
Features
The ZL8801 has internal nonvolatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the device to a level that has been
made available to them. During the initialization process, the
ZL8801 checks for stored values contained in its internal
nonvolatile memory. The ZL8801 offers two internal memory
storage units that are accessible by the user as follows:
To select the appropriate external components for the desired
performance goals, the power supply requirements listed in
Table 8 must be known.
TABLE 8. POWER SUPPLY REQUIREMENTS
PARAMETER
EXAMPLE VALUE
Input Voltage (V
)
12V
1.2V
30A
IN
User Store: The User Store is the most commonly used store. It
provides the ability to modify certain power supply settings while
still protecting the equipment from modifying values that can
lead to a system level fault. The equipment manufacturer would
use the User Store to achieve this goal.
Output Voltage (V
Output Current (I
)
OUT
)
OUT
Output Voltage Ripple (V
)
1% of V
OUT
orip
Output Load Step (I
)
50% of I
o
ostep
Default Store: The default store is less commonly used. It
provides a means to protect the circuit from damage by
preventing the user from modifying certain values that are
related to the physical construction of the circuit. In this case, the
Original Equipment Manufacturer (OEM) would use the “Default
Store” in a protected mode and allow the user to restore the
device to its default settings. In this case, the “User Store” would
be available to the end-user for making changes, but would
restrict the user from restoring the device to the factory settings
or modifying the default store.
Output Load Step Rate
10A/µs
Output Deviation Due to Load Step
Maximum PCB Temperature
Desired Efficiency
±2%
+85°C
90%
Other Considerations
Optimize for small size
DESIGN GOAL TRADE-OFFS
The design of the buck power stage requires several
compromises among size, efficiency and cost. The inductor core
loss increases with frequency, so there is a trade-off between a
small output filter made possible by a higher switching frequency
and getting better power supply efficiency. Size can be decreased
by increasing the switching frequency at the expense of
efficiency. Cost can be minimized by using through-hole
inductors and capacitors; however these components are
physically large.
The “User Store” takes priority over the “Default Store”. If there
are no values set in the “User or Default Store”, then the device
will use the pin-strap setting value.
For details regarding protection of the user and default stores,
see the PASSWORD PMBus command.
DC/DC Converter Design
The ZL8801 operates as a voltage-mode, synchronous buck
converter with a selectable constant frequency pulse width
modulator (PWM) control scheme that uses external driver,
MOSFETs, capacitors and an inductor to perform power
conversion.
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ZL8801
To start the design, select a switching frequency based on
OUTPUT CAPACITOR SELECTION
Table 9. This frequency is a starting point and may be adjusted as
the design progresses.
Several trade-offs must also be considered when selecting an
output capacitor. Low ESR values are needed to have a small
output deviation (V
) during transient load steps and low
TABLE 9. CIRCUIT DESIGN CONSIDERATIONS
step
output voltage ripple (ΔV). However, capacitors with low ESR,
such as X5R and X7R dielectric ceramic capacitors, also have
relatively low capacitance values. Many designs can use a
combination of high capacitance devices and low ESR devices in
parallel.
FREQUENCY RANGE
200 to 400kHz
EFFICIENCY
Highest
CIRCUIT SIZE
Larger
400 to 800kHz
Moderate
Lower
Smaller
800kHz to 1.33MHz
Smallest
For high ripple currents, a low capacitance value can cause a
significant amount of output voltage ripple. Likewise, in high
transient load steps, a relatively large amount of capacitance is
needed to minimize the output voltage deviation while the
inductor current ramps up or down to the new steady state
output current value.
INDUCTOR SELECTION
The output inductor selection process must include several
trade-offs. A high inductance value will result in a low ripple
current (ΔI ), which will reduce output capacitance and produce a
L
low output ripple voltage, but may also compromise output
transient load performance. Therefore, a balance must be struck
between output ripple and optimal load transient performance. A
good starting point is to select the output inductor ripple equal to
As a starting point, apportion one-half of the output ripple
voltage to the capacitor ESR and the other half to capacitance, as
shown in Equations 13 and 14:
IL
30% to 50% of the maximum output current (I
).
OUT
COUT
(EQ. 13)
V
ΔI = 0.5*I
OUT
L
8 fsw
2
Now the output inductance can be calculated using Equation 9,
where V is the input voltage:
IN
V
ESR
(EQ. 14)
VOUT
VIN
2IL
VOUT 1
(EQ. 9)
Use these values to make an initial capacitor selection, using a
single capacitor or several capacitors in parallel.
L
fsw IL
After a capacitor has been selected, the resulting output voltage
ripple can be calculated using Equation 15:
The average inductor current is equal to the maximum output
current. The peak inductor current (I ) is calculated using
Lpk
is the maximum output current:
IL
8 fsw COUT
Equation 10, where I
OUT
(EQ. 15)
V IL ESR
I
(EQ. 10)
ILpk IOUT
Because each part of this equation was made to be less than or
equal to half of the allowed output ripple voltage, the ΔV should
be less than the desired maximum output ripple.
2
Select an inductor rated for the average DC current and with
saturation current rating above the peak current calculated.
ChargeMode control achieves a fast-acting, low deviation
transient response by detecting and reacting to very small
variations in the output voltage. ChargeMode control
performance is optimized when ΔV due to capacitor ripple is 1%
or less of the output voltage.
Once an inductor is selected, the DCR and core losses in the
inductor are calculated. Use the DCR specified in the inductor
manufacturer’s datasheet, as shown in Equation 11:
2
(EQ. 11)
(EQ. 12)
P
DCR ILrms
LDCR
INPUT CAPACITOR
It is highly recommended that dedicated input capacitors be
used in any point-of-load design, even when the supply is
powered from a heavily filtered 5V or 12V “bulk” supply from an
off-line power supply. This is because of the high RMS ripple
current that is drawn by the buck converter topology. This ripple
I
is given by Equation 12:
Lrms
2
IL
12
ILrms IOUT 2
(I
) can be determined from Equation 16:
inRMS
Where I
OUT
is the maximum output current. Next, calculate the
(EQ. 16)
core loss of the selected inductor. Since this calculation is
specific to each inductor and manufacturer, refer to the chosen
inductor datasheet. Add the core loss and the ESR loss and
compare the total loss to the maximum power dissipation
recommendation in the inductor datasheet.
IinRMS IOUT D
Without capacitive filtering near the power supply circuit, this
current would flow through the supply bus and return planes,
coupling noise into other system circuitry. The input capacitors
should be rated above the ripple current calculated above and
the maximum expected input voltage.
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ZL8801
QL SELECTION
The bottom or lower MOSFET should be selected with the lowest
MOSFET THERMAL CHECK
Once the power dissipations for QH and QL have been calculated,
the MOSFET’s junction temperature can be estimated. Using the
junction to case thermal resistance (R ) given in the MOSFET
possible r
cost.
while maintaining the desired circuit size and
DS(ON)
th
manufacturer’s datasheet and the expected maximum printed
circuit board temperature, calculate the junction temperature
using Equation 25:
Calculate the RMS current in QL as shown by Equation 17:
(EQ. 17)
IQLRMS IOUT 1 D
(EQ. 25)
Tj max Tpcb P Rth
Q
Calculate the power dissipated due to r
Equation 18:
as shown in
DS(ON)
To calculate power losses and junction temperature rise in
DrMOS devices, consult the datasheet and application notes for
the DrMOS device selected.
2
(EQ. 18)
P
= r
I
QL
DSON botrms
NOTE: r
+25°C.
given in the manufacturer’s datasheet is measured at
DS(ON)
EFFICIENCY OPTIMIZED DRIVER DEADTIME CONTROL
The ZL8801 utilizes a closed loop algorithm to optimize the
deadtime applied between the gate drive signals for the top and
bottom FETs. In a synchronous buck converter, the MOSFET drive
circuitry must be designed such that the top and bottom
MOSFETs are never in the conducting state at the same time.
Potentially damaging currents flow in the circuit if both top and
bottom MOSFETs are simultaneously on for periods of time
exceeding a few nanoseconds. Conversely, long periods of time in
which both MOSFETs are off, reduce overall circuit efficiency by
allowing current to flow in their parasitic body diodes.
The actual r
DS(ON)
Select a candidate MOSFET and calculate the required gate drive
current using Equation 19:
in the end-use application will be much higher.
(EQ. 19)
Ig fSW Qg
MOSFETs with lower r
DS(ON)
requirements, which increases the current and resulting power
required to turn them on and off.
tend to have higher gate charge
QH SELECTION
It is therefore advantageous to minimize this deadtime to provide
optimum circuit efficiency. In the first order model of a buck
converter, the duty cycle is determined by Equation 26:
In addition to the r
loss and gate charge loss, QH also has
DS(ON)
switching loss. Select QH with a lower gate charge, keeping in
mind that QH’s r will be higher as a result. As was done
DS(ON)
with QL, calculate the RMS current using Equations 20 and 21:
VOUT
(EQ. 26)
D
VIN
(EQ. 20)
IQHRMS IOUT D
However, nonidealities exist that cause the real duty cycle to
extend beyond the ideal. Deadtime is one of those nonidealities
that can be manipulated to improve efficiency. The ZL8801 has
an internal algorithm that constantly adjusts deadtime
nonoverlap to minimize duty cycle, thus maximizing efficiency.
This circuit will null out deadtime differences due to component
variation, temperature and loading effects. This algorithm is
independent of application circuit parameters such as MOSFET
type, gate driver delays, rise and fall times and circuit layout. In
addition, it does not require drive or MOSFET voltage or current
waveform measurements. Adaptive deadtime is enabled using
the DEADTIME_CONFIG PMBus™ command. Adaptive deadtime
is only effective when a discrete driver (such as the ZL1505) and
MOSFETs are used. When DrMOS devices are selected using
USER_CONFIG, adaptive deadtime is automatically disabled.
Deadtime minimum and maximum limits can be set using the
DEADTIME PMBus™ command.
2
(EQ. 21)
(EQ. 22)
P
= r
I
QH
DSON QHRMS
Next, calculate the switching time using Equation 22:
Qg
tSW
IDR
where Q is the gate charge of the selected QH and I is the
DR
peak gate drive current available from the gate drive IC.
g
To calculate the switching time, use the ZL1505s minimum
guaranteed drive current of 3A for a conservative design. Using
the calculated switching time, calculate the switching power loss
in QH using Equation 23:
(EQ. 23)
P
VINM tsw IOUT fsw
swtop
The total power dissipated by QH is given by Equation 24:
Monitoring via SMBus
(EQ. 24)
PQHtot P P
QH
swtop
A system controller can monitor a wide variety of different
ZL8801 parameters through the SMBus interface. The device can
monitor for fault conditions by monitoring the SALRT pin, which
will be asserted when any number of preconfigured fault
conditions occur.
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ZL8801
The device can also be monitored continuously for any number of
power conversion parameters including but not limited to the
following:
The PMBus™ Host should respond to SALRT as follows:
1. ZL device pulls SALRT Low.
2. PMBus™ Host detects that SALRT is now low, performs
transmission with Alert Response Address to find which ZL
device is pulling SALRT low.
• Input voltage
• Output voltage
3. PMBus™ Host talks to the ZL device that has pulled SALRT
low. The actions that the host performs are up to the System
Designer.
• Input current
• Output current
• Internal junction temperature
• Temperature of an external device
• Switching frequency
• Duty cycle
If multiple devices are faulting, SALRT will still be low after doing
the above steps and will require transmission with the Alert
Response Address repeatedly until all faults are cleared.
Please refer to the “PMBus™ Command Detail” section, starting
on page 30, for details on how to monitor specific parameters via
the SMBus interface.
• Fault status information
PMBus™ Command Summary
DATA
TYPE FORMAT
DEFAULT
VALUE
CODE
COMMAND NAME
DESCRIPTION
Enable/disable, margin settings.
On/off configure settings.
Clears faults.
DEFAULT SETTING
01h OPERATION
R/W
R/W
BIT
BIT
00h
17h
N/A
N/A
N/A
N/A
N/A
13h
Immediate Off, Nominal Margin
02h ON_OFF_CONFIG
03h CLEAR_FAULTS
11h STORE_DEFAULT_ALL
12h RESTORE_DEFAULT_ALL
15h STORE_USER_ALL
16h RESTORE_USER_ALL
20h VOUT_MODE
ENABLE Pin Control, Active High
Write N/A
Write N/A
Write N/A
Write N/A
Write N/A
N/A
Stores values to default store.
Restores values from default store.
Stores values to user store.
Restores values from user store.
N/A
N/A
N/A
N/A
Reports VOUT_COMMAND Mode value. Read
BIT
13h, Fixed Value
Pin-strap Setting
0V
21h VOUT_COMMAND
23h VOUT_CAL_OFFSET
24h VOUT_MAX
Sets nominal V
OUT
setpoint.
R/W L16u
setpoint. R/W L16u
R/W L16u
Applies offset voltage to V
OUT
0000h
Sets maximum V
OUT
setpoint.
1.10 X VOUT_COMMAND Pin-strap
Setting
25h VOUT_MARGIN_HIGH
26h VOUT_MARGIN_LOW
27h VOUT_TRANSITION_RATE
28h VOUT_DROOP
Sets V
Sets V
Sets V
set point during margin high. R/W L16u
setpoint during margin low. R/W L16u
1.05 x VOUT_COMMAND Pin-strap
Setting
OUT
OUT
OUT
0.95 x VOUT_COMMAND Pin-strap
Setting
transition rate during margin R/W
L11
L11
BA00h
0000h
1V/ms
commands.
Sets V/I slope for total rail output
current (all phases combined).
R/W
R/W
0mV/A
33h FREQUENCY_SWITCH
37h INTERLEAVE
Sets switching frequency.
L11
BIT
Pin-strap Setting
Configures phase offset during group R/W
operation.
Set by Pin-Strapped PMBus™
Address
40h VOUT_OV_FAULT_LIMIT
41h VOUT_OV_FAULT_RESPONSE
44h VOUT_UV_FAULT_LIMIT
45h VOUT_UV_FAULT_RESPONSE
46h IOUT_OC_FAULT_LIMIT
Sets the V
threshold.
overvoltage fault
R/W L16u
R/W BIT
R/W L16u
1.15 x VOUT_COMMAND Pin-strap
Setting
OUT
OUT
OUT
OUT
OUT
Sets the V
response.
overvoltage fault
80h
Disable, No Retry
Sets the V
threshold.
undervoltage fault
undervoltage fault
peak overcurrent fault
0.85 x VOUT_COMMAND Pin-strap
Setting
Sets the V
response.
R/W
R/W
BIT
80h
Disable, No Retry
Sets the I
L11
DBC0h
30A
threshold for each phase.
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ZL8801
PMBus™ Command Summary (Continued)
DATA
TYPE FORMAT
DEFAULT
VALUE
CODE
COMMAND NAME
DESCRIPTION
DEFAULT SETTING
4Bh IOUT_UC_FAULT_LIMIT
Sets the I
valley undercurrent fault R/W
L11
D440h
-15A
OUT
threshold for each phase.
4Fh OT_FAULT_LIMIT
Sets the over-temperature fault limit.
R/W
R/W
L11
BIT
EBE8h
80h
+125˚C
50h OT_FAULT_RESPONSE
Sets the over-temperature fault
response.
Disable, No Retry
51h OT_WARN_LIMIT
52h UT_WARN_LIMIT
Sets the over-temperature warning
limit.
R/W
R/W
L11
L11
EB70h
DC40h
+110°C
Sets the under-temperature warning
limit.
-30°C
53h UT_FAULT_LIMIT
Sets the under-temperature fault limit. R/W
L11
BIT
E530h
80h
-45°C
54h UT_FAULT_RESPONSE
Sets the under-temperature fault
response.
R/W
Disable, No Retry
55h VIN_OV_FAULT_LIMIT
56h VIN_OV_FAULT_RESPONSE
57h VIN_OV_WARN_LIMIT
Sets the V overvoltage fault threshold. R/W
IN
L11
BIT
D380h
80h
14V
Sets the V overvoltage fault response. R/W
IN
Disable, No Retry
13.5V
Sets the V overvoltage warning
IN
threshold.
R/W
R/W
R/W
R/W
L11
D360h
58h VIN_UV_WARN_LIMIT
59h VIN_UV_FAULT_LIMIT
5Ah VIN_UV_FAULT_RESPONSE
5Eh POWER_GOOD_ON
60h TON_DELAY
Sets the V undervoltage warning
IN
threshold.
L11
L11
BIT
N/A
N/A
1.1 x VIN_UV_FAULT_LIMIT Pin-strap
Setting
Sets the V undervoltage fault
IN
threshold.
Pin-strap Setting
Sets the V undervoltage fault
IN
80h
Disable, No Retry
response.
Sets the voltage threshold for
Power-good indication.
R/W L16u
N/A
0.9 x VOUT_COMMAND Pin-strap
Setting
Sets the delay time from enable to V
rise.
R/W
L11
L11
L11
L11
CA80h
CA80h
CA80h
CA80h
5ms
5ms
5ms
5ms
OUT
61h TON_RISE
Sets the rise time of V after ENABLE R/W
OUT
and TON_DELAY.
64h TOFF_DELAY
Sets the delay time from DISABLE to
start of V fall.
R/W
R/W
OUT
Sets the fall time for V
65h TOFF_FALL
after
OUT
DISABLE and TOFF_DELAY.
First byte of STATUS_WORD.
Summary of critical faults.
78h STATUS_BYTE
79h STATUS_WORD
7Ah STATUS_VOUT
7Bh STATUS_IOUT
Read
Read
Read
Read
Read
BIT
BIT
BIT
BIT
BIT
BIT
BIT
0000h
0000h
00h
No Faults
No Faults
No Faults
No Faults
No Faults
No Faults
No Errors
Reports V
warnings/faults.
warnings/faults.
OUT
Reports I
00h
OUT
7Ch STATUS_INPUT
7Dh STATUS_TEMPERATURE
7Eh STATUS_CML
Reports input warnings/faults.
00h
Reports temperature warnings/faults. Read
00h
Reports Communication, memory,
logic errors.
Read
00h
80h STATUS_MFR_SPECIFIC
Reports voltage monitoring/clock
synchronization faults.
Read
BIT
00h
No Faults
88h READ_VIN
89h READ_IIN
8Bh READ_VOUT
8Ch READ_IOUT
Reports input voltage measurement.
Reports input current measurement.
Read L11
Read L11
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Reports output voltage measurement. Read L16u
Reports output total current
measurement.
Read L11
8Dh READ_TEMPERATURE_1
Reports internal temperature
measurement.
Read L11
N/A
N/A
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ZL8801
PMBus™ Command Summary (Continued)
DATA
TYPE FORMAT
DEFAULT
VALUE
CODE
COMMAND NAME
DESCRIPTION
DEFAULT SETTING
8Eh READ_TEMPERATURE_2
Reports external temperature 0
measurement.
Read L11
Read L11
N/A
N/A
N/A
8Fh READ_TEMPERATURE_3
Reports external temperature 1
measurement.
N/A
94h READ_DUTY_CYCLE
95h READ_FREQUENCY
98h PMBUS_REVISION
Reports actual duty cycle.
Read L11
Read L11
N/A
N/A
11h
N/A
N/A
Reports actual switching frequency.
Returns the revision of the PMBus
Specification to which the device is
compliant.
Read
BIT
Part 1 Revision 1.2,
Part 2 Revision 1.2
99h MFR_ID
Sets a user defined identification.
Sets a user defined model.
R/W
R/W
R/W
ASC
ASC
ASC
ASC
ASC
ASC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
<null>
<null>
<null>
<null>
<null
9Ah MFR_MODEL
9Bh MFR_REVISION
9Ch MFR_LOCATION
9Dh MFR_DATE
Sets a user defined revision.
Sets a user defined location identifier. R/W
Sets a user defined date. R/W
Sets a user defined serialized identifier. R/W
9Eh MFR_SERIAL
A1h READ_IOUT0
A2h READ_IOUT1
A8h LEGACY_FAULT_GROUP
<null>
N/A
Reports phase 0 output current.
Reports phase 1 output current.
Read L11
Read L11
N/A
Configures fault group compatibility
with older Intersil digital power devices.
R/W
BIT
<null>
ADh IC_DEVICE_ID
AEh IC_DEVICE_REV
Reports device identification
information.
Block CUS 49A02300h Intersil, ZL8801
Read
Reports device revision information.
Block CUS 01000000h Initial Release
Read
B0h USER_DATA_00
BFh DEADTIME_MAX
Sets a user defined data.
R/W
R/W
ASC
BIT
N/A
<null>
Sets the max deadtime value for the
adaptive deadtime.
3838h
56ns/56ns
CAh IOUT0_CAL_GAIN
CBh IOUT1_CAL_GAIN
Sets impedance of phase 0 current
sense circuit.
R/W
R/W
L11
L11
AA66h
AA66h
0.3mΩ
0.3mΩ
Sets impedance of phase 1 current
sense circuit.
CCh IOUT0_CAL_OFFSET
CDh IOUT1_CAL_OFFSET
CEh MIN_VOUT_REG
Sets an offset to IOUT0 sense circuit.
Sets an offset to IOUT1 sense circuit.
Sets a minimum start-up voltage.
Configures current sensing circuitry.
R/W
R/W
R/W
R/W
L11
L11
L11
BIT
0000h
0000h
F258h
4204h
0A
0A
150mV
D0h ISENSE_CONFIG
Downslope, 5 Fault Count, 256ns
Blanking, Low Range
D1h USER_CONFIG
Configures several user-level features. R/W
BIT
L11
BIT
0402h
C200h
N/A
Enable XTEMP0,1, PG Open Drain,
DrMOS Enabled
D2h IIN_CAL_GAIN
Sets the resistance of the input current R/W
sensing resistor
2mΩ
D3h DDC_CONFIG
Configures the DDC addressing and
current sharing.
R/W
R/W
R/W
Set By Pin-strapped PMBus™
Address
D4h POWER_GOOD_DELAY
D5h MULTI_PHASE_RAMP_GAIN
Sets the delay between PG threshold
and PG assertion.
L11
CUS
CA00h
03h
4ms
Adjusts the ramp-up and ramp-down
rate by setting the feedback gain.
Gain of 3
D6h INDUCTOR
Sets the inductance of both phases.
R/W
R/W
L11
L11
B23Dh
CA80h
0.56µH
5%
D7h VOUT_MARGIN_RATIO
% MARGIN_HIGH, LOW above/below
VOUT_COMMAND.
D8h OVUV_CONFIG
Configures output voltage OV/UV fault R/W
detection.
BIT
00000000h Low-side FET Off On Fault, 1 Violation
Triggers Fault.
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ZL8801
PMBus™ Command Summary (Continued)
DATA
TYPE FORMAT
DEFAULT
VALUE
CODE
COMMAND NAME
DESCRIPTION
DEFAULT SETTING
D9h XTEMP_SCALE
DAh XTEMP_OFFSET
Calibrates external temperature sensor. R/W
L11
L11
BA00h
0000h
1/°C
Offset calibration for external
temperature sensor.
R/W
No Offset
DCh TEMPCO_CONFIG
DDh DEADTIME
Sets tempco settings.
R/W
R/W
R/W
BIT
CUS
BIT
27h
3900ppm/°C
16ns/16ns
Sets default deadtime settings.
1010h
8888h
DEh DEADTIME_CONFIG
Configures the adaptive deadtime
optimization mode.
Adaptive Deadtime Enabled,
8ns/8ns
DFh ASCR_CONFIG
Configures the ASCR settings.
R/W
BIT
015A0190h ASCR Enabled, 400 Gain,
90 Residual
E0h SEQUENCE
DDC rail sequencing configuration.
Configures voltage tracking modes.
Configures group ID, fault spreading,
R/W
R/W
R/W
BIT
BIT
BIT
00h
00h
Prequel and Sequel Disabled
Tracking Disabled
E1h TRACK_CONFIG
E2h DDC_GROUP
000000h Ignore Broadcast, Sequenced
Shutdown, Fault Spreading
OPERATION and V
.
OUT
E4h DEVICE_ID
Returns the device identifier string.
Block ASC
Read
N/A
<Part Number/Die
Revision/Firmware Revision>
E5h MFR_IOUT_OC_FAULT_RESPONSE Configures the I
response.
overcurrent fault
R/W
BIT
BIT
L11
L11
BIT
BIT
BIT
BIT
80h
Disable, No Retry
Disable, No Retry
20A
OUT
E6h MFR_IOUT_UC_FAULT_RESPONSE
E7h IOUT_AVG_OC_FAULT_LIMIT
E8h IOUT_AVG_UC_FAULT_LIMIT
E9h MFR_USER_CONFIG
Configures the I
response.
undercurrent fault R/W
80h
OUT
Sets the I
OUT
average overcurrent fault R/W
DA80h
D580h
0000h
N/A
threshold for each phase.
Sets the I average undercurrent
R/W
R/W
-10A
OUT
fault threshold for each phase.
Sets options pertaining to advanced
features.
Numerous Device Settings
<null>
EAh SNAPSHOT
32 byte read-back of parametric and Block
status values.
Read
EBh BLANK_PARAMS
Indicates recently saved parameter
values.
Block
Read
FF…FFh <null>
F3h SNAPSHOT_CONTROL
F4h RESTORE_FACTORY
Snapshot feature control command.
R/W
00h
N/A
N/A
N/A
Restores device to the hard-coded
default values.
Write N/A
F5h MFR_VMON_OV_FAULT_LIMIT
F6h MFR_VMON_UV_FAULT_LIMIT
F7h MFR_READ_VMON
Sets the VMON overvoltage fault
threshold.
R/W
R/W
L11
L11
D300h
CA00h
12V
Sets the VMON undervoltage fault
threshold.
4.0V
Reads the VMON voltage.
Read L11
N/A
80h
N/A
F8h MFR_VMON_OV_FAULT_RESPONSE Configures the VMON overvoltage fault R/W
response.
BIT
Disable, No Retry
F9h MFR_VMON_UV_FAULT_RESPONSE Configures the VMON undervoltage
fault response.
R/W
BIT
80h
Disable, No Retry
FAh SECURITY_LEVEL
FBh PRIVATE_PASSWORD
FCh PUBLIC_PASSWORD
FDh UNPROTECT
Reports the security level.
Read Hex
01h
Public Security Level
Sets the private password string.
Sets the public password string.
R/W
R/W
ASC
ASC
00…00h <null>
00…00h <null>
FF…FFh N/A
Identifies which commands are
protected.
R/W Custom
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ZL8801
PMBus™ User Guidelines
The PMBus is a powerful tool that allows the user to optimize circuit performance by configuring the ZL8801 for their application. When
configuring the ZL8801 in a circuit, the ZL8801 should be disabled whenever most settings are changed with PMBus commands. Some
exceptions to this recommendation are OPERATION, ON_OFF_CONFIG, CLEAR_FAULTS, VOUT_COMMAND, VOUT_MARGIN_HIGH,
VOUT_MARGIN_LOW and ASCCR_CONFIG. While the device is enabled any command can be read. Many commands do not take effect
until after the device has been reenabled, hence the recommendation that commands that change device settings are written while
the device is disabled.
SUMMARY:
All commands can be read at any time.
Always disable the ZL8801 when writing commands that change device settings. Exceptions to this rule are commands intended to be
written while the device is enabled, for example, VOUT_MARGIN_HIGH.
To be sure a device setting change has taken effect, write the STORE_USER_ALL command, then cycle input power and reenable the
device.
PMBus™ Data Formats
Linear-11 (L11)
L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world decimal
value (X).
Data Byte High
Data Byte Low
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Exponent (N)
Mantissa (Y)
N
Relation between real world decimal value (X), N and Y is: X = Y x 2
Linear-16 Unsigned (L16u)
L16u data format uses a fixed exponent (hardcode to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world
-13
decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y x 2
Linear-16 Signed (L16s)
L16s data format uses a fixed exponent (hardcode to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real world
decimal value (X).
-13
Relation between real world decimal value (X), N and Y is: X = Y x 2
Bit Field (BIT)
Breakdown of Bit Field is provided in “PMBus™ Command Detail” section, starting on page 30.
Custom (CUS)
Breakdown of Custom data format is provided in “PMBus™ Command Detail” section, starting on page 30. A combination of Bit Field
and integer are common types of Custom data format.
ASCII (ASC)
A variable length string of text characters uses ASCII data format.
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ZL8801
PMBus™ Command Detail
OPERATION (01h)
Definition: Sets Enable, Disable and VOUT Margin settings. Data values of OPERATION that force margin high or low only take effect
when the MGN pin is left open (i.e., in the NOMINAL margin state). This command can also be monitored to read the operating state of
the device on bits 7:6. Writing Immediate off will turn off the output and ignore TOFF_DELAY and TOFF_FALL settings. This command is
not stored like other PMBus commands. The value read reflects the current state of the device. When this command is written, the
command takes effect. If a STORE _USER_ALL written and the device is reenabled, the OPERATION settings may not be the same
settings that were written before the device was reenabled.
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 00h (immediate off)
Units: N/A
COMMAND
OPERATION (01h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BITS 3:0
UNIT
BITS 7:6
00
BITS 5:4
00
(NOT USED)
ON OR OFF
MARGIN STATE
N/A
0000
0000
Immediate off
(No sequencing)
01
00
Soft-off
N/A
(With sequencing)
10
10
10
00
01
10
0000
0100
0100
On
On
On
Nominal
Margin Low
Margin High
NOTE: Bit combinations not listed above may cause command errors.
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ZL8801
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN). When Bit 0 is set to 1
(Turn-off the output immediately) TOFF_DELAY and TOFF_FALL settings are ignored.
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 17h (ENABLE pin control, active high, turn off output immediately – no ramp down)
Units: N/A
COMMAND
ON_OFF_CONFIG (02h)
BIT FIELD
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
1
0
1
1
1
BIT NUMBER
7:5
PURPOSE
BIT VALUE
000
MEANING
Not Used
Not used
Not used
Sets the default to either operate any time
power is present or for the on/off to be
controlled by ENABLE pin or OPERATION
command
000
4:2
101
110
Device starts from ENABLE pin only.
Device starts from OPERATION command only.
Not used
1
0
Not Used
0
0
1
Use the configured ramp down settings.
Turn off the output immediately.
ENABLE pin action when commanding the unit
to turn off
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the
bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Data Length in Bytes: 0 Byte
Data Format: N/A
Type: Write Only
Protectable: Yes
Default Value: N/A
Units: N/A
STORE_DEFAULT_ALL (11h)
Definition: Stores all current PMBus™ values from the operating memory into the nonvolatile (NVRAM) DEFAULT store memory. To clear
the DEFAULT store, perform a RESTORE_FACTORY then STORE_DEFAULT_ALL. To add to the DEFAULT store, perform a
RESTORE_DEFAULT_ALL, write commands to be added, then STORE_DEFAULT_ALL. This command should not be used during device
operation, the device will be unresponsive for 20ms while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Default Value: N/A
Units: N/A
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ZL8801
RESTORE_DEFAULT_ALL (12h)
Definition: Restores PMBus™ settings from the nonvolatile (NVRAM) DEFAULT Store memory into the operating memory. These settings
are loaded during at power-up if not superseded by settings in USER store. Security level is changed to level 1 following this command.
This command should not be used during device operation, the device will be unresponsive for 20ms while restoring values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Default Value: N/A
Units: N/A
STORE_USER_ALL (15h)
Definition: Stores all PMBus™ settings from the operating memory to the nonvolatile (NVRAM) USER store memory. To clear the USER
store, perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write
commands to be added, then STORE_USER_ALL. This command should not be used during device operation, the device will be
unresponsive for 20ms while storing values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Default Value: N/A
Units: N/A
RESTORE_USER_ALL (16h)
Definition: Restores all PMBus™ settings from the USER store memory to the operating memory. Security level is changed to Level 1
following this command. This command should not be used during device operation, the device will be unresponsive for 20ms while
restoring values.
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Default Value: N/A
Units: N/A
VOUT_MODE (20h)
Definition: Reports the V
Data Length in Bytes: 1
Data Format: BIT Field
Type: Read ONLY
mode and provides the exponent used in calculating several V
OUT
settings.
OUT
Protectable: N/A
Default Value: 13h (Linear Mode, Exponent is -13d)
Units: N/A
COMMAND
Format
VOUT_MODE (20h)
BIT FIELD
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
1
0
0
1
1
BIT
7:0
FIELD NAME
Mode
VALUE
13h
DESCRIPTION
Five bit two’s complement exponent for the mantissa delivered as the data bytes for an output
voltage related command.
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ZL8801
VOUT_COMMAND (21h)
Definition: This command sets or reports the target output voltage. The integer value is multiplied by 2 raised to the power of -13h. This
command cannot be set to be higher than VOUT_MAX.
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned
Type: R/W
Protectable: Yes
Default Value: Pin-strap Setting
Units: Volts
Equation: VOUT = VOUT_COMMAND × 2
-13
Range: 0 to VOUT_MAX
Example: VOUT_COMMAND = 699Ah = 27,034
-13
Target voltage equals 27034 × 2
= 3.3V
COMMAND
Format
VOUT_COMMAND (21h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
Pin-strap setting
VOUT_CAL_OFFSET (23h)
Definition: The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the output voltage command value. This
command is typically used by the user to calibrate a device in the application circuit. The two bytes are formatted as a two’s
complement binary mantissa, used in conjunction with the exponent of -13h.
Data Length in Bytes: 2
Data Format: Linear -16 Signed
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: V
Equation: V
-13
cal offset = VOUT_CAL_OFFSET × 2
OUT
Range: ±3.99V
COMMAND
Format
VOUT_CAL_OFFSET (23h)
Linear-16 Signed
Bit Position
Access
15
r/w
0
14
r/w
0
13
r/w
0
12
r/w
0
11
r/w
0
10
r/w
0
9
r/w
0
8
r/w
0
7
r/w
0
6
r/w
0
5
r/w
0
4
r/w
0
3
r/w
0
2
r/w
0
1
r/w
0
0
r/w
0
Default Value
VOUT_MAX (24h)
Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output
voltage to a possibly destructive level rather than to be the primary output overprotection. If a VOUT_COMMAND is sent with a value
higher than VOUT_MAX, the device will set the output voltage to VOUT_MAX.
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 1.10 × VOUT_COMMAND pin-strap setting
Units: V
-13
Equation: VOUT max = VOUT_MAX × 2
Range: 0V to 5.5V
COMMAND
Format
VOUT_MAX (24h)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
1.10 x VOUT_COMMAND Pin-strap Setting
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ZL8801
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the V
which the output is to be changed when the OPERATION command is set to “Margin High”.
during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to
OUT
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned.
Type: R/W Word
Protectable: Yes
Default Value: 1.05 x VOUT_COMMAND pin-strap setting
Units: V
-13
Equation: VOUT margin high = VOUT_MARGIN_HIGH x 2
Range: 0V to VOUT_MAX
COMMAND
Format
VOUT_MARGIN_HIGH (25h)
Linear-16 Unsigned
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
1.05 x VOUT_COMMAND pin-strap setting
VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the V
the output is to be changed when the OPERATION command is set to “Margin Low”.
during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which
OUT
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 0.95 x VOUT_COMMAND pin-strap setting
Units: V
Equation: VOUT margin low = VOUT_MARGIN_LOW
Range: 0V to VOUT_MAX
COMMAND
Format
VOUT_MARGIN_LOW (26h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
0.95 x VOUT_COMMAND pin-strap setting
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ZL8801
VOUT_TRANSITION_RATE (27h)
Definition: This command sets the rate at which the output should change voltage when the device receives an OPERATION command
(Margin High, Margin Low) that causes the output voltage to change. The maximum possible positive value of the two data bytes
indicates that the device should make the transition as quickly as possible. This commanded rate does not apply when the device is
commanded to turn on or to turn off.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h (1.0V/ms)
Units: V/ms
Equation: VOUT_TRANSITION_RATE = Y x 2N
Range: 0.1 to 4V/ms
COMMAND
Format
VOUT_TRANSITION_RATE (27h)
Linear Data Format
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
VOUT_DROOP (28h)
Definition: The VOUT_DROOP sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A at
which the output voltage decreases with increasing output current for use with Adaptive Voltage Positioning requirements and passive
current sharing schemes. For devices that are set to sink output current (negative output current), the output voltage continues to
increase as the output current is negative. VOUT_DROOP is not needed with a single (2-phase) ZL8801. VOUT_DROOP is needed when
multiple ZL8801s are operated in current sharing mode, i.e. 4-, 6- and 8-phase configurations. In this case, VOUT_DROOP is calculated
based on the combined output current of all 4, 6 or 8 phases as applicable.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0mV/A)
Units: mV/A
Equation: VOUT_DROOP = Y x 2N
Range: 0 to 40mV/A
COMMAND
Format
VOUT_DROOP (28h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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ZL8801
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin-strap and this value can be overridden by
writing this command. If an external SYNC is utilized, this value should be set as close as possible to the external clock value. The
output must be disabled when writing this command. Available frequencies are defined by equation f = 16MHz/n where 12 ≤ n ≤ 80.
sw
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: Pin-strap Setting
Units: kHz
Equation: FREQUENCY_SWITCH = Y x 2N
Range: 200kHz to 1.33MHz
COMMAND
Format
FREQUENCY_SWITCH (33h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
Pin-strap setting
INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. A desired phase position is
specified. Interleave is used for setting the phase offset between individual devices, current sharing groups and/or combinations of
devices and current sharing groups. For devices within a single current sharing group the phase offset is set automatically. The ZL8801
uses dual edge modulation. Phase offset should measured with respect to the center of PWM4 pulses.
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by pin-strapped PMBus address
Units: N/A
COMMAND
Format
INTERLEAVE (37h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
Four LSB’s of PMBus Address
BITS
15:4
3:0
PURPOSE
Not Used
VALUE
0
DESCRIPTION
Not used
Position in Group
0 to 15
Sets position of the device’s rail within the group. A value of 0 is interpreted as 16.
Position 1 will have a 22.5° offset.
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ZL8801
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the V
overvoltage fault threshold.
OUT
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 1.15 x VOUT_COMMAND pin-strap setting
Units: V
Equation: VOUT OV fault limit = VOUT_OV_FAULT_LIMIT x 2
Range: 0V to 7.99V
-13
COMMAND
Format
VOUT_OV_FAULT_LIMIT (40h)
Linear-16 Unsigned
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
1.15 x VOUT_COMMAND pin-strap setting
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the V
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
overvoltage fault response.
OUT
Protectable: Yes
Default Value: 80h (Shut down immediately, no retries)
Units: Retry time unit = 70ms
COMMAND
Format
VOUT_OV_FAULT_RESPONSE (41h)
Bit Field
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior: the device:
• Pulls SALRT low
Not Used
Disable and retry according to the setting in Bits [5:3].
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
7:6
11
Not Used
CLEAR_FAULTS command.
000
No retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
111
111
Not used. Retry time is fixed at 70ms.
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ZL8801
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the V
device is disabled.
undervoltage fault threshold. This fault is masked during ramp, before power-good is asserted or when the
OUT
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 0.85 x VOUT_COMMAND pin-strap setting
Units: V
Equation: VOUT UV fault limit = VOUT_UV_FAULT_LIMIT x 2
Range: 0V to 7.99V
-13
COMMAND
Format
VOUT_UV_FAULT_LIMIT (44h)
Linear-16 unsigned
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
0.85 x VOUT_COMMAND
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the V
OUT
undervoltage fault response. Note that VOUT UV faults can only occur after power-good (PG) has been
asserted. Under some circumstances this will cause the output to stay fixed below the power-good threshold indefinitely.
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 80h (Shut down immediately, no retry)
Units: Retry time = 70ms
COMMAND
VOUT_UV_FAULT_RESPONSE (45h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior: the device:
• Pulls SALRT low
Not Used
Disable and retry according to the setting in Bits [5:3].
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
7:6
11
Not Used
CLEAR_FAULTS command.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not Used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the ENABLE
pin or OPERATION command or both), bias power is removed, or another fault condition causes
the unit to shut down.
111
111
Not used. Retry time is fixed at 70ms.
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ZL8801
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the I
OUT
peak overcurrent fault threshold for each inductor (Phase 0 and Phase 1). Either phase can trigger an overcurrent
fault. This limit is applied to current measurement samples taken after the Current Sense Blanking Time has expired. A fault occurs after
this limit is exceeded for the number of consecutive switching periods as defined in ISENSE_CONFIG. This feature shares the OC fault bit
operation (in STATUS_IOUT) and OC fault response with IOUT_AVG_OC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: DBC0h (30A)
Units: A
Equation: IOUT_OC_FAULT_LIMIT = Y x 2
N
Range: -100 to 100A
COMMAND
Format
IOUT_OC_FAULT_LIMIT (46h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
1
0
1
1
1
1
0
0
0
0
0
0
IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the I
OUT
valley undercurrent fault threshold for each inductor (Phase 0 and Phase 1). Either phase can trigger an
undercurrent fault. This limit is applied to current measurement samples taken after the Current Sense Blanking Time has expired. A fault
occurs after this limit is exceeded for the number of consecutive switching periods as defined in ISENSE_CONFIG. This feature shares the
UC fault bit operation (in STATUS_IOUT) and UC fault response with IOUT_AVG_UC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D440h (-15A)
Units: A
Equation: IOUT_UC_FAULT_LIMIT = Y x 2
N
Range: -100 to 100A
COMMAND
Format
IOUT_UC_FAULT_LIMIT (4Bh)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
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ZL8801
OT_FAULT_LIMIT (4Fh)
Definition: The OT_FAULT_LIMIT command sets the temperature at which the device should indicate an over-temperature fault. When using
XTEMP (0, 1), either temperature sensor can trigger a fault. In response to the OT_FAULT_LIMIT being exceeded, the device: Sets the
TEMPERATURE bit in STATUS_WORD, Sets the OT_WARNING bit in STATUS_TEMPERATURE and the FAULT_INT, FAULT_XTEMP0 or
FAULT_XTEMP1 as applicable and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: EBE8h (+125˚C)
Units: Celsius
Equation: OT_FAULT_LIMIT = Y x 2
N
Range: 0°C to +175°C
COMMAND
Format
OT_FAULT_LIMIT (4Fh)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
0
OT_FAULT_RESPONSE (50h)
Definition: The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an over-temperature fault.
The setting “10” in Bits 7:6 should not be used with setting “111” in Bits 5:3 since this could result in a thermal runaway condition.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (Shut down immediately, no retry)
Units: Retry time = 210ms
COMMAND
OT_FAULT_RESPONSE (50h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior: The Device:
• Pulls SALRT low
Not Used
Disable and retry according to the setting in Bits [5:3].
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
7:6
11
Not Used
CLEAR_FAULTS command.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not Used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down.
111
111
Not used. Retry delay is 210ms.
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ZL8801
OT_WARN_LIMIT (51h)
Definition: The OT_WARN_LIMIT command sets the temperature at which the device should indicate an over-temperature warning
alarm. When using XTEMP (0,1), either temperature sensor can trigger a warning. In response to the OT_WARN_LIMIT being exceeded,
the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the OT_WARNING bit in STATUS_TEMPERATURE and the FAULT_INT,
FAULT_XTEMP0 or FAULT_XTEMP1 as applicable and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: EB70h (+110°C)
Units: Celsius
Equation: OT_WARN_LIMIT = Y x 2
N
Range: 0°C to +175°C
COMMAND
Format
OT_WARN_LIMIT (51h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
0
1
0
1
1
0
1
1
1
0
0
0
0
UT_WARN_LIMIT (52h)
Definition: The UT_WARN_LIMIT command set the temperature at which the device should indicate an under-temperature warning
alarm. When using XTEMP (0,1), either temperature sensor can trigger a warning. In response to the UT_WARN_LIMIT being exceeded,
the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the UT_WARNING bit in STATUS_TEMPERATURE and the FAULT_INT,
FAULT_XTEMP0 or FAULT_XTEMP1 as applicable and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: DC40h (-30°C)
Units: Celsius
Equation: UT_WARN_LIMIT = Y x 2
N
Range: -55°C to +25°C
COMMAND
Format
UT_WARN_LIMIT (52h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
0
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ZL8801
UT_FAULT_LIMIT (53h)
Definition: The UT_FAULT_LIMIT command sets the temperature, in degrees Celsius, of the unit at which it should indicate an
under-temperature fault. When using XTEMP (0,1), either temperature sensor can trigger a fault. In response to the UT_FAULT_LIMIT
being exceeded, the device: Sets the TEMPERATURE bit in STATUS_WORD, Sets the UT_FAULT bit in STATUS_TEMPERATURE and the
FAULT_INT, FAULT_XTEMP0 or FAULT_XTEMP1 as applicable and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: E530h (-45°C)
Units: Celsius
Equation: UT_FAULT_LIMIT = Y x 2
N
Range: -55°C to +25°C
COMMAND
Format
UT_FAULT_LIMIT (53h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
0
0
1
0
1
0
0
1
1
0
0
0
0
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response as defined by the following table. The delay time is the time between
restart attempts.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (Shut down immediately, no retry)
Units: Retry time unit = 210ms
COMMAND
UT_FAULT_RESPONSE (54h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior: The Device:
• Pulls SALRT low
Not Used
Disable and retry according to the setting in bits [5:3].
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
7:6
11
Not Used
CLEAR_FAULTS command.
000
No retry. The output remains disabled until the device is restarted.
001-110 Not Used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down.
111
111
Not used. Retry time is fixed at 210ms.
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ZL8801
VIN_OV_FAULT_LIMIT (55h)
Definition: Sets the V overvoltage fault threshold.
IN
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D380h (14V)
Units: V
Equation: VIN_OV_FAULT_LIMIT = Y x 2
N
Range: 0 to 19V
COMMAND
Format
VIN_OV_FAULT_LIMIT (55h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
0
1
1
1
0
0
0
0
0
0
0
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the V overvoltage fault response as defined by the following table. The delay time is the time between restart
IN
attempts.
Data Length in Bytes: 1
Data Format: BIT Field.
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shutdown, no retry)
Units: Retry time unit = 70ms
COMMAND
VIN_OV_FAULT_RESPONSE (56h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior: The Device:
• Pulls SALRT low
Not Used
Disable and retry according to the setting in Bits[5:3].
• Sets the related fault bit in the
status registers. Fault bits are
only cleared by the
7:6
11
Not Used
CLEAR_FAULTS command.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not Used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down.
111
111
Not used. Retry time is fixed at 70ms.
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ZL8801
VIN_OV_WARN_LIMIT (57h)
Definition: Sets the V overvoltage warning threshold as defined by the following table. In response to the OV_WARN_LIMIT being
IN
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_OV_WARNING bit in STATUS_INPUT
and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D360h (13.5V)
Units: V
Equation: VIN_OV_FAULT_LIMIT = Y x 2
N
Range: 0 to 19V
COMMAND
Format
VIN_OV_WARN_LIMIT (57h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the V undervoltage warning threshold. In response to the UV_WARN_LIMIT being exceeded, the device: Sets the NONE
IN
OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_UV_WARNING bit in STATUS_INPUT and notifies the host.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 1.10 x VIN_UV_FAULT_LIMIT pin-strap setting
Units: V
N
Equation: VIN_UV_WARN_LIMIT = Y x 2
Range: 0 to 19V
COMMAND
Format
VIN_UV_WARN_LIMIT (58h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
1.10 x VIN_UV_FAULT_LIMIT pin-strap setting
Default Value
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ZL8801
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the V undervoltage fault threshold.
IN
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: Pin-strap setting
Units: V
Equation: VIN_UV_FAULT_LIMIT = Y x 2
N
Range: 0 to 19V
COMMAND
Format
VIN_UV_FAULT_LIMIT (59h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
Pin-strapped Value
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the V undervoltage fault response as defined by the following table. The delay time is the time between restart
IN
attempts.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shut down, no retry)
Units: Retry time unit = 70ms
COMMAND
VIN_UV_FAULT_RESPONSE (5Ah)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00-01
10
DESCRIPTION
Response Behavior: The Device:
• Pulls SALRT low
Not Used
Disable and retry according to the setting in Bits [5:3].
• Sets the related fault bit in the
status registers. Fault Bits are
only cleared by the
7:6
11
Not Used
CLEAR_FAULTS command.
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not Used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command), bias power is removed, or another fault condition
causes the unit to shut down.
111
111
Not used. Retry time is fixed at 70ms.
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ZL8801
POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for power-good indication. Power-good asserts when the output voltage exceeds
POWER_GOOD_ON and deasserts when the output voltage is less than VOUT_UV_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 0.9 x VOUT_COMMAND pin-strap setting
Units: V
COMMAND
Format
POWER_GOOD_ON (5Eh)
Linear, unsigned binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default Value
0.9 x VOUT_COMMAND pin-strap setting
TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of V
rise.
OUT
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h, 5ms
Units: ms
Equation: TON_DELAY = Y x 2
N
Range: 0 to 5 seconds
COMMAND
Format
TON_DELAY (60h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
TON_RISE (61h)
Definition: Sets the rise time of V
or 8-phase operation, use MULTI_PHASE_RAMP_GAIN (70h).
after ENABLE and TON_DELAY for 2-phase (single device) operation. To adjust the rise time in 4-, 6-
OUT
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h, 5ms
Units: ms
Equation: TON_RISE = Y x 2
N
Range: 5 to 100ms. Short rise times may cause excessive input and output currents to flow, thus triggering overcurrent faults at
start-up.
COMMAND
Format
TON_RISE (61h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
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ZL8801
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of V
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
fall.
OUT
Protectable: Yes
Default Value: CA80h, 5ms
Units: ms
Equation: TON_DELAY = Y x 2
N
Range: 0 to 5 seconds
COMMAND
Format
TOFF_DELAY (64h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
TOFF_FALL (65h)
Definition: Sets the fall time for V
OUT
after DISABLE and TOFF_DELAY. This setting is only valid in 2-phase operation. Setting the
TOFF_FALL to values less than 5ms will cause the ZL8801 to turn off both the high and low-side FETs (or disable the DrMOS device)
immediately after the expiration of the TOFF_DELAY time. In 4-, 6- or 8-phase operation, the ZL8801 will always turn off both the high
and low-side FETs (or disable the DrMOS device) immediately after the expiration of the TOFF_DELAY time.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h, 5ms
Units: ms
Equation: TOFF_FALL = Y x 2
N
Range: 5 to 100ms. Short fall times may cause excessive negative output current to flow, thus triggering undercurrent faults at
shutdown.
COMMAND
Format
TOFF_FALL (65h)
Linear, two’s complement binary
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
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ZL8801
STATUS_BYTE (78h)
Definition: The STATUS_BYTE command returns the low byte of information from the STATUS_WORD. Based on the information in this
byte, the host can get more information by reading the appropriate status registers.
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 0000h
Units: N/A
COMMAND
STATUS_BYTE (78h)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT NUMBER
7
STATUS BIT NAME
BUSY
MEANING
A fault was declared because the device was busy and unable to
respond.
6
OFF
This bit is asserted if the unit is not providing power to the output,
regardless of the reason, including simply not being enabled.
5
4
3
2
1
0
VOUT_OV_FAULT
IOUT_OC_FAULT
VIN_UV_FAULT
TEMPERATURE
CML
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
An input undervoltage fault has occurred.
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
Not used
Not Used
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ZL8801
STATUS_WORD (79h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the
information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the
STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Data Length in Bytes: 2
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 0000h
Units: N/A
COMMAND
Format
STATUS_WORD (79h)
Bit Field
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
VOUT
MEANING
15
14
13
An output voltage fault or warning has occurred.
An output current or output power fault or warning has occurred.
IOUT
INPUT
An input voltage, input current, or input power fault or warning has
occurred.
12
11
10
9
MFG_SPECIFIC
POWER_GOOD #
Not Used
A manufacturer specific fault or warning has occurred.
The POWER_GOOD signal, if present, is negated. (Note 15).
Not used
OTHER
A bit in STATUS_VOUT, STATUS_IOUT, STATUS_INPUT,
STATUS_TEMPERATURE, STATUS_CML or STATUS_MFR_SPECIFIC is
set.
8
7
Not Used
BUSY
Not used
A fault was declared because the device was busy and unable to
respond.
6
OFF
This bit is asserted if the unit is not providing power to the output,
regardless of the reason, including simply not being enabled.
5
4
3
2
1
0
VOUT_OV_FAULT
IOUT_OC_FAULT
VIN_UV_FAULT
TEMPERATURE
CML
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
An input undervoltage fault has occurred.
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
Not used
Not Used
NOTE:
15. If the POWER_GOOD# bit is set, this indicates that the POWER_GOOD signal, if present, is signaling that the output power is not good.
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ZL8801
STATUS_VOUT (7Ah)
Definition: The STATUS_VOUT command returns one data byte with the status of the output voltage.
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_VOUT (7Ah)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
VOUT_OV_FAULT
VOUT_OV_WARNING
VOUT_UV_WARNING
VOUT_UV_FAULT
N/A
MEANING
7
6
Indicates an output overvoltage fault.
These bits are not used.
5
Indicates an output undervoltage.
Indicates an output undervoltage fault.
These bits are not used.
4
3:0
STATUS_IOUT (7Bh)
Definition: The STATUS_IOUT command returns one data byte with the status of the output current.
Data Length in Bytes: 1
Data Format: BIT Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_IOUT (7Bh)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
IOUT_OC_FAULT
IOUT_OC_LV_FAULT
IOUT_OC_WARNING
IOUT_UC_FAULT
Phase 0 FAULT
Phase 1 FAULT
Not Used
MEANING
7
6
An output overcurrent fault has occurred.
An output overcurrent and low voltage fault has occurred.
An output overcurrent warning has occurred.
An output undercurrent fault has occurred.
A fault occurred on Phase 0.
5
4
3
2
A fault occurred on Phase 1.
0:1
These bits are not used.
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ZL8801
STATUS_INPUT (7Ch)
Definition: The STATUS_INPUT command returns input voltage and input current status information.
Data Length in Bytes: 1
Data Format: BIT Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_INPUT (7Ch)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
VIN_OV_FAULT
VIN_OV_WARNING
VIN_UV_WARNING
VIN_UV_FAULT
Not Used
MEANING
7
6
An input overvoltage fault has occurred.
An input overvoltage warning has occurred.
An input undervoltage warning has occurred.
An input undervoltage fault has occurred.
Not used
5
4
3:0
STATUS_TEMPERATURE (7Dh)
Definition: The STATUS_TEMPERATURE command returns one byte of information with a summary of any temperature related faults or
warnings.
Data Length in Bytes: 1
Data Format: BIT Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_TEMPERATURE (7Dh)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
OT_FAULT
MEANING
7
6
5
4
3
2
1
0
An over-temperature fault has occurred.
An over-temperature warning has occurred.
An under-temperature warning has occurred.
An under-temperature fault has occurred.
OT_WARNING
UT_WARNING
UT_FAULT
FAULT_INT
A warning or fault occurred from the internal temperature sensor.
FAULT_XTEMP0
FAULT_XTEMP1
Not Used
A warning or fault occurred from the external temperature sensor 0.
A warning or fault occurred from the external temperature sensor 1.
Not used
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ZL8801
STATUS_CML (7Eh)
Definition: The STATUS_WORD command returns one byte of information with a summary of any Communications, Logic and/or Memory
errors.
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_CML (7Eh)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT NUMBER
MEANING
7
6
Invalid or unsupported PMBus™ Command was received.
The PMBus™ command was sent with Invalid or Unsupported data.
A packet error was detected in the PMBus™ command.
Not used
5
4:2
1
A PMBus™ command tried to write to a read only or protected command, or a communication fault other than the ones listed in
this table has occurred.
0
Not used
STATUS_MFR_SPECIFIC (80h)
Definition: The STATUS_MFR_SPECIFIC command returns one byte of information providing the status of the device’s voltage
monitoring and clock synchronization faults. Note: The VMON OV/UV warnings are set at ±10% of the VMON_XX_FAULT commands.
Data Length in Bytes: 1
Data Format: BIT Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_MFR_SPECIFIC (80h)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT
7
FIELD NAME
Not Used
MEANING
Not used
A phase or phases of a multi-phase current sharing group did not initialize.
6
Phase
5
VMON UV Warning
VMON OV Warning
The voltage on the VMON pin has dropped 10% below the level set by MFR_VMON_UV_FAULT.
The voltage on the VMON pin has risen 10% above the level set by MFR_VMON_OV_FAULT.
4
3
2
1
0
External Switching Period Fault Loss of external clock synchronization has occurred.
Not Used
Not used
VMON UV Fault
VMON OV Fault
The voltage on the VMON pin has dropped below the level set by MFR_VMON_UV_FAULT.
The voltage on the VMON pin has risen above the level set by MFR_VMON_OV_FAULT.
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ZL8801
READ_VIN (88h)
Definition: Returns the input voltage reading.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: V
Equation: READ_VIN = Y x 2
N
Range: N/A
COMMAND
Format
READ_VIN (88h)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_IIN (89h)
Definition: Returns the input current reading.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IIN = Y x 2
N
Range: N/A
COMMAND
Format
READ_IIN (89h)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
9
r
8
r
7
r
6
5
r
4
r
3
r
2
r
1
r
0
r
r
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
Default Value N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned.
Type: Read Only
Protectable: No
Default Value: N/A
Equation: READ_VOUT = READ_VOUT x 2
-13
Units: V
COMMAND
Format
READ_VOUT (8Bh)
Linear-16 Unsigned
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
r
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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ZL8801
READ_IOUT (8Ch)
Definition: Returns the combined output current of Phase 0 and Phase 1, i.e., the total output current.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IOUT = Y x 2
N
Range: N/A
COMMAND
Format
READ_IOUT (8Ch)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_TEMPERATURE_1 (8Dh)
Definition: Returns the temperature reading internal to the device.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_1 = Y x 2
N
Range: N/A
COMMAND
Format
READ_INTERNAL_TEMP_1 (8Dh)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
N/A N/A N/A
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_TEMPERATURE_2 (8Eh)
Definition: Returns the temperature reading from the external temperature device connected to XTEMP0.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_2 = Y x 2
N
Range: N/A
COMMAND
Format
READ_EXTERNAL_TEMP_2 (8Eh)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
N/A N/A N/A
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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ZL8801
READ_TEMPERATURE_3 (8Fh)
Definition: Returns the temperature reading from the external temperature device connected to XTEMP1.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_2 = Y x 2
N
Range: N/A
COMMAND
Format
READ_EXTERNAL_TEMP_3 (8Fh)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
N/A N/A N/A
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_DUTY_CYCLE (94h)
Definition: Reports the duty cycle of the converter during the enable state. The duty cycle read is essentially an average of the duty
cycles of Phase 0 and Phase 1.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: %
Equation: READ_DUTY_CYCLE = Y x 2
N
Range: 0 to 100%
COMMAND
Format
READ_DUTY_CYCLE (94h)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Default Value: N/A
Units: kHz
Equation: READ_FREQUENCY = Y x 2
N
Range: N/A
Units: N/A
COMMAND
Format
READ_FREQUENCY (95h)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
N/A N/A N/A
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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ZL8801
PMBUS_REVISION (98h)
Definition: The PMBUS_REVISION command returns the revision of the PMBus Specification to which the device is compliant.
Data Length in Bytes: 1
Data Format: BIT Field
Type: Read Only
Protectable: N/A
Default Value: 11h (Part 1 Revision 1.2, Part 2 Revision 1.2)
Units: N/A
COMMAND
PMBUS_REVISION (98h)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
1
0
0
0
1
0
BITS 7:4
0000
PART 1 REVISION
BITS 3:0
0000
PART 2 REVISION
1.0
1.1
1.2
1.0
1.1
1.2
0001
0001
0010
0010
MFR_ID (99h)
Definition: MFR_ID sets a user defined identification string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,
MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 bytes. This
limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this
command then perform a STORE/RESTORE.
Data Length in Bytes: User Defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: null
Units: N/A
MFR_MODEL (9Ah)
Definition: MFR_MODEL sets a user defined model string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,
MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 bytes.
This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write
this command then perform a STORE/RESTORE.
Data Length in Bytes: User Defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: null
Units: N/A
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ZL8801
MFR_REVISION (9Bh)
Definition: MFR_REVISION sets a user defined revision string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot
exceed 128 bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform
a RESTORE, write this command then perform a STORE/RESTORE.
Data Length in Bytes: User Defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: null
Units: N/A
MFR_LOCATION (9Ch)
Definition: MFR_LOCATION sets a user defined location identifier string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed
128 bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE,
write this command then perform a STORE/RESTORE.
Data Length in Bytes: User Defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: null
Units: N/A
MFR_DATE (9Dh)
Definition: MFR_DATE sets a user defined date string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,
MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 bytes.
This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write
this command then perform a STORE/RESTORE.
Data Length in Bytes: User Defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: null
Units: N/A
MFR_SERIAL (9Eh)
Definition: MFR_SERIAL sets a user defined serialized identifier string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot
exceed 128 bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform
a RESTORE, write this command then perform a STORE/RESTORE.
Data Length in Bytes: User Defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: null
Units: N/A
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ZL8801
READ_IOUT0 (A1h)
Definition: Returns the output current of phase 0.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IOUT = Y x 2
N
Range: N/A
COMMAND
Format
READ_IOUT0 (A1h)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_IOUT1 (A2h)
Definition: Returns the output current of Phase 1.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IOUT = Y x 2
N
Range: N/A
COMMAND
Format
READ_IOUT1 (A2h)
Linear-11
Bit Position
Access
15
r
14
r
13
r
12
r
11
r
10
r
9
r
8
r
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
N/A N/A N/A
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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ZL8801
LEGACY_FAULT_GROUP (A8h)
Definition: This command allows the ZL8801 to sequence and fault spread with devices other than the ZL8800 and ZL8801. This
command sets which rail DDC IDs should be listened to for fault spreading information. The data sent is a 4-byte, 32-bit vector where
every bit represents a rail’s DDC ID. A bit set to 1 indicates a device DDC ID to which the configured device will respond upon receiving
a fault spreading event. In this vector, Bit 0 of byte 0 corresponds to the rail with DDC ID 0. Following through, Bit 7 of byte 3
corresponds to the rail with DDC ID 31.
NOTE: The device/rail’s own DDC ID should not be set within the LEGACY_FAULT_GROUP command for that device/rail.
All devices in a current share rail (devices other than the ZL8800/1) must shut down for the rail to report a shut down.
If fault spread mode is enabled in USER_CONFIG, the device will immediately shut down if one of its DDC_GROUP members fail. The
device/rail will attempt its configured restart only after all devices/rails within the DDC_GROUP have cleared their faults.
If fault spread mode is disabled in USER_CONFIG, the device will perform a sequenced shutdown as defined by the SEQUENCE
command setting. The rails/devices in a sequencing set only attempt their configured restart after all faults have cleared within the
DDC_GROUP. If fault spread mode is disabled and sequencing is also disabled, the device will ignore faults from other devices and stay
enabled.
Data Length in Bytes: 4
Data Format: BIT Field
Type: Block R/W
Protectable: Yes
Default Value: 00000000h
Units: N/A
COMMAND
Format
LEGACY_FAULT_GROUP (A8h)
Bit Field
Bit Position
Access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
Format
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
FIELD NAME
Fault Group
VALUE
NA
SETTING
DESCRIPTION
31:0
00000000h Identifies the devices in the fault spreading group.
IC_DEVICE_ID (ADh)
Definition: Reports device identification information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Protectable: No
Default Value: 49A02300h
Units: N/A
COMMAND
Format
IC_DEVICE_ID (ADh)
Block Read
Byte Position
Function
3
2
1
0
MFR code
49h
ID High Byte
A0h
ID Low Byte
23h
Reserved
00h
Default Value
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ZL8801
IC_DEVICE_REV (AEh)
Definition: Reports device revision information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Protectable: No
Default Value: 01000000h
Units: N/A
COMMAND
Format
IC_DEVICE_REV (AEh)
Block Read
Byte Position
3
2
1
0
Function
Firmware Major
01h
Firmware Minor
00h
Factory Config
00h
Reserved
00h
Default Value
USER_DATA_00 (B0h)
Definition: USER_DATA_00 sets a user defined data string not to exceed 32 bytes. The sum total of characters in MFR_ID, MFR_MODEL,
MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command cannot exceed 128 bytes
This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write
this command then perform a STORE/RESTORE.
Data Length in Bytes: user defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: null
Units: N/A
DEADTIME_MAX (BFh)
Definition: Sets the maximum dead time value for the adaptive dead time algorithm. Settings are applied to both phases.
Data Length in Bytes: 2
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 3838h (56ns/56ns)
Units: ns
Range: 0 to 60ns
Reference: N/A
COMMAND
Format
DEADTIME_MAX (BFh)
Bit Field/Linear-7 Unsigned
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
BITS
15
PURPOSE
VALUE
DESCRIPTION
Not Used
0
H
Not used
14:8
Sets the maximum H-to-L dead time
Limits the maximum allowed H-to-L dead time when using the adaptive
dead time algorithm. Dead time = Hns (signed).
7
Not Used
0
L
Not used
6:0
Sets the maximum L-to-H dead time
Limits the maximum allowed L-to-H dead time when using the adaptive
dead time algorithm. Dead time = Lns (signed).
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ZL8801
IOUT0_CAL_GAIN (CAh)
Definition: Sets the effective impedance across the Phase 0 current sense circuit for use in calculating output current at +25°C.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: AA66h (0.3mΩ)
Units: mΩ
Equation: IOUT_CAL_GAIN = Y x 2
N
COMMAND
Format
IOUT0_CAL_GAIN (CAh)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
IOUT1_CAL_GAIN (CBh)
Definition: Sets the effective impedance across the Phase 1 current sense circuit for use in calculating output current at +25°C.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: AA66h (0.3mΩ)
Units: mΩ
Equation: IOUT_CAL_GAIN = Y x 2N
COMMAND
Format
IOUT1_CAL_GAIN (CBh)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
IOUT0_CAL_OFFSET (CCh)
Definition: Used to null out any offsets in the output current sensing circuit and to compensate for delayed measurements of current
ramp due to ISENSE blanking time for Phase 0.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0A)
Units: A
Equation: IOUT_CAL_OFFSET = Y x 2
N
COMMAND
Format
IOUT0_CAL_OFFSET (CCh)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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ZL8801
IOUT1_CAL_OFFSET (CDh)
Definition: Used to null out any offsets in the output current sensing circuit and to compensate for delayed measurements of current
ramp due to ISENSE blanking time for Phase 1.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0A)
Units: A
Equation: IOUT_CAL_OFFSET = Y x 2
N
COMMAND
Format
IOUT1_CAL_OFFSET (CDh)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MIN_VOUT_REG (CEh)
Definition: Sets the minimum output voltage in millivolts (mV) that the device will attempt to regulate to during start-up and shutdown
ramps.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: F258h (150mV)
Units: A
N
Equation: MIN_VOUT_REG = Y x 2
COMMAND
Format
MIN_VOUT_REG (CEh)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
1
1
0
0
1
0
0
1
0
1
1
0
0
0
ISENSE_CONFIG (D0h)
Definition: Configures current sense circuitry. Settings are applied to both phases.
Data Length in Bytes: 2
Data Format: BIT Field
Type: R/W Word
Protectable: Yes
Default Value: 4204h (256ns, 5 counts, downslope, low range)
Units: N/A
Range: N/A
COMMAND
Format
ISENSE_CONFIG (D0h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
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ZL8801
BIT
FIELD NAME
VALUE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
000
SETTING
0
DESCRIPTION
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
1
15:11 Current Sense Blanking Time
Sets the blanking time current sense blanking time in increments of 32ns
001
3
010
5
Sets the number of consecutive overcurrent (OC) or undercurrent (UC) events
required for a fault. An event can occur once during each switching cycle. For
example, if 5 is selected, an OC or UC event must occur for 5 consecutive
switching cycles, resulting in a delay of at least 5 switching periods.
011
7
10:8 Current Sense Fault Count
100
9
101
11
110
13
111
15
7:4
Not Used
000
Not Used
Not Used
Not used
00
DCR (Down
Slope)
01
3:2 Current Sense Control
Selection of current sensing method (DCR based: V referenced).
OUT
10
11
00
01
10
11
DCR (Up Slope)
Not Used
Low Range
Medium Range
High Range
Not Used
1:0 Current Sense Range
Low Range ±25mV, Medium Range ±35mV, High Range ±50mV
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ZL8801
USER_CONFIG (D1h)
Definition: Configures several user-level features.
Data Length in Bytes: 2
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 0402h
Units: N/A
COMMAND
Format
USER_CONFIG (D1h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
BIT
FIELD NAME
VALUE
SETTING
0-31d
DESCRIPTION
15:11 Minimum Duty Cycle
10 Enable DR MOS
9:8 Not Used
00000
Sets the minimum duty-cycle to 2x (VALUE+1)/512. Must be enabled with Bit 7.
0 = PWML and PWMH are direct drive to MOSFET driver.
1 = PWML is DrMOS Enable, PWMH is DrMOS PWM input.
Not Used
0
1
Disable
Enable
00
0
Not Used
Disable
Enable
1 = Minimum Duty Cycle Control is Enabled, 0 = Minimum Duty Cycle Control is
Disabled.
7
Minimum Duty Cycle Control
1
6:5 Not Used
00
0
Not Used
Disable
Enable
Not Used
4
3
2
Margin Ratio Enable
Use VOUT_MARGIN_RATIO to configure margin values when enabled.
1
Not Used
0
Not Used
Open Drain
Push-pull
Disable
Enable
Not Used
0
0 = PG is open-drain output.
1 = PG is push-pull output.
Power-good Configuration
1
0
1
0
XTEMP Enable
Enable external temperature sensor.
1
0
Disable
Enable
XTEMP Fault Select
Selects external temperature sensor to determine temperature faults.
1
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ZL8801
IIN_CAL_GAIN (D2h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating input current at +25°C.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: C200h (2mΩ)
Units: mΩ
Equation: IIN_CAL_GAIN = Y x 2
N
COMMAND
Format
IIN_CAL_GAIN (D2h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
DDC_CONFIG (D3h)
Definition: Configures DDC addressing and current sharing for up to 8 phases. To operate as a 4-phase controller, set both devices to
the same Rail ID, set Phases in Rail to 4, then set each phase ID sequentially, for example, 0 and 1. The ZL8801 will automatically
equally offset all phases in the rail. Note that phase spreading is done automatically as part of the DDC_CONFIG command, the
INTERLEAVE command only applies to non-current sharing rails. Following is a table illustrating how DDC_CONFIG automatically sets
phases for multi-phase configurations. In 2-phase single device operation, the phases are set to position 0 and 4 automatically.
4 PHASES
6 PHASES
8 PHASES
ID # PHASE PHASE 0
PHASE 1
ID
0
# PHASE
PHASE 0
PHASE 1
ID
0
# PHASE
PHASE 0
PHASE 1
Device 1
Device 2
Device 3
Device 4
0
1
4
4
0
2
4
6
6
6
6
0
1
2
4
5
6
8
8
8
8
0
1
2
3
4
5
6
7
1
1
2
2
3
Data Length in Bytes: 2
Data Format: Bit FIELD
Type: R/W
Protectable: Yes
Default Value: PMBus™ address pin-strap dependent
Units: N/A
COMMAND
Format
DDC_CONFIG (D3h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
Lower 5 bits of device address
0
0
0
0
0
0
0
0
BIT
15:13
12:8
7:3
FIELD NAME
Phase ID
VALUE
0 to 3
0 to 31d
00
SETTING
DESCRIPTION
0
0
Sets the device’s phase position within the rail (see chart above)
Identifies the device as part of a current sharing rail (Shared output).
Not used
Rail ID
Not Used
00
0
2:0
Phases In Rail
1, 3, 5, 7d
Identifies the number of phases on the same rail (+1).
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ZL8801
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The
delay time can range from 0ms up to 500s, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper
debounce to this signal.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA00h, 4ms
Units: ms
Equation: POWER_GOOD_DELAY = Y x 2
N
Range: 0 to 5 seconds
COMMAND
Format
POWER_GOOD_DELAY (D4h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
MULTI_PHASE_RAMP_GAIN (D5h)
Definition: MULTI_PHASE_RAMP_GAIN command value indirectly determines the output voltage rise time during the turn-on ramp.
Typical gain values range from 1 to 5. Lower gain values produce longer ramp times.
MULTI_PHASE_RAMP_GAIN mode is automatically selected when the ZL8801 is configured to operate in a 4-, 6- or 8-phase current
sharing group. When in MULTI_PHASE_RAMP_GAIN mode the turn-on ramp-up is done with the high bandwidth ASCR control circuitry
disabled, resulting in a lower loop bandwidth during start-up ramps. Once POWER_GOOD has been asserted, ASCR circuitry is enabled
and the ZL8801 operates normally. When MULTI_PHASE_RAMP_GAIN mode is enabled, Soft-off ramps are not allowed (TOFF_FALL is
ignored). When the ZL8801 is commanded to shut down, both the high-side and low-side MOSFETs are turned off, or in the case of
DrMOS, the enable pin is pulled low (DrMOS disabled). Large load current transitions during multi-phase ramp ups will cause output
voltage discontinuities.
When the phase count is 2; i.e., when the ZL8801 is operating standalone, ASCR is enabled at all times and all commands associated
with turn-on and turn-off (TON_RISE, TOFF_FALL, Soft-Off) operate normally.
Data Length in Bytes: 1
Data Format: 1 byte binary
Type: R/W
Protectable: Yes
Default Value: 03h
Units: N/A
COMMAND
MULTI_PHASE_RAMP_GAIN (D5h)
1 Byte Binary
Format
Bit Position
Access
7
r/w
0
6
r/w
0
5
r/w
0
4
r/w
0
3
r/w
0
2
r/w
0
1
r/w
1
0
r/w
1
Default Value
BIT
FIELD NAME
VALUE
00-FF
DESCRIPTION
Start-up ramp gain
7:0
• Gain
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ZL8801
INDUCTOR (D6h)
Definition: Informs the device of the circuit’s inductor value. This is used in adaptive algorithm calculations relating to the inductor
ripple current.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: B23Dh (0.56µH)
Units: µH
N
Equation: INDUCTOR = Y x 2
Range: 0 to 100µH
COMMAND
Format
INDUCTOR (D6h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
0
1
1
0
0
1
0
0
0
1
1
1
1
0
1
VOUT_MARGIN RATIO (D7h)
Definition: Percentage to set MARGIN_HIGH and MARGIN_LOW above and below VOUT_COMMAND when feature is enabled by
USER_CONFIG.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 5 (CA80h)
Units: %
N
Equation: VOUT_MARGIN_RATIO = Y x 2
Range: 0 to 50%
COMMAND
Format
VOUT_MARGIN_RATIO (D7h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
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ZL8801
OVUV_CONFIG (D8h)
Definition: Configures the output voltage OV and UV fault detection feature
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
OVUV_CONFIG (D8h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BITS
PURPOSE
VALUE
DESCRIPTION
0
1
0
N
An OV fault does not enable low-side power device.
An OV fault enables the low-side power device.
Not used
Controls how an OV fault response shutdown sets the output
driver state
7
6:4 Not Used
3:0 Defines the number of consecutive limit violations required to
declare an OV or UV fault
N+1 consecutive OV or UV violations initiate a fault response.
XTEMP_SCALE (D9h)
Definition: Sets a scalar value that is used for calibrating both of the external temperature sensors (Phase 0 and Phase 1). The constant
is applied in Equation 27 to produce the read value of XTEMP via the PMBus™ command READ_TEMPERATURE_2 and
READ_TEMPERATURE_3.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h (1.0)
Units: 1/°C
Equation:
1
READ_TEMPERATURE_2 ExternalTemperature
Range: 0.1 to 10
XTEMP_OFFSET
(EQ. 27)
XTEMP_SCALE
COMMAND
Format
XTEMP_SCALE (D9h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
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ZL8801
XTEMP_OFFSET (DAh)
Definition: Sets an offset value that is used for calibrating both of the external temperature sensors (Phase 0 and Phase 1). The
constant is applied in Equation 28 to produce the read value of XTEMP via the PMBus™ command READ_TEMPERATURE_2 and
READ_TEMPERATURE_3.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0)
Units: °C
Equation:
1
(EQ. 28)
READ_TEMPERATURE_2 ExternalTemperature
XTEMP_OFFSET
XTEMP_SCALE
Range: -100°C to +100°C
COMMAND
Format
XTEMP_OFFSET (DAh)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMPCO_CONFIG (DCh)
Definition: Configures the correction factor and temperature measurement source when performing temperature coefficient correction
for current sense. TEMPCO_CONFIG values are applied as negative correction to a positive temperature coefficient. When using
external temperature sensors, the coefficient applies to both temperature sensors.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 27h (3900ppm/°C)
Equation: To determine the hex value of the Tempco Correction factor (TC) for current scale of a power stage current sensing, first
determine the temperature coefficient of resistance for the sensing element, α. This is found with Equation 29:
RREF R
(EQ. 29)
RREF (TREF T )
Where:
R = Sensing element resistance at temperature “T”
= Sensing element resistance at reference temperature T
R
REF
REF
α = Temperature coefficient of resistance for the sensing element material
T = Temperature measured by temperature sensor, in Degrees Celsius
T
= Reference temperature that α is specified at for the sensing element material
REF
After α is determined, convert the value in units of 100ppm/°C. This value is then converted to a hex value by using Equation 30:
106
(EQ. 30)
TC
100
Typical Values: Copper = 3900ppm/˚C (27h), silicon = 4800ppm/˚C (30h)
Range: 0 to 6300ppm/˚C
COMMAND
TEMPCO_CONFIG (DCh)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
1
0
0
1
1
1
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ZL8801
BITS
7
PURPOSE
VALUE
DESCRIPTION
Selects the internal temperature sensor.
0
1
Selects the temp sensor source for tempco correction
Selects the XTEMP0 and XTEMP1 pins for temperature measurements
(2N3904 Junction) Note that XTEMP must be enabled in USER_CONFIG, Bit1.
6:0 Sets the tempco correction in units of 100ppm/°C for
IOUT_CAL_GAIN
TC RSEN (DCR) = IOUT_CAL_GAIN x (1+TC x (T-25)).
where RSEN = resistance of sense element.
DEADTIME (DDh)
Definition: Sets the nonoverlap between PWM transitions using a 2 byte data field. The most significant byte controls the high-side to
low-side deadtime value as a single 2’s-complement signed value in units of ns. The least-significant byte controls the low-side to
high-side deadtime value. Positive values imply a nonoverlap of the FET drive on-times. Negative values imply an overlap of the FET
drive on-times. Writing a value to this command immediately before writing the DEADTIME_CONFIG command will set a new maximum
for the adaptive deadtime algorithm. The device will operate at the deadtime values written to this command when adaptive deadtime
is disabled.
Data Length in Bytes: 2
Data Format: CUS
Type: R/W
Protectable: Yes
Default Value: 1010h (16ns/16ns)
Units: ns
Range: -15ns to 60ns
COMMAND
Format
DEADTIME (DDh)
Linear-8 Signed
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
High to low-side deadtime 8 bit two's complement signed
Low to high-side deadtime 8 bit two's complement signed
Default Value
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
DEADTIME_CONFIG (DEh)
Definition: Configures the adaptive deadtime optimization mode. Also sets the minimum deadtime value for the adaptive deadtime
mode range.
Data Length in Bytes: 2
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 8888h (Frozen deadtime control, 8ns/8ns minimum deadtime)
Units: N/A
COMMAND
Format
DEADTIME_CONFIG (DEh)
Bit Field/Linear-7 Unsigned
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
BITS
15
PURPOSE
VALUE
DESCRIPTION
0
1
Adaptive H-to-L deadtime control.
Freeze the H-to-L deadtime.
Sets the high-to-low transition deadtime mode
Sets the minimum H-to-L deadtime
14:8
0-126d Limits the minimum allowed H-to-L deadtime when using the
adaptive deadtime algorithm (2ns resolution).
0
1
Adaptive L-to-H deadtime control.
Freeze the L-to-H deadtime.
7
Sets the low-to-high transition deadtime mode
Sets the minimum L-to-H deadtime
6:0
0-126d Limits the minimum allowed L-to-H deadtime when using the
adaptive deadtime algorithm (2ns resolution).
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ZL8801
ASCR_CONFIG (DFh)
Definition: Allows user configuration of ASCR settings. ChargeMode control achieves a fast acting, low deviation transient response by
detecting and reacting to very small variations in the output voltage. ChargeMode control performance is optimized when ΔV due to
capacitor ripple is 1% or less of the output voltage.
Data Length in Bytes: 4
Data Format: BIT Field and non-signed binary
Type: R/W
Protectable: Yes
Default Value: 015A0190h (ASCR enabled, Gain 400, Residual 90)
Units: N/A
COMMAND
Format
ASCR_CONFIG (DFh)
Bit Field/Linear-8 Unsigned
Bit Position
Access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
Format
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
0
Linear-16 Unsigned
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
BITS
PURPOSE
VALUE
DESCRIPTION
31:25
Not Used
0000000h
Not Used
1
0
Enable
24
ASCR Enable
Disable
23:16
15:0
ASCR Residual Setting
ASCR Gain Setting
90
400
ASCR residual
ASCR gain
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ZL8801
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multirail sequencing. The device will enable its
output when its EN or OPERATION enable state, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a power-good
event on the DDC bus. The device will disable its output (using the configured delay values) when the sequel device has issued a
power-down event on the DDC bus.
The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant
byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or
sequel mode.
Data Length in Bytes: 2
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 00h (Prequel and Sequel disabled)
Units: N/A
COMMAND
Format
SEQUENCE (E0h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
SETTING
Disable
Enable
DESCRIPTION
Disable, no prequel preceding this rail.
0
15
Prequel Enable
1
Enable, prequel to this rail is defined by Bits 12:8.
Not used
14:13 Not Used
12:8 Prequel Rail DDC ID
0
0-31d
0
Not Used
DDC ID
Disable
Enable
Set to the DDC ID of the prequel rail.
Disable, no sequel following this rail.
Enable, sequel to this rail is defined by Bits 4:0.
Not used
7
Sequel Enable
1
6:5
4:0
Not Used
0
Not Used
DDC ID
Sequel Rail DDC ID
0-31d
Set to the DDC ID of the sequel rail.
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ZL8801
TRACK_CONFIG (E1h)
Definition: Configures the voltage tracking modes of the device. Single device (2-phase) tracking is supported. Tracking as part of a
4-, 6- or 8-phase current sharing group is not supported.
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
TRACK_CONFIG (E1h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
SETTING
Disable
Enable
Not Used
100%
DESCRIPTION
0
Tracking is disabled.
Tracking is enabled.
Not used
7
6:3
2
Voltage Tracking Control
Not Used
1
0000
0
1
0
1
0
Output tracks at 100% ratio of VTRK input.
Output tracks at 50% ratio of VTRK input.
Output voltage is limited by target voltage.
Output voltage is limited by VTRK voltage.
Not used
Tracking Ratio Control
50%
Target Voltage
VTRK Voltage
Not Used
1
0
Tracking Upper Limit
Not Used
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ZL8801
DDC_GROUP (E2h)
Definition: Rails (output voltages) are assigned group numbers in order to share specified behaviors. The DDC_GROUP command
configures fault spreading group ID and enable, broadcast OPERATION group ID and enable and broadcast VOUT_COMMAND group ID
and enable. Note that DDC Groups are separate and unique from DDC Phases. Current sharing rails need to be in the same DDC Group
in order to respond to broadcast VOUT_COMMAND and OPERATION commands. Power fail event responses are automatically spread in
current sharing rails when they are configured using DDC_CONFIG, regardless of their setting in DDC_GROUP.
Data Length in Bytes: 3
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 000000h (Ignore broadcast VOUT_COMMAND and operation, sequence shutdown on power fail event)
Units: N/A
COMMAND
Format
DDC_GROUP (E2h)
Bit Field
Bit Position 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Access
r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w
See Following Table
Function
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BITS
PURPOSE
VALUE
DESCRIPTION
1
0
Responds to broadcast margin command with same Group ID.
Ignores broadcast margin command.
23 Broadcast Margin Command Response
22:18 Broadcast VOUT_COMMAND Group ID
17 Broadcast VOUT_COMMAND Response
16:12 Broadcast VOUT_COMMAND Group ID
11 Broadcast Operation Response
0-31d Group ID sent as data for broadcast VOUT_COMMAND events.
1
0
Responds to broadcast VOUT_COMMAND with same Group ID.
Ignores broadcast VOUT_COMMAND.
0-31d Group ID sent as data for broadcast VOUT_COMMAND events.
1
0
Responds to broadcast operation with same Group ID.
Ignores broadcast operation.
10:6 Broadcast Operation Group ID
0-31d Group ID sent as data for broadcast Broadcast operation events.
1
0
Responds to power fail events with same group ID by shutting down immediately.
Responds to power fail events with same group ID with sequenced shutdown.
5
Power Fail Response
4:0 Power Fail Group ID
0-31d Group ID sent as data for broadcast power fail events.
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string.
Data Length in Bytes: 16
Data Format: ASCII. ISO/IEC 8859-1
Type: Block Read
Protectable: No
Default Value: <part number/die revision/firmware revision>
Units: N/A
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ZL8801
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the I
PMBus™ standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT.
overcurrent fault response as defined by the table below. The command format is the same as the
OUT
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shut down, no retries)
Units: Retry time = 70ms
COMMAND
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00
DESCRIPTION
Response Behavior: For all modes, the
device:
• Pulls SALRT low
Not used
Not used
01
7:6
10
Disable without delay and retry according to the setting in Bits 5:3.
• Sets the related fault bit in the
status registers. Fault bits are only
cleared by the CLEAR_FAULTS
command.
11
Not used
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
111
111
Not used. Retry time is 70ms.
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ZL8801
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the I
OUT
undercurrent fault response as defined by the table below. The command format is the same as the
PMBus™ standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT.
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shutdown, no retries)
Units: Retry time = 70ms
COMMAND
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00
DESCRIPTION
Response Behavior: For all modes, the device:
• Pulls SALRT low
Not used
Not used
01
7:6
• Sets the related fault bit in the status
registers. Fault bits are only cleared by the
CLEAR_FAULTS command.
10
Disable without delay and retry according to the setting in Bits 5:3.
Not used
11
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by
the CONTROL pin or OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down.
111
111
Not used. Retry time is 70ms.
IOUT_AVG_OC_FAULT_LIMIT (E7h)
Definition: Sets the I
average overcurrent fault threshold for each phase (Phase 0 and Phase 1). For downslope sensing, this
OUT
corresponds to the average of all the current samples taken during the (1-D) time interval, excluding the current sense blanking time
(which occurs at the beginning of the 1-D interval). For upslope sensing, this corresponds to the average of all the current samples
taken during the D time interval, excluding the current sense blanking time (which occurs at the beginning of the D interval). This
feature shares the OC fault bit operation (in STATUS_IOUT) and OC fault response with IOUT_ OC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: DA80h (20A)
Units: Amperes
Equation: IOUT_AVG_OC_FAULT_LIMIT = Y x 2N
Range: -100 to 100A
COMMAND
Format
IOUT_AVG_OC_FAULT_LIMIT (E7h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
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ZL8801
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Definition: Sets the I
OUT
average undercurrent fault threshold for each phase (Phase 0 and Phase 1). For downslope sensing, this
corresponds to the average of all the current samples taken during the (1-D) time interval, excluding the current sense blanking time
(which occurs at the beginning of the 1-D interval). For upslope sensing, this corresponds to the average of all the current samples
taken during the D time interval, excluding the current sense blanking time (which occurs at the beginning of the D interval). This
feature shares the UC fault bit operation (in STATUS_IOUT) and UC fault response with IOUT_ UC_FAULT_LIMIT.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D580h (-10A)
Units: Amperes
Equation: IOUT_AVG_UC_FAULT_LIMIT = Y x 2N
Range: -100 to 100A
COMMAND
Format
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
MFR_USER_CONFIG (E9h)
Definition: This command is used to set options for output voltage sensing, maximum output voltage override, SMBus time out and
DDC and SYNC output configurations.
Data Length in Bytes: 2
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: N/A
COMMAND
Format
MFR_USER_CONFIG (E9h)
Bit Field
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BITS
15:7
PURPOSE
VALUE
000000000 Not used
DESCRIPTION
Not Used
0
1
DDC output open drain.
DDC output push-pull.
Not used
6
5
4
3
DDC output Configuration
Not Used
0
0
SMBus time outs enabled.
SMBus time outs disabled.
Not used
Disable SMBus Time-outs
Not Used
1
0
00
01
10
11
0
Use internal clock.
Use internal clock and output internal clock.
2:1
0
Sync I/O Control
Not Used
Use external clock.
Not used
Not used
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ZL8801
SNAPSHOT (EAh)
Definition: The SNAPSHOT command is a 32 Byte read-back of parametric and status values. It allows monitoring and status data to be
stored to NVRAM either during a fault condition or via a system-defined time using the SNAPSHOT_CONTROL command. Snapshot is
continuously updated in RAM and can be read using the SNAPSHOT command after a SNAPSHOT_CONTROL 03h (erase snapshot data)
has been written when the device is disabled. When a fault occurs, the latest snapshot in RAM is stored to NVRAM. Snapshot data can
read back by writing a 01h to the SNAPSHOT_CONTROL command, then reading SNAPSHOT. SNAPSHOT data will not update
automatically and SNAPSHOT data in NVRAM will not be written after a fault until a SNAPSHOT_CONTROL 03h has been written again.
Note: It is advised that this step be performed while the device’s operation is disabled.
Data Length in Bytes: 32
Data Format: BIT Field
Type: Block Read
Protectable: No
Default Value: N/A
Units: N/Al
BYTE NUMBER
31:29
28:27
26:25
24:23
22
VALUE
PMBus™ COMMAND
FORMAT
Not Used
Not Used
0000h
I
I
1
0
READ_IOUT1 (A1h)
2 Byte Linear-11
2 Byte Linear-11
2 Byte Linear-11
Bit Field
OUT
OUT
READ_IOUT0 (A2h)
External Temperature 1
NVRAM Memory Status Byte
Manufacturer Specific Status Byte
CML Status Byte
READ_TEMPERATURE_3 (8Fh)
N/A
21
STATUS_MFR_SPECIFIC (80h)
STATUS_CML (7Eh)
1 Byte Bit Field
1 Byte Bit Field
1 Byte Bit Field
1 Byte Bit Field
1 Byte Bit Field
1 Byte Bit Field
2 Byte Linear-11
2 Byte Linear-11
2 Byte Linear-11
2 Byte Linear-11
2 Byte Linear-11
2 Byte Linear-11
2 Byte Linear-16 Unsigned
2 Byte Linear-11
20
19
Temperature Status Byte
Input Status Byte
STATUS_TEMPERATURE (7Dh)
STATUS_INPUT (7Ch)
STATUS_IOUT (7Bh)
STATUS_VOUT (7Ah)
READ_FREQUENCY (95h)
READ_TEMPERATURE_2 (8Eh)
READ_TEMPERATURE_1 (8Dh)
READ_DUTY_CYCLE (94h)
N/A
18
17
I
Status Byte
Status Byte
OUT
16
V
OUT
15:14
13:12
11:10
9:8
Switching Frequency
External Temperature 0
Internal Temperature
Duty Cycle
7:6
Highest Measured Output Current
Output Current
5:4
READ_IOUT (8Ch)
3:2
Output Voltage
READ_VOUT (8Bh)
1:0
Input Voltage
READ_VIN (88h)
BLANK_PARAMS (EBh)
Definition: Returns a 16 Byte string which indicates which parameter values were either retrieved by the last RESTORE operation or
have been written since that time. Reading BLANK_PARAMS immediately after a restore operation allows the user to determine which
parameters are stored in that store. A one indicates the parameter is not present in the store and has not been written since the
RESTORE operation.
Data Length in Bytes: 16
Data Format: BIT Field
Type: Block Read
Protectable: No
Default Value: FF…FFh
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ZL8801
SNAPSHOT_CONTROL (F3h)
Definition: Writing a 01h will cause the device to copy the current SNAPSHOT values from NVRAM to the 32 Byte SNAPSHOT command
parameter. Writing a 02h will cause the device to write the current SNAPSHOT values to NVRAM, 03 will erase all SNAPSHOT values
from NVRAM. All other values will be ignored. SNAPSHOT 03h must be written to the device when the device is DISABLED. Data will not
be updated, or written to NVRAM after a fault occurs until the SNAPSHOT 03h command has been written.
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W Byte
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
SNAPSHOT_CONTROL (F3h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
VALUE
DESCRIPTION
01
02
03
Read SNAPSHOT values from NVRAM
Write SNAPSHOT values to NVRAM
Erase SNAPSHOT values from NV RAM
RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard-coded factory default values and pin-strap definitions. The device retains the DEFAULT and
USER stores for restoring. Security level is changed to Level 1 following this command.
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Protectable: Yes
Default Value: N/A
Units: N/A
MFR_VMON_OV_FAULT_LIMIT (F5h)
Definition: Sets the VMON overvoltage fault threshold. A VMON parameter equals 16 times the voltage applied to the VMON pin. The
VMON overvoltage warn limit is automatically set to 90% of this fault value.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D300h (12V)
Units: V
Equation: MFR_VMON_OV_FAULT_LIMIT = Y x 2
N
Range: 0 to 19V
COMMAND
Format
MFR_VMON_OV_FAULT_LIMIT (F5h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
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ZL8801
MFR_VMON_UV_FAULT_LIMIT (F6h)
Definition: Sets the VMON undervoltage fault threshold. A VMON parameter equals 16 times the voltage applied to the VMON pin. The
VMON undervoltage warn limit is automatically set to 110% of this fault value.
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA00h (4.0V)
Units: V
Equation: MFR_VMON_UV_FAULT_LIMIT = Y x 2
N
Range: 0 to 19V
COMMAND
Format
MFR_VMON_UV_FAULT_LIMIT (F6h)
Linear-11
Bit Position
Access
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
MFR_READ_VMON (F7h)
Definition: Reads the VMON voltage.
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: V
N
Equation: MFR_READ_VMON = Y x 2
Range: 0 to 19V
COMMAND
Format
MFR_READ_VMON (F7h)
Linear-11
Bit Position
Access
15
14
13
r/w
12
11
10
9
8
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
Signed Exponent, N
N/A N/A N/A
Signed Mantissa, Y
N/A N/A N/A
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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ZL8801
MFR_VMON_OV_FAULT_RESPONSE (F8h)
Definition: Configures the VMON overvoltage fault response as defined by the following table.
Note: The delay time is the time between restart attempts
Data Length in Bytes: 1
Data Format: BIT Field
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shut down, no retries)
Units: Retry time = 70ms
COMMAND
MFR_VMON_OV_FAULT_RESPONSE (F8h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00
DESCRIPTION
Response Behavior: The Device:
• Pulls SALRT low
• Sets the related fault bit in the
status registers. Fault bits are only
cleared by the CLEAR_FAULTS
command.
Not used
Not used
01
7:6
10
Disable without delay and retry according to the setting in Bits 5:3.
Not used
11
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
Retry Setting
Not Used
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
111
111
Not used. Retry time is 70ms.
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ZL8801
MFR_VMON_UV_FAULT_RESPONSE (F9h)
Definition: Configures the VMON undervoltage fault response as defined by the following table. Note: The delay time is the time
between restart attempts.
Data Length in Bytes: 1
Data Format: BIT Field.
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shut down, no retries)
Units: Retry time = 70ms
COMMAND
MFR_VMON_UV_FAULT_RESPONSE (F9h)
Bit Field
Format
Bit Position
Access
7
6
5
4
3
2
1
0
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Function
See Following Table
Default Value
1
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
00
DESCRIPTION
Response Behavior: The Device:
• Pulls SALRT low
• Sets the related fault bit in the
status registers. Fault bits are only
cleared by the CLEAR_FAULTS
command.
Not used
Not used
01
7:6
10
Disable without delay and retry according to the setting in Bits 5:3.
Not used
11
000
No retry. The output remains disabled until the fault is cleared.
001-110 Not used
5:3
2:0
Retry Setting
Not Used
111
111
Attempts to restart continuously, without limitation, until it is commanded OFF (by the
CONTROL pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
Not used. Retry time is 70ms.
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ZL8801
SECURITY_LEVEL (FAh)
Definition: The device provides write protection for individual commands. Each bit in the UNPROTECT parameter controls whether its
corresponding command is writable (commands are always readable). If a command is not writable, a password must be entered in order to
change its parameter (i.e., to enable writes to that command). There are two types of passwords, public and private. The public password
provides a simple lock-and-key protection against accidental changes to the device. It would typically be sent to the device in the application
prior to making changes. Private passwords allow commands marked as nonwritable in the UNPROTECT parameter to be changed. Private
passwords are intended for protecting Default-installed configurations and would not typically be used in the application. Each store (USER
and DEFAULT) can have its own UNPROTECT string and private password. If a command is marked as nonwritable in the DEFAULT UNPROTECT
parameter (its corresponding bit is cleared), the private password in the DEFAULT store must be sent in order to change that command. If a
command is writable according to the Default UNPROTECT parameter, it may still be marked as nonwritable in the User Store UNPROTECT
parameter. In this case, the User private password can be sent to make the command writable.
The device supports four levels of security. Each level is designed to be used by a particular class of users, ranging from module
manufacturers to end users, as discussed in the following. Levels 0 and 1 correspond to the public password. All other levels require a private
password. Writing a private password can only raise the security level. Writing a public password will reset the level down to 0 or 1.
Figure 13 shows the algorithm used by the device to determine if a particular command write is allowed.
Write
Attempted
Always
Writeable
Y
?
N
Read
Only
?
Y
N
Security
Level == 3
?
Y
N
Default
Y
UNPROTECT
== 0
?
N
Security
Level == 2
?
Y
N
User
Y
UNPROTECT
== 0
?
N
Security
Level == 1
?
Write
Prohibited
Write
Allowed
N
Y
FIGURE 13. ALGORITHM USED TO DETERMINE WHEN A COMMAND IS WRITABLE
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Security Level 3 – Module Vendor
Level 3 is intended primarily for use by Module vendors to protect device configurations in the Default Store. Clearing a UNPROTECT bit in the
Default Store implies that a command is writable only at Level 3 and above. The device’s security level is raised to Level 3 by writing the
private password value previously stored in the Default Store. To be effective, the module vendor must clear the UNPROTECT bit corresponding
to the STORE_DEFAULT_ALL and RESTORE_DEFAULT commands. Otherwise, Level 3 protection is ineffective since the entire store could be
replaced by the user, including the enclosed private password.
Security Level 2 – User
Level 2 is intended for use by the end user of the device. Clearing a UNPROTECT bit in the User Store implies that a command is writable only
at Level 2 and above. The device’s security level is raised to Level 2 by writing the private password value previously stored in the User Store. To
be effective, the user must clear the UNPROTECT bit corresponding to the STORE_USER_ALL, RESTORE_DEFAULT_ALL, STORE_DEFAULT_ALL
and RESTORE_DEFAULT commands. Otherwise, Level 2 protection is ineffective since the entire store could be replaced, including the
enclosed private password.
Security Level 1 – Public
Level 1 is intended to protect against accidental changes to ordinary commands by providing a global write-enable. It can be used to protect
the device from erroneous bus operations. It provides access to commands whose UNPROTECT bit is set in both the Default and User Store.
Security is raised to Level 1 by writing the public password stored in the User Store using the PUBLIC_PASSWORD command. The public
password stored in the Default Store has no effect.
Security Level 0 - Unprotected
Level 0 implies that only commands which are always writable (e.g., PUBLIC_PASSWORD) are available. This represents the lowest authority
level and hence the most protected state of the device. The level can be reduced to 0 by using PUBLIC_PASSWORD to write any value, which
does not match the stored public password.
Data Length in Bytes: 1
Data Format: Hex
Type: Read Byte
Protectable: No
Default Value: 01h
Units: N/A
Reference: AN2031 - Writing Configuration Files for Intersil Digital Power Devices
COMMAND
SECURITY_LEVEL (FAh)
Bit Field
Format
Bit Position
Access
7
r
6
r
5
r
4
r
3
r
2
r
1
r
0
r
Function
See Following Table
Default Value
0
0
0
0
0
0
1
1
BIT
FIELD NAME
VALUE
DESCRIPTION
7:2
1:0
Not Used
00000 Not used
00
01
10
11
Security level 0
Security level 1
Security level 2
Security level 3
Security Level
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PRIVATE_PASSWORD (FBh)
Definition: Sets the private password string.
Data Length in Bytes: 9
Data Format: ASCII. ISO/IEC 8859-1
Type: R/W Block
Protectable: No
Default Value: 000000000000000000h
Units: N/A
Reference: AN2031 - Writing Configuration Files for Intersil Digital Power Devices
PUBLIC_PASSWORD (FCh)
Definition: Sets the public password string.
Data Length in Bytes: 4
Data Format: ASCII. ISO/IEC 8859-1
Type: R/W
Protectable: No
Default Value: 00000000h
Units: N/A
Reference: AN2031 - Writing Configuration Files for Intersil Digital Power Devices
UNPROTECT (FDh)
Definition: Sets a 256-bit (32-byte) parameter which identifies which commands are to be protected against write-access at lower security
levels. Each bit in this parameter corresponds to a command according to the command’s code. The command with a code of 01h
(OPERATION), for example, is protected by the 2nd least-significant bit of the least-significant byte, followed by the command with a code of
02h (ON_OFF_CONFIG) and so forth. Note that all possible commands have a corresponding bit regardless of whether they are protectable or
supported by the device. Clearing a command’s UNPROTECT bit indicates that write-access to that command is only allowed if the device’s
security level has been raised to an appropriate level. The UNPROTECT bits in the DEFAULT store require a security level 3 to be writable. The
UNPROTECT bits in the USER store require a security level of 2 or higher to be writable.
Data Length in Bytes: 32
Data Format: Custom
Type: R/W Block
Protectable: No
Default Value: FF…FFh
Units: N/A
Reference: AN2031 - Writing Configuration Files for Intersil Digital Power Devices
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the Intersil website to
make sure you have the latest revision.
DATE
REVISION
FN8614.3
FN8614.2
CHANGE
March 27, 2015
January 8, 2015
“Simplified Application” on page 3 removed wire connecting ISENA0, ISENB0, and VDRV.
• Pin Configuration, page 6, pin names swapped for Pins 40 and 41:
Pin 40 - XTEMP1P changed to: XTEMP1N
Pin 41 - XTEMP1N changed to: XTEMP1P
•Pin Description table, page 6, pin names swapped for Pins 40 and 41:
Pin 40 - XTEMP1P changed to: XTEMP1N
Pin 41 - XTEMP1N changed to: XTEMP1P
September 25, 2014
June 18, 2014
FN8614.1
FN8614.0
Added table “KEY DIFFERENCES BETWEEN FAMILY OF PARTS” on page 1.
On page 1: Added related literature.
Added part number ZL8801ALAFT7A and Demonstration boards to ordering information table.
Added Demo boards to ordering information table
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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Package Outline Drawing
L44.7x7B
44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 10/09
5.00 TYP
40X 0.50
7.00
A
6
B
44
PIN #1
INDEX
AREA
34
1
6
33
PIN 1
INDEX
AREA
5.20 ±0.1
EXP. DAP
23
11
44X 0.25 4
0.10 M C A B
(4X)
0.15
22
12
SIDE VIEW
TOP VIEW
5.20 ±0.1 EXP. DAP
BOTTOM VIEW
44X 0.55 ±0.1
( 6.65 )
SEE DETAIL "X"
( 5.20)
0.10C
C
1.00 MAX
0.08C
SIDE VIEW
( 6.65 )
( 5.20 )
(40X 0.50)
5
C
0.2 REF
(44X .25)
0 . 00 MIN.
0 . 05 MAX.
( 44 X 0.75)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
Complies to JEDEC MO220 VKKD-1.
7.
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