ZL8802ALAFT7A_技术文档

DATASHEET

ZL8802

FN8760

Rev.3.00

Nov 8, 2017

Dual Channel/Dual Phase PMBus ChargeMode Control DC/DC Digital Controller

The ZL8802 is a dual output or dual phase digital DC/DC

Features

controller. Each output can operate independently or be used

• Unique compensation-free design – always stable

together in a dual phase configuration for high current

applications supporting 2-, 4-, 6-, and 8-phase operation with

up to four ZL8802 controllers.

• Output voltage range: 0.54V to 5.5V

• Input voltage range: 4.5V to 14V

The ZL8802 supports a wide range of output voltages

(0.54V to 5.5V) operating from input voltages as low as 4.5V

up to 14V.

• 1% output voltage accuracy over line, load, and temperature

• ChargeMode control achieves fast transient response,

reduced output capacitance, and provides output stability

without compensation.

With the fully digital ChargeMode control, the ZL8802 will

respond to a transient load step within a single switching cycle.

This unique compensation-free modulation technique allows

designs to meet transient specifications with minimum output

capacitance, thus saving cost and board space.

• 2-channel output, 2-, 4-, 6-, or 8-phase output with two,

three, or four devices

• Switching frequency range 200kHz to 1.33MHz

• Proprietary single-wire DDC (Digital-DC) serial bus enables

voltage sequencing and fault spreading with other Intersil

digital power ICs

The proprietary single-wire Digital-DC™ (DDC) serial bus

enables the ZL8802 to communicate between other Intersil

digital power ICs. By using the DDC, the ZL8802 achieves

complex functions such as inter-IC phase current balancing,

sequencing, and fault spreading. This eliminates complicated

power supply managers with numerous external discrete

components.

• Inductor peak and averaged over and undercurrent

protection

• Digital fault protection for output voltage UV/OV, input

voltage UV/OV, temperature, and MOSFET driver voltage

The ZL8802 features fast output overcurrent protection. The

input voltage, output voltages, and DrMOS/MOSFET driver

supply voltages are overvoltage and undervoltage protected.

Two external temperature sensors and one internal

temperature sensor are available for temperature monitoring,

one of which can be configured for under- and over-

temperature protection. A snapshot parametric capture

feature allows users to take a snapshot of operating and fault

data during normal or fault conditions.

• Accurate average output current measurement with

adjustable gain settings for sensing with SPS current

monitor outputs or high current, low DCR inductors

• Monitor ADC measures input voltage, input current, output

voltage, driver voltage, internal and external temperature

• Nonvolatile memory for storing operating parameters and

fault events

• PMBus compliant

Integrated Low Dropout (LDO) regulators allow the ZL8802 to

operate from a single input supply eliminating the need for

additional linear regulators. The VDRV LDO output can be used

to power external drivers or DrMOS devices.

Applications

• Servers and storage equipment

• Telecom and datacom equipment

• Power supplies (memory, DSP, ASIC, FPGA)

With full PMBus compliance, the ZL8802 is capable of

measuring and reporting input voltage, input current, output

voltage, output current, as well as the device’s internal

temperature, two external temperatures, and an auxiliary

voltage or temperature input.

Related Literature

• For a full list of related documents, visit our website

- ZL8802 product page

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

PART NUMBER

ZL8800

DUAL OUTPUT

DUAL PHASE

DDC CURRENT SHARE

SPS SUPPORT

Yes

No

Yes

No

Yes

No

ZL8801

ZL8802

Yes

FN8760 Rev.3.00

Nov 8, 2017

Page 1 of 91

ZL8802

Table of Contents

Two-Phase Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ZL8802 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Digital-DC Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin-Strap Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Configurable Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Voltage and VOUT_MAX Selection (VSET0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Switching Frequency Setting (SYNC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Input Voltage Undervoltage Lockout Setting (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Configuration Setting (CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

ChargeMode Control (ASCR) Setting (ASCRCFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Start-Up and Shutdown Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Ton-Delay and Rise Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Enable Pin Operation and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Current Limit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Input Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

External Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Temperature Monitoring Using XTEMP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Nonvolatile Memory and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Monitoring Through SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PMBus Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PMBus Command Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MFR_SMBALERT_MASK (DBh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

FN8760 Rev.3.00

Nov 8, 2017

Page 2 of 91

ZL8802

Block Diagram

PWMH0

ASCR

DIGITAL PWM

MODULATOR

PWM+

DEAD TIME

ADC

VSEN0P/N

PGA

PWMEN0

DAC

PWMH1

ASCR

DIGITAL PWM

MODULATOR

PWM+

DEAD TIME

VSEN1P/N

PWMEN1

XTEMP1P/N

XTEMP0P/N

VMON/TMON

MONITOR

ADC

DIGITAL LOGIC

+

OV/UV/OC/UC

COMPARATORS

VDD

EN0/1

PG0/1

VTRKP/N

OSC

ISENA0

Ipeak/IAVG

CLK GEN

PLL

SYNC

DDC

ADC

ISENB0

ISENA1

Digital-DC

MICROCONTROLLER

AND

INTER-DEVICE

COMMUNICATIONS

Ipeak/IAVG

ADC

NONVOLATILE

MEMORY

ISENB1

SDA

IIN

ADC

I²C AND SMBus

SERIAL

INTERFACE

SCL

SALRT

PIN-STRAP RESISTOR

DETECTION

LDOs

VDD

GAIN

FIGURE 2. BLOCK DIAGRAM

FN8760 Rev.3.00

Nov 8, 2017

Page 4 of 91

ZL8802

Pin Configuration

ZL8802

(44 LD QFN)

TOP VIEW

(PAD)

Pin Description

#

TYPE

PIN NAME (Note 1)

DESCRIPTION

Serial clock. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V

(VR5 recommended, do not use V25) source. Pull-up supply must be from an “always on” source or VR5.

1

2

3

4

SCL

I/O

O

Serial data. Connect to external host and/or to other ZL devices. Requires a pull-up resistor to a 2.5V to 5.5V

(VR5 recommended, do not use V25) source. Pull-up supply must be from an “always on” source or VR5.

SDA

Serial alert. Connect to external host if desired. Requires a pull-up resistor to a 2.5V to 5.5V (recommend VR5, do not use

V25) source. Leave floating if not used.

SALRT

SGND

Connect to low impedance ground plane. Internal connection to SGND. All pin-strap resistors should be connected to SGND.

SGND must be connected to DGND and PGND using a single point connection.

PWR

Serial address select pin. Used to assign unique address for each individual device. See Table 3 on page 12 for PMBus

address options. Connect resistor to SGND.

5

6

SA

M

I

Smart power stage temperature monitoring or general purpose voltage monitoring pin. Requires an external 2:1 resistor

divider network to correctly read temperature. Requires an external 16:1 resistor divider network to read voltage. Connect

bottom of resistor divider network to SGND. Connect VMON/TMON pin to SGND if not used.

VMON/

TMON

Digital ground. Must connect to SGND and PGND using a single point connection.

7

8

DGND

ASCRCFG

CFG

PWR

M

Selects ChargeMode control (ASCR) configuration settings. See “Configurable Pins” on page 12 and Table 8 on page 14

for details.

Selects current sense, current limit, and operating mode. See “Configurable Pins” on page 12 and Table 8 on page 14 for

details.

9

M

Channel 0 output voltage selection pin. Used to set V

and V

max. See Table 4 on page 12 for V

pin-strap

setting, but this can be overridden through the PMBus interface with the

10

VSET0

VSET1

PG0

M

O

OUT0

OUT

options. Default V

OUT

max is 115% of V

OUT

VOUT_MAX command. Connect resistor to SGND.

Channel 1 output voltage selection pin. Used to set V

and V

OUT1

max. See Table 4 on page 12 for V pin-strap

OUT

11

12

OUT1

options. Default V

OUT

max is 115% of V setting, but this can be overridden through the PMBus interface with the

OUT

VOUT_MAX command. Connect resistor to SGND. NOT USED IN 2-PHASE MODE. Leave floating in 2-phase mode.

Channel 0 Power-Good output. Can be configured as open-drain or push-pull using the PMBus interface. Default setting is

open-drain.

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Nov 8, 2017

Page 5 of 91

ZL8802

Pin Description (Continued)

#

TYPE

PIN NAME (Note 1)

DESCRIPTION

Undervoltage lockout selection. Sets the minimum value for V voltage to enable V . See Table 6 on page 13 for UVLO

13

UVLO

M

DD

OUT

setting options. Pin-strapped (configured) values can be overridden by the PMBus interface. Connect resistor to SGND. If

enabling the device by tying the EN0 and or EN1 pins high (self-enabling), set the UVLO level to 16V with a 100k resistor

so the device will not turn on until after a configuration file has been loaded.

Single-wire DDC bus (current sharing, interdevice communication). Requires a pull-up resistor to a 2.5V to 5.5V

(recommend VR5, do not use V25) source. Pull-up voltage must be present when the device is powered. Pull-up supply

must be from an “always on” source or VR5.

14

DDC

I/O

I

External temperature sensor input for Channel 0. Connect to external 2N3904 (base emitter junction) or equivalent

embedded thermal diode. If not used connect to SGND.

15 XTEMP0P

16 XTEMP0N

External temperature sensor input for Channel 0 return. If not used connect to SGND.

I

-

Tracking sense positive input. Used to track an external voltage source. Tracking is only possible in 2-phase operation, or

with a single channel in a 2-channel configuration. Tracking is disabled in 4-, 6-, and 8-phase operation. If not used, connect

to SGND.

17

VTRKP

Tracking sense negative input (return). If not used connect to SGND.

18

19

20

21

22

VTRKN

VSEN0P

VSEN0N

VDRVEN

ISENA0

-

I

Differential output Channel 0 voltage sense feedback. Connect to positive output regulation point.

Differential output Channel 0 voltage sense feedback. Connect to negative output regulation point.

VDRV (MOSFET Driver Bias Supply) enable. Leave unconnected (float) or pull up to VR5 to enable, tie to ground to disable.

Positive differential voltage input for Channel 0 DCR current sensing. Should be routed as a pair with ISENB0. Should

connect to resistor located close to output inductor. See “SPS Current Sensing” on page 17.

Negative differential voltage input for Channel 0 DCR current sensing. Should be routed as a pair with ISENA0. Should be

connected to output inductor terminal. See “SPS Current Sensing” on page 17.

23

ISENB0

I

Used to drive DrMOS enable where applicable. Leave unconnected when not used.

PWM0 high signal.

24 PWMEN0

O

I

25

26

PWMH0

PWMH1

PWM1 high signal.

Used to drive DrMOS enable where applicable. Leave unconnected when not used.

27 PWMEN1

Negative differential voltage input for Channel 1 DCR current sensing. Should be routed as a pair with ISENA1. Should be

connected to output inductor terminal. See “SPS Current Sensing” on page 17 for details.

28

29

30

31

32

ISENB1

ISENA1

VDRV

VR6

Positive differential voltage input for Channel 1 DCR current sensing. Should be routed as a pair with ISENB1. Should

connect to resistor located close to output inductor. See “SPS Current Sensing” on page 17 for details.

I

MOSFET driver bias supply regulator output. If disabled, this pin can be left floating. Decouple with a high quality 4.7µF

X7R or better ceramic capacitor placed close to this pin.

PWR

Bypass for internal 6V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better ceramic

capacitor placed close to this pin. Keep this net as small as possible. Do not route near switching signals.

Bypass for internal 5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better ceramic

capacitor placed close to this pin.

VR5

Supply voltage. Decouple with a high quality 1µF X7R or better ceramic capacitor placed close to this pin.

Input current monitor negative input. If not used connect to VDD.

33

34

35

36

VDD

IINN

IINP

V25

PWR

I

Input current monitor positive input. If not used connect to VDD.

Internal 2.5V reference used to power internal circuitry. Decouple with a high quality 4.7µF X7R or better ceramic capacitor

placed close to this pin.

PWR

Channel 1 Power-Good output. Can be configured as open-drain or push-pull using the PMBus interface. Default setting is

open-drain.

37

38

39

PG1

O

I

Differential output Channel 1 voltage sense feedback. Connect to negative output regulation point. NOT USED IN 2-PHASE

MODE. Leave floating in 2-phase mode.

VSEN1N

VSEN1P

Differential output Channel 1 voltage sense feedback. Connect to positive output regulation point. NOT USED IN 2-PHASE

MODE. Leave floating in 2-phase mode.

I

External temperature sensor input for Channel 1 return. If not used connect to SGND.

40 XTEMP1N

41 XTEMP1P

I

External temperature sensor input for Channel/Phase 1. Connect to external 2N3904 (base emitter junction) or equivalent

embedded thermal diode. If not used connect to SGND.

FN8760 Rev.3.00

Nov 8, 2017

Page 6 of 91

ZL8802

Pin Description (Continued)

#

TYPE

PIN NAME (Note 1)

DESCRIPTION

Enable Channel 0. Active signal enables PWM0 switching. Recommended to be tied low during device configuration. Refer

to “Enable Pin Operation and Timing” on page 16 for additional information.

42

EN0

I

Enable Channel 1. Active signal enables PWM1 switching. Recommended to be tied low during device configuration. Refer

to “Enable Pin Operation and Timing” on page 16 for additional information. NOT USED IN 2-PHASE MODE. When not used,

we recommend connecting this pin to ground.

43

EN1

I

Clock synchronization input. Used to set the frequency of the internal clock, to sync to an external clock or to output internal

clock. When configured as an output this pin is push-pull and does not require a pull-up. See “Switching Frequency Setting

(SYNC)” on page 12 and Table 5 on page 12 for additional information.

44

SYNC

SGND

M/I/O

PWR

Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.

PAD

NOTE:

1. I = Input, O = Output, PWR = Power or Ground, M = Multimode pins.

Ordering Information

TAPE AND REEL

QUANTITY

(Units)

PART

NUMBER

(Notes 2, 3, 4)

TEMP. RANGE

(°C)

PACKAGE

(RoHS Compliant)

PART

MARKING

PKG.

DWG. #

ZL8802ALAFT

8802

-40 to +85

4k

250

1k

44 Ld QFN

L44.7x7B

ZL8802ALAFT7A

ZL8802ALAFTK

NOTES:

2. Refer to TB347 for details on reel specifications.

3. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), refer to the product information page for the ZL8802. For more information on MSL, refer to TB363.

ZL8802

A L A F T

Product Designator

Shipping Option

T = Tape and Reel - 4000 pcs

Contact factory for other options

Lead Finish

F = Lead-free matte tin

Firmware Revision

Alpha character

Operating Temperature Range

L = -40°C to +85°C

Package Designator

A = QFN package

FN8760 Rev.3.00

Nov 8, 2017

Page 7 of 91

ZL8802

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage: VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V

Logic I/O Voltage: DDC, EN0, EN1, PG0, PG1, SA, VDRVEN,

Thermal Resistance (Typical)

44 Ld QFN Package (Notes 6, 7) . . . . . . . .



(°C/W)

25



(°C/W)

1.5

JA

JC

SALRT, SCL, SDA, SYNC, UVLO, VMON/TMON, VSET0,

VSET1, CFG, ASCRCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Analog Input Voltages: VSEN0P, VSEN0N, VSEN1P, VSEN1N,

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493

ISENA0, ISENA1, ISENB0, ISENB1 . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

XTEMP0P, XTEMP1P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

XTEMP0N, XTEMP1N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V

IINN, IINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V

Logic Reference: V25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V

Bias Supplies: VR5, VR6, VDRV. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

PWM Logic Outputs, PWMH0, PWMH1, PWML0, PWML1 . . . .-0.3V to 6.5V

Ground Voltage Differential (VDGND-VSGND), . . . . . . . . . . . . . . .-0.3V to +0.3V

ESD Ratings

Recommended Operating Conditions

Input Supply Voltage Range, VDD . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V

Output Voltage Range, VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V

Operating Junction Temperature Range, T . . . . . . . . . . . .-40°C to +125°C

J

Ambient Temperature Range, T . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

A

5V (VR5) Supply Total Supplied Current (Note 8) . . . . . . . . . . . . . . . . . 5mA

5V LDO Supply (VDRV) (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 80mA

Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . 3000V

Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V

Charged Device Model (Tested per JESD22-C1010-D) . . . . . . . . . . 1000V

Latch-Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

5. Output current is limited by device thermal dissipation.

6.  is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.

JA

7. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

8. Total of current used by pull-ups to SDA, SCL, SALRT, DDC, EN, and PG (including push-pull configuration).

Electrical Specifications

V

= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature

DD A

range, T -40°C to +85°C

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 14) TYP (Note 14) UNIT

IC INPUT AND BIAS SUPPLY CHARACTERISTICS

IDD Supply Current

f

= 200kHz

-

26

50

80

mA

V

SW

= 1.33MHz

SW

IDD Device Disabled Current

EN = 0V, SMBus inactive, VDD = 12V, f

VDD > 6V, I < 5mA

= 1.33MHz

-

20

40

SW

VR5 Reference Output Voltage

4.5

2.25

5.5

4.5

5.0

2.5

6.1

5.25

5.5

2.75

6.6

5.5

V25 Reference Output Voltage

For reference only, VR > 3V

For reference only, VDD = 12V

V

VR6 Reference Output Voltage

V

VDRV 5V Output Voltage (Note 9)

OUTPUT CHARACTERISTICS

V

> 6.0V; 0 to 80mA

V

DD

Output Voltage Adjustment Range

Output Voltage Set-point Accuracy (Note 11)

Output Voltage Set-point Resolution (Note 10)

Output Voltage Positive Sensing Bias Current

Output Voltage Negative Sensing Bias Current

LOGIC INPUT/OUTPUT CHARACTERISTICS

Logic Input Leakage Current

V

> V

OUT

+ 1.1V

0.54

-

5.5

V

IN

Across line, load, temperature variation 0.72 < V

Set using PMBus command

< 5.50

-1

1

% V

OUT

-

-100

-

±0.025

20

-

100

-

% V

OUT

VSEN[0,1] P = 4V (negative = sinking)

VSEN[0,1] N = 0V

µA

20

µA

Logic I/O - multimode pins

-100

-

100

0.8

-

nA

V

Logic Input Low, V

IL

-

Logic Input High, V

2

-

V

IH

Logic Output Low, V

2mA sinking

0.5

-

V

OL

Logic Output High, V

2mA sourcing

2.25

V

OH

FN8760 Rev.3.00

Nov 8, 2017

Page 8 of 91

ZL8802

Electrical Specifications

V

= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature

DD A

range, T -40°C to +85°C (Continued)

A

MIN

MAX

PARAMETER

PWM OUTPUT CHARACTERISTICS

PWM Output Low

TEST CONDITIONS

(Note 14) TYP (Note 14) UNIT

2mA sinking

-

4.25

-

0.5

-

V

PWM Output High

2mA sourcing

PWM Tri-State Input Bias Current (PWMH0, 1)

V

= 2.5V

-

10

µA

µs

PWM

PWM Tri-State Transition (Always Starts from LOW) 10pF Maximum Load

OSCILLATOR AND SWITCHING CHARACTERISTICS

Switching Frequency Range

1

200

-5

-

1334

5

kHz

%

Switching Frequency Set-point Accuracy

Minimum SYNC Pulse Width

50% to 50%

150

-10

100

-

ns

Input Clock Frequency Drift Tolerance

PMBus Clock Frequency (Note 12)

Maximum allowed drift of external clock

10

400

%

kHz

POWER MANAGEMENT

SOFT START/RAMP CHARACTERISTICS

Ton-delay/Toff-Delay Range

Ton-Delay Accuracy

Set using PMBus command

0

5000

ms

µs

2-phase Ton-Delay > 4ms

-

+/-1

-

Toff-Delay Accuracy

Set to immediate off

-0/+1

Ton-Rise/Toff-Fall Duration Range

Ton-Rise/Toff-Fall Duration Accuracy

Set using PMBus command (2-phase or 2-channel only)

2-phase or 2-channel only

0.0

100

-

±250

-

MONITORING AND FAULT MANAGEMENT

INPUT VOLTAGE MONITOR AND FAULT DETECTION

VDD/VIN UVLO Threshold Range

VDD/VIN Monitor Accuracy

2.85

-

16

V

Full Scale (FS) = 14V

-

±2

-

% FS

µs

VDD/VIN Monitor Resolution

±0.15

100

VIN UV Fault Response Delay

INPUT CURRENT

Input Current Sense Differential Input Voltage

Input Current Sense Input Offset Voltage

Input Current Sense Accuracy

V

-V

IINP IINN

0

-

20

mV

µV

V

-V

IINP IINN

±100

±5

-

% of Full Scale (20mV)

-

% FS

OUTPUT VOLTAGE MONITOR AND FAULT DETECTION

VOUT Monitor Accuracy

FS = V

voltage (VOUT)

-2

-

2

-

% FS

µs

SET

VOUT Monitor Resolution

VOUT UV Fault Response Delay

FS = V

-

± 0.15

10

SET

-

OUTPUT CURRENT

OUTPUT CURRENT SENSE RESOLUTION

Low Range

±25mV Full Scale

±35mV Full Scale

±50mV Full Scale

-

37.5

56.25

75.0

-

µV

Medium Range

High Range

OUTPUT CURRENT SENSE INPUT BIAS CURRENT

VOUT Referenced

ISENA0 or ISENA1

ISENB0 or ISENB1

-100

-25

-

100

25

nA

µA

OUTPUT CURRENT SENSE MONITOR AND FAULT DETECTION

Output Current DCR Monitor Temperature

Compensation

Configurable through PMBus

0

12700 ppm/°C

FN8760 Rev.3.00

Nov 8, 2017

Page 9 of 91

ZL8802

Electrical Specifications

V

= 12V. Typical values are at T = +25°C. Boldface limits apply across the operating ambient temperature

DD A

range, T -40°C to +85°C (Continued)

A

MIN

MAX

PARAMETER

TEST CONDITIONS

(Note 14) TYP (Note 14) UNIT

TMON BIAS MONITOR AND FAULT DETECTION

TMON UVLO Threshold Range

TMON Accuracy (Note 13)

Using TMON pin with 16:1 resistor divider

Full Scale (FS) = 1.15V

2.85

-2

–

5

2

–

V

% FS

µs

TMON Resolution

Full Scale (FS) = 1.15V

–

±0.15

200

TMON UV/OV Fault Response Delay

–

TEMPERATURE SENSING

Tested at +100°C

INTERNAL TEMPERATURE SENSOR

Internal Temperature Accuracy

Internal Temperature Resolution

-5

–

1

5

–

°C

Thermal Protection Threshold

(Junction temperature)

Factory default

–

125

–

Configurable through PMBus

-40

125

EXTERNAL TEMPERATURE SENSOR: XTEMP0 AND XTEMP1

External Temperature Accuracy

External Temperature Resolution

Thermal Protection Threshold

Filter capacitance <100pF

-

–

±5

1

-

–

°C

Factory default

–

125

–

Configurable through PMBus

-40

125

NOTES:

9. Output current is limited by device thermal dissipation.

10. Percentage of Full Scale (FS) with temperature compensation applied.

11. V

OUT

measured at the termination of the VSENxP and VSENxN sense points.

12. For operation at 400kHz, see PMBus Power System Management Protocol Specification Part 1, Section 5.2.6.2 for timing parameter limits.

13. Does not include errors due to resistor divider tolerances.

14. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.

FN8760 Rev.3.00

Nov 8, 2017

Page 10 of 91

ZL8802

All power management functions can be configured using either

pin configuration techniques described in this document or

through the SMBus interface using PMBus commands.

Monitoring parameters can also be preconfigured to provide

alerts for specific conditions. The “PMBus Command Summary”

on page 22 contains a listing of all the PMBus commands

supported by the ZL8802 and a detailed description of the use of

each of these commands.

ZL8802 Overview

Digital-DC Architecture Overview

The ZL8802 is an innovative mixed-signal power conversion and

power management IC based on Intersil’s patented Digital-DC

technology that provides an integrated, high performance

step-down converter for a wide variety of power supply

applications.

Pin-Strap Pins

The ZL8802 DC/DC controller is a dual channel, dual phase

controller based on an architecture that does not require loop

compensation.

To simplify circuit design, the ZL8802 incorporates patented

pin-strap pins that allow the user to easily configure many

aspects of the device with no programming. Most power

management features can be configured using these pins. The

pin-strap pins will read the value of the resistor connected to

those pins when power is applied to the device and set certain

device configuration settings as specified by those resistor

values.

The ZL8802’s full digital loop achieves precise control of the

entire power conversion process with no software required

resulting in a very flexible device that is also very easy to use. The

ChargeMode control algorithm is implemented to respond to

output current changes within a single PWM switching cycle. This

achieves a smaller total output voltage variation with less output

capacitance than traditional PWM controllers. An extensive set of

power management functions are fully integrated and can be

configured using simple pin connections. The user configuration

can be saved in an internal Nonvolatile Memory (NVRAM).

Additionally, all functions can be configured and monitored

through the SMBus hardware interface using standard PMBus

commands, allowing ultimate flexibility. The ZL8802 is compliant

with the PMBus Power System Management Protocol

V25

LOGIC

HIGH

MULTIMODE

OPEN

LOGIC

LOW

Specification Part I and II version 1.2.

When enabled, the ZL8802 is immediately ready to regulate

power and perform power management tasks with no

programming required. Advanced configuration options and

real-time configuration changes are available through PMBus

commands if desired and continuous monitoring of multiple

operating parameters is possible with minimal interaction from a

host controller. Integrated subregulation circuitry enables single

supply operation from any supply between 4.5V and 14V with no

bias supplies needed.

PIN-STRAP

SETTINGS

RESISTOR

SETTINGS

FIGURE 3. PIN-STRAP AND RESISTOR SETTINGS

TABLE 2.

PIN TIED TO

VALUE

The ZL8802 can be configured by simply connecting its pins

according to the tables provided in the following sections.

Additionally, a comprehensive set of online tools and application

notes are available to help simplify the design process. An

evaluation board is also available to help the user become

familiar with the device. This board can be evaluated as a

standalone platform using pin configuration settings.

PowerNavigator™, a Windows based GUI, is also provided to

enable full configuration and monitoring capability through the

PMBus interface and the included USB cable.

LOW (Logic LOW)

<0.8 VDC

OPEN (N/C)

No connection

>2.0 VDC

HIGH (Logic HIGH)

Resistor to SGND

Set by resistor value

Device configuration settings are made when connecting a finite

value resistor (in a specified range) between the pin-strap pin and

SGND. Standard 1% resistor values are used, and only every

fourth E96 resistor value is used so the device can reliably

recognize the value of resistance connected to the pin while

eliminating the error associated with the resistor accuracy. Up to

31 unique selections are available using a single resistor.

Power Management Overview

The ZL8802 incorporates a wide range of configurable power

management features that are simple to implement with no

external components. Additionally, the ZL8802 includes circuit

protection features that continuously safeguard the device and

load from damage due to unexpected system faults. The ZL8802

can continuously monitor input voltage and current, output

voltage and current, internal temperature, and the temperature

of two external thermal diodes. A Power-Good output signal is

also included to enable power-on reset functionality for an

external processor.

SMBus: Almost any ZL8802 function can be configured through

the SMBus interface using standard PMBus commands.

Additionally, any value that has been configured using the

pin-strap setting method can also be reconfigured and/or verified

through SMBus. “PMBus Command Detail” on page 27 explains

the use of the PMBus commands in detail.

FN8760 Rev.3.00

Nov 8, 2017

Page 11 of 91

ZL8802

Configurable Pins

Output Voltage and VOUT_MAX Selection

(VSET0, 1)

The output voltage can be set to any voltage between 0.54V and

5.5V provided that the input voltage is higher than the desired

Numerous operating parameters can be set using the pin-strap

resistor setting method: SMBus address (pin 5, SA), output

voltage (pins 10 and 11, VSET0, 1), switching frequency (pin 44,

SYNC), input voltage undervoltage lockout (pin 13, UVLO). ASCR

gain is set by ASCRCFG (pin 8). CFG (pin 9) sets the power stage

settings such as over and undercurrent limits.

output voltage by at least 1.1V. Using the pin-strap method, V

OUT

can be set to any of the voltages shown in Table 4. V

OUT

can also

be set using a PMBus command. VOUT_MAX is also determined

by this pin-strap setting, and is 15% greater than the VSET0 and

VSET1 voltage settings by default, however, VOUT_MAX can be

changed through PMBus.

The SMBus device address is the only parameter that must be

set by a pin-strap setting pin. All other device parameters can be

set through PMBus. The device address is set using the SA pin.

TABLE 4. OUTPUT VOLTAGE SETTINGS

SMBus Device Address Selection (SA)

RVSET (kΩ)

LOW

OPEN

HIGH

10

VOUT (V)

1.00

1.20

0.90

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

RVSET (kΩ)

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

VOUT (V)

1.30

1.40

1.50

1.60

1.70

1.80

1.90

2.00

2.10

2.20

2.30

2.50

2.80

3.00

3.30

4.00

5.00

When communicating with multiple SMBus devices using the

SMBus interface, each device must have its own unique address

so the host can distinguish between the devices. The device

address can be set according to the pin-strap options listed in

Table 3. When operating in 2-channel mode, care must be taken

when using sequential PMBus addresses. Because DDC

addresses are automatically set using the PMBus address, it is

possible for a device with a PMBus address immediately after a

2-channel ZL8802 to be automatically configured with the same

DDC address as one of the ZL8802 channels, which could cause

unintended operating modes. For this reason, do not use the next

higher PMBus address when using the ZL8802 as a 2-channel

device. See PMBus command “DDC_CONFIG (D3h)” on page 65

for details. The SMBus address cannot be changed with a PMBus

command.

11

12.1

13.3

14.7

16.2

17.8

82.5

90.9

100

19.6

21.5

23.7

26.1

28.7

31.6

34.8

TABLE 3. SMBus DEVICE ADDRESS SELECTION

110

RSA

SMBus

RSA

SMBus

(kΩ)

ADDRESS

(kΩ)

ADDRESS

121

LOW

OPEN

10

40h

42h

41h

43h

44h

45h

46h

47h

48h

49h

4Ah

61h

4Ch

4Dh

4Eh

4Fh

50h

42.2

46.4

51.1

56.2

61.9

68.1

75

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

133

147

162

11

178

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

Switching Frequency Setting (SYNC)

The device’s switching frequency is set from 200kHz to 1333kHz

using the pin-strap method as shown in Table 5, or by using a

PMBus command. The ZL8802 generates the device switching

frequency by dividing an internal precision 16MHz clock by

integers from 11 to 80.500kHz (n = 32) and 1000kHz (n = 16)

are not recommended operating frequencies; use 533kHz and

1067kHz for best performance.

82.5

90.9

100

110

121

133

147

162

178

TABLE 5. SWITCHING FREQUENCY SETTINGS

RSYNC (kΩ)

LOW

FREQ (kHz)

302

RSYNC (kΩ)

23.7

FREQ (kHz)

457

OPEN

HIGH

10

400

26.1

533

485

28.7

571

200

31.6

615

11

222

34.8

727

12.1

242

38.3

800

FN8760 Rev.3.00

Nov 8, 2017

Page 12 of 91

ZL8802

TABLE 5. SWITCHING FREQUENCY SETTINGS (Continued)

TABLE 6. INPUT VOLTAGE UNDERVOLTAGE LOCKOUT SETTING

RSYNC (kΩ)

FREQ (kHz)

267

RSYNC (kΩ)

42.2

FREQ (kHz)

842

RUVLO (kΩ)

LOW

UVLO (V)

5.50

RUVLO (kΩ)

46.4

51.1

56.2

61.9

68.1

75

UVLO (V)

7.42

13.3

14.7

16.2

17.8

19.6

21.5

OPEN

HIGH

26.1

4.50

8.18

286

46.4

889

10.80

4.18

8.99

320

51.1

1067

1143

1231

1333

9.90

364

56.2

28.7

4.59

10.90

12.00

13.20

14.54

16.00

381

61.9

31.6

5.06

432

68.1

34.8

5.57

82.5

90.9

100

38.3

6.13

The ZL8802 incorporates an internal Phase-Locked Loop (PLL) to

clock the internal circuitry. The PLL can be driven by an external

clock source connected to the SYNC pin. When using the internal

oscillator, the SYNC pin can be configured as a clock source for

other Intersil digital power devices.

42.2

6.75

When an input undervoltage fault condition occurs, the user can

determine the desired response to the fault condition. The

following input undervoltage protection response options are

available:

By default, the SYNC pin is configured as an input. The device will

automatically check for a clock signal on the SYNC pin each time

EN is asserted. The ZL8802’s oscillator will then synchronize with

the rising edge of the external clock.

• Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

• Shut down and restart continuously after a delay.

The incoming clock signal must be in the range of 200kHz to

1.33MHz and must be stable when the enable pin (EN0, EN1) is

asserted. When using an external clock, the frequencies are not

limited to discrete values as when using the internal clock. The

external clock signal must not vary more than 10% from its initial

value and should have a minimum pulse width of 150ns. In the

event of a loss of the external clock signal, the output voltage

may show transient overshoot or undershoot.

Refer to “PMBus Command Detail” on page 27 for details on how

to select specific overvoltage fault response options using the

VIN_UV_FAULT_RESPONSE command.

When controlling the ZL8802 exclusively through the PMBus, a

high voltage setting for UVLO can be used to prevent the ZL8802

from being enabled until a lower voltage for UVLO is set using the

VIN_UV_FAULT_LIMIT command.

If loss of synchronization occurs, the ZL8802 will automatically

switch to its internal oscillator and switch at its programmed

frequency.

Configuration Setting (CFG)

The Configuration pin (CFG) sets several device configuration

settings allowing the device to be used in applications without the

need for loading configuration files. The settings are shown in

Table 7. When using the ZL8802 in a 4-phase application, the

master device address must be 1 higher than the slave address.

This must be done for the two devices to be recognized as part of a

current sharing group. See PMBus command “DDC_CONFIG

(D3h)” on page 65 for details.

When used in a multiphase (4-, 6-, and 8-phase) application, the

SYNC pin of one of the devices must be configured as an output.

The device will run from its internal oscillator and will drive the

SYNC pin so other devices can be synchronized to it. The SYNC

pin will not be checked for an incoming clock signal while in this

mode.

The switching frequency can be set to any value between 200kHz

and 1.33MHz using a PMBus command. The available

TABLE 7. CONFIGURATION SETTINGS

frequencies below 1.33MHz are defined by f

= 16MHz/N,

Page 0

Page 1

SW

where 12 ≤ N ≤ 80.

RCFG AVERAGE OC PEAK OC AVERAGE OC PEAK OC

(kΩ)

10

LIMIT (A)

25

LIMIT (A)

28

LIMIT (A)

25

LIMIT (A)

28

CIRCUIT

2 Output

If a value other than f

SW

= 16MHz/N is entered using a PMBus

command, the internal circuitry will select the switching

frequency value using N as a whole number to achieve a value

close to the entered value. For example, if 810kHz is entered, the

device will select 800kHz (N = 20).

11

35

37.5

48

35

37.5

48

2 Output

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

45

55

60

55

60

Input Voltage Undervoltage Lockout Setting

(UVLO)

The input Undervoltage Lockout (UVLO) prevents the ZL8802 from

operating when the input falls below a preset threshold, indicating

the input supply is out of its specified range. The input voltage

undervoltage lockout threshold can be set between 4.18V and 16V

using the pin-strap method as shown in Table 6. UVLO can also be

set or changed using the VIN_UV_FAULT_LIMIT command.

60

65

60

65

70

65

70

35

37.5

48

25

28

45

25

28

55

60

25

28

45

48

35

37.5

FN8760 Rev.3.00

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Page 13 of 91

ZL8802

TABLE 7. CONFIGURATION SETTINGS (Continued)

Page 0 Page 1

RCFG AVERAGE OC PEAK OC AVERAGE OC PEAK OC

TABLE 8. ChargeMode CONTROL (ASCR) SETTINGS (Continued)

ASCRCFG

kΩ)

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

GAIN P0 GAIN P1

(kΩ)

GAIN P0 GAIN P1

(kΩ)

26.1

28.7

31.6

34.8

38.3

42.2

46.4

51.1

56.2

61.9

68.1

75

LIMIT (A)

55

25

35

45

25

35

45

55

65

35

45

55

65

20

35

LIMIT (A)

35

45

35

45

55

45

55

25

35

45

55

65

35

45

55

65

20

35

LIMIT (A)

37.5

48

CIRCUIT

400

600

800

200

400

600

800

1000

200

400

600

800

1000

200

400

82.5

90.9

100

110

121

133

147

1000

100

600

800

1000

100

300

500

700

900

1100

300

500

700

60

2 Output

60

2 Output

28

37.5

48

2 Output

28

2 Output

300

28

60

2 Output

500

37.5

48

2 Output

700

60

2 Output

162

178

900

60

2 Output

1100

300

28

2-Phase

LOW

OPEN

HIGH

37.5

48

37.5

48

2-Phase

500

2-Phase

700

60

2-Phase

Start-Up and Shutdown Settings

The device’s start-up and shutdown settings can be set by using

the following PMBus Commands:

82.5

90.9

100

110

121

133

147

70

2-Phase

37.5

48

37.5

48

4-PH Master

4-PH Slave

4-PH Master

4-PH Slave

4-PH Master

4-PH Slave

4-PH Master

4-PH Slave

TON_DELAY: Sets the time from a low to high EN0 or EN1

transition, or the receipt of an OPERATION command through

PMBus, to the start of an output voltage ramp.

48

TON_RISE: Sets the time from the end of the TON_DELAY to the

output voltage reaching regulation.

60

TOFF_DELAY: Sets the time from a high to low EN0 or EN1

transition, or the receipt of an OPERATION command through

PMBus, to the start of an output voltage ramp down.

162

70

178

70

TOFF_FALL: Sets the time from the end of the TOFF_DELAY to the

output voltage reaching 0V.

LOW

OPEN

HIGH

22.5

37.5

22.5 2-Phase

22.5 2 Output

Note that in the case of 2-channel operation, these settings will

apply to both channels. Each channel can be configured to have

different settings by using the TON_DELAY, TON_RISE,

TOFF_DELAY, and TOFF_FALL PMBus commands.

37.5

2 Output

ChargeMode Control (ASCR) Setting

(ASCRCFG)

The device’s ChargeMode response can be optimized by

adjusting the ASCR gain and residual settings, either by using the

ASCRCFG pin-strap resistor method as shown in Table 8, or by

using the ASCR_CONFIG PMBus command. When using Table 8,

the ASCR Residual is fixed at 90.

Internal Bias Regulators and Input Supply

Connections

The ZL8802 employs internal Low Dropout (LDO) regulators to

supply bias voltages for internal circuitry, allowing it to operate

from a single input supply. The internal bias regulators are as

follows:

TABLE 8. ChargeMode CONTROL (ASCR) SETTINGS

VR6: The VR6 LDO provides a regulated 6.1V bias supply for

internal circuitry. It is powered from the VDD pin. A 4.7µF

ceramic X7R filter capacitor to SGND is required at the VR6 pin.

Keep this net as small as possible and avoid routing this trace

near any switching signals.

ASCRCFG

(kΩ)

kΩ)

GAIN P0 GAIN P1

10

200

400

600

800

1000

51.1

56.2

61.9

68.1

75

800

600

800

1000

200

400

11

VR5: The VR5 LDO provides a regulated 5.1V bias supply for

internal circuitry. It is powered from the VDD pin. A 4.7µF

ceramic X7R filter capacitor to SGND is required at the VR5 pin.

This supply can be used for to provide a pull-up supply as long as

load current does not exceed 5mA.

12.1

13.3

14.7

800

1000

FN8760 Rev.3.00

Nov 8, 2017

Page 14 of 91

ZL8802

V25: The V25 LDO provides a regulated 2.5V bias supply for the

main controller circuitry. It is powered from an internal 5V node.

A 4.7µF ceramic X7R filter capacitor to SGND is required at the

V25 pin. This voltage should only be used to set pin-strap pins to

the HIGH state.

After the Ton-delay period has expired, the output will begin to

ramp towards its target voltage according to the preconfigured

Ton-rise time.

Internal Memory Check

50ms – 70ms

Input Power Applied

Device will ignore an

enable signal or PMBus

commands

VDRV: The VDRV LDO provides a regulated 5.25V bias supply for

external MOSFET driver ICs or DrMOS integrated drivers/FETs. A

4.7µF ceramic X7R filter capacitor to PGND is required, however,

additional capacitance will be needed as specified by the

MOSFET driver or DrMOS device selected. The maximum rated

output current is 80mA, but device thermal limits must be

considered. The power dissipated by the VDRV supply will be

(VIN-5.25V) X IDRV, where IDRV is the current supplied by the

VDRV bias supply. VDRV is enabled by leaving the VDRVEN

unconnected (floating) or connecting it to VR5, and is disabled by

connecting VDRVEN to ground.

Pre-ramp delay

minimum 2ms

delay between enable

signal and start of output

ramp. Additional delay may

be added with PMBus

command

Device Ready

NOTE: The internal bias regulators, VR6, VR5, and V25, are not

designed to be outputs for powering other circuitry. The

FIGURE 5. ZL8802 INTERNAL START-UP PROCEDURE

multimode pins can be connected to the V25 pin for logic HIGH

settings, and the VR5 supply can be used to provide up to 5mA of

pull-up current for the SDA, SCL, SALRT, DDC, and PG pins.

V

should be above the ZL8802’s UVLO limit

IN

(VIN_UV_FAULT_LIMIT) before the Enable pin is driven high.

Following this sequence will result in the most consistent turn-on

delays. If a configuration file is needed to ensure proper circuit

Operation with 5V VDD: When operating the ZL8802 at voltages

below 5.5V, the VR6 and VR5 supplies should be connected

directly to VDD for best performance. The VDRV supply should

not be used; the 5V VDD supply should be used instead for

powering DrMOS and MOSFET driver ICs.

operation, when V is first applied to the ZL8802, for example,

IN

during initial PCB turn-on and test, the Enable pin must be held

low by some means until the ZL8802 configuration file can be

loaded. If the Enable pin is not held low, then the ZL8802 may

attempt to turn on with incorrect configuration settings, possibly

causing circuit failure.

V

IN

V

IN

VDD

VR6

VDD

VR6

In those cases in which a configuration file is needed to ensure

proper circuit operation and the Enable pin cannot be held low

during the initial application of power, two options are available:

• Limit V to 3.0V during initial testing. The ZL8802

IN

configuration file can be loaded when V is as low as 3.0V.

IN

When the configuration file is loaded V can be increased to

IN

the normal input voltage range.

VR5

• Use a 100kΩ pin-strap resistor to set UVLO to 16V. This will

keep the ZL8802 disabled while the configuration file is

loaded. Ensure that the VIN_UV_FAULT_LIMIT command is the

last command in the configuration file.

4.5V < V_IN< 5.5V

5.5V < V_IN< 14V

Ton-Delay and Rise Times

FIGURE 4. VR SUPPLY CONNECTIONS

Ton- and Toff-delay and Ramp times are initially set to 5ms. In

some applications, it may be necessary to set a delay from when

an enable signal is received until the output voltage starts to

ramp to its target value. In addition, the designer may wish to

Start-Up Procedure

The ZL8802 follows a specific internal start-up procedure after

power is applied to the VDD pin, as shown in Figure 5.

precisely set the time required for V

to ramp to its target

OUT

The device requires approximately 60ms to check for specific

values stored in its internal memory. If the user has stored values

in memory, those values will be loaded.

value after the delay period has expired. These features can be

used as part of an overall inrush current management strategy or

to precisely control how fast a load IC is turned on. The ZL8802

gives the system designer several options for precisely and

independently controlling both the delay and ramp time periods.

When this process is completed, the device is ready to accept

commands through the serial interface and the device is ready to

be enabled. If the device is to be synchronized to an external

clock source, the clock frequency must be stable before

asserting the EN pin. When enabled, the device requires

approximately 2ms before its output voltage will be allowed to

start its ramp-up process.

The Ton-delay time begins when the EN pin is asserted. The

Ton-delay time is set using the PMBus command TON_DELAY.

The Ton-rise time enables a precisely controlled ramp to the

nominal V

value that begins when the Ton-delay time has

OUT

FN8760 Rev.3.00

Nov 8, 2017

Page 15 of 91

ZL8802

expired. The ramp-up is monotonic and its slope can be precisely

set using the PMBus command TON_RISE.

EN low and EN high times shorter than these minimums may

result in the device not responding to the trailing edge of the

pulse. For example, a EN low pulse below the EN low minimum

pulse width may stay in the OFF state until a valid EN low pulse is

applied to the EN pin.

The Ton-delay and Ton-ramp times can be set using PMBus

commands TON_DELAY and TON_RISE over the serial bus

interface. When the Ton-delay time is set to 0ms, the device will

begin its ramp after the internal circuitry has initialized

When operating the IC in 2 channel mode, avoid transitioning

EN0 or EN1 high within 1ms of the beginning of the opposite

channel’s start-up ramp. For example, if the Page 0 output

(VSEN0, PWM) begins to ramp up at the end of the TON_DELAY of

5ms, EN1 should not transition high between 4ms and 6ms.

The Ton-delay and Ton-ramp times can be set using PMBus

commands TON_DELAY and TON_RISE over the serial bus

interface. When the Ton-delay time is set to 0ms, the device will

begin its ramp after the internal circuitry has initialized which takes

approximately 2ms to complete. The Ton-rise time can be set to

values less than 2ms; however, the Ton-rise time should be set to a

value greater than 500µs to prevent inadvertent fault conditions

due to excessive inrush current. A lower Ton-rise time limit can be

Power-Good

The ZL8802 provides a Power-Good (PG0, PG1) signal for each

channel that indicates the output voltage is within a specified

tolerance of its target level and no fault condition exists. By

default, the PG pin will assert if the output is within 10% of the

target voltage. These limits and the polarity of the pin can be

changed using PMBus commands.

estimated using the formula: Ton-rise = C *V /I

where

is the output voltage,

is the current limit setting for the ZL8802.

OUT OUT LIMIT

is the total output capacitance, V

OUT

C

OUT

and I

LIMIT

When using interdevice current sharing (4 phases), the output

voltage rise time varies by application. The rise time can be

adjusted using the PMBus command

MULTI_PHASE_RAMP_GAIN. Higher gain values produce faster

turn-on ramps. Typical MULTI_PHASE_RAMP_GAIN values range

between 1 and 10; the default value is 3. The slew rate of the

output voltage during ramp-up is directly proportional to this

A PG delay period is defined as the time from when all conditions

within the ZL8802 for asserting PG are met to when the PG pin is

actually asserted. This feature is commonly used instead of using

an external reset controller to control external digital logic. By

default, the ZL8802 PG delay is set equal to 1ms. The PG delay

can be set using a PMBus command as described in

“POWER_GOOD_DELAY (D4h)” on page 66.

gain, as well as the input voltage (V ) and the device switching

IN

frequency (FREQUENCY_SWITCH). Use the following formula to

calculate the slew rate of the output voltage during turn-on:

Power Management Functional

Description

Slew Rate (mV/ms) = 14*(VIN)*(MULTI_PHASE_RAMP_GAIN) *

(FREQUENCY_SWITCH in MHz)

Output Overvoltage Protection

The resulting total rise time can then be calculated:

Rise Time = Output Voltage/Slew Rate

The ZL8802 offers an internal output overvoltage protection

circuit that can be used to protect sensitive load circuitry from

being subjected to a voltage higher than its prescribed limits. A

hardware comparator is used to compare the actual output

voltage (seen at the VSEN pin) to a programmable threshold set

to 10% higher than the target output voltage (the default setting).

If the VSEN voltage exceeds this threshold, the PG pin will

deassert and the device can then respond in the following ways:

Enable Pin Operation and Timing

The enable pins (EN0 and EN1) are used to enable and disable

each channel of the ZL8802. When operated as a 2-phase

converter, use EN0 and ground EN1. The enable pins should be

held low whenever a configuration file or script is used to

configure the ZL8802, or a PMBus command is sent that could

potentially damage the application circuit. When the ZL8802 is

used in a self-enabled mode, for example, when EN0 or EN1 is

tied to VR5, or to a resistor divider to VIN, the user must consider

the ZL8802's default factory settings. When a configuration file

is used to configure the ZL8802, the factory default settings are

restored to both the user and default stores to set the ZL8802 to

an initialized state. Because the default state of the ZL8802 is to

be enabled when the enable pin is high, it is possible for the

ZL8802 to be enabled while the PMBus commands are sent to

the ZL8802 during the configuration process.

• Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

• Shut down, and when the fault is no longer present, attempt to

restart.

Refer to “VOUT_OV_FAULT_RESPONSE (41h)” on page 37 for

details on how to select specific overvoltage fault response

options using the VOUT_OV_FAULT_RESPONSE command.

Output Prebias Protection

The ZL8802 provides prebiased start-up operation in 2-channel

and single device 2-phase operation. Prebias protection is not

provided when operating in current sharing 4-, 6- or 8-phase

configurations. An output prebias condition exists when an

externally applied voltage is present on a power supply's output

before the power supply's control IC is enabled. Certain

applications require that the converter not be allowed to sink

current during start up if a prebias condition exists at the output.

The ZL8802 provides prebias protection by sampling the output

voltage before initiating an output ramp.

The Enable pin is edge triggered to achieve fast turn-off times. As

a result, minimum Enable high and Enable low pulse widths must

be observed to ensure correct operation. The minimum high and

low pulse widths are dependent on the configured rise, fall, and

delay times and can be calculated using Equations 1 and 2:

(EQ. 1)

EN low  TOFF_DELAY + TOFF_FALL + 10.5ms

EN high  TON_DELAY + TON_RISE +

POWER_GOOD_DELAY + 5.5ms

(EQ. 2)

FN8760 Rev.3.00

Nov 8, 2017

Page 16 of 91

ZL8802

If a prebias voltage lower than the desired output voltage is

present after the Ton-delay time the ZL8802 starts switching

with a duty cycle that matches the prebias voltage. This ensures

that the ramp-up from the prebias voltage is monotonic. The

output voltage is then ramped to the desired output voltage at

the ramp rate set by the TON_RISE command.

Refer to the “PMBus Command Detail” on page 27 for details on

how to select specific overvoltage fault response options using

the IOUT_OC_FAULT_RESPONSE command.

SPS CURRENT SENSING

By default, the ZL8802 senses current by utilizing the IMON

output from the ISL9922X Smart Power Stage (SPS). A 6:1

resistor divider is needed between the SPS IMON output and the

ISENA and ISENB inputs of the ZL8802, as shown in Figure 7.

The resulting output voltage rise time will vary depending on the

prebias voltage, but the total time elapsed from the end of the

Ton-delay time to when the Ton-rise time is complete and the

output is at the desired value will match the preconfigured ramp

time (see Figure 6).

Using an ISL9922x device will provide the best current sense

accuracy with no action needed from the user.

V

IN

V_OUT

DESIRED OUTPUT

VOLTAGE

VIN

VDRV

ZL8802

PREBIAS

VOLTAGE

VDD VIN

PWM

V

OUT

PWMH

SW

SPS

6 * R

ISENA

IMON

TIME

Ton

DELAY

RISE

ISL99227B

REFIN

R

V_PREBIAS< V_TARGET

ISENB

V_OUT

PREBIAS

FIGURE 7. SPS CURRENT SENSING

VOLTAGE

DESIRED OUTPUT

VOLTAGE

DRMOS CURRENT SENSING

If a DrMOS device must be used, the ZL8802 can also use the

inductor DCR current sensing technique. Current sensing is

achieved with an R/C network as shown in Figure 8.

TIME

V

IN

Ton

DELAY

Ton

RISE

VIN

ZL8802

V_PREBIAS> V_TARGET

L

FIGURE 6. OUTPUT RESPONSES TO PREBIAS VOLTAGES

V

OUT

DRMOS

PWMH

If a prebias voltage higher than the target voltage exists after the

preconfigured Ton-delay time and Ton-rise time have completed,

the ZL8802 starts switching with a duty cycle that matches the

prebias voltage. This ensures that the ramp-down from the

prebias voltage is monotonic. The output voltage is then ramped

down to the desired output voltage

R₁

ISENA

ISENB

C₁

If a prebias voltage higher than the overvoltage limit exists, the

device will not initiate a turn-on sequence and will stay off.

FIGURE 8. DCR CURRENT SENSING

For the voltage across C to reflect the voltage across the DCR of

1

Output Overcurrent Protection

the inductor, the time constant of the inductor must match the

time constant of the RC network.

_RC_{L / DCR}

The ZL8802 can protect the power supply from damage from an

overloaded or shorted output. When the current limit threshold

has been selected (see “Current Limit Configuration” on

page 18), the user can determine the desired response to the

fault condition. The following overcurrent protection response

options are available:

(EQ. 3)

L

R1 C1

DCR

This capacitor, shown as C in Figure 8, should be an X7R or better

1

dielectric, and C should be placed as close to the ZL8802 as

possible for the best noise performance. The L and DCR values

should be set using the INDUCTOR and IOUT(0/1)_CAL_GAIN

• Shut down and stay off until the device has been disabled and

reenabled.

1

• Shut down and restart continuously after a delay.

FN8760 Rev.3.00

Nov 8, 2017

Page 17 of 91

ZL8802

commands. For L, use the average of the nominal value and the

minimum value. Include the effects of tolerance, DC bias, and

switching frequency on the inductance when determining the

minimum value of L. Use the typical room temperature value for DCR.

current sense resistor value does not exceed the maximum

current sensing input voltage of 20mV.

If this feature is not used, IINN and IINP should be tied to VDD.

Thermal Overload Protection

Current Limit Configuration

The ZL8802 includes an on-chip thermal sensor that continuously

measures the internal temperature of the die. This thermal sensor

is used to provide both over-temperature and under-temperature

protection. If the over-temperature limit is exceeded, or the

temperature falls below the under-temperature limit, the ZL8802

is shut down. The over-temperature and under-temperature limits

are set by the OT_FAULT_LIMIT and UT_FAULT_LIMIT respectively.

The ZL8802 will not attempt to restart until the temperature has

fallen below the OT_WARN_LIMIT for over-temperature faults or

has risen above the UT_WARN_LIMIT for under-temperature faults.

The default temperature limits are +125°C and -45°C, but the

user can set the limits to different values if desired. Note that

setting a higher over-temperature or under-temperature limit may

result in permanent damage to the device. When the device has

been disabled due to an internal temperature fault, the user can

select one of several fault response options as follows:

The ZL8802 gives the power supply designer several choices for

the fault response during overcurrent or undercurrent conditions.

The user can select the number of violations allowed before

declaring fault, a blanking time, and the action taken when a

fault is detected. These parameters can be configured using the

ISENSE_CONFIG command.

The blanking time represents the time when no current

measurement is taken. This is to avoid taking a reading just after

a current load step (less accurate due to potential ringing). It is a

configurable parameter from 0 to 832ns.

ZL8802 provides an adjustable maximum full scale sensing

range. Three ranges are available: ±25mV, ±35mV, and ±50mV

maximum input voltage.

By default, current sensing is enabled during the inductor current

down-slope period of the switching period (D’). In applications

where the steady state duty cycle is >0.5, for example, a 5V to

3.3V converter, the ZL8802 can be configured to sense current

during the inductor up-slope period of the switching cycle (D).

• Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

• Shut down and restart continuously after a delay.

Refer to “PMBus Command Detail” on page 27 for details on how

to select specific overvoltage fault response options using the

OT_FAULT_RESPONSE and UT_FAULT_ RESPONSE commands.

The user has the option of selecting how many consecutive

overcurrent readings must occur before an overcurrent fault and

subsequent shutdown are initiated. Either 1, 3, 5, 7, 9, 11, or 13

consecutive faults can be selected.

Voltage Tracking

The current limit thresholds are set with four commands:

Numerous high performance systems place stringent demands

on the order in which the power supply voltages are turned on.

This is particularly true when powering FPGAs, ASICs, and other

advanced processor devices that require multiple supply voltages

to power a single die. In most cases, the I/O interface operates at

a higher voltage than the core and therefore the core supply

voltage must not exceed the I/O supply voltage according to

manufacturer specifications.

1. IOUT_OC_FAULT_LIMIT – This sets the overcurrent threshold

that must be exceeded by the number of consecutive times

chosen in ISENSE_CONFIG.

2. IOUT_UC_FAULT_LIMIT – This is the same as

IOUT_OC_FAULT_LIMIT, but represents the negative current

that flows lower FET during the D’ interval. Large negative

currents can flow during faults such as a higher voltage rail

being shorted to a lower voltage rail.

The ZL8802 integrates a tracking scheme that allows one of its

outputs (Channel 0 or Channel 1), or the single output in a dual

phase application, to track a voltage that is applied to the VTRK

pin with no external components required. The VTRK pin is an

analog input that, when tracking mode is enabled, configures the

voltage applied to the VTRK pin to act as a reference for the

device’s output regulation.

3. IOUT_AVG_OC_FAULT_LIMIT – This limit is similar to

IOUT_OC_FAULT_LIMIT, but the limit represents an average

reading over several switching cycles. Because it is an

average, the response time is slower, but the limit can be set

closer to the maximum average expected output current.

4. IOUT_AVG_UC_FAULT_LIMIT – This limit is similar to

IOUT_AVG_OC_FAULT_LIMIT, but represents the negative

current that flows lower FET during the D’ interval.

Coincident. This mode configures the ZL8802 to ramp its output

voltage at the same rate as the voltage applied to the VTRK pin

until it reaches its desired output voltage. The device that is

tracking another output voltage (slave) must be set to its desired

steady state output voltage, that is, the VOUT_COMMAND is set

to the final output voltage.

Input Current Monitor

The input current can be monitored through the IINN and IINP

pins. The input current monitor input should be connected across

a current sensing resistor in series with the input supply. The IINP

pin is connected to the input supply side of the current sense

resistor and the IINN pin is connected to the ZL8802 VDD side of

the current sense resistor. Using the IIN_SCALE command, set

the current sense resistor value. Select the current sense resistor

value such that the maximum expected input current times the

Ratiometric. This mode configures the ZL8802 to ramp its output

voltage at a rate that is a percentage of the voltage applied to the

VTRK pin. The default setting is 50%, but an external resistor

string can be used to configure a different tracking ratio. The

device that is tracking another output voltage (slave) must be set

to its desired steady-state output voltage, that is, the

VOUT_COMMAND is set to the final output voltage.

FN8760 Rev.3.00

Nov 8, 2017

Page 18 of 91

ZL8802

The master ZL8802 device in a tracking group is defined as the

device that has the highest target output voltage within the

group. This master device will control the ramp rate of all

tracking devices and is not configured for tracking mode. The

maximum tracking rise time is 1V/ms. The slave device must be

enabled before the master.

SMBus Communications

The ZL8802 provides a SMBus digital interface. The ZL8802 can

be used with any standard 2-wire SMBus host device. In addition,

the device is compatible with SMBus version 2.0 and includes an

SALRT line to help mitigate bandwidth limitations related to

continuous fault monitoring. Pull-up resistors are required on the

SMBus. The pull-up resistor can be tied to VR5 or to an external

3.3V or 5V supply as long as this voltage is present before or

during device power-up. The ideal design will use a central pull-up

resistor that is well-matched to the total load capacitance. The

minimum pull-up resistance should be limited to a value that

enables any device to assert the bus to a voltage that will ensure

a logic 0 (typically 0.8V at the device monitoring point) given the

pull-up voltage (5V if tied to VR5) and the pull-down current

capability of the ZL8802 (nominally 4mA). A pull-up resistor of

10kΩ is a good value for most applications.

Any device that is configured for tracking mode will ignore its

Ton-delay and Ton-rise settings and its output will take on the

turn-on/turn-off characteristics of the reference voltage present

at the VTRK pin.

Tracking mode can be configured by using the TRACK_CONFIG

command.

Note that current sharing groups that are also configured to track

another voltage do not offer prebias protection; a minimum load

should therefore be enforced to avoid the output voltage from

being held up by an outside force.

SMBus data and clock lines should be routed with a closely

coupled return or ground plane to minimize coupled interference

(noise). Excessive noise on the data and clock lines that cause

the voltage on these lines to cross the high and low logic

thresholds of 2.0V and 0.8V respectively will cause command

transmissions to be interrupted and result in slow bus operation

or missed commands. A 10kΩ resistor on each line provides

good performance on an SMBus with fewer than 10 devices.

V_OUT

Vo1

Vo2

The ZL8802 accepts most standard PMBus commands. When

enabling the device with ON_OFF_CONFIG command, it is

recommended that the enable pin is tied to SGND.

TIME

COINCIDENT

V_OUT

In addition to bus noise considerations, it is important to ensure

that user connections to the SMBus are compliant to the PMBus

command standards. Any device that can malfunction in a way

that permanently shorts SMBus lines will disable PMBus

communications. Incomplete PMBus commands can also cause

the ZL8802 to halt PMBus communications. This can be

corrected by disabling, then reenabling the device.

Vo1

Vo2

TIME

Digital-DC Bus

RATIOMETRIC

The Digital-DC Communications (DDC) bus is used to

FIGURE 9. TRACKING MODES

communicate between Intersil Digital-DC devices, and within the

ZL8802 itself. This dedicated bus provides the communication

channel between devices for features such as sequencing, fault

spreading and current sharing. The DDC pin must be pulled-up to

an external 2.5V to 5.0V supply, (or configured as a push-pull

output using the USER_GLOBAL_CONFIG command) even if the

ZL8802 is operating stand-alone. In addition, the DDC pin must

be pulled up or configured as a push-pull output before the

Enable pin is set high. Push-pull mode can only be used when the

ZL8802 is operating stand-alone. The DDC pin on all Digital-DC

devices that utilize sequencing, fault spreading or current sharing

must be connected together. The DDC pin on all Digital-DC

devices in an application should be connected together. A pull-up

resistor is required on the DDC bus to guarantee the rise time as

follows:

External Voltage Monitoring

The voltage monitoring (TMON) pin is available to monitor the

voltage supply for the external driver IC. The TMON input must be

scaled by a 16:1 ratio to read-back the TMON voltage correctly. A

100kΩ and 6.65kΩ resistor divider is recommended. Overvoltage

and undervoltage fault thresholds can be set using

MFR_TMON_OV_FAULT_LIMIT and MFR_ TMON_UV_FAULT_LIMIT

commands. The response to these limits are set using the

TMON_OV_FAULT_RESPONSE and TMON_ UV_FAULT_RESPONSE

commands. To ignore the TMON input, set the TMON_OV and

_UV_FAULT_RESPONSE to 00h.

When the device has been disabled due to TMON fault, the user

can select one of several fault response options as follows:

Riset time = R

 C

 1s

LOAD

(EQ. 4)

• Shut down and stay off until the fault has cleared and the

device has been disabled and reenabled.

PU

Where R is the DDC bus pull-up resistance and C

PU LOAD

is the

• Shut down and restart continuously after a delay.

bus loading. The pull-up resistor can be tied to VR5 or to an

external 3.3V or 5V supply as long as this voltage is present

before or during device power-up. Generally, each device

FN8760 Rev.3.00

Nov 8, 2017

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ZL8802

connected to the DDC bus presents approximately 12pF of

capacitive loading. The ideal design will use a central pull-up

resistor that is well-matched to the total load capacitance. In

power module applications, the user should consider whether to

place the pull-up resistor on the module or on the PCB of the end

application. The minimum pull-up resistance should be limited to

a value that enables any device to assert the bus to a voltage that

will ensure a logic 0 (typically 0.8V at the device monitoring

point) given the pull-up voltage (5V if tied to VR5) and the

pull-down current capability of the ZL8802 (nominally 4mA). As

with SMBus data and clock lines, the DDC data line should be

routed with a closely coupled return or ground plane to minimize

coupled interference (noise). Excessive noise on the DDC signal

can cause the voltage on this line to cross the high and low logic

thresholds of 2.0V and 0.8V respectively and will cause

off using the “soft-off”, or ramped down behavior, in the

ON_OFF_CONFIG PMBus command.

When sequencing on, the first device to ramp up, called the

“prequel”, sends a message through the DDC bus to the next

device, called the “sequel” when the prequel’s Power-Good (PG)

signal is driven high.

When sequencing off, the sequel will send a message to the

prequel to begin the prequel’s ramp down after the sequel has

completed its own ramp down.

Sequencing can also be accomplished by connecting the enable

pin of a sequel device to the Power-Good pin of a prequel device.

Sequencing is also achieved by using the TON_DELAY and

TON_RISE commands and choosing appropriate delay and rise

durations such that sequel devices start after their associated

prequel devices. The drawback to this method is that if a prequel

device fails to start properly, its sequel device will still start and

ramp on according to its delay and rise time settings.

command transmissions to be interrupted and result in slow bus

operation or missed commands. For less than 10 devices on the

DDC bus a 10kΩ resistor provides good performance.

Phase Spreading

Fault Spreading

When multiple point-of-load converters share a common DC

input supply, it is desirable to adjust the clock phase offset of

each device such that not all devices have coincident rising

edges. Setting each converter to start its switching cycle at a

different point in time can dramatically reduce input capacitance

requirements. Because the peak current drawn from the input

supply is effectively spread out over a period of time, the peak

Digital-DC devices can be configured to broadcast a fault event

over the DDC bus to the other devices in the group. When a fault

occurs and the device is configured to shut down on a fault, the

device will shut down and broadcast the fault event over the DDC

bus. The other devices on the DDC bus will shut down together if

configured to do so, and will attempt to restart in their prescribed

order if configured to do so.

current drawn at any given moment is reduced and the power

2

losses proportional to I

are reduced.

RMS

Active Current Sharing

To enable phase spreading, all converters must be synchronized

to the same switching clock. Configuring the SYNC pin is

described in “Configurable Pins” on page 12. Selecting the phase

offset for the device is accomplished by selecting a device

address according to Equation 5:

The PWM outputs of the ZL8802 are used in parallel to create a

dual phase power rail. The device outputs will share the current

equally within a few percent, assuming all external sensing

element variations and tolerances are negligible. Current sensing

element tolerances must be taken into account, or adjusted for

using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands in

any application.

Phase offset = device address  45

(EQ. 5)

The phase offset of each device can also be set to any value

between 0° and 360° in 22.5° increments using the

INTERLEAVE PMBus command.

The ZL8802 will current share between phases without utilizing

output voltage droop.

Droop resistance is used in 4-phase current sharing to add

artificial resistance in the output voltage path to control the slope

of the load line curve, calibrating out the physical parasitic

mismatches due to power train components and PCB layout.

Output Sequencing

A group of Intersil digital power devices can be configured to

power up in a predetermined sequence. This feature is especially

useful when powering advanced processors, FPGAs, and ASICs

that require one supply to reach its operating voltage before

another supply reaching its operating voltage to avoid latch-up

from occurring. Multidevice sequencing can be achieved by

configuring each device using the SEQUENCE PMBus command.

V_REFERENCE

-R

V_MEMBER

Multiple device sequencing is achieved by issuing PMBus

commands to assign the preceding device in the sequencing

chain as well as the device that will follow in the sequencing

chain.

-R

The enable (EN) pins of all devices in a sequencing group must be

tied together and driven high to initiate a sequenced turn-on of

the group. Enable must be driven low to initiate a sequenced

turn-off of the group. To achieve sequenced turn-off of a group of

sequenced devices, all the devices should be configured to turn

I_MEMBER

I_OUT

I_REFERENCE

FIGURE 10. ACTIVE CURRENT SHARING

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Nov 8, 2017

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ZL8802

When current sharing up to 2 ZL8802s (4 phases total), the

ZL8802 uses a low-bandwidth, first-order digital current sharing

technique to balance the unequal device output loading by

aligning the load lines of member devices to a reference device.

Nonvolatile Memory and Security Features

The ZL8802 has internal nonvolatile memory where user

configurations are stored. Integrated security measures ensure

that the user can only restore the device to a level that has been

made available to them. During the initialization process, the

ZL8802 checks for stored values contained in its internal

nonvolatile memory. The ZL8802 offers two internal memory

storage units that are accessible by the user as follows:

Upon system start-up, the lowest numbered phase is defined as

the reference phase and all other phases are member phases.

The reference phase broadcasts its current over the DDC bus. The

member phases use the reference current information to trim

their reference voltages (V

loading of each device in the system.

) to balance the current

MEMBER

User Store: The user store is the most commonly used store. It

provides the ability to modify certain power supply settings while

still protecting the equipment from modifying values that can

lead to a system level fault. The equipment manufacturer would

use the user store to achieve this goal.

Figure 10 on page 20 shows that, for load lines with identical

slopes, the member reference voltage is increased towards the

reference voltage which closes the gap between the inductor

currents.

Default Store: The default store is less commonly used. It

provides a means to protect the circuit from damage by

preventing the user from modifying certain values that are

related to the physical construction of the circuit. In this case, the

Original Equipment Manufacturer (OEM) would use the default

store in a protected mode and allow the user to restore the

device to its default settings. In this case the user store would be

available to the end-user for making changes, but would restrict

the user from restoring the device to the factory settings or

modifying the default store.

The relation between reference and member current and voltage

is given by the following Equation 6:

V_MEMBERV_OUT R



I_REFERENCE I_MEMBER



(EQ. 6)

Where R is the value of the droop resistance. The VOUT_DROOP

command is used to set the device output voltage droop to

achieve 4-, 6- or 8-phase current sharing.

4-, 6-, and 8-phase current sharing groups must have their DDC

and SYNC pins tied together to achieve current sensing and ensure

accurate phase offsets between current sharing phases.

The user store takes priority over the Default Store. If there are

no values set in the user or default store, then the device will use

the pin-strap setting value.

Temperature Monitoring Using XTEMP Pin

For details regarding protection of the user and default stores,

see the PASSWORD PMBus command.

Each channel of the ZL8802 supports measurement of an external

device temperature using either a thermal diode integrated in a

processor, FPGA or ASIC, or using a discrete diode-connected

2N3904 NPN transistor. Figure 11 illustrates the typical

connections required. A noise filtering capacitor, not exceeding

100pF, should be connected across the external temperature

sensing device. The external temperature sensors can be used to

provide the temperature reading for over-temperature and

under-temperature faults. The external sensors can also be used

to provide more accurate temperature compensation for inductor

DCR current sensing by being placed close to the inductor. These

options for the external temperature sensors are selected using

the USER_CONFIG PMBus command.

Monitoring Through SMBus

A system controller can monitor a wide variety of different

ZL8802 parameters through the SMBus interface. The device

can monitor for fault conditions by monitoring the SALRT pin,

which will be asserted when any number of preconfigured fault

conditions occur.

The device can also be monitored continuously for any number of

power conversion parameters including, but not limited to, the

following:

• Input voltage

• Output voltage

XTEMPxP

• Input current

ZL8802

XTEMPxN

100pF

2N3904

• Output current

• Internal junction temperature

• Temperature of an external device

• Switching frequency

• Duty cycle

DISCRETE NPN

XTEMPxP

ZL8802

• Fault status information

100pF

ASIC

The PMBus Host should respond to SALRT as follows:

XTEMPxN

1. ZL device pulls SALRT low.

2. PMBus host detects that SALRT is now low, and performs

transmission with Alert Response Address to find which ZL

device is pulling SALRT low.

EMBEDDED THERMAL DIODE

FIGURE 11. EXTERNAL TEMPERATURE MONITORING

FN8760 Rev.3.00

Nov 8, 2017

Page 21 of 91

ZL8802

3. PMBus host talks to the ZL device that has pulled SALRT low.

The actions that the host performs are up to the system

designer.

Refer to “PMBus Command Detail” on page 27 for details on how

to monitor specific parameters through the SMBus interface.

If multiple devices are faulting, SALRT will still be low after doing

the above steps and will require transmission with the Alert

Response Address repeatedly until all faults are cleared.

PMBus Command Summary

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

Selects Controller 0, 1, or both

Enable/disable, margin settings

On/off configuration settings

Clears faults

DEFAULT SETTING

00h PAGE

R/W

Write

Read

BIT

00h

Page 0 Controller addressed

01h OPERATION

Immediate off, nominal margin

02h ON_OFF_CONFIG

03h CLEAR_FAULTS

11h STORE_DEFAULT_ALL

12h RESTORE_DEFAULT_ALL

15h STORE_USER_ALL

16h RESTORE_USER_ALL

20h VOUT_MODE

BIT

17h

ENABLE pin control, active high

N/A

BIT

N/A

Stores values to default store

Restores values from default store

Stores values to user store

Restores values from user store

N/A

Reports V

OUT

mode and exponent

set-point

13h

Linear mode, exponent = -13

Pin-strap setting

21h VOUT_COMMAND

22h VOUT_TRIM

Sets nominal V

OUT

R/W L16u

R/W L16s

R/W L16u

N/A

Applies offset voltage to V

set-point

0000h

N/A

0V

OUT

23h VOUT_CAL_OFFSET

24h VOUT_MAX

Applies offset voltage to V

0V

Sets maximum V

OUT

set-point

1.15 x VSET pin-strap setting

1.05 x VSET pin-strap setting

0.95 x VSET pin-strap setting

25h VOUT_MARGIN_HIGH

26h VOUT_MARGIN_LOW

Sets V

set-point during margin high

set-point during margin low

transition rate during margin

N/A

OUT

N/A

27h VOUT_TRANSITION_RATE

R/W

L11

BA00h

1V/ms

commands

Sets V/I slope for total rail output current

(all phases combined)

28h VOUT_DROOP

33h FREQUENCY_SWITCH

37h INTERLEAVE

R/W

L11

BIT

N/A

CFG pin-strap setting

SYNC pin-strap setting

CFG pin-strap setting

Sets switching frequency

Configures phase offset during group

operation

38h IOUT_CAL_GAIN

Sets impedance of current sense circuit

R/W

L11

B2AEh

BD00h

N/A

0.67mΩ

39h IOUT_CAL_OFFSET

Sets an offset to I

OUT

sense circuit

-1.5A

40h VOUT_OV_FAULT_LIMIT

41h VOUT_OV_FAULT_RESPONSE

44h VOUT_UV_FAULT_LIMIT

45h VOUT_UV_FAULT_RESPONSE

Sets the V

overvoltage fault threshold R/W L16u

1.10 x VSET pin-strap setting

Disable, no retry

0.85 x VSET pin-strap setting

Disable, no retry

OUT

overvoltage fault response

R/W

BIT

80h

undervoltage fault threshold R/W L16u

N/A

undervoltage fault response R/W

BIT

80h

Sets the I

threshold for each phase

peak overcurrent fault

R/W

46h IOUT_OC_FAULT_LIMIT

L11

N/A

CFG pin-strap setting

Sets the I

threshold for each phase

valley undercurrent fault

-1*IOUT_OC_FAULT_LIMIT from

CFG pin-strap setting

OUT

4Bh IOUT_UC_FAULT_LIMIT

4Fh OT_FAULT_LIMIT

R/W

L11

BIT

N/A

EBE8h

BFh

Sets the over-temperature fault limit

+125°C

Continuous retry, 280ms retry

delay

50h OT_FAULT_RESPONSE

Sets the over-temperature fault response R/W

51h OT_WARN_LIMIT

52h UT_WARN_LIMIT

Sets the over-temperature warning limit

R/W

L11

EB70h

DC40h

+110°C

-30°C

Sets the under-temperature warning limit R/W

FN8760 Rev.3.00

Nov 8, 2017

Page 22 of 91

ZL8802

PMBus Command Summary (Continued)

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

DEFAULT SETTING

53h UT_FAULT_LIMIT

Sets the under-temperature fault limit

R/W

L11

BIT

E530h

BFh

-45°C

Continuous retry, 280ms retry

delay

54h UT_FAULT_RESPONSE

Sets the under-temperature fault response R/W

55h VIN_OV_FAULT_LIMIT

56h VIN_OV_FAULT_RESPONSE

57h VIN_OV_WARN_LIMIT

Sets the V overvoltage fault threshold

IN

R/W

L11

BIT

D380h

80h

14V

Sets the V overvoltage fault response

IN

Disable, no retry

13.5V

Sets the V overvoltage warning threshold R/W

IN

L11

D360h

Sets the V undervoltage warning

IN

threshold

58h VIN_UV_WARN_LIMIT

59h VIN_UV_FAULT_LIMIT

5Ah VIN_UV_FAULT_RESPONSE

R/W

L11

BIT

N/A

BFh

1.1 x UVLO pin-strap setting

UVLO pin-strap setting

Sets the V undervoltage fault threshold R/W

IN

Continuous retries, 280ms retry

delay

Sets the V undervoltage fault response

IN

R/W

Sets the voltage threshold for Power-Good

indication

5Eh POWER_GOOD_ON

60h TON_DELAY

61h TON_RISE

R/W L16u

N/A

0.9 x VSET pin-strap setting

Sets the delay time from enable to V

rise

OUT

R/W

L11

CA80h

5ms

Sets the rise time of V

and TON_DELAY

after ENABLE

OUT

Sets the delay time from DISABLE to start

of V fall

64h TOFF_DELAY

65h TOFF_FALL

OUT

Sets the fall time for VOUT after DISABLE

and TOFF_DELAY

78h STATUS_BYTE

79h STATUS_WORD

7Ah STATUS_VOUT

7Bh STATUS_IOUT

7Ch STATUS_INPUT

7Dh STATUS_TEMP

First byte of STATUS_WORD

Summary of critical faults

Read

BIT

00h

0000h

00h

No faults

Reports V

warnings/faults

OUT

Reports I

00h

OUT

Reports input warnings/faults

00h

Reports temperature warnings/faults

00h

Reports communication, memory, logic

errors

7Eh STATUS_CML

Read

BIT

00h

No faults

no faults

Reports voltage monitoring/clock

synchronization faults

80h STATUS_MFR_SPECIFIC

88h READ_VIN

89h READ_IIN

8Bh READ_VOUT

8Ch READ_IOUT

Reports input voltage measurement

Reports input current measurement

Reports output voltage measurement

Reports output current measurement

Read

L11

N/A

Read L16u

Read

L11

Reports internal temperature

measurement

8Dh READ_TEMPERATURE_1

8Eh READ_TEMPERATURE_2

8Fh READ_TEMPERATURE_3

N/A

Reports external temperature

measurement from XTEMP pins

Read

L11

Reports external temperature

measurement from VMON/TMON pin.

94h READ_DUTY_CYCLE

95h READ_FREQUENCY

98h PMBUS_REVISION

Reports actual duty cycle

Read

L11

BIT

N/A

22h

N/A

Reports actual switching frequency

Reports the PMBUS revision used

N/A

P1 R1.2, P2 R1.2

FN8760 Rev.3.00

Nov 8, 2017

Page 23 of 91

ZL8802

PMBus Command Summary (Continued)

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

Sets a user defined identification

Sets a user defined model

DEFAULT SETTING

99h MFR_ID

R/W

ASC

CUS

ASC

L11

N/A

<null>

9Ah MFR_MODEL

9Bh MFR_REVISION

9Ch MFR_LOCATION

9Dh MFR_DATE

Sets a user defined revision

Sets a user defined location identifier

Sets a user defined date

9Eh MFR_SERIAL

ADh IC_DEVICE_ID

AEh IC_DEVICE_REV

B0h USER_DATA_00

CEh MIN_VOUT_REG

Sets a user defined serialized identifier

Reports device identification information Read

49A02D00h Intersil ZL8802

01000000h Initial Release

Reports device revision information

Sets user defined data

Read

R/W

N/A

<null>

0mV

Sets a minimum start-up voltage

0000h

Downslope, 5 fault count, 384ns

blanking, high range

D0h ISENSE_CONFIG

D1h USER_CONFIG

D2h IIN_CAL_GAIN

Configures current sensing circuitry

Configures several user-level features

R/W

BIT

620Eh

N/A

Set by CFG pin-strap setting

Sets the resistance of the input current

sensing resistor

L11

C200h

2mΩ

Configures the DDC addressing and current

sharing

Set by pin-strapped PMBus

address and CFG pin-strap setting

D3h DDC_CONFIG

R/W

BIT

N/A

Sets the delay between PG threshold and

PG assertion

D4h POWER_GOOD_DELAY

L11

BA00h

1ms

Adjusts the ramp-up and ramp-down rate

by setting the feedback gain

D5h MULTI_PHASE_RAMP_GAIN

D6h INDUCTOR

R/W

CUS

L11

BIT

03h

3

Sets the inductor value

B133h

0000h

0.3µH

Masks faults that cause a snapshot to be

taken

D7h SNAPSHOT_FAULT_MASK

No faults masked

Configures output voltage OV/UV fault

detection

Low side FET off on fault, 1

violation triggers fault.

D8h OVUV_CONFIG

D9h XTEMP_SCALE

DAh XTEMP_OFFSET

R/W

BIT

L11

00h

Calibrates external temperature sensor

BA00h

0000h

1/degree C

No offset

Offset calibration for external temperature

sensor

Identifies which fault limits will not assert

SALRT

DBh MFR_SMBALERT_MASK

R/W Custom

00..00h

N/A

DCh TEMPCO_CONFIG

DDh PINSTRAP_READ_STATUS

DFh ASCR_CONFIG

Sets tempco settings

R/W

Read

R/W

BIT

00h

N/A

0ppm/°C

Reads pin-strap settings

Set by pin-straps

Configures the ASCR settings

DDC rail sequencing configuration

Configures voltage tracking

Configures group ID, fault spreading,

ASCRCFG pin-strap setting

Prequel and sequel disabled

Tracking disabled

E0h SEQUENCE

00h

E1h TRACK_CONFIG

E2h DDC_GROUP

R/W

Read

R/W

BIT

ASC

BIT

N/A

TBD

80h

Set by CFG pin-strap

ZL8802, current revisions

Disable, no retry

OPERATION, and V

OUT

E4h DEVICE_ID

Returns the device identifier string

Configures the I

response

overcurrent fault

OUT

E5h MFR_IOUT_OC_FAULT_RESPONSE

Configures the I

response

undercurrent fault

OUT

E6h MFR_IOUT_UC_FAULT_RESPONSE

R/W

BIT

80h

Disable, no retry

FN8760 Rev.3.00

Nov 8, 2017

Page 24 of 91

ZL8802

PMBus Command Summary (Continued)

DATA

TYPE FORMAT

DEFAULT

VALUE

CODE

COMMAND NAME

DESCRIPTION

DEFAULT SETTING

Set by CFG pin-strap

Sets the I

threshold

average overcurrent fault

OUT

E7h IOUT_AVG_OC_FAULT_LIMIT

E8h IOUT_AVG_UC_FAULT_LIMIT

E9h USER_GLOBAL_CONFIG

EAh SNAPSHOT

R/W

Read

L11

BIT

N/A

Sets the I

threshold

average undercurrent fault

-1* IOUT_AVG_OC_FAULT_LIMIT

from CFG pin-strap setting

OUT

Sets options pertaining to advanced

features

Set by CFG pin-strap setting

<null>

32-byte read-back of parametric and

status values

BIT

Configures fault group compatibility with

older Intersil digital power devices

F0h LEGACY_FAULT_GROUP

F3h SNAPSHOT_CONTROL

F4h RESTORE_FACTORY

R/W

Write

BIT

00000000h <null>

Snapshot feature control command

00h

N/A

Restores device to the hard-coded default

values

N/A

L11

BIT

N/A

F5h MFR_VMON_OV_FAULT_LIMIT

F6h MFR_VMON_UV_FAULT_LIMIT

F7h MFR_READ_VMON

Sets the VMON overvoltage fault threshold R/W

C266h

B0CCh

N/A

2.4V, SPS OT trip voltage

0.2V, corresponds to -50°C

N/A

Sets the VMON undervoltage fault

threshold

R/W

Reads the VMON voltage

Read

R/W

Configures the VMON overvoltage fault

response

F8h VMON_OV_FAULT_RESPONSE

BFh

Continuous retry

Configures the VMON undervoltage fault

response

F9h VMON_UV_FAULT_RESPONSE

R/W

BIT

BFh

Continuous retry

FAh SECURITY_LEVEL

FBh PRIVATE_PASSWORD

FCh PUBLIC_PASSWORD

FDh UNPROTECT

Reports the security level

Read

R/W

Hex

ASC

01h

Public security level

<null>

Sets the private password string

Sets the public password string

00…00h

FF…FFh

<null>

Identifies which commands are protected R/W Custom

No commands are protected

PMBus Use Guidelines

The PMBus is a powerful tool that allows the user to optimize circuit performance by configuring the ZL8802 for their application. When

configuring the ZL8802 in a circuit, the ZL8802 should be disabled whenever most settings are changed with PMBus commands. Some

exceptions to this recommendation are OPERATION, ON_OFF_CONFIG, CLEAR_FAULTS, VOUT_COMMAND, VOUT_MARGIN_HIGH,

VOUT_MARGIN_LOW, and ASCCR_CONFIG. While the device is enabled any command can be read. Many commands do not take effect

until after the device has been reenabled, hence the recommendation that commands that change device settings are written while

the device is disabled.

When sending the STORE_DEFAULT_ALL, STORE_USER_ALL, RESTORE_DEFAULT_ALL, and RESTORE_USER_ALL commands, it is

recommended that no other commands are sent to the device for 100ms after sending STORE or RESTORE commands.

In addition, there should be a 2ms delay between repeated READ commands sent to the same device. When sending any other

command, a 5ms delay is recommended between repeated commands sent to the same device.

SUMMARY:

All commands can be read at any time.

Always disable the ZL8802 when writing commands that change device settings. Exceptions to this rule are commands intended to be

written while the device is enabled, for example, VOUT_MARGIN_HIGH.

To be sure a change to a device setting has taken effect, write the STORE_USER_ALL command, then cycle input power and reenable

the device.

FN8760 Rev.3.00

Nov 8, 2017

Page 25 of 91

ZL8802

PMBus Data Formats

Linear-11 (L11)

The L11 data format uses 5-bit two’s complement exponent (N) and 11-bit two’s complement mantissa (Y) to represent real world

decimal value (X).

Data Byte High

Data Byte Low

7 6 5 4 3 2 1 0

Exponent (N)

Mantissa (Y)

N

Relation between real world decimal value (X), N, and Y is: X = Y·2

Linear-16 Unsigned (L16u)

The L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real world

-13

decimal value (X). Relation between real world decimal value (X), N, and Y is: X = Y·2

Linear-16 Signed (L16s)

The L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s complement mantissa (Y) to represent real

world decimal value (X).

-13

The relation between real world decimal value (X), N, and Y is: X = Y·2

Bit Field (BIT)

An explanation of Bit Field is provided in “PMBus Command Detail” starting on page 27.

Custom (CUS)

An explanation of the Custom data format is provided in “PMBus Command Detail”. A combination of Bit Field and integer are a

common type of Custom data format.

ASCII (ASC)

A variable length string of text characters in the ASCII data format.

FN8760 Rev.3.00

Nov 8, 2017

Page 26 of 91

ZL8802

PMBus Command Detail

PAGE (00h)

Definition: Selects Controller 0, Controller 1, or both Controllers 0 and 1 to receive commands. All commands following this command

will be received and acted on by the selected controller or controllers.

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: No

Default Value: 00h (Page 0)

Units: N/A

COMMAND

Format

PAGE (00h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS 7:4

BITS 3:0

0000

PAGE

0000

1111

0

1

0001

1111

Both

FN8760 Rev.3.00

Nov 8, 2017

Page 27 of 91

ZL8802

OPERATION (01h)

Definition: Sets Enable, Disable, and V

Margin settings. This command can also be monitored to read the operating state of the

OUT

device on bits 7:6. Writing immediate off will turn off the output and ignore TOFF_DELAY and TOFF_FALL settings. This command is not

stored like other PMBus commands. The value read reflects the current state of the device. When this command is written the

command takes effect, but if a STORE _USER_ALL written and the device is reenabled, the OPERATION settings may not be the same

settings that were written before the device was reenabled.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h (immediate off)

Units: N/A

COMMAND

Format

OPERATION (01h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS 3:0

BITS 7:6

BITS 5:4

00

(NOT USED)

UNIT ON OR OFF

MARGIN STATE

N/A

00

01

10

0000

Immediate off (No sequencing)

00

Soft off (With sequencing)

N/A

00

On

Nominal

Margin Low

Margin High

01

10

NOTE: Bit combinations not listed above may cause command errors.

FN8760 Rev.3.00

Nov 8, 2017

Page 28 of 91

ZL8802

ON_OFF_CONFIG (02h)

Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN). When bit 0 is set to 1

(turn off the output immediately), the TOFF_FALL setting is ignored.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 17h (ENABLE pin control, active high, turn off output immediately – no ramp down)

Units: N/A

COMMAND

Format

ON_OFF_CONFIG (02h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

BIT NUMBER

PURPOSE

BIT VALUE

MEANING

7:5

Not Used

000

101

110

1

Not used

Sets the default to either operate any time

power is present or for the on/off to be

controlled by ENABLE pin or OPERATION

command

4:2

Device starts from ENABLE pin only.

Device starts from OPERATION command only.

Active high only.

1

0

(Polarity of ENABLE pin - not used)

ENABLE pin action when commanding the unit

to turn off

0

Use the configured ramp-down settings (“soft-off”).

Turn off the output immediately.

1

CLEAR_FAULTS (03h)

Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the

bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.

Paged or Global: Global

Data Length in Bytes: 0 Byte

Data Format: N/A

Type: Write Only

Protectable: Yes

Default Value: N/A

Units: N/A

STORE_DEFAULT_ALL (11h)

Definition: Stores all current PMBus values from the operating memory into the nonvolatile DEFAULT store memory. To clear the

DEFAULT store, perform a RESTORE_FACTORY then STORE_DEFAULT_ALL. To add to the DEFAULT store, perform a

RESTORE_DEFAULT_ALL, write commands to be added, then STORE_DEFAULT_ALL. This command should not be used during device

operation. The device will be unresponsive for 100ms while storing values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write Only

Default Value: N/A

Units: N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 29 of 91

ZL8802

RESTORE_DEFAULT_ALL (12h)

Definition: Restores PMBus settings from the nonvolatile DEFAULT store memory into the operating memory. These settings are loaded

during power-up if not superseded by settings in USER store. Security level is changed to level 1 following this command. This command

should not be used during device operation. The device will be unresponsive for 100ms while storing values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write Only

Default Value: N/A

Units: N/A

STORE_USER_ALL (15h)

Definition: Stores all PMBus settings from the operating memory to the nonvolatile USER store memory. To clear the USER store,

perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a RESTORE_USER_ALL, write commands to

be added, then STORE_USER_ALL. This command should not be used during device operation. The device will be unresponsive for

100ms while storing values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write Only

Default Value: N/A

Units: N/A

RESTORE_USER_ALL (16h)

Definition: Restores all PMBus settings from the USER store memory to the operating memory. Command performed at power-up.

Security level is changed to Level 1 following this command. This command should not be used during device operation. The device will

be unresponsive for 100ms while restoring values.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write Only

Default Value: N/A

Units: N/A

VOUT_MODE (20H)

Definition: Reports the V

Data Length in Bytes: 1

Data Format: BIT

mode and provides the exponent used in calculating several V

settings.

OUT

Type: Read Only

Default Value: 13h (Linear Mode, Exponent = -13)

Units: N/A

COMMAND

Format

VOUT_MODE (20h)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

1

0

1

MODE

Linear

BITS 7:5

000

BITS 4:0 (PARAMETER)

5-bit two’s complement exponent for the mantissa delivered as the data bytes for an output

voltage related command.

FN8760 Rev.3.00

Nov 8, 2017

Page 30 of 91

ZL8802

VOUT_COMMAND (21h)

Definition: Sets or reports the target output voltage. The integer value is multiplied by 2 raised to the power of -13h. This command

cannot be set to be higher than 115% of the pin-strap VSET setting, or VOUT_MAX if VOUT_MAX is set higher than 115% of the pin-strap

VSET setting.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear -16 Unsigned

Type: R/W

Protectable: Yes

Default Value: VSET pin-strap setting

Units: Volts

Equation: V

-13

= VOUT_COMMAND × 2

OUT

Range: 0 to VOUT_MAX

Example: VOUT_COMMAND = 699Ah = 27,034

-13

Target voltage equals 27034 × 2

= 3.3V

COMMAND

Format

VOUT_COMMAND (21h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

VSET Pin-strap Setting

Default Value

VOUT_TRIM (22h)

Definition: Applies a fixed trim voltage to the output voltage command value. This command is typically used by the manufacturer of a

power supply subassembly to calibrate a device in the subassembly circuit. The two bytes are formatted as a two’s complement binary

mantissa, used in conjunction with the exponent of -13h.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear -16 Signed

Type: R/W

Protectable: Yes

Default Value: 0000h

Units: Volts

-13

Equation: VOUT trim = VOUT_TRIM×2

Range: ±150mV

COMMAND

Format

VOUT_TRIM (22h)

Linear-16 Signed

Bit Position

Access

15

R/W

0

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10

R/W

0

9

R/W

0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Default Value

FN8760 Rev.3.00

Nov 8, 2017

Page 31 of 91

ZL8802

VOUT_CAL_OFFSET (23h)

Definition: Applies a fixed offset voltage to the output voltage command value. This command is typically used to calibrate a device in

the application circuit. The two bytes are formatted as a two’s complement binary mantissa, used in conjunction with the exponent of

-13h.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear -16 Signed

Type: R/W

Protectable: Yes

Default Value: 0000h

Units: Volts

Equation: V

-13

calibration offset = VOUT_CAL_OFFSET×2

OUT

Range: ±150mVV

COMMAND

Format

VOUT_CAL_OFFSET (23h)

Linear-16 Signed

Bit Position

Access

15

14

R/W

0

13

R/W

0

12

R/W

0

11

R/W

0

10

R/W

0

9

R/W

0

8

R/W

0

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

R/W

0

Default Value

VOUT_MAX (24h)

Definition: Sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. The

intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level

rather than to be the primary output overprotection. If a VOUT_COMMAND is sent with a value higher than VOUT_MAX, the device will

set the output voltage to VOUT_MAX. Note that this command setting does not automatically scale with a stored VOUT_COMMAND

setting.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear -16 Unsigned

Type: R/W

Protectable: Yes

Default Value: 1.15 x VSET pin-strap setting

Units: Volts

Equation: V

-13

max = VOUT_MAX × 2

OUT

Range: 0V to 5.5V

COMMAND

Format

VOUT_MAX (24h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

1.15 x VSET Pin-strap Setting

Default Value

FN8760 Rev.3.00

Nov 8, 2017

Page 32 of 91

ZL8802

VOUT_MARGIN_HIGH (25h)

Definition: Sets the value of the V

during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the voltage to

OUT

which the output is to be changed when the OPERATION command is set to “Margin High”.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned

Type: R/W word

Protectable: Yes

Default Value: 1.05 x VSET pin-strap setting

Units: V

Equation: V

-13

margin high = VOUT_MARGIN_HIGH x 2

OUT

Range: 0V to VOUT_MAX

COMMAND

Format

VOUT_MARGIN_HIGH (25h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

1.05 x VSET Pin-strap Setting

Default Value

VOUT_MARGIN_LOW (26h)

Definition: Sets the value of the V

during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage to which

OUT

the output is to be changed when the OPERATION command is set to “Margin Low”.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned

Type: R/W

Protectable: Yes

Default Value: 0.95 x VSET pin-strap setting

Units: V

Equation: V

OUT

margin low = VOUT_MARGIN_LOW

Range: 0V to VOUT_MAX

COMMAND

Format

VOUT_MARGIN_LOW (26h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

0.95 x VSET Pin-strap Setting

Default Value

FN8760 Rev.3.00

Nov 8, 2017

Page 33 of 91

ZL8802

VOUT_TRANSITION_RATE (27h)

Definition: Sets the rate at which the output should change voltage when the device receives an OPERATION command (Margin High,

Margin Low) that causes the output voltage to change. The maximum possible positive value of the two data bytes indicates that the

device should make the transition as quickly as possible. This commanded rate does not apply when the device is commanded to turn

on or to turn off.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: BA00h (1.0V/ms)

Units: V/ms

N

Equation: VOUT_TRANSITION_RATE = Y×2

Range: 0.1 to 4V/ms

COMMAND

Format

VOUT_TRANSITION_RATE (27h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

VOUT_DROOP (28h)

Definition: Sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A, at which the output

voltage decreases with increasing output current for use with passive current sharing schemes. For devices that are set to sink output

current (negative output current), the output voltage continues to increase as the output current is negative. VOUT_DROOP is not

needed with a single (2-phase) ZL8802. VOUT_DROOP is needed when multiple ZL8802s are operated in current sharing mode, that is,

4-, 6-, and 8-phase configurations. In this case, VOUT_DROOP is calculated based on the combined output current of all phases as

applicable.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: Set by CFG pin-strap setting

Units: mV/A

N

Equation: VOUT_DROOP = Y×2

Range: 0 to 40mV/A

COMMAND

Format

VOUT_DROOP (28h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Set by CFG Pin-strap Setting

Default Value

FN8760 Rev.3.00

Nov 8, 2017

Page 34 of 91

ZL8802

FREQUENCY_SWITCH (33h)

Definition: Sets the switching frequency of the device. Initial default value is defined by a pin-strap and this value can be overridden by

writing this command. If an external SYNC is utilized, this value should be set as close as possible to the external clock value. The

output must be disabled when writing this command. Available frequencies are defined by the equation f

= 16MHz/n where

SW

12 ≤ n ≤ 80.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: SYNC pin-strap setting

Units: kHz

N

Equation: FREQUENCY_SWITCH = Y×2

Range: 200kHz-1.33MHz

COMMAND

Format

FREQUENCY_SWITCH (33h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

SYNC Pin-strapped Value

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

INTERLEAVE (37h)

Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. A desired phase position is

specified. Interleave is used for setting the phase offset between individual devices, current sharing groups, and/or combinations of

devices and current sharing groups. For devices within single current sharing group the phase offset is set automatically. In a

multiphase current share group the same interleave settings must be stored in all devices in the current sharing group to phase spread

properly. Interleave Offset refers to the phase offset of Phase 0 of the device; Phase 1 is always Phase 0 + 180 degrees.

INTERLEAVE Phase offset is calculated with Equation 7:

(EQ. 7)

Phase Offset (in degrees) = RoundedPosition  16  Number  22.5

Phase offsets greater than 360 degrees are “wrapped around” by subtracting 360 degrees.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: Set by CFG pin-strap setting.

Units: N/A

COMMAND

Format

INTERLEAVE (37h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Function

See Following Table

Default Value

Set by CFG Pin-strap Setting

BITS

15:8

7:4

PURPOSE

Not Used

VALUE

0

DESCRIPTION

Not used

Number In Group

0 to 15d Sets the number of devices in the interleave group. A value of 0 is interpreted as 16.

Position in Group

(Interleave Order)

Sets position of the device’s rail within the group. A value of 0 is interpreted as 16. Position 1

will have a 22.5 degree offset.

3:0

0 to 15d

FN8760 Rev.3.00

Nov 8, 2017

Page 35 of 91

ZL8802

IOUT_CAL_GAIN (38h)

Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: B2AEh (0.67mΩ)

Units: mΩ

N

Equation: IOUT_CAL_GAIN = Y×2

COMMAND

Format

IOUT_CAL_GAIN (38h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

1

0

1

0

IOUT_CAL_OFFSET (39h)

Definition: Used to null out any offsets in the output current sensing circuit, and to compensate for delayed measurements of current

ramp due to the current sense blanking time (see “ISENSE_CONFIG (D0h)” on page 62).

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: BD00h (-1.5A)

Units: A

N

Equation: IOUT_CAL_OFFSET = Y×2

COMMAND

Format

IOUT_CAL_OFFSET (39h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 36 of 91

ZL8802

VOUT_OV_FAULT_LIMIT (40h)

Definition: Sets the V

OUT

overvoltage fault threshold.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned

Type: R/W

Protectable: Yes

Default Value: 1.10 x VSET pin-strap setting

Units: V

-13

Equation: VOUT OV fault limit = VOUT_OV_FAULT_LIMIT×2

Range: 0V to 7.99V

COMMAND

Format

VOUT_OV_FAULT_LIMIT (40h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

1.10 x VSET Pin-strap Setting

Default Value

VOUT_OV_FAULT_RESPONSE (41h)

Definition: Configures the V

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

overvoltage fault response. The retry time is the time between restart attempts.

OUT

Protectable: Yes

Default Value: 80h (shut down immediately, no retries)

Units: Retry time = 35ms increments

COMMAND

Format

VOUT_OV_FAULT_RESPONSE (41h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

FIELD NAME

VALUE

00-01

DESCRIPTION

Response behavior, the device:

• Pulls SALRT low

Not used

Disable and retry according to the setting in Bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

7:6

10-11

000

CLEAR_FAULTS command.

No retry. The output remains disabled until the device is restarted.

001-110 Not used

5:3

2:0

Retry Setting

Retry Delay

Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION

command or both), bias power is removed, or another fault condition causes the unit to shut

down. The time between the start of each attempt to restart is set by the value in Bits [2:0]

multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range

is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 37 of 91

ZL8802

VOUT_UV_FAULT_LIMIT (44h)

Definition: Sets the V

undervoltage fault threshold. This fault is masked during ramp, before Power-Good is asserted or when the

OUT

device is disabled. VOUT_UV_FAULT_LIMIT should be set to a value below POWER_GOOD.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned

Type: R/W

Protectable: Yes

Default Value: 0.85 x VSET pin-strap setting

Units: V

Equation: V

-13

UV fault limit = VOUT_UV_FAULT_LIMIT×2

OUT

Range: 0V to 7.99V

COMMAND

Format

VOUT_UV_FAULT_LIMIT (44h)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

0.85 x VSET Pin-strap Setting

Default Value

VOUT_UV_FAULT_RESPONSE (45h)

Definition: Configures the V undervoltage fault response. Note that V

UV faults can only occur after Power-Good (PG) has been

OUT OUT

asserted. Under some circumstances this will cause the output to stay fixed below the Power-Good threshold indefinitely. If this

behavior is undesired, use setting 80h. The retry time is the time between restart attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 80h (shut down immediately, no retries)

Units: Retry time unit = 35ms

COMMAND

VOUT_UV_FAULT_RESPONSE (45h)

Bit Field

Format

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

FIELD NAME

VALUE

00-01

DESCRIPTION

Response Behavior: the device:

• Pulls SALRT low

Not used

Disable and Retry according to the setting in Bits [5:3].

7:6

• Sets the related fault bit in the status

registers. Fault bits are only cleared by

the CLEAR_FAULTS command.

10-11

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

5:3

2:0

Retry Setting

Retry Delay

Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or

OPERATION command or both), bias power is removed, or another fault condition

causes the unit to shut down. The time between the start of each attempt to restart is

set by the value in Bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms

increments. Range is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 38 of 91

ZL8802

IOUT_OC_FAULT_LIMIT (46h)

Definition: Sets the I

peak overcurrent fault threshold. This limit is applied to current measurement samples taken after the Current

OUT

Sense Blanking Time has expired (see “ISENSE_CONFIG (D0h)” on page 62)). A fault occurs after this limit is exceeded for the number of

consecutive samples as defined in ISENSE_CONFIG. This feature shares the OC fault bit operation (in STATUS_IOUT) and OC fault response

with IOUT_AVG_OC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: CFG pin-strap setting

Units: A

N

Equation: IOUT_OC_FAULT_LIMIT = Y×2

Range: -100A to 100A

COMMAND

Format

IOUT_OC_FAULT_LIMIT (46h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

CFG Pin-strap Setting

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

IOUT_UC_FAULT_LIMIT (4Bh)

Definition: Sets the I valley undercurrent fault threshold. This limit is applied to current measurement samples taken after the Current

OUT

Sense Blanking Time has expired. A fault occurs after this limit is exceeded for the number of consecutive sample as defined in

ISENSE_CONFIG. This feature shares the UC fault bit operation (in STATUS_IOUT) and UC fault response with IOUT_AVG_UC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: -1 * IOUT_OC_FAULT_LIMIT from CFG pin-strap setting

Units: A

N

Equation: IOUT_OC_FAULT_LIMIT = Y×2

Range: -100A to 100A

COMMAND

Format

IOUT_UC_FAULT_LIMIT (4Bh)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

-1 * IOUT_OC_FAULT_LIMIT from CFG Pin-strap Setting

FN8760 Rev.3.00

Nov 8, 2017

Page 39 of 91

ZL8802

OT_FAULT_LIMIT (4Fh)

Definition: Sets the temperature at which the device should indicate an over-temperature fault.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: EBE8h (+125°C)

Units: Celsius

N

Equation: OT_FAULT_LIMIT = Y×2

Range: 0 to 175°C

COMMAND

Format

OT_FAULT_LIMIT (4Fh)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

OT_FAULT_RESPONSE (50h)

Definition: Instructs the device on what action to take in response to an over-temperature fault. The retry time is the time between

restart attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: BFh (Continuous retries, retry delay 280ms)

Units: Retry time unit = 35ms

COMMAND

Format

OT_FAULT_RESPONSE (50h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

1

BIT

7:6

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response behavior, the device:

• Pulls SALRT low

Not used

Disable and Retry according to the setting in Bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

Output is disabled while the fault is present. Operation resumes and the output is enabled when

the temperature falls below the OT_WARN_LIMIT.

11

CLEAR_FAULTS command.

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION

5:3

2:0

Retry Setting

Retry Delay

command or both), bias power is removed, or another fault condition causes the unit to shut

down. A retry is attempted after the temperature falls below the OT_WARN_LIMIT. The time

between the start of each attempt to restart is set by the value in Bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range

is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 40 of 91

ZL8802

OT_WARN_LIMIT (51h)

Definition: Sets the temperature at which the device should indicate an over-temperature warning alarm. In response to the

OT_WARN_LIMIT being exceeded, the device sets the TEMPERATURE bit in STATUS_WORD, sets the OT_WARNING bit in

STATUS_TEMPERATURE, and notifies the host.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: EB70h (+110°C)

Units: Celsius

N

Equation: OT_WARN_LIMIT = Y×2

Range: 0 to 175°C

COMMAND

Format

OT_WARN_LIMIT (51h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

UT_WARN_LIMIT (52h)

Definition: Sets the temperature at which the device should indicate an under-temperature warning alarm. In response to the

UT_WARN_LIMIT being exceeded, the device sets the TEMPERATURE bit in STATUS_WORD, sets the UT_WARNING bit in

STATUS_TEMPERATURE, and notifies the host.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: DC40h (-30°C)

Units: Celsius

N

Equation: UT_WARN_LIMIT = Y×2

Range: -55°C to +25°C

COMMAND

Format

UT_WARN_LIMIT (52h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 41 of 91

ZL8802

UT_FAULT_LIMIT (53h)

Definition: Sets the temperature, in degrees Celsius, of the unit at which it should indicate an under-temperature fault.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: E530h (-45°C)

Units: Celsius

N

Equation: UT_FAULT_LIMIT = Y×2

Range: -55°C to +25°C

COMMAND

Format

UT_FAULT_LIMIT (53h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

UT_FAULT_RESPONSE (54h)

Definition: Configures the under-temperature fault response as defined by the table below. The retry time is the time between restart

attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: BFh (Continuous retries, 280ms retry delay)

Units: Retry time unit = 35ms

COMMAND

Format

UT_FAULT_RESPONSE (54h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

1

BIT

7:6

FIELD NAME

VALUE

00-01 Not used

DESCRIPTION

Response behavior, the device:

• Pulls SALRT low

10

Disable and Retry according to the setting in Bits [5:3].

• Sets the related fault bit in the status

registers. Fault bits are only cleared

by the CLEAR_FAULTS command.

Output is disabled while the fault is present. Operation resumes and the output is enabled when

the temperature rises above the UT_WARN_LIMIT.

11

000

No retry. The output remains disabled until the device is restarted.

001-110 Not used

Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION

5:3

2:0

Retry Setting

Retry Delay

command or both), bias power is removed, or another fault condition causes the unit to shut

down. A retry is attempted after the temperature rises above UT_WARN_LIMIT. The time

between the start of each attempt to restart is set by the value in Bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range

is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 42 of 91

ZL8802

VIN_OV_FAULT_LIMIT (55h)

Definition: Sets the V overvoltage fault threshold.

IN

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: D380h (14V)

Units: V

N

Equation: VIN_OV_FAULT_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_OV_FAULT_LIMIT (55h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

VIN_OV_FAULT_RESPONSE (56h)

Definition: Configures the V overvoltage fault response as defined by the table below.

IN

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 80h (Disable, no retry)

Units: N/A

COMMAND

Format

VIN_OV_FAULT_RESPONSE (56h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00-01

10

DESCRIPTION

Response behavior, the device:

• Pulls SALRT low

Not used

Disable and Retry according to the setting in bits [5:3].

• Sets the related fault bit in the

status registers. Fault bits are

only cleared by the

Output is disabled while the fault is present. Operation resumes and the output is enabled when

VIN falls below the VIN_OV_WARN_LIMIT.

11

CLEAR_FAULTS command.

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION

5:3

2:0

Retry Setting

Retry Delay

command or both), bias power is removed, or another fault condition causes the unit to shut

down. A retry is attempted after the output falls below the VIN_OV_WARN_LIMIT. The time

between the start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range

is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 43 of 91

ZL8802

VIN_OV_WARN_LIMIT (57h)

Definition: Sets the V overvoltage warning threshold as defined by the table below. In response to the OV_WARN_LIMIT being

IN

exceeded, the device sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, sets the VIN_OV_WARNING bit in STATUS_INPUT,

and notifies the host.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: D360h (13.5V)

Units: V

N

Equation: VIN_OV_FAULT_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_OV_WARN_LIMIT (57h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

VIN_UV_WARN_LIMIT (58h)

Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above

VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT being

exceeded, the device sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, sets the VIN_UV_WARNING bit in STATUS_INPUT,

and notifies the host.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: 1.10 x UVLO pin-strap setting

Units: V

N

Equation: VIN_UV_WARN_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_UV_WARN_LIMIT (58h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

1.10 x UVLO Pin-strap Setting

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

FN8760 Rev.3.00

Nov 8, 2017

Page 44 of 91

ZL8802

VIN_UV_FAULT_LIMIT (59h)

Definition: Sets the V undervoltage fault threshold.

IN

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: UVLO pin-strap setting

Units: V

N

Equation: VIN_UV_FAULT_LIMIT = Y×2

Range: 0 to 19V

COMMAND

Format

VIN_UV_FAULT_LIMIT (59h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

UVLO pin-strapped value

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

VIN_UV_FAULT_RESPONSE (5Ah)

Definition: Configures the VIN undervoltage fault response as defined by the table below. The retry time is the time between restart

attempts.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: BFh (continuous retries, 280ms retry delay)

Units: Retry time unit = 35ms

COMMAND

Format

VIN_UV_FAULT_RESPONSE (5Ah)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00-01 Not used

DESCRIPTION

Response behavior, the device:

• Pulls SALRT low

10

Disable and retry according to the setting in Bits [5:3].

• Sets the related fault bit in the status

registers. Fault bits are only cleared

by the CLEAR_FAULTS command.

Output is disabled while the fault is present. Operation resumes and the output is enabled when

11

V

rises above the VIN_UV_WARN_LIMIT.

IN

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

Attempts to restart continuously, until it is commanded OFF (by the ENABLE pin or OPERATION

5:3

2:0

Retry Setting

command or both), bias power is removed, or another fault condition causes the unit to shut

down. A retry is attempted after the input voltage rises above the VIN_UV_WARN_LIMIT. The time

between the start of each attempt to restart is set by the value in Bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments. Range

is 35ms to 280ms.

Retry Delay

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 45 of 91

ZL8802

POWER_GOOD_ON (5Eh)

Definition: Sets the voltage threshold for Power-Good indication. Power-good asserts when the output voltage exceeds

POWER_GOOD_ON and deasserts when the output voltage is less than VOUT_UV_FAULT_LIMIT. POWER_GOOD_ON should be set to a

value above VOUT_UV_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned

Type: R/W

Protectable: Yes

Default Value: 0.9 x VSET pin-strap setting.

Units: V

COMMAND

Format

POWER_GOOD_ON (5Eh)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

0.9 x VSET Pin-strap Setting

Default Value

TON_DELAY (60h)

Definition: Sets the delay time from when the device is enabled to the start of V

rise.

OUT

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: CA80h (5ms)

Units: ms

N

Equation: TON_DELAY = Y×2

Range: 0 to 5 seconds

COMMAND

Format

TON_DELAY (60h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 46 of 91

ZL8802

TON_RISE (61h)

Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY for single and dual channel operation. To adjust the rise time in 4-,

6- or 8-phase operation, use MULTI_PHASE_RAMP_GAIN (D5h).

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: CA80h (5ms)

Units: ms

N

Equation: TON_RISE = Y×2

Range: 0 to 100ms. Although values can be set below 0.50ms, rise time accuracy cannot be guaranteed. In addition, short rise times

may cause excessive input and output currents to flow, thus triggering overcurrent faults at start-up.

COMMAND

Format

TON_RISE (61h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

0 0 0

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

TOFF_DELAY (64h)

Definition: Sets the delay time from DISABLE to start of VOUT fall.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: CA80h (5ms)

Units: ms

N

Equation: TON_DELAY = Y×2

Range: 0 to 5 seconds

COMMAND

Format

TOFF_DELAY (64h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 47 of 91

ZL8802

TOFF_FALL (65h)

Definition: Sets the fall time for V

after DISABLE and TOFF_DELAY. This setting is only valid in single or 2-phase operation. Setting

OUT

the TOFF_FALL to values less than 0.5ms will cause the ZL8802 to turn-off both the high and low-side FETs (or disable the DrMOS

device) immediately after the expiration of the TOFF_DELAY time. In 4-, 6- or 8-phase operation, the ZL8802 will always turn-off both

the high and low-side FETs (or disable the DrMOS device) immediately after the expiration of the TOFF_DELAY time.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: CA80h (5ms)

Units: ms

N

Equation: TOFF_FALL = Y×2

Range: 0 to 100ms. Values less than 0.5ms will cause the ZL8802 to tri-state the PWM signal (turn-off both the high and low-side FETs)

immediately after the expiration of the TOFF_DELAY time.

COMMAND

Format

TOFF_FALL (65h)

Linear-11

Bit Position

Access

15

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Signed Exponent, N Signed Mantissa, Y

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Function

Default Value

1

0

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 48 of 91

ZL8802

STATUS_BYTE (78h)

Definition: Returns two bytes of information with a summary of the unit’s fault condition. Based on the information in these bytes, the

host can get more information by reading the appropriate status registers. The low byte of the STATUS_WORD is the same register as

the STATUS_BYTE (78h) command.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: Read Only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_BYTE (78h)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

STATUS BIT

NAME

BIT NUMBER

MEANING

7

6

BUSY

OFF

A fault was declared because the device was busy and unable to respond.

This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being

enabled.

5

4

3

2

1

0

VOUT_OV_FAULT An output overvoltage fault has occurred.

IOUT_OC_FAULT An output overcurrent fault has occurred.

VIN_UV_FAULT An input undervoltage fault has occurred.

TEMPERATURE A temperature fault or warning has occurred.

CML

A communications, memory, or logic fault has occurred.

None of the

above

A fault other than the faults listed in Bits 7:1 above has occurred. The source of the fault will be in bits 15:8 of the

STATUS_WORD

FN8760 Rev.3.00

Nov 8, 2017

Page 49 of 91

ZL8802

STATUS_WORD (79h)

Definition: Returns two bytes of information with a summary of the unit’s fault condition. Based on the information in these bytes, the

host can get more information by reading the appropriate status registers. The low byte of the STATUS_WORD is the same register as

the STATUS_BYTE (78h) command.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: Read Only

Protectable: No

Default Value: 0000h

Units: N/A

COMMAND

Format

STATUS_WORD (79h)

Bit Field

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

VOUT

MEANING

15

14

13

12

11

10

An output voltage fault or warning has occurred.

An output current fault has occurred.

IOUT

INPUT

An input voltage fault or warning has occurred.

MFG_SPECIFIC

POWER_GOOD #

NOT USED

A manufacturer specific fault or warning has occurred.

The POWER_GOOD signal, if present, is negated. (Note 15)

Not used

A bit in STATUS_VOUT, STATUS_IOUT, STATUS_INPUT,

9

OTHER

STATUS_TEMPERATURE, STATUS_CML, or STATUS_MFR_SPECIFIC is

set.

8

7

Not Used

BUSY

Not used

A fault was declared because the device was busy and unable to

respond.

This bit is asserted if the unit is not providing power to the output,

regardless of the reason, including simply not being enabled.

6

OFF

5

4

3

2

1

0

VOUT_OV_FAULT

IOUT_OC_FAULT

VIN_UV_FAULT

TEMPERATURE

CML

An output overvoltage fault has occurred.

An output overcurrent fault has occurred.

An input undervoltage fault has occurred.

A temperature fault or warning has occurred.

A communications, memory, or logic fault has occurred.

None of the above

A fault other than the faults listed in Bits 7:1 above has occurred. The

source of the fault will be in Bits 15:8 of the STATUS_WORD

NOTE:

15. If the POWER_GOOD# bit is set, this indicates that the POWER_GOOD signal, if present, is signaling that the output power is not good.

FN8760 Rev.3.00

Nov 8, 2017

Page 50 of 91

ZL8802

STATUS_VOUT (7Ah)

Definition: Returns one data byte with the status of the output voltage.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read Only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_VOUT (7Ah)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

VOUT_OV_FAULT

VOUT_OV_WARNING

VOUT_UV_WARNING

VOUT_UV_FAULT

Not Used

MEANING

7

6

Indicates an output overvoltage fault.

Not used

5

Not used

4

Indicates an output undervoltage fault.

Not used

3:0

STATUS_IOUT (7Bh)

Definition: Returns one data byte with the status of the output current.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read Only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_IOUT (7Bh)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

IOUT_OC_FAULT

Not Used

MEANING

7

6

An output overcurrent fault has occurred.

Not used

5

Not Used

4

IOUT_UC_FAULT

Not Used

An output undercurrent fault has occurred.

Not used

3:0

FN8760 Rev.3.00

Nov 8, 2017

Page 51 of 91

ZL8802

STATUS_INPUT (7Ch)

Definition: Returns input voltage and input current status information.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_INPUT (7Ch)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

VIN_OV_FAULT

VIN_OV_WARNING

VIN_UV_WARNING

VIN_UV_FAULT

Not Used

MEANING

7

6

An input overvoltage fault has occurred.

An input overvoltage warning has occurred.

An input undervoltage warning has occurred.

An input undervoltage fault has occurred.

Not used

5

4

3:0

STATUS_TEMPERATURE (7Dh)

Definition: Returns one byte of information with a summary of any temperature related faults or warnings.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read-only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_TEMP (7Dh)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

OT_FAULT

MEANING

7

6

An over-temperature fault has occurred.

An over-temperature warning has occurred.

An under-temperature warning has occurred.

An under-temperature fault has occurred.

Not used

OT_WARNING

UT_WARNING

UT_FAULT

5

4

3:0

Not Used

FN8760 Rev.3.00

Nov 8, 2017

Page 52 of 91

ZL8802

STATUS_CML (7Eh)

Definition: Returns one byte of information with a summary of any communications, logic, and/or memory errors.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read Only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_CML (7Eh)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

MEANING

7

6

Invalid or unsupported PMBus command was received.

The PMBus command was sent with invalid or unsupported data.

A packet error was detected in the PMBus command.

Not used

5

4:2

A PMBus command tried to write to a read-only or protected command, or a communication fault other than the ones listed in

this table has occurred.

1

0

Not used

FN8760 Rev.3.00

Nov 8, 2017

Page 53 of 91

ZL8802

STATUS_MFR_SPECIFIC (80h)

Definition: Returns one byte of information providing the status of the device’s voltage monitoring and clock synchronization faults.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read Only

Protectable: No

Default Value: 00h

Units: N/A

COMMAND

Format

STATUS_MFR_SPECIFIC (80h)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT

7

FIELD NAME

MEANING

Not Used

Not used

An error was detected on the DDC bus.

6

DDC Warning

5

VMON UV Warning

VMON OV Warning

The voltage on the VMON pin has dropped 10% below the level set by MFR_VMON_UV_FAULT.

The voltage on the VMON pin has risen 10% above the level set by MFR_VMON_OV_FAULT.

4

3

External Switching Period Fault Loss of external clock synchronization has occurred.

2

Not Used

Not used

1

VMON UV Fault

VMON OV Fault

The voltage on the VMON pin has dropped below the level set by MFR_VMON_UV_FAULT.

The voltage on the VMON pin has risen above the level set by MFR_VMON_OV_FAULT.

0

READ_VIN (88h)

Definition: Returns the input voltage reading.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Protectable: No

Default Value: N/A

Units: V

N

Equation: READ_VIN = Y×2

Range: N/A

COMMAND

Format

READ_VIN (88h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 54 of 91

ZL8802

READ_IIN (89h)

Definition: Returns the input current reading.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Protectable: No

Default Value: N/A

Units: A

N

Equation: READ_IIN = Y×2

Range: N/A

COMMAND

Format

READ_IIN (89h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

Default Value N/A

N/A

READ_VOUT (8Bh)

Definition: Returns the output voltage reading.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-16 Unsigned

Type: Read Only

Protectable: No

Default Value: N/A

-13

Equation: READ_VOUT = READ_VOUT × 2

Units: V

COMMAND

Format

READ_VOUT (8Bh)

Linear-16 Unsigned

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Default Value

N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 55 of 91

ZL8802

READ_IOUT (8Ch)

Definition: Returns the output current reading.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Protectable: No

Default Value: N/A

Units: A

N

Equation: READ_IOUT = Y×2

Range: N/A

COMMAND

Format

READ_IOUT (8Ch)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

Default Value

N/A

READ_TEMPERATURE_1 (8Dh)

Definition: Returns the temperature reading internal to the device.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Protectable: No

Default Value: N/A

Units: °C

N

Equation: READ_TEMPERATURE_1 = Y×2

Range: N/A

COMMAND

Format

READ_TEMPERATURE_1 (8Dh)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 56 of 91

ZL8802

READ_TEMPERATURE_2 (8Eh)

Definition: Returns the temperature reading from the external temperature device connected to XTEMP.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Protectable: No

Default Value: N/A

Units: °C

N

Equation: READ_TEMPERATURE_2 = Y×2

Range: N/A

COMMAND

Format

READ_TEMPERATURE_2 (8Eh)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

READ_TEMPERATURE_3 (8Fh)

Definition: Returns the temperature reading from the VMON/TMON pin when the device is configured to read temperature on the

VMON/TMON pin by setting bit 12 in the USER_GLOBAL_CONFIG command to 1. The voltage on the VMON/TMON pin is converted to °C

by the equation TEMPERTATURE 3 = (VMON voltage - 0.6V)/0.008. See MFR_VMON commands starting on page 85 (F5h, F6h, F8h,

F9H) for fault limits when reading temperature on the VMON/TMON pin. When using the Intersil ISL9922X smart power stage, a 2:1

voltage divider is needed between the TMON pin of the ISL9922X and the VMON/TMON pin of the ZL8802.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Protectable: No

Default Value: N/A

Units: °C

N

Equation: READ_TEMPERATURE_3 = Y×2

Range: N/A

COMMAND

Format

READ_TEMPERATURE_3 (8Fh)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 57 of 91

ZL8802

READ_DUTY_CYCLE (94h)

Definition: Reports the actual duty cycle of the converter during the enable state.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Protectable: No

Default Value: N/A

Units: %

N

Equation: READ_DUTY_CYCLE = Y×2

Range: 0 to 100%

COMMAND

Format

READ_DUTY_CYCLE (94h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

Default Value

N/A

READ_FREQUENCY (95h)

Definition: Reports the actual switching frequency of the converter during the enable state.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: Read Only

Default Value: N/A

Units: kHz

N

Equation: READ_FREQUENCY = Y×2

Range: N/A

COMMAND

Format

READ_FREQUENCY (95h)

Linear-11

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 58 of 91

ZL8802

PMBUS_REVISION (98h)

Definition: Returns the revision of the PMBus specification to which the device is compliant.

Data Length in Bytes: 1

Data Format: Bit Field

Type: Read Only

Protectable: N/A

Default Value: 22h (Part 1 Revision 1.2, Part 2 Revision 1.2)

Units: N/A

COMMAND

Format

PMBUS_REVISION (98h)

Bit Field

Bit Position

Access

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

1

0

1

0

BITS 7:4

0000

PART 1 REVISION

BITS 3:0

0000

PART 2 REVISION

1.0

1.1

1.2

1.0

1.1

1.2

0001

0010

MFR_ID (99h)

Definition: Sets a user defined identification string not to exceed 32bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128bytes.

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII, ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: Null

Units: N/A

MFR_MODEL (9Ah)

Definition: Sets a user defined model string not to exceed 32bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128bytes.

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII, ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: Null

Units: N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 59 of 91

ZL8802

MFR_REVISION (9Bh)

Definition: Sets a user defined revision string not to exceed 32bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128bytes.

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: Null

Units: N/A

MFR_LOCATION (9Ch)

Definition: Sets a user defined location identifier string not to exceed 32bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128bytes.

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: Null

Units: N/A

MFR_DATE (9Dh)

Definition: Sets a user defined date string not to exceed 32bytes. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,

MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128bytes. This limitation

includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command

then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: Null

Units: N/A

MFR_SERIAL (9Eh)

Definition: Sets a user defined serialized identifier string not to exceed 32bytes. The sum total of characters in MFR_ID, MFR_MODEL,

MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128bytes.

This limitation includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write

this command then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: Null

Units: N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 60 of 91

ZL8802

IC_DEVICE_ID (ADh)

Definition: Reports device identification information.

Data Length in Bytes: 4

Data Format: CUS

Type: Block Read

Protectable: No

Default Value: 49A02D00h (ZL8802)

Units: N/A

COMMAND

Format

IC_DEVICE_ID (ADh)

Block Read

Byte Position

Function

3

2

1

0

MFR code

49h

ID High Byte

A0h

ID Low Byte

2Ah

Reserved

00h

Default Value

IC_DEVICE_REV (AEh)

Definition: Reports device revision information.

Data Length in Bytes: 4

Data Format: CUS

Type: Block Read

Protectable: No

Default Value: 01000000h (initial release)

Units: N/A

COMMAND

Format

IC_DEVICE_REV (AEh)

Block Read

Byte Position

3

2

1

0

Function

Firmware Major

01h

Firmware Minor

00h

Factory Configuration

00h

Reserved

00h

Default Value

USER_DATA_00 (B0h)

Definition: Sets a user defined data string not to exceed 32bytes. The sum total of characters in MFR_ID, MFR_MODEL, MFR_REVISION,

MFR_LOCATION, MFR_DATE, MFR_SERIAL, and USER_DATA_00 plus one byte per command cannot exceed 128bytes. This limitation

includes multiple writes of this command before a STORE command. To clear multiple writes, perform a RESTORE, write this command

then perform a STORE/RESTORE.

Paged or Global: Global

Data Length in Bytes: User defined

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: Yes

Default Value: Null

Units: N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 61 of 91

ZL8802

MIN_VOUT_REG (CEh)

Definition: Sets the minimum output voltage in millivolts (mV) that the device will attempt to regulate to during start-up and shutdown

ramps.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: 0000h (0mV)

Units: A

N

Equation: MIN_VOUT_REG = Y x 2

COMMAND

Format

MIN_VOUT_REG (CEh)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

ISENSE_CONFIG (D0h)

Definition: Configures current sense circuitry.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W word

Protectable: Yes

Default Value: 620Eh (384ns blanking, SPS sensing, high range)

Units: N/A

Range: N/A

COMMAND

Format

ISENSE_CONFIG (D0h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 62 of 91

ZL8802

BIT

FIELD NAME

VALUE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

000

SETTING

DESCRIPTION

0

32

64

96

128

160

192

224

256

288

320

352

384

Current Sense Blanking

Time

15:11

416

Sets the blanking time current sense blanking time in increments of 32ns

448

480

512

544

576

608

640

672

704

736

768

800

832

1

001

3

010

5

7

Sets the number of consecutive overcurrent (OC) or undercurrent (UC) events

required for a fault. An event can occur once during each switching cycle. For

example, if 5 is selected, an OC or UC event must occur for 5 consecutive

switching cycles, resulting in a delay of at least 5 switching periods.

011

10:8 Current Sense Fault Count

100

9

101

11

110

13

111

15

7:4

3:2

Not Used

0000

00

Not Used

DCR (Down Slope)

DCR (Up Slope)

SPS

Not used

01

Current Sense Control

Selection of current sensing method (SPS IMON)

10

11

00

Low Range

Medium Range

High Range

Not Used

01

1:0

Current Sense Range

Low range ±25mV, medium range ±35mV, high range ±50mV

10

11

FN8760 Rev.3.00

Nov 8, 2017

Page 63 of 91

ZL8802

USER_CONFIG (D1h)

Definition: Configures several user-level features. This command should be saved immediately after being written to the desired user or

default store. This is recommended when written as an individual command or as part of a series of commands in a configuration file

or script.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: Set by CFG pin-strap setting

Units: N/A

COMMAND

Format

USER_CONFIG (D1h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

CFG Pin-strap Setting

Default Value

BIT

FIELD NAME

VALUE

SETTING

0-31d

DESCRIPTION

15:11 Minimum Duty Cycle 00000

Sets the minimum duty-cycle to 2X(VALUE+1)/512. Must be enabled with Bit 7

10

Not Used

1

00

0

1

0

1

0

1

0

1

0

1

0

1

Not Used

Disable

Enable

Not used

9:8

Minimum Duty Cycle

Control

7

6

5

4

3

Control for minimum duty cycle

Not Used

VSET Select

Not Used

VSET0

Not used

0 = Uses only VSET0 to set the pin-strapped output voltage

1 = Uses only VSET1 to set the pin-strapped output voltage

Not used

VSET1

Not Used

Low when disabled

High when disabled

Open-Drain

Push-Pull

PWML is low (off) when device is disabled (Bit 3 set to 0), or high (on) when device

is disabled (Bit 3 set to 1)

PWML disabled state

0 = PG is open-drain output

1 = PG is push-pull output

Power-good

Configuration

2

1

0

Disable

XTEMP Enable

Enable external temperature sensor

Enable

Disable

XTEMP Fault Select

Selects external temperature sensor to determine temperature faults

Enable

FN8760 Rev.3.00

Nov 8, 2017

Page 64 of 91

ZL8802

IIN_CAL_GAIN (D2h)

Definition: Sets the effective impedance across the current sense circuit for use in calculating input current at +25°C.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: C200h (2mΩ)

Units: mΩ

N

Equation: IIN_CAL_GAIN = Y×2

COMMAND

Format

IIN_CAL_GAIN (D2h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

DDC_CONFIG (D3h)

Definition: Configures DDC addressing and current sharing for up to 8 phases. To operate as a 2-phase controller, set both phases to the

same rail ID, set phases in rail to 2, then set each phase ID sequentially as 0 and 1. To operate as a 4-phase controller, set all phases to

the same rail ID, set phases in rail to 4, then set each phase ID alternately, for example, the first ZL8802 will be set to 0 and 2, the

second ZL8802 will be set to 1 and 3. The ZL8802 will automatically equally offset the phases in the rail. Phase spreading is done

automatically as part of the DDC_CONFIG command. When using CFG pin-strap settings, the DDC_CONFIG command is set

automatically.

NOTE: The output MUST be connected to VSEN0P and VSEN0N when operating as a 2-phase controller.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: PMBus address pin-strap dependent.

Units: N/A

COMMAND

Format

DDC_CONFIG (D3h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

Lower 5 bits of device address

0

BIT

15:13

12:8

7:3

FIELD NAME

Phase ID

VALUE

0 to 7

SETTING

DESCRIPTION

0

Sets the output's phase position within the rail

Rail ID

0 to 31d

00

Identifies the device as part of a current sharing rail (shared output)

Not used

Not Used

00

0

2:0

Phases In Rail

0 to 7

Identifies the number of phases on the same rail (+1)

FN8760 Rev.3.00

Nov 8, 2017

Page 65 of 91

ZL8802

POWER_GOOD_DELAY (D4h)

Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG pin. The

delay time can range from 0ms up to 500ms, in steps of 125ns. A 1ms minimum configured value is recommended to apply proper

debounce to this signal.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: BA00h, 1ms

Units: ms

N

Equation: POWER_GOOD_DELAY = Y×2

Range: 0 to 500ms

COMMAND

Format

POWER_GOOD_DELAY (D4h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

MULTI_PHASE_RAMP_GAIN (D5h)

Definition: Indirectly determines the output voltage rise time during the turn-on ramp. Typical gain values range from 1 to 10. Lower

gain values produce longer ramp times.

MULTI_PHASE_RAMP_GAIN mode is automatically selected when the ZLS8802 is configured to operate in a 4-phase current sharing

group. When in MULTI_PHASE_RAMP_GAIN mode, the turn-on ramp up is done with the high bandwidth ASCR control circuitry disabled,

resulting in a lower loop bandwidth during start-up ramps. After POWER_GOOD has been asserted, ASCR circuitry is enabled and the

ZLS8802 operates normally. When MULTI_PHASE_RAMP_GAIN mode is enabled, soft-off ramps are not allowed (TOFF_FALL is

ignored). When the ZL8802 is commanded to shutdown, the PWMHO/1 output is tri-stated, turning both the high-side and low-side

MOSFETs off, and the PWML0/1 pin is pulled low (DrMOS disabled). Large load current transitions during multiphase ramp-ups will

cause output voltage discontinuities.

When the phase count is 2; that is, when the ZL8802 is operating standalone, ASCR is enabled at all times and all commands

associated with turn-on and turn-off (TON_RISE, TOFF_FALL, Soft-Off) operate normally.

Rise time can be calculated using Equation 8:

RiseTime = VOUT_COMMAND  14  Input Voltage  FREQUENCY_SWITCH (in MHz)  MULTI_PHASE_RAMP_GAIN

(EQ. 8)

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Custom

Type: R/W

Protectable: Yes

Default Value: 03h

Units: N/A

COMMAND

Format

MULTI_PHASE_RAMP_GAIN (D5h)

1 Byte Binary

Bit Position

Access

7

R/W

0

6

R/W

0

5

R/W

0

4

R/W

0

3

R/W

0

2

R/W

0

1

R/W

1

0

R/W

1

Default Value

BIT

7:0

FIELD NAME

Gain

VALUE

00-FF

DESCRIPTION

Start-up ramp gain

FN8760 Rev.3.00

Nov 8, 2017

Page 66 of 91

ZL8802

INDUCTOR (D6h)

Definition: Informs the device of the circuit’s inductor value. This is used in adaptive algorithm calculations relating to the inductor

ripple current.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: B133h (0.3µH)

Units: µH

N

Equation: INDUCTOR = Y×2

Range: 0 to 100µH

COMMAND

Format

INDUCTOR (D6h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

1

SNAPSHOT_FAULT_MASK (D7h)

Definition: Prevents faults from causing a SNAPSHOT event (and store) from occurring.

Data Length in Bytes: 2

Data Format: BIT

Type: R/W

Protectable: Yes

Default Value: 0000h

Units: NA

Range: NA

COMMAND

Format

SNAPSHOT_FAULT_MASK (D7h)

Bit Field

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

4

3

R

2

R

1

R

0

R

Function

See Following Table

Default Value

0

BIT NUMBER

STATUS BIT NAME

Not Used

MEANING

15:14

13

12

11

10

9

Not used

Group

Ignore Fault Spreading faults

Ignore Other Phase faults

Ignore CPU faults

Phase

CPU

CRC

Ignore CRC Memory faults

Not used

Not Used

8

Not Used

Not used

7

IOUT_UC_FAULT

IOUT_OC_FAULT

VIN_UV_FAULT

VIN_OV_FAULT

UT_FAULT

Ignore output undercurrent faults

Ignore output overcurrent faults

Ignore input undervoltage faults

Ignore Input undervoltage faults

Ignore under-temperature faults

Ignore over-temperature faults

Ignore output undervoltage faults

Ignore output overvoltage faults

6

5

4

3

2

OT_FAULT

1

VOUT_UV_FAULT

VOUT_OV_FAULT

0

FN8760 Rev.3.00

Nov 8, 2017

Page 67 of 91

ZL8802

OVUV_CONFIG (D8h)

Definition: Configures the output voltage OV and UV fault detection feature

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h

Units: N/A

COMMAND

Format

OVUV_CONFIG (D8h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS

7

PURPOSE

VALUE

0

DESCRIPTION

Controls how an OV fault response shutdown sets the output

driver state

An OV fault does not enable low-side power device

An OV fault enables the low-side power device

Not used

1

0

6:4 Not Used

Defines the number of consecutive limit violations required to

declare an OV or UV fault

3:0

N

N+1 consecutive OV or UV violations initiate a fault response

XTEMP_SCALE (D9h)

Definition: Sets a scalar value that is used for calibrating the external temperature. The constant is applied in the equation below to

produce the read value of XTEMP through the PMBus command READ_TEMPERATURE_2.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: BA00h (1.0)

Units: 1/°C





1

Equation:

READ_TEMPERATURE_2  ExternalTemperature 

  XTEMP_OFFSET





XTEMP_SCALE





Range: 0.1 to 10

COMMAND

Format

XTEMP_SCALE (D9h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 68 of 91

ZL8802

XTEMP_OFFSET (DAh)

Definition: Sets an offset value that is used for calibrating the external temperature. The constant is applied in the equation below to

produce the read value of XTEMP through the PMBus command READ_TEMPERATURE_2.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: 0000h (0)

Units: °C



1



Equation:

READ_TEMPERATURE_2 ExternalTemperature

  XTEMP_OFFSET





XTEMP_SCALE





Range: -100°C to +100°C

COMMAND

Format

XTEMP_OFFSET (DAh)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

0

FN8760 Rev.3.00

Nov 8, 2017

Page 69 of 91

ZL8802

MFR_SMBALERT_MASK (DBh)

Definition: Used to prevent faults from activating the SALRT pin. The bits in each byte correspond to a specific fault type as defined in

the STATUS command.

Data Length in Bytes: 7

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00 00 00 00 00 00 00h (No faults masked)

Units: N/A

COMMAND

Format

MFR_SMBALT_MASK (DBh)

Bit Field

Access

R/W

Function

See following table

Bit Position

55

0

54

0

53

0

52

0

51

0

50

0

49

0

48

0

Default Value Byte 6

Bit Position

47

0

46

0

45

0

44

0

43

0

42

0

41

0

40

0

Default Value Byte 5

Bit Position

39

0

38

0

37

0

36

0

35

0

34

0

33

0

32

0

Default Value Byte 4

Bit Position

31

0

30

0

29

0

28

0

27

0

26

0

25

0

24

0

Default Value Byte 3

Bit Position

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

Default Value Byte 2

Bit Position

15

0

14

0

13

0

12

0

11

0

10

0

9

8

Default Value Byte 1

Bit Position

0

7

6

5

4

3

2

1

0

Default Value Byte 0

0

BYTE

STATUS BYTE NAME

STATUS_MFR_SPECIFIC

STATUS_OTHER

MEANING

6

5

4

Mask manufacturer specific faults as identified in the STATUS_MFR_SPECIFIC byte.

Not used

STATUS_CML

Mask communications, memory, or logic specific faults as identified in the STATUS_CML

byte.

3

2

1

0

STATUS_TEMPERATURE

STATUS_INPUT

Mask temperature specific faults as identified in the STATUS_TEMPERATURE byte.

Mask input specific faults as identified in the STATUS_INPUT byte.

STATUS_IOUT

Mask output current specific faults as identified in the STATUS_IOUT byte.

Mask output voltage specific faults as identified in the STATUS_VOUT byte.

STATUS_VOUT

FN8760 Rev.3.00

Nov 8, 2017

Page 70 of 91

ZL8802

TEMPCO_CONFIG (DCh)

Definition: Configures the correction factor and temperature measurement source when performing temperature coefficient correction

for current sense. TEMPCO_CONFIG values are applied as negative correction to a positive temperature coefficient. TEMPCO_CONFIG

should be set to 3900ppm (27h) when using inductor DCR current sensing to compensate for the variation in inductor resistance due to

the temperature coefficient of copper. When using the ISL9922X Smart Power Stage, TEMPCO_CONFIG should be set to 0ppm (00h)

because the IMON signal from the ISL9922X is internally compensated for temperature.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h (0ppm/°C, copper)

Equation: To determine the hex value of the Tempco Correction factor (TC) for current scale of a power stage current sensing, first

determine the temperature coefficient of resistance for the sensing element, α. This is found with Equation 9:

R_REF R

 

(EQ. 9)

R_REF(T_REFT )

Where:

R = Sensing element resistance at temperature “T”

R

= Sensing element resistance at reference temperature T

REF

α = Temperature coefficient of resistance for the sensing element material

T = Temperature measured by temperature sensor, in degrees Celsius

T

= Reference temperature that α is specified at for the sensing element material

REF

After α is determined, convert the value in units of 100ppm/°C. This value is then converted to a hex value with Equation 10:

 10⁶

(EQ. 10)

TC 

100

Range: 0 to 12700ppm/˚C

COMMAND

Format

TEMPCO_CONFIG (DCh)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BITS

7

PURPOSE

VALUE

0

DESCRIPTION

Selects the internal temperature sensor.

Selects the temp sensor source for tempco correction

Selects the XTEMP pin for temperature measurements (2N3904 Junction).

Note that XTEMP must be enabled in USER_CONFIG, Bit 1.

1

Sets the tempco correction in units of 100ppm/˚C for

IOUT_CAL_GAIN

RSEN (DCR) = IOUT_CAL_GAIN x (1+TC x (T-25))

where RSEN = resistance of sense element.

6:0

TC

FN8760 Rev.3.00

Nov 8, 2017

Page 71 of 91

ZL8802

PINSTRAP_READ_STATUS (DDh)

Definition: Reads back 7 bytes of 8-bit values that represent the pin-strap settings of each of the device’s pin-strap pins. This value

corresponds to a resistor value, a high, a low, or an open condition. The pin decode values correspond to pin-strap settings according to

Table 9:

TABLE 9. PIN DECODE VALUES

R (kΩ)

10

DECODE

R (kΩ)

51.1

56.2

61.9

68.1

75

DECODE

11

12

13

14

15

16

00

11

01

12.1

13.3

14.7

16.2

17.8

19.6

21.5

23.7

26.1

28.7

31.6

34.8

38.3

42.2

46.4

02

03

04

05

82.5

90.9

100

06

17

07

18

19

1A

1B

1C

08

110

09

121

0A

133

147

0B

0C

162

1D

1E

0D

178

0E

LOW

OPEN

HIGH

F1

0F

F2

10

F3

Unmeasured

F4

Paged or Global: Global

Data Length in Bytes: 7

Data Format: Bit Field

Type: Read Only

Protectable: Yes

Default Value: Pin-strap settings

Units: N/A

COMMAND

Format

READ_PINSTRAP (DDh)

Bit Field

Bit Position

Access

55

R

54

R

53

R

52

R

51

R

50

R

49

R

48

R

Function

ASCRCFG Pin Decode

ASCRCFG Pin-strap Setting

Default Value

Format

Bit Field

Bit Position

Access

47

R

46

R

45

R

44

R

43

R

42

R

41

R

40

R

39

R

38

R

37

R

36

R

35

R

34

R

33

R

32

R

Function

CFG Pin Decode

CFG Pin-strap Setting

SYNC Pin Decode

Default Value

Format

SYNC Pin-strap Setting

Bit Field

FN8760 Rev.3.00

Nov 8, 2017

Page 72 of 91

ZL8802

COMMAND

Bit Position

Access

READ_PINSTRAP (DDh) (Continued)

31

R

30

R

29

R

28

R

27

R

26

R

25

R

24

R

23

R

22

R

21

R

20

R

19

R

18

R

17

R

16

R

Function

UVLO Pin Decode

VSET0 Pin Decode

VSET0 Pin-strap Setting

Default Value

Format

UVLO Pin-strap Setting

Bit Field

Bit Position

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

VSET1 Pin Decode

Reserved

N/A

Default Value

VSET1 Pin-strap Setting

BITS

55:48

47:40

39:32

31:24

23:16

15:8

PURPOSE

VALUE

00-F4h

FF

DESCRIPTION

ASCRCFG Pin Decode

Decode value of ASCRCFG pin-strap setting.

Decode value of CFG pin-strap setting.

Decode value of SYNC pin-strap setting.

Decode value of UVLO pin-strap setting.

Decode value of VSET0 pin-strap setting.

Decode value of VSET1 pin-strap setting.

Not used

CFG Pin Decode

SYNC Pin Decode

UVLO Pin Decode

VSET0 Pin Decode

VSET1 Pin Decode

Not Used

7:0

FN8760 Rev.3.00

Nov 8, 2017

Page 73 of 91

ZL8802

ASCR_CONFIG (DFh)

Definition: Allows user configuration of ASCR settings. ASCR gain and residual value are automatically set by the ZL8802 based on

input voltage and output voltage. ASCR gain is analogous to bandwidth, ASCR residual is analogous to damping. To improve load

transient response performance, increase ASCR gain. To lower transient response overshoot, increase ASCR residual. Increasing ASCR

gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain can lead to excessive

output voltage ripple. Increasing ASCR residual to improve transient response damping can result in slower recovery times, but will not

affect the peak output voltage deviation. Typical ASCR gain settings range from 100 to 1000, and ASCR residual settings range from

10 to 90.

Paged or Global: Paged

Data Length in Bytes: 4

Data Format: Bit Field and nonsigned binary

Type: R/W

Protectable: Yes

Default Value: ASCRCFG pin-strap setting

Units: N/A

COMMAND

Format

ASCR_CONFIG (DFh)

Bit Field/Linear-8 Unsigned

Bit Position

Access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R/W

Function

See Following Table

1

Default Value

Format

0

ASCRCFG Pin-strap Setting (residual)

Linear-16 Unsigned

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

ASCRCFG Pin-strap Setting (gain)

BITS

PURPOSE

Not Used

VALUE

DESCRIPTION

31:25

0000000h

Not used

Enable

1

0

24

ASCR Enable

Disable

23:16

15:0

ASCR Residual Setting

ASCR Gain Setting

0 - 7Fh

0-FFh

ASCR residual

ASCR gain

FN8760 Rev.3.00

Nov 8, 2017

Page 74 of 91

ZL8802

SEQUENCE (E0h)

Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multirail sequencing. The device will enable its

output when its EN or OPERATION enable state, as defined by ON_OFF_CONFIG, is set and the prequel device has issued a Power-Good

event on the DDC bus as a result of the prequel’s Power-good (PG) signal going high. The device will disable its output (using the

programmed delay values) when the sequel device has issued a power-down event on the DDC bus at the completion of its ramp-down

(its output voltage is 0V).

The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The least-significant

byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of the prequel or

sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin settings.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h (prequel and sequel disabled)

Units: N/A

COMMAND

Format

SEQUENCE (E0h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BIT

FIELD NAME

VALUE

SETTING

Disable

Enable

DESCRIPTION

Disable, no prequel preceding this rail.

0

15

Prequel Enable

1

Enable, prequel to this rail is defined by Bits 12:8.

Not used

14:13

12:8

Not Used

0

0-31d

0

Not Used

DDC ID

Disable

Enable

Prequel Rail DDC ID

Set to the DDC ID of the prequel rail.

Disable, no sequel following this rail.

Enable, sequel to this rail is defined by Bits 4:0.

Not used

7

Sequel Enable

1

6:5

4:0

Not Used

0

Not Used

DDC ID

Sequel Rail DDC ID

0-31d

Set to the DDC ID of the sequel rail.

FN8760 Rev.3.00

Nov 8, 2017

Page 75 of 91

ZL8802

TRACK_CONFIG (E1h)

Definition: Configures the voltage tracking modes of the device. Single device (Channel 0, Channel 1 or 2-phase) tracking is supported.

Tracking as part of a 4-, 6- or 8-phase current sharing group is not supported. When tracking, the TOFF_DELAY in the tracking device

must be greater than TOFF_DELAY + TOFF_FALL in the device being tracked. When configured to track, VOUT_COMMAND must be set to

the desired steady state output voltage.

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 00h

Units: N/A

COMMAND

Format

TRACK_CONFIG (E1h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BIT

7

FIELD NAME

VALUE

SETTING

Disable

Enable

Not Used

100%

DESCRIPTION

0

Tracking is disabled.

Tracking is enabled.

Not used

Voltage Tracking Control

Not Used

1

6:3

2

0000

0

1

0

1

0

Output Tracks at 100% ratio of VTRK input.

Output Tracks at 50% ratio of VTRK input.

Output Voltage is Limited by Target Voltage.

Output Voltage is Limited by VTRK Voltage.

Not used

Tracking Ratio Control

50%

Target Voltage

VTRK Voltage

Not Used

1

0

Tracking Upper Limit

Not Used

FN8760 Rev.3.00

Nov 8, 2017

Page 76 of 91

ZL8802

DDC_GROUP (E2h)

Definition: Rails (output voltages) are assigned Group numbers to share specified behaviors. The DDC_GROUP command configures

fault spreading group ID and enable, broadcast OPERATION group ID and enable, and broadcast VOUT_COMMAND group ID and enable.

Note that DDC Groups are separate and unique from DDC Rail IDs (see “DDC_CONFIG (D3h)” on page 65). Current sharing rails need to

be in the same DDC Group to respond to broadcast VOUT_COMMAND and OPERATION commands. Power fail event responses (and

phases) are automatically spread in Phase 0 and 1 when the ZL8802 is operating in 2-phase current sharing mode when it is

configured using DDC_CONFIG, regardless of its setting in DDC_GROUP.

Paged or Global: Paged

Data Length in Bytes: 34

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: Set by CFG pin-strap setting

Units: N/A

COMMAND

Format

DDC_GROUP (E2h)

Bit Field

Bit Position

Access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R/W

EN>

R/W

Function

Not Used

VOUT_COMMAND Group ID

Default Value

Format

Set by CFG Pin-strap Setting

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

EN>

R/W

EN>

R/W

Function

Not Used

OPERATION Group ID

Not Used

Power Fail Group ID

Default Value

Set by CFG Pin-strap Setting

BITS

PURPOSE

Not Used

VALUE

DESCRIPTION

31:22

00

1

Not used

Responds to broadcast VOUT_COMMAND with same Group ID.

Ignores broadcast VOUT_COMMAND.

21

BROADCAST_VOUT_COMMAND response

0

20:16 BROADCAST_VOUT_COMMAND group ID

0-31d Group ID sent as data for broadcast VOUT_COMMAND events.

15:14

13

Not Used

00

1

Not used

Responds to broadcast OPERATION with same Group ID.

Ignores broadcast OPERATION.

BROADCAST_OPERATION response

0

12:8

7:6

BROADCAST_OPERATION group ID

Not Used

0-31d Group ID sent as data for broadcast OPERATION events.

00

1

Not used

Responds to POWER_FAIL events with same Group ID by shutting down immediately.

Responds to POWER_FAIL events with same Group ID with sequenced shutdown.

5

POWER_FAIL response

POWER_FAIL group ID

0

4:0

0-31d Group ID sent as data for broadcast POWER_FAIL events.

FN8760 Rev.3.00

Nov 8, 2017

Page 77 of 91

ZL8802

DEVICE_ID (E4h)

Definition: Returns the 16-byte (character) device identifier string. The format is: Part number, Major Revision, (period), Minor Revision,

Engineering version letter

Paged or Global: Global

Data Length in Bytes: 16

Data Format: ASCII. ISO/IEC 8859-1

Type: Block Read

Protectable: Read Only

Default Value: ZL8802, current major revision, (period), current minor revision, current engineering version letter

Units: N/A

COMMAND

Format

DEVICE_ID (E4h)

Characters (Bytes)

Characters

Access

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

Function

Part Number

Maj. Rev.

.

Min. Rev

Engr.

*

Default Value

Z

L

8

0

*

* Current revision at time of manufacture

MFR_IOUT_OC_FAULT_RESPONSE (E5h)

Definition: Configures the I overcurrent fault response as defined by the table below. The command format is the same as the

OUT

PMBus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT. The retry time is the time between restart

attempts.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 80h (immediate shutdown, no retries)

Units: Retry time unit = 35ms

COMMAND

Format

MFR_IOUT_OC_FAULT_RESPONSE (E5h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

DESCRIPTION

Response behavior, for all modes, the

device:

• Pulls SALRT low

• Sets the related fault bit in the

status registers. Fault bits are only

cleared by the CLEAR_FAULTS

command.

00

01

10

Not used

Disable without delay and retry according to the setting in bits 5:3.

Output is disabled while the fault is present. Operation resumes and the output is enabled

when the fault is no longer present.

11

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

5:3

2:0

Retry Setting

Retry Delay

Attempts to restart continuously, without checking if the fault is still present, until it is

commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is

removed, or another fault condition causes the unit to shut down. The time between the

start of each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments.

Range is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 78 of 91

ZL8802

MFR_IOUT_UC_FAULT_RESPONSE (E6h)

Definition: Configures the I

undercurrent fault response as defined by the table below. The command format is the same as the

OUT

PMBus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT. The retry time is the time between

restart attempts.

Data Length in Bytes: 1

Paged or Global: Paged

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: 80h (Immediate shutdown, no retries)

Units: Retry time unit = 35ms

COMMAND

Format

MFR_IOUT_UC_FAULT_RESPONSE (E6h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

BIT

7:6

FIELD NAME

VALUE

00

DESCRIPTION

Response behavior, for all modes, the device:

• Pulls SALRT low

• Sets the related fault bit in the status

registers. Fault bits are only cleared by the

CLEAR_FAULTS command.

Not used

01

10

Disable without delay and retry according to the setting in bits 5:3.

11

Output is disabled while the fault is present. Operation resumes and the output is

enabled when the fault is no longer present.

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

Attempts to restart continuously, without checking if the fault is still present, until it

5:3

2:0

Retry Setting

Retry Delay

is commanded OFF (by the CONTROL pin or OPERATION command or both), bias

power is removed, or another fault condition causes the unit to shut down. The time

between the start of each attempt to restart is set by the value in bits [2:0] multiplied

by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms

increments. Range is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 79 of 91

ZL8802

IOUT_AVG_OC_FAULT_LIMIT (E7h)

Definition: Sets the I

average overcurrent fault threshold. For down-slope sensing, this corresponds to the average of all the current

OUT

samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the beginning of the 1-D

interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval, excluding the

current sense blanking time (which occurs at the beginning of the D interval). This feature shares the OC fault bit operation (in

STATUS_IOUT) and OC fault response with IOUT_ OC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: CFG pin-strap setting

Units: Amperes

N

Equation: IOUT_AVG_OC_FAULT_LIMIT = Y×2

Range: -100A to 100A

COMMAND

Format

IOUT_AVG_OC_FAULT_LIMIT (E7h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

CFG Pin-strap Setting

IOUT_AVG_UC_FAULT_LIMIT (E8h)

Definition: Sets the I average undercurrent fault threshold. For down-slope sensing, this corresponds to the average of all the current

OUT

samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the beginning of the 1-D

interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time interval, excluding the

current sense blanking time (which occurs at the beginning of the D interval). This feature shares the UC fault bit operation (in

STATUS_IOUT) and UC fault response with IOUT_ UC_FAULT_LIMIT.

Paged or Global: Paged

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: -1 X IOUT_AVG_OC_FAULT_LIMIT as set by CFG pin-strap setting

Units: Amperes

N

Equation: IOUT_AVG_UC_FAULT_LIMIT = Y×2

Range: -100A to 100A

COMMAND

Format

IOUT_AVG_UC_FAULT_LIMIT (E8h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

-1 X IOUT_AVG_OC_FAULT_LIMIT as set by CFG Pin-strap Setting

Default Value

FN8760 Rev.3.00

Nov 8, 2017

Page 80 of 91

ZL8802

USER_GLOBAL_CONFIG (E9h)

Definition: Used to set options for output voltage sensing, VMON/TMON pin configuration, SMBus time-out, and DDC and SYNC output

configurations.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: Set by CFG pin-strap setting

Units: N/A

COMMAND

Format

USER_GLOBAL_CONFIG (E9h)

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Set by CFG Pin-strap Setting

Default Value

BITS

15:13

12

PURPOSE

Not Used

VALUE

DESCRIPTION

000000

0

Not used

VMON/TMON Config

MFR_READ_VMON returns voltage on VMON pin in Volts. External 16:1

voltage divider needed on VMON/TMON pin (pin 6) to voltage being

monitored.

1

READ_TEMPERATURE_3 returns TMON in °C. External 2:1 voltage divider

needed on VMON/TMON pin (pin 6) to SPS TMON pin.

11:10

9:8

Not Used

00

01

10-11

0

Not used

Output 0 uses VSEN0, Output 1 uses VSEN1

VSENSE Select for monitoring and fault

detection

Both outputs use VSEN0

Not used

7

6

5

4

3

Not Used

DDC output Configuration

Not Used

Not used

0

DDC output open-drain

1

DDC output push-pull

0

Not used

0

SMBus time-outs enabled

Disable SMBus Time-Outs

Not Used

1

SMBus time-outs disabled

0

Not used

00

01

10

11

0

Use internal clock (frequency initially set with pin-strap)

Use internal clock and output internal clock (not for use with pin-strap)

2:1

0

Sync I/O Control

Not Used

Use external clock

Not used

FN8760 Rev.3.00

Nov 8, 2017

Page 81 of 91

ZL8802

SNAPSHOT (EAh)

Definition: A 32-byte read-back of parametric and status values. It allows monitoring and status data to be stored to flash either during

a fault condition or through a system-defined time using the SNAPSHOT_CONTROL command. Snapshot is continuously updated in

RAM and can be read using the SNAPSHOT command. When a fault occurs, the latest snapshot in RAM is stored to flash. Snapshot

data can read back by writing a 01h to the SNAPSHOT_CONTROL command, then reading SNAPSHOT.

Paged or Global: Paged

Data Length in Bytes: 32

Data Format: Bit Field

Type: Block Read

Protectable: No

Default Value: N/A

Units: N/A

BYTE NUMBER

VALUE

Not Used

PMBus COMMAND

Not Used

FORMAT

0000h

31:23

22

Flash Memory Status Byte

Manufacturer Specific Status Byte

CML Status Byte

N/A

Bit Field

21

STATUS_MFR_SPECIFIC (80h)

STATUS_CML (7Eh)

STATUS_TEMPERATURE (7Dh)

STATUS_INPUT (7Ch)

STATUS_IOUT (7Bh)

STATUS_VOUT (7Ah)

READ_FREQUENCY (95h)

READ_TEMPERATURE_2 (8Eh)

READ_TEMPERATURE_1 (8Dh)

READ_DUTY_CYCLE (94h)

N/A

1 Byte Bit Field

2 Byte Linear-11

2 Byte Linear-16 Unsigned

2 Byte Linear-11

20

19

Temperature Status Byte

Input Status Byte

18

17

I

Status Byte

OUT

16

V

OUT

15:14

13:12

11:10

9:8

Switching Frequency

External Temperature

Internal Temperature

Duty Cycle

7:6

Highest Measured Output Current

Output Current

5:4

READ_IOUT (8Ch)

3:2

Output Voltage

READ_VOUT (8Bh)

1:0

Input Voltage

READ_VIN (88h)

FN8760 Rev.3.00

Nov 8, 2017

Page 82 of 91

ZL8802

LEGACY_FAULT_GROUP (F0h)

Definition: Allows the ZL8802 to sequence and fault spread with devices other than the ZL8800 family of ICs. This command sets

which rail DDC IDs should be listened to for fault spreading information. The data sent is a 4-byte, 32-bit bit vector where every bit

represents a rail’s DDC ID. A bit set to 1 indicates a device DDC ID to which the configured device will respond upon receiving a fault

spreading event. In this vector, bit 0 of byte 0 corresponds to the rail with DDC ID 0. Following through, Bit 7 of byte 3 corresponds to the

rail with DDC ID 31.

NOTE: The device/rail’s own DDC ID should not be set within the LEGACY_FAULT_GROUP command for that device/rail.

All devices in a current share rail (devices other than the ZL8800 family ICs) must shut down for the rail to report a shutdown.

If fault spread mode is enabled in USER_CONFIG, the device will immediately shut down if on of its DDC_GROUP members fail. The

device/rail will attempt its configured restart only after all devices/rails within the DDC_GROUP have cleared their faults.

If fault spread mode is disabled in USER_CONFIG, the device will perform a sequenced shutdown as defined by the SEQUENCE

command setting. The rails/devices in a sequencing set only attempt their configured restart after all faults have cleared within the

DDC_GROUP. If fault spread mode is disabled and sequencing is also disabled, the device will ignore faults from other devices and stay

enabled.

Paged or Global: Paged

Data Length in Bytes: 4

Data Format: Bit field

Type: Block R/W

Protectable: Yes

Default Value: 00000000h

Units: N/A

COMMAND

Format

LEGACY_FAULT_GROUP (F0h)

Bit Field

Bit Position

Access

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R/W

Function

See Following Table

Default Value

Format

0

Bit Field

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

BIT

FIELD NAME

Fault Group

VALUE

NA

SETTING

DESCRIPTION

31:0

00000000h Identifies the devices in the fault spreading group.

FN8760 Rev.3.00

Nov 8, 2017

Page 83 of 91

ZL8802

SNAPSHOT_CONTROL (F3h)

Definition: Writing a 01h will cause the device to copy the current SNAPSHOT values from NVRAM to the 32-byte SNAPSHOT command

parameter. Writing a 02h will cause the device to write the current SNAPSHOT values to NVRAM, 03h will erase all SNAPSHOT values

from NVRAM. Write (02h) and Erase (03h) can only be used when the device is disabled. All other values will be ignored. SNAPSHOT

03h must be written to the device when the device is DISABLED. Data will not be updated, or written to NVRAM after a fault occurs until

the SNAPSHOT 03h command has been written.

Paged or Global: Paged

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W Byte

Protectable: Yes

Default Value: 00h

Units: N/A

COMMAND

Format

SNAPSHOT_CONTROL (F3h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

0

VALUE

01

DESCRIPTION

Read SNAPSHOT values from NVRAM

Write SNAPSHOT values to NVRAM

Erase SNAPSHOT values from NVRAM

02

03

RESTORE_FACTORY (F4h)

Definition: Restores the device to the hard-coded factory default values and pin-strap definitions. The device retains the DEFAULT and

USER stores for restoring. Security level is changed to Level 1 following this command.

Paged or Global: Global

Data Length in Bytes: 0

Data Format: N/A

Type: Write Only

Protectable: Yes

Default Value: N/A

Units: N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 84 of 91

ZL8802

MFR_VMON_OV_FAULT_LIMIT (F5h)

Definition: Sets the VMON over-temperature fault threshold. The VMON overvoltage warn limit is automatically set to 90% of this fault

value. If VMON is not used, set VMON_OV_FAULT_RESPONSE to 00h, which will disable VMON OV faults entirely.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: C266h (2.4V)

Units: Volts

N

Equation: MFR_VMON_OV_FAULT_LIMIT = Y×2

Range: 0 to 20V

COMMAND

Format

MFR_VMON_OV_FAULT_LIMIT (F5h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

MFR_VMON_UV_FAULT_LIMIT (F6h)

Definition: Sets the VMON undervoltage fault threshold. The VMON undervoltage warn limit is automatically set to 110% of this fault

value. If VMON is not used, set VMON_UV_FAULT_RESPONSE to 00h, which will disable VMON UV faults entirely.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: Yes

Default Value: B0CCh (0.2V)

Units: Volts

N

Equation: MFR_VMON_UV_FAULT_LIMIT = Y x 2

Range: 0 to 20V

COMMAND

Format

MFR_VMON_UV_FAULT_LIMIT (F6h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

Signed Mantissa, Y

Default Value

1

0

1

0

1

0

1

0

FN8760 Rev.3.00

Nov 8, 2017

Page 85 of 91

ZL8802

MFR_READ_VMON (F7h)

Definition: Reads the voltage on the VMON pin.

Paged or Global: Global

Data Length in Bytes: 2

Data Format: Linear-11

Type: R/W

Protectable: No

Default Value: N/A

Units: °C

N

Equation: MFR_READ_VMON = Y x 2

Range: -200°C to +200°C

COMMAND

Format

MFR_READ_VMON (F7h)

Linear-11

Bit Position

Access

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R/W

Function

Signed Exponent, N

N/A N/A N/A

Signed Mantissa, Y

N/A N/A N/A

Default Value

N/A

VMON_OV_FAULT_RESPONSE (F8h)

Definition: Configures the VMON overvoltage fault response as defined by the table below. Note: The retry time is the time between

restart attempts. If VMON is not used, set this response to 00h, which will disable VMON OV faults entirely.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: BFh (continuous retries)

Units: N/A

COMMAND

Format

VMON_OV_FAULT_RESPONSE (F8h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

1

BIT

FIELD NAME

VALUE

DESCRIPTION

00

01

10

Ignore faults

Not used

Response behavior, the device:

• Pulls SALRT low

7:6 • Sets the related fault bit in the status

registers. Fault bits are only cleared by the

CLEAR_FAULTS command.

Disable without delay and retry according to the setting in bits 5:3.

Output is disabled while the fault is present. Operation resumes and the output is enabled

when VMON falls below 95% of the VMON_OV_FAULT_LIMIT setting.

11

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

Attempts to restart continuously, without checking if the fault is still present, until it is

5:3

2:0

Retry Setting

Retry Delay

commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is

removed, or another fault condition causes the unit to shut down. A retry is attempted after

VMON falls below 95% of the VMON_OV_FAULT_LIMIT. The time between the start of each

attempt to restart is set by the value in bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments.

Range is 35ms to 280ms.

000-111

FN8760 Rev.3.00

Nov 8, 2017

Page 86 of 91

ZL8802

VMON_UV_FAULT_RESPONSE (F9h)

Definition: Configures the VMON undervoltage fault response as defined by the table below. Note: The retry time is the time between

restart attempts. If VMON is not used, set this response to 00h, which will disable VMON UV faults entirely.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Bit Field

Type: R/W

Protectable: Yes

Default Value: BFh (continuous retries)

Units: Retry time unit = 35ms

COMMAND

Format

VMON_UV_FAULT_RESPONSE (F9h)

Bit Field

Bit Position

Access

7

6

5

4

3

2

1

0

R/W

Function

See Following Table

Default Value

1

0

1

BIT

7:6

FIELD NAME

VALUE

DESCRIPTION

Response behavior, the device:

• Pulls SALRT low

• Sets the related fault bit in the

status registers. Fault bits are only

cleared by the CLEAR_FAULTS

command.

00

01

10

Fault ignored

Not used

Disable without delay and retry according to the setting in bits 5:3.

Output is disabled while the fault is present. Operation resumes and the output is enabled

when VMON rises above 105% of the VMON_UV_FAULT_LIMIT setting.

11

000

No retry. The output remains disabled until the fault is cleared.

001-110 Not used

Attempts to restart continuously, without checking if the fault is still present, until it is

5:3

2:0

Retry Setting

Retry Delay

commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is

removed, or another fault condition causes the unit to shut down. A retry is attempted after

VMON has risen above 105% of VMON_UV_FAULT_LIMIT. The time between the start of

each attempt to restart is set by the value in bits [2:0] multiplied by 35ms.

111

Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms increments.

Range is 35ms to 280ms.

000-111

SECURITY_LEVEL (FAh)

Definition: The device provides write protection for individual commands. Each bit in the UNPROTECT parameter controls whether its

corresponding command is writable (commands are always readable). If a command is not writable, a password must be entered to

change its parameter (that is, to enable writes to that command). Passwords can be either public or private. The public password provides

a simple lock-and-key protection against accidental changes to the device. It would typically be sent to the device in the application before

making changes. Private passwords allow commands marked as nonwritable in the UNPROTECT parameter to be changed. Private

passwords are intended for protecting default-installed configurations and would not typically be used in the application. Each store (USER

and DEFAULT) can have its own UNPROTECT string and private password. If a command is marked as nonwritable in the DEFAULT

UNPROTECT parameter (its corresponding bit is cleared), the private password in the DEFAULT store must be sent to change that

command. If a command is writable according to the default UNPROTECT parameter, it may still be marked as nonwritable in the user

store UNPROTECT parameter. In this case, the user private password can be sent to make the command writable.

The device supports four levels of security. Each level is designed to be used by a particular class of users, ranging from module

manufacturers to end users, as discussed below. Levels 0 and 1 correspond to the public password. All other levels require a private

password. Writing a private password can only raise the security level. Writing a public password will reset the level down to 0 or 1.

Figure 12 on page 88 shows the algorithm used by the device to determine if a particular command write is allowed.

Paged or Global: Global

Data Length in Bytes: 1

Data Format: Hex

Type: Read Byte

Protectable: No

Default Value: 01h

Units: N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 87 of 91

ZL8802

Write

Attempted

Always

Writeable

?

Y

N

Read

Only

?

Y

N

Security

Level == 3

?

Y

N

Default

UNPROTECT

Y

== 0

?

N

Security

Level == 2

?

Y

N

User

UNPROTECT

Y

== 0

?

N

Security

Level == 1

?

Write

Prohibited

Write

Allowed

N

Y

FIGURE 12. ALGORITHM TO DETERMINE WHEN A COMMAND IS WRITABLE

Security Level 3 – Module Vendor

Level 3 is intended primarily for use by module vendors to protect device configurations in the default store. Clearing a UNPROTECT bit

in the default store implies that a command is writable only at Level 3 and above. The device’s security level is raised to Level 3 by

writing the private password value previously stored in the default store. To be effective, the module vendor must clear the UNPROTECT

bit corresponding to the STORE_DEFAULT_ALL and RESTORE_DEFAULT commands. Otherwise, Level 3 protection is ineffective because

the entire store could be replaced by the user, including the enclosed private password.

FN8760 Rev.3.00

Nov 8, 2017

Page 88 of 91

ZL8802

Security Level 2 – User

Level 2 is intended for use by the end user of the device. Clearing a UNPROTECT bit in the user store implies that a command is writable

only at Level 2 and above. The device’s security level is raised to Level 2 by writing the private password value previously stored in the

User Store. To be effective, the user must clear the UNPROTECT bit corresponding to the STORE_USER_ALL, RESTORE_DEFAULT_ALL,

STORE_DEFAULT_ALL, and RESTORE_DEFAULT commands. Otherwise, Level 2 protection is ineffective because the entire store could

be replaced, including the enclosed private password.

Security Level 1 – Public

Level 1 is intended to protect against accidental changes to ordinary commands by providing a global write-enable. It can be used to

protect the device from erroneous bus operations. It provides access to commands whose UNPROTECT bit is set in both the default and

User Store. Security is raised to Level 1 by writing the public password stored in the user store using the PUBLIC_PASSWORD command.

The public password stored in the default store has no effect.

Security Level 0 - Unprotected

Level 0 implies that only commands which are always writable (e.g., PUBLIC_PASSWORD) are available. This represents the lowest

authority level and hence the most protected state of the device. The level can be reduced to 0 by using PUBLIC_PASSWORD to write

any value which does not match the stored public password.

PRIVATE_PASSWORD (FBh)

Definition: Sets the private password string.

Paged or Global: Global

Data Length in Bytes: 9

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: No

Default Value: 000000000000000000h

Units: N/A

PUBLIC_PASSWORD (FCh)

Definition: Sets the public password string.

Paged or Global: Global

Data Length in Bytes: 4

Data Format: ASCII. ISO/IEC 8859-1

Type: Block R/W

Protectable: No

Default Value: 00000000h

Units: N/A

UNPROTECT (FDh)

Definition: Sets a 256-bit (32-byte) parameter which identifies which commands are to be protected against write-access at lower

security levels. Each bit in this parameter corresponds to a command according to the command’s code. The command with a code of

00h (PAGE) is protected by the least-significant bit of the least-significant byte, followed by the command with a code of 01h and so

forth. Note that all possible commands have a corresponding bit regardless of whether they are protectable or supported by the device.

Clearing a command’s UNPROTECT bit indicates that write-access to that command is only allowed if the device’s security level has

been raised to an appropriate level. The UNPROTECT bits in the default store require a security level 3 or greater to be writable. The

UNPROTECT bits in the user store require a security level of 2 or higher.

Data Length in Bytes: 32

Paged or Global: Global

Data Format: Custom

Type: Block R/W

Protectable: No

Default Value: FF…FFh

Units: N/A

FN8760 Rev.3.00

Nov 8, 2017

Page 89 of 91

ZL8802

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure

you have the latest revision.

DATE

REVISION

FN8760.3

CHANGE

Nov 8, 2017

Changed all SPS references from ISL99227 to ISL99227B.

Added an explanation of the EN0 and EN1 timing restrictions to “Enable Pin Operation and Timing” on

page 16.

Updated to the current Renesas format.

May 25, 2017

FN8760.2

Changed ISL99226 to ISL99227 in Figure 1 on page 3.

Added Related Literature section.

Updated disclaimer.

Dec 11, 2015

Aug 6, 2015

FN8760.1

FN8760.0

Added Junction Temperature to the “Thermal Information” on page 8.

Added ZL8802ALAFT7A to the ordering information table on page 7.

Initial release

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.

For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information

page found at www.intersil.com.

For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.

You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

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For information regarding Intersil Corporation and its products, see www.intersil.com

FN8760 Rev.3.00

Nov 8, 2017

Page 90 of 91

ZL8802

For the most recent package outline drawing, see L44.7x7B.

Package Outline Drawing

L44.7x7B

44 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 10/09

5.00 TYP

7.00

A

40X 0.50

6

B

44

PIN #1

INDEX

AREA

34

1

6

33

PIN 1

INDEX

AREA

5.20 ±0.1

EXP. DAP

23

11

44X 0.25 4

0.10 M C A B

(4X)

0.15

22

12

SIDE VIEW

TOP VIEW

5.20 ±0.1 EXP. DAP

BOTTOM VIEW

44X 0.55 ±0.1

( 6.65 )

SEE DETAIL "X"

( 5.20)

0.10C

C

1.00 MAX

0.08C

SIDE VIEW

( 6.65 )

( 5.20 )

( 40X 0.50)

5

C

0.2 REF

(44X .25)

0 . 00 MIN.

0 . 05 MAX.

( 44 X 0.75)

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

Complies to JEDEC MO220 VKKD-1.

7.

FN8760 Rev.3.00

Nov 8, 2017

Page 91 of 91


型号：	ZL8802ALAFT7A
厂家：	RENESAS TECHNOLOGY CORP
描述：	Dual Channel/Dual Phase PMBus ChargeMode Control DC/DC Digital Controller
文件：	总91页 (文件大小：3019K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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