X9428WV14-2.7 [INTERSIL]
Single Digitally Controlled Potentiometer; 单数字控制电位器
| 型号： | X9428WV14-2.7 |
| 厂家： | 
Intersil |
| 描述： | Single Digitally Controlled Potentiometer |
| 文件： | 总21页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9428
Low Noise/Low Power/2-Wire Bus
®
April 26, 2006
FN8197.1
DESCRIPTION
The X9428 integrates
Single Digitally Controlled Potentiometer
(XDCP™)
a
digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
FEATURES
• Solid state potentiometer
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer wiper position
—Store as many as four positions per
potentiometer
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
• Power supplies
—V
= 2.7V to 5.5V
CC
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for battery operated applications
• High reliability
The XDCP can be used as
a three-terminal
—Endurance–100,000 Data changes per bit per
register
—Register data retention–100 years
• 4-bytes of nonvolatile memory
• 10kΩ resistor array
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• Resolution: 64 taps each potentiometer
• 16 Ld SOIC, 14 Ld TSSOP packages
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
V
V
CC
SS
V+
V–
R0 R1
R2 R3
V /R
H
H
SCL
Wiper
Counter
Register
(WCR)
Interface
and
Control
SDA
A0
V /R
8
L
L
A2
A3
Circuitry
V
/R
W
Data
W
WP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9428
Ordering Information
PART
MARKING
POTENTIOMETER
LIMITS (V) ORGANIZATION (kΩ)
TEMP. RANGE
(°C)
PART NUMBER
X9428WS16*
V
PACKAGE
PKG. DWG. #
CC
X9428WS
X9428WS16Z* (Note) X9428WS Z
5 to ±10%
10
0 to +70
0 to +70
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3
(Pb-free)
X9428WS16I*
X9428WS I
-40 to +85
-40 to +85
16 Ld SOIC (300 mil) M16.3
X9428WS16IZ* (Note) X9428WS ZI
16 Ld SOIC (300 mil) M16.3
(Pb-free)
X9428WV14*
X9428 W
0 to +70
0 to +70
14 Ld TSSOP
(4.4mm)
M14.173
X9428WV14Z* (Note) X9428 Z
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
X9428WV14I*
X9428 WI
-40 to +85
-40 to +85
14 Ld TSSOP
(4.4mm)
X9428WV14IZ* (Note) X9428 ZI
14 Ld TSSOP
(4.4mm) (Pb-free)
X9428YS16*
X9428YS
2
0 to +70
0 to +70
16 Ld SOIC (300 mil) M16.3
X9428YS16Z* (Note)
X9428YS Z
16 Ld SOIC (300 mil) M16.3
(Pb-free)
X9428YS16I*
X9428YS I
-40 to +85
-40 to +85
16 Ld SOIC (300 mil) M16.3
X9428YS16IZ* (Note) X9428YS ZI
16 Ld SOIC (300 mil) M16.3
(Pb-free)
X9428YV14*
X9428 Y
X9428 YZ
X9428 YI
0 to +70
0 to +70
14 Ld TSSOP
(4.4mm)
M14.173
X9428YV14Z* (Note)
X9428YV14I*
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
-40 to +85
-40 to +85
14 Ld TSSOP
(4.4mm)
X9428YV14IZ* (Note) X9428 YZI
14 Ld TSSOP
(4.4mm) (Pb-free)
X9428WS16-2.7*
X9428WS F
2.7 to 5.5
10
0 to +70
0 to +70
16 Ld SOIC (300 mil) M16.3
X9428WS16Z-2.7*
(Note)
X9428WS ZF
16 Ld SOIC (300 mil) M16.3
(Pb-free)
X9428WS16I-2.7*
X9428WS G
-40 to +85
-40 to +85
16 Ld SOIC (300 mil) M16.3
X9428WS16IZ-2.7*
(Note)
X9428WS ZG
16 Ld SOIC (300 mil) M16.3
(Pb-free)
X9428WV14-2.7*
X9428 WF
X9428 ZF
X9428 WG
X9428 ZG
0 to +70
0 to +70
14 Ld TSSOP
(4.4mm)
M14.173
X9428WV14Z-2.7*
(Note)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
X9428WV14I-2.7*
-40 to +85
-40 to +85
14 Ld TSSOP
(4.4mm)
X9428WV14IZ-2.7*
(Note)
14 Ld TSSOP
(4.4mm) (Pb-free)
X9428YS16-2.7*
X9428YS F
2
0 to +70
0 to +70
16 Ld SOIC (300 mil) M16.3
X9428YS16Z-2.7*
(Note)
X9428YS ZF
16 Ld SOIC (300 mil) M16.3
(Pb-free)
FN8197.1
April 26, 2006
2
X9428
Ordering Information (Continued)
PART
POTENTIOMETER
LIMITS (V) ORGANIZATION (kΩ)
TEMP. RANGE
(°C)
PART NUMBER
MARKING
X9428YS G
X9428YS ZG
V
PACKAGE
PKG. DWG. #
CC
X9428YS16I-2.7*
2.7 to 5.5
2
-40 to +85
-40 to +85
16 Ld SOIC (300 mil) M16.3
X9428YS16IZ-2.7*
(Note)
16 Ld SOIC (300 mil) M16.3
(Pb-free)
X9428YV14-2.7*
X9428 YF
X9428 YZF
X9428 YG
X9428 YZG
0 to +70
0 to +70
14 Ld TSSOP
(4.4mm)
M14.173
X9428YV14Z-2.7*
(Note)
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
M14.173
M14.173
X9428YV14I-2.7*
-40 to +85
-40 to +85
14 Ld TSSOP
(4.4mm)
X9428YV14IZ-2.7*
(Note)
14 Ld TSSOP
(4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8197.1
April 26, 2006
3
X9428
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
PIN CONFIGURATION
DIP/SOIC
X9428
V+
NC
A0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
A2
The SCL input is used to clock data into and out of the
X9428.
R /V
L
L
NC
A3
R /V
H
H
Serial Data (SDA)
R
/V
W
W
SCL
NC
V-
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
SDA
WP
V
SS
TSSOP
X9428
V
Device Address (A , A , A )
A2
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
0
2
3
R
L
V+
The Address inputs are used to set the least
significant 3 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9428. A maximum of 8
devices may occupy the 2-wire serial bus.
A0
R
H
NC
A3
R
W
SDA
WP
SCL
V-
V
8
SS
Potentiometer Pins
PIN NAMES
R /V , R /V
L
H
H
L
The R /V and R /V inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
H
H
L
L
Symbol
SCL
Description
Serial clock
Serial data
SDA
R /V
W
W
A0, A2, A3
Device address
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
R /V , V /R
Potentiometer Pins
(terminal equivalent)
H
H
L
H
R /V
W
Potentiometer Pin (wiper equivalent)
Hardware write protection
Analog and voltage follower
System supply voltage
System ground
W
Hardware Write Protect Input WP
WP
The WP pin when low prevents nonvolatile writes to
the Data Registers.
V+,V-
V
CC
Analog Supply V+, V-
V
SS
NC
The Analog Supply V+, V- are the supply voltages for
the XDCP analog section.
No connection
FN8197.1
April 26, 2006
4
X9428
PRINCIPLES OF OPERATION
The X9428 is highly integrated microcircuit
incorporating a resistor array and its associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
The X9428 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9428 will respond with a final acknowledge.
a
Array Description
The X9428 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are
connected in series. The physical ends of the array
are equivalent to the fixed terminals of a mechanical
Serial Interface
The X9428 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9428 will be considered a
slave device in all applications.
potentiometer (V /R and V /R inputs).
H
H
L
L
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within each individual array only one
W
W
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.
Start Condition
Device Addressing
All commands to the X9428 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9428
this is fixed as 0101[B].
). The X9428 continuously
HIGH
Figure 1. Slave Address
Stop Condition
Device Type
Identifier
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
0
1
0
1
A3
A2
0
A0
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A , A , A inputs. The X9428
0
2
3
compares the serial data stream with the address
input state; a successful compare of all four address
bits is required for the X9428 to respond with an
acknowledge. The A , A , A inputs can be actively
0
2
3
driven by CMOS input signals or tied to V
or V
.
CC
SS
FN8197.1
April 26, 2006
5
X9428
Acknowledge Polling
Figure 2. Instruction Byte Format
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9428
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9428 is still busy with the write operation no ACK will
be returned. If the X9428 has completed the write
operation an ACK will be returned, and the master can
then proceed with the next operation.
Register
Select
I3
I2
I1
I0
R1 R0
0
0
Instructions
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. Bits 0 and 1 are defined to be 0.
Flow 1. ACK Polling Sequence
Four of the seven instructions end with the transmission
of the instruction byte. The basic sequence is illustrated
in Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the
Data Registers. A transfer from a Data Register to a
Wiper Counter Register is essentially a write to a static
RAM. The response of the wiper to this action will be
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
delayed t
. A transfer from the Wiper Counter
WRL
Register (current wiper position), to a Data Register is a
write to nonvolatile memory and takes a minimum of
t
to complete.
Issue Slave
Issue STOP
Address
WR
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9428; either between the host and one of
the Data Registers or directly between the host and the
Wiper Counter Register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected
nonvolatile register) and write Data Register (write a
new value to the selected Data Register). The
sequence of operations is shown in Figure 4.
ACK
Returned?
NO
YES
NO
Further
Operation?
YES
Issue
Instruction
Issue STOP
Proceed
Proceed
Instruction Structure
The next byte sent to the X9428 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of four associated registers. The format is
shown below in Figure 2.
FN8197.1
April 26, 2006
6
X9428
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3 I2
I1 I0 R1 R0
0
0
A
C
K
S
T
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9428 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
move one resistor segment towards the V /R
H H
terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the V /R terminal. A detailed
L
L
illustration of the sequence and timing for this
operation are shown in Figures 5 and 6 respectively.
(t
) while SDA is HIGH, the selected wiper will
HIGH
Table 1. Instruction Set
Instruction Set
Instruction
I
I
I
I
R
R
X
X
0
Operation
3
2
1
0
1
0
1
Read Wiper Counter
Register
1
0
0
0
1
1
1
0
0
1
0
0
0
0
Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
1
1
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write new value to the Wiper Counter Register
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
1/0 1/0
Read the contents of the Data Register pointed to by
R - R
1
0
Write Data Register
Write new value to the Data Register pointed to by
R - R
1
0
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register pointed to
by R - R to its Wiper Counter Register
1
0
XFR Wiper Counter
Register to Data Register
Transfer the contents of the Wiper Counter Register
to the Data Register pointed to by R - R
1
0
Increment/Decrement
Wiper Counter Register
0
0
1/0 Enable Increment/decrement of the Wiper Counter
Register
Note: (7) 1/0 = data is one or zero
FN8197.1
April 26, 2006
7
X9428
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3 I2
I1 I0 R1 R0
0
0
A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
X
X
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3 I2
I1 I0 R1 R0
0
0
A
C
K
I
I
D
E
C
1
S
T
I
D
N
C
1
N
C
2
N
C
n
E
C
n
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
t
WRID
SCL
SDA
Voltage Out
V
/R
W
W
FN8197.1
April 26, 2006
8
X9428
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
FN8197.1
April 26, 2006
9
X9428
DETAILED OPERATION
Register Descriptions
The potentiometer has a Wiper Counter Register and
four Data Registers. A detailed discussion of the
register organization and array operation follows.
Data Registers, (6-Bit), Nonvolatile
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
D0
NV
Wiper Counter Register
(MSB)
(LSB)
The X9428 contains a Wiper Counter Register. The
Wiper Counter Register can be envisioned as a 6-bit
parallel and serial load counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via
the write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the
contents of one of four associated Data Registers via
the XFR Data Register instruction (parallel load); it can
Four 6-bit Data Registers for each XDCP. (eight 6-bit
registers in total).
– {D5~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the Wiper Counter
Register on power-up.
Wiper Counter Register, (6-Bit), Volatile
be modified one step at
a
time by the
Increment/Decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
WP5
V
WP4
V
WP3
V
WP2
V
WP1
V
WP0
V
(MSB)
(LSB)
The WCR is a volatile register; that is, its contents are
lost when the X9428 is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be
different from the value present at power-down.
One 6-bit wiper counter register for each XDCP. (Four
6-bit registers in total.)
– {D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
Data Registers
The potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the Wiper Counter Register. It
should be noted all operations changing data in one of
these registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
FN8197.1
April 26, 2006
10
X9428
Instruction Format
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
wiper position
(sent by slave on SDA)
S
A
C
K
S
A
C
K
M S
A T
C O
K P
W W W W W W
0 0 P P P P P P
A A
A
0
0
1
0
1
0
1
0
0
1
0
0
0
0
3
2
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
wiper position
(sent by master on SDA)
S
A
C
K
S
A
C
K
S S
A T
C O
K P
W W W W W W
0 0 P P P P P P
A A
A
0
0
1
0
1
0
1
0
1
0
0
0
0
0
3
2
5
4 3 2 1 0
Read Data Register (DR)
S device type
device
addresses
instruction
opcode
register
addresses
wiper position/data
(sent by slave on SDA)
S
A
C
K
S
A
C
K
M S
A T
C O
K P
T
A
R
T
identifier
W W W W W W
0 0 P P P P P P
A A
A
0
R R
1 0
0
1
0
1
0
1
0
1
1
0
0
3
2
5
4 3 2 1 0
Write Data Register (DR)
S device type
device
addresses
instruction
opcode
register
addresses
wiper position/data
(sent by master on SDA)
S
S
A
C
K
S S
T
A
R
T
identifier
A
C
K
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
W W W W W W
0 0 P P P P P P
A A
A
0
R R
1 0
0
1
0
1
0
1
1
0
0
0
0
3
2
5
4 3 2 1 0
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type
device
addresses
instruction
opcode
register
addresses
S
A
C
K
S S
A T
C O
K P
T
A
R
T
identifier
A A
A
0
R R
1 0
0
1
0
1
0
1
1
0
1
0 0
3
2
FN8197.1
April 26, 2006
11
X9428
XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type
device
addresses
instruction
opcode
register
addresses
S
A
C
K
S S
T
A
R
T
identifier
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
A A
A
0
R R
1 0
0
1
0
1
0
1
1
1
0
0 0
3
2
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
device type
identifier
device
addresses
instruction
opcode
increment/decrement
(sent by master on SDA)
S
A
C
K
S
A
C
K
S
T
O
P
A A
A
0
I/ I/
D D
I/ I/
D D
0
1
0
1
0
0
0
1
0
0
0
0
0
.
.
.
.
3
2
SYMBOL TABLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
120
V
I
CC MAX
OL MIN
R
=
=1.8kΩ
MIN
Must be
steady
Will be
steady
100
80
t
R
R
=
MAX
C
BUS
May change
from Low to
High
Will change
from Low to
High
Max.
Resistance
60
40
20
0
May change
from High to
Low
Will change
from High to
Low
Min.
Resistance
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
0
20 40 60 80 100 120
N/A
Center Line
is High
Impedance
Bus Capacitance (pF)
FN8197.1
April 26, 2006
12
X9428
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification)
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
input with respect to V ......................... -1V to +7V
SS
Voltage on V+ (referenced to V )........................10V
SS
Voltage on V- (referenced to V )........................-10V
SS
(V+) - (V-) ..............................................................12V
Any V /R ..............................................................V+
H
H
Any V /R .................................................................V-
L
L
Lead temperature (soldering, 10 seconds)........ 300°C
(10 seconds)................................................±12mA
I
W
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9428
Supply Voltage (V ) Limits
CC
5V ± 10%
2.7V to 5.5V
X9428-2.7
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance tolerance
Power rating
Min.
Typ.
Max.
±20
50
Unit
%
Test Conditions
25 C, each pot
mW
mA
Ω
I
Wiper current
±6
W
R
Wiper resistance
150
40
250
100
+5.5
+5.5
-4.5
-2.7
V+
Wiper current = ± 1mA, V = 3V
CC
W
Ω
Wiper current = ± 1mA, V = 5V
CC
V+
V-
Voltage on V+ pin
Voltage on V- pin
X9428
+4.5
+2.7
-5.5
-5.5
V-
V
X9428-2.7
X9428
V
X9428-2.7
V
Voltage on any V /R or V /R pin
V
dBV
%
TERM
H
H
L
L
Noise
-140
1.6
Ref: 1kHz
(4)
Resolution
(1)
(3)
Absolute linearity
Relative linearity
±1
MI
V
V
- V
w(n)(expected)
w(n)(actual)
- [V
(2)
(3)
MI
±0.2
]
w(n) + MI
w(n + 1 )
Temperature Coefficient of R
±300
ppm/°C
TOTAL
Ratiometric Temperature Coefficient
±20 ppm/ C
pF
C /C /C Potentiometer Capacitances
10/10/25
See Circuit #3,
H
L
Spice Macromodel
W
FN8197.1
April 26, 2006
13
X9428
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
supply current
1
mA
f = 400kHz, SDA = Open,
SCL
CC1
CC
(nonvolatile write)
Other Inputs = V
SS
I
V
supply current
100
µA
f
= 400kHz, SDA = Open,
CC2
CC
(move wiper, write, read)
SCL
Other Inputs = V
SS
I
V
current (standby)
1
µA
µA
µA
V
SCL = SDA = V , Addr. = V
CC SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS
LI
IN
CC
CC
I
= V to V
SS
LO
OUT
V
V
x 0.7
V
V
x 0.5
IH
CC
-0.5
CC
V
x 0.1
V
IL
CC
V
0.4
V
I
= 3mA
OL
OL
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R - R )/63, single pot
H
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
(5)
C
Input/output capacitance (SDA)
8
6
V
= 0V
= 0V
I/O
I/O
(5)
C
Input capacitance (A0, A1, A2, A3, and SCL)
pF
V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Typ.
Max.
1
Unit
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
ms
ms
PUR
(6)
(7)
t
5
PUW
t V
V
Power-up ramp rate
CC
0.2
50
V/msec
R CC
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-down sequencing of the bias supplies V , V+, and V- provided
CC
that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory
is not in effect until all supplies reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) t
and t
are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific
PUR
PUW CC
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
FN8197.1
April 26, 2006
14
X9428
A.C. TEST CONDITIONS
Circuit #3 SPICE Macro Model
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
R
TOTAL
Input rise and fall times
Input and output timing level
10ns
R
R
L
H
C
V
L
CC
C
H
C
W
10pF
EQUIVALENT A.C. LOAD CIRCUIT
10pF
25pF
5V
2.7V
R
W
1533Ω
SDA Output
100pF
100pF
AC TIMING (over recommended operating conditions)
Symbol Parameter
Min.
100
2500
600
1300
600
600
600
100
30
Max.
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
Clock frequency
400
SCL
t
Clock cycle time
CYC
t
Clock high time
HIGH
t
Clock low time
LOW
t
Start setup time
SU:STA
HD:STA
SU:STO
t
Start hold time
t
Stop setup time
t
SDA data input setup time
SDA data input hold time
SCL and SDA rise time
SCL and SDA fall time
SU:DAT
t
HD:DAT
t
300
300
900
R
t
F
t
SCL low to SDA data output valid time
SDA data output hold time
AA
DH
t
50
50
T
Noise suppression time constant at SCL and SDA inputs
Bus free time (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
I
t
1300
0
BUF
t
SU:WPA
HD:WPA
t
WP, A0, A1, A2 and A3 hold time
0
FN8197.1
April 26, 2006
15
X9428
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
10
µs
µs
µs
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
WRID
Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS
START and STOP Timing
(START)
(STOP)
t
t
F
R
SCL
SDA
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
FN8197.1
April 26, 2006
16
X9428
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
LSB
t
WRL
V
/R
W
W
XDCP Timing (for Increment/Decrement Instruction)
SCL
Wiper Register Address
Inc/Dec
Inc/Dec
SDA
t
WRID
V
/R
W
W
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A2, A3
FN8197.1
April 26, 2006
17
X9428
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysteresis
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10kΩ
-12V
= {R /(R +R )} V (min)
1
1
2
O
FN8197.1
April 26, 2006
18
X9428
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
1
2
O
–
R
V
O
V
+
S
R
3
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
FN8197.1
April 26, 2006
19
X9428
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN8197.1
April 26, 2006
20
X9428
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
10.10
7.40
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4133
0.2992
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.3977
0.2914
0.32
-
-A-
10.50
7.60
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8197.1
April 26, 2006
21
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