X9271UV14Z-2.7T1 [INTERSIL]
Single, Digitally Controlled Potentiometer;
| 型号： | X9271UV14Z-2.7T1 |
| 厂家： | 
Intersil |
| 描述： | Single, Digitally Controlled Potentiometer |
| 文件： | 总18页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9271
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
July 18, 2014
FN8174.4
Single, Digitally Controlled (XDCP™)
Potentiometer
Features
• 256 Resistor Taps
The X9271 integrates a single, digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
• SPI Serial Interface for Write, Read, and Transfer
Operations of Potentiometer
• Wiper Resistance, 100Ω typical at V
= 5V
CC
The digitally controlled potentiometer is implemented by
using 255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile data registers that can
be directly written to and read by the user. The contents of
the WCR control the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall; Loads Saved Wiper Position on
Power-up
• Standby Current <3µA Max
• V
CC
= 2.7V to 5.5V Operation
• 50kΩ End-to-End Resistance
• 100-yr Data Retention
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Endurance: 100,000 Data Changes per Bit per Register
• 14-Lead TSSOP
• Low-power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant)
Functional Diagram
V
R
H
CC
WRITE
READ
50kΩ
256 TAPS
ADDRESS
DATA
STATUS
TRANSFER
INC/DEC
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
BUS
INTERFACE
AND CONTROL
SPI
BUS
INTERFACE
POT
DATA REGISTERS
16 Bytes
CONTROL
R
V
R
W
SS
L
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2011, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
X9271
Ordering Information
PART NUMBER
PART
V
LIMITS
(V)
POTENTIOMETER TEMP. RANGE
PACKAGE
Pb-Free
PKG.
DWG. #
CC
(Notes 2, 3)
X9271UV14IZ (Note 1)
X9271UV14Z (Note 1)
X9271UV14IZ-2.7
X9271UV14IZ-2.7T1
X9271UV14Z-2.7
X9271UV14Z-2.7T1
NOTES:
MARKING
X9271 UVZI
X9271 UVZ
ORGANIZATION (kΩ)
(°C)
5 ±10%
5 ±10%
50
50
50
50
50
50
-40 to +85
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
X9271 UVZG 2.7 to 5.5
X9271 UVZG 2.7 to 5.5
X9271 UVZF
X9271 UVZF
2.7 to 5.5
2.7 to 5.5
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363.
Pin Configuration
X9271
14 LD TSSOP
TOP VIEW
S0
A0
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
R
R
R
L
NC
CS
H
W
SCK
SI
HOLD
A1
8
V
WP
SS
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
2
SO
A0
Serial Data Output
Device Address
No Connect
3
NC
CS
SCK
SI
4
Chip Select
5
Serial Clock
6
Serial Data Input
System Ground
Hardware Write Protect
Device Address
7
V
SS
8
WP
A1
9
10
11
12
13
14
HOLD
Device Select. Pause the serial bus.
Wiper Terminal of Potentiometer
High Terminal of Potentiometer
Low Terminal of Potentiometer
System Supply Voltage
R
W
R
H
R
L
V
CC
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X9271
Detailed Functional Diagram
V
CC
Power-on Recall
50kΩ
256 Taps
Bank 0
R
H
R
R
0
1
Wiper
Counter
Register
(WCR)
HOLD
CS
SCK
SO
R
R
L
R
R
2
3
Interface
and
W
SI
Control
Circuitry
A0
A1
Bank 1
Bank 2
Bank 3
DATA
R
R
R
R
R
R
0
1
0
1
0
1
WP
R
R
R
R
R
R
2
3
2
3
2
3
Control
12 Additional Nonvolatile Registers
3 Banks of 4 Registers x 8 Bits
V
SS
Circuit-Level Applications
System-Level Applications
• Vary the gain of a voltage amplifier.
• Adjust the contrast in LCD displays.
• Provide programmable DC reference voltages for
comparators and detectors.
• Control the power level of LED transmitters in
communication systems.
• Control the volume in audio circuits.
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems.
• Trim out the offset voltage error in a voltage amplifier
circuit.
• Control the gain in audio and home entertainment
systems.
• Set the output voltage of a voltage regulator.
• Provide the variable DC bias for tuners in RF
wireless systems.
• Trim the resistance in Wheatstone bridge circuits.
• Control the gain, characteristic frequency, and
Q-factor in filter circuits.
• Set the operating points in temperature control
systems.
• Set the scale factor and zero point in sensor signal
conditioning circuits.
• Control the operating point for sensors in industrial
systems.
• Vary the frequency and duty cycle of timer ICs.
• Trim offset and gain errors in artificial intelligence
systems.
• Vary the DC biasing of a pin diode attenuator in RF
circuits.
• Provide a control variable (I, V, or R) in feedback
circuits.
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X9271
Supply Pins
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
CC
GROUND (V
)
SS
The System Supply Voltage (V ) pin is the system supply
CC
The Serial Output (SO) is the serial data output pin. During a
read cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
voltage. The Supply Ground (V ) pin is the system ground.
SS
Other Pins
HARDWARE WRITE PROTECT INPUT (WP)
SERIAL INPUT (SI)
The Hardware Write Protect Input (WP) pin, when LOW,
prevents nonvolatile writes to the data registers.
The Serial Input (SI) is the serial data input pin. All
operational codes, byte addresses, and data to be written to
the potentiometers and potentiometer registers are input on
this pin. Data is latched by the rising edge of the serial clock.
NO CONNECT
No Connect pins should be left floating. These pins are used
for Intersil manufacturing and testing purposes.
SERIAL CLOCK (SCK)
The Serial Clock (SCK) input is used to clock data into and
out of the X9271.
Principles of Operation
Device Description
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is under
way, HOLD may be used to pause the serial communication with
the controller without resetting the serial sequence. To pause,
HOLD must be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while SCK is LOW.
If the pause feature is not used, HOLD should be held HIGH at all
times. CMOS level input.
SERIAL INTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input with
data clocked in on the rising SCK. CS must be LOW and the
HOLD and WP pins must be HIGH during the entire
operation.
The SO and SI pins can be connected together, since they
have three-state outputs. This can help to reduce system pin
count.
DEVICE ADDRESS (A1 - A0)
The Device Address (A1 - A0) inputs are used to set the 8-bit
slave address. A match in the slave address serial data
stream must be made with the address input in order to
initiate communication with the X9271.
ARRAY DESCRIPTION
The X9271 is composed of a resistor array (Figure 1). The
array contains the equivalent of 255 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
CHIP SELECT (CS)
When Chip Select (CS) is HIGH, the X9271 is deselected,
the SO pin is at high impedance and (unless an internal write
cycle is under way) the device is in standby state. CS LOW
enables the X9271, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
mechanical potentiometer (R and R inputs).
H L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R )
output. Within each individual array, only one switch may be
turned on at a time.
W
These switches are controlled by a Wiper Counter Register
(WCR). The eight bits of the WCR (WCR[7:0]) are decoded
to select, and enable, one of 256 switches (Table 1).
Potentiometer Pins
R , R
H
L
POWER-UP AND POWER-DOWN RECOMMENDATIONS
The R and R pins are equivalent to the terminal
connections on a mechanical potentiometer.
H
L
There are no restrictions on the power-up or power-down
conditions of V
potentiometer pins, provided that V
CC
positive than or equal to V , V , and V ; i.e., V
and the voltages applied to the
is always more
V , V ,
CC
R
W
H
L
W
CC
H
L
The wiper pin (R ) is equivalent to the wiper terminal of a
W
mechanical potentiometer.
V . The V
CC
ramp rate specification is always in effect.
W
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SERIAL DATA PATH
R
SERIAL
BUS
INPUT
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
E
R
REGISTER 0
(DR0)
REGISTER 1
(DR1)
PARALLEL
BUS
INPUT
8
8
BANK_0 Only
REGISTER 3
(DR3)
REGISTER 2
(DR2)
D
E
C
O
D
E
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
IF WCR = FF[H] THEN R = R
UP/DN
CLK
W
H
R
R
MODIFIED SCK
L
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Registers and the associated WCR. All operations changing
data in one of the Data Registers are nonvolatile operations
and take a maximum of 10ms.
Device Description
Wiper Counter Register (WCR)
The X9271 contains a Wiper Counter Register (WCR) for the
DCP potentiometer. The WCR can be envisioned as an 8-bit
parallel and serial load counter, with its outputs decoded to
select one of 256 switches along its resistor array (Table 1).
The contents of the WCR can be altered in four ways:
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~255).
1. It can be written directly by the host via the Write Wiper
Counter Register instruction (serial load).
2. It can be written indirectly by transferring the contents of
one of four associated data registers via the XFR Data
Register instruction (parallel load).
Status Register (SR)
The 1-bit Status Register is used to store the system status
(Table 3).
3. It can be modified one step at a time by the Increment/
Decrement instruction.
WIP: Write In Progress status bit; read only.
4. It is loaded with the contents of its Data Register zero
(DR0) upon power-up.
• WIP = 1 indicates that a high-voltage write cycle is in
progress.
The WCR is a volatile register; that is, its contents are lost
when the X9271 is powered down. Although the register is
automatically loaded with the value in DR0 upon power-up,
this may be different from the value present at power-down.
Power-up guidelines are recommended to ensure proper
loading of the R0 value into the WCR. The DR0 value of
Bank 0 is the default value.
• WIP = 0 indicates that no high-voltage write cycle is in
progress
.
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit),
WCR[7:0]: Used to store current wiper position
(Volatile, V)
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
Data Registers (DR3–DR0)
V
V
V
V
V
V
V
V
The potentiometer has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host (Table 2).
Data can also be transferred between any of the four Data
(MSB)
(LSB)
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X9271
.
REGISTER BANK SELECTION (R1, R0, P1, P0)
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to
store wiper positions or data (Nonvolatile, NV)
There are 16 registers organized into four banks. Bank 0 is
the default bank of registers. Only Bank 0 registers can be
used for the data register to Wiper Counter Register
operations.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Banks 1, 2, and 3 are additional banks of registers (12 total)
that can be used for SPI write and read operations. The data
registers in Banks 1, 2, and 3 cannot be used for direct
read/write operations to the Wiper Counter Register
(Tables 5 and 6).
TABLE 3. STATUS REGISTER, SR (WIP is 1-bit)
WIP
(LSB)
TABLE 4. IDENTIFICATION BYTE FORMAT
Device Description
Instructions
SET TO 0 FOR
PROPER
OPERATION
INTERNAL
SLAVE
ADDRESS
DEVICE TYPE IDENTIFIER
IDENTIFICATION BYTE (ID AND A)
ID3
0
ID2
ID1
ID0
0
0
A1
A0
The first byte sent to the X9271 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bit is the device ID for the X9271;
this is fixed as 0101[B] (Table 4).
1
0
1
(MSB)
(LSB)
TABLE 5. REGISTER SELECTION (DR0 TO DR3)
REGISTER
The A1 - A0 bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the A1
- A0 input pins. The slave address is externally specified by
the user. The X9271 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9271 to successfully
continue the command sequence. Only the device for which
slave address matches the incoming device address sent by
the master executes the instruction. The A1 - A0 inputs can
RB
RA SELECTION
OPERATIONS
0
0
1
0
1
0
1
2
3
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
Data Register Read and Write; Wiper
Counter Register Operations
Data Register Read and Write; Wiper
Counter Register Operations
Data Register Read and Write; Wiper
Counter Register Operations
be actively driven by CMOS input signals or tied to V
or
CC
V
.
SS
INSTRUCTION BYTE (I[3:0])
TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
BANK
The next byte sent to the X9271 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction operation code (I[3:0]).
The RB and RA bits point to one of the four Data Registers.
P0 is the POT selection; since the X9271 is single POT,
P0 = 0. The format is shown in Table 7.
P1
P0 SELECTION
OPERATIONS
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
1
0
1
1
2
3
Data Register Read and Write Only
Data Register Read and Write Only
Data Register Read and Write Only
TABLE 7. INSTRUCTION BYTE FORMAT
REGISTER BANK SELECTION FOR
SP1 REGISTER WRITE AND READ OPERATIONS)
REGISTER
SELECTION
POTENTIOMETER SELECTION
(WCR SELECTION) (Note 4)
INSTRUCTION OPCODE
I2 I1
I3
P0
RB
RA
P1
P0
(MSB)
(LSB)
NOTE:
4. Set to P0 = 0 for potentiometer operations.
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X9271
associated register. The Read Status Register instruction is
the only unique format (Figure 3).
Device Description
Instructions
Two instructions require a 2-byte sequence to complete
(Figure 4). These instructions transfer data between the host
and the X9271; either between the host and one of the data
registers, or directly between the host and the Wiper
Counter Register. These instructions are:
Five of the eight instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register: Read the current wiper
position of the potentiometer.
• Write Wiper Counter Register: Change current wiper
position of the potentiometer.
• XFR Data Register to Wiper Counter Register:
Transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• Read Data Register: Read the contents of the selected
Data Register.
• XFR Wiper Counter Register to Data Register:
Transfers the contents of the specified Wiper Counter
Register to the associated Data Register.
• Write Data Register: Write a new value to the selected
Data Register.
The final command is Increment/Decrement
• Read Status: This command returns the contents of the
WIP bit, which indicates if the internal write cycle is in
progress.
(Figures 5 and 6). It is different from the other commands,
because its length is indeterminate. Once the command is
issued, the master can clock the selected wiper up and/or
down in one resistor segment step, thereby providing a fine-
tuning capability to the host. For each SCK clock pulse
See Table 8 for details of the instruction set.
The basic sequence of the 3-byte instruction is shown in
Figure 2. These 3-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a
Data Register to a WCR is essentially a write to a static
RAM, with the static RAM controlling the wiper position. The
(t
) while SI is HIGH, the selected wiper moves one
HIGH
resistor segment towards the R terminal. Similarly, for each
H
SCK clock pulse while SI is LOW, the selected wiper moves
one resistor segment towards the R terminal.
L
response of the wiper to this action is delayed by t
transfer from the WCR (current wiper position) to a Data
Register is a write to nonvolatile memory and takes a
. A
WRL
Write-in-Process (WIP) Bit
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
the Write-in-Process bit (WIP). The WIP bit is read with a
Read Status command.
minimum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers, or it may occur globally, where the
transfer occurs between all potentiometers and one
CS
SCL
SI
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
A1 A0
RB RA P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
I1
I3 I2
I0
Internal
Address
Instruction
Opcode
Register
Address
Pot/Bank
Address
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 2. THREE-BYTE INSTRUCTION SEQUENCE (WRITE)
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X9271
CS
SCL
SI
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
X
A1 A0
I3
RB RA P1 P0
I1
I2
I0
ID3 ID2 ID1 ID0
Device ID
Don’t Care
Internal
Address
Pot/Bank
Address
Instruction
Opcode
Register
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE (READ)
CS
SCK
SI
0
0
0
0
0
0
1
0
1
0
A1 A0
I0
ID3 ID2 ID1 ID0
Device ID
I1
RB RA
P0
I3
P1
I2
Internal
Address
Instruction
Opcode
Register
Address
Pot/Bank
Address
These commands only valid when P1 = P0 = 0
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCL
0
SI
0
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
P1
A1 A0
RA RB
P0
I1
I3 I2
I0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Internal
Address
Pot/Bank
Address
Instruction
Opcode
Register
Address
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
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X9271
t
WRID
SCK
SI
VOLTAGE OUT
V
W
INC/DEC CMD ISSUED
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
TABLE 8. INSTRUCTION SET
INSTRUCTION SET
(1/0 = DATA IS ONE OR ZERO)
INSTRUCTION
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
I3
1
I2
0
I1
0
I0
1
RB
0
RA
0
P
P
OPERATION
1
0
0
1/0 Read contents of Wiper Counter Register.
1/0 Write new value to Wiper Counter Register.
1
0
1
0
0
0
0
1
0
1
1
1/0
1/0
1/0
1/0 Read contents of Data Register pointed to by P1 - P0
and RB - RA.
Write Data Register
1
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1/0
1/0
1/0
0
1/0
1/0
1/0
0
1/0
0
1/0 Write new value to Data Register pointed to by P1 - P0
and RB - RA.
XFR Data Register to
Wiper Counter Register
0
0
0
1
Transfer contents of Data Register pointed to by
RB - RA (Bank 0 only) to Wiper Counter Register.
XFR Wiper Counter
Register to Data Register
0
Transfer contents of Wiper CounterRegister to Register
pointed to by RB-RA (Bank 0 only).
Increment/Decrement
Wiper Counter Register
0
Enable increment/decrement of the Wiper Counter
Register.
Read Status (WIP Bit)
0
0
0
Read status of internal write cycle by checking WIP bit.
Instruction Format
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by X9271 on SO)
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
1
0
0
1
0
0
0
0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
Write Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
1
0
1
0
0
0
0
0
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
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X9271
Read Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
1
0
1
1
RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0
Write Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
1
1
0
0
RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
0
A1 A0
1
1
1
0
RB
RA
0
0
Transfer Data Register (DR) to Wiper Counter Register (WCR) (Notes 5, 6)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
CS
Rising
Edge
0
1
0
1
0
0
A1
A0
1
1
0
1
RB RA
0
0
Increment/Decrement Wiper Counter Register (WCR) (Notes 5, 6, 7, 8, 9)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Increment/Decrement
(Sent by Master on SDA)
CS
Rising
Edge
0
1
0
1
0
0
A1
A0
0
0
0
1
0
1
X
X
0
0
I/D I/D
.
.
.
.
I/D I/D
Read Status Register (SR) (Note 5)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
0
1
0
1
0
0
A1
A0
1
0
0
0
0
1
0
0
0
0
0
0
0
WIP
NOTES:
5. “A1 ~ A0”: stands for the device addresses sent by the master.
6. WCRx refers to wiper position data in the Wiper Counter Register.
7. “I”: stands for the increment operation. SI held HIGH during active SCK phase (high).
8. “D”: stands for the decrement operation. SI held LOW during active SCK phase (high).
9. “X:”: Don’t Care.
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X9271
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Voltage on SCK, any Address Input,
with Respect to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
V = |(VH - VL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
I
(10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Supply Voltage (V ) Limits:
CC
X9271. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9271-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Recommended Operating Conditions
Temperature Range (Commercial). . . . . . . . . . . . . . . . 0°C to +70°C
Temperature Range (Industrial) . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Analog Characteristics Across recommended industrial operating conditions unless otherwise specified.
LIMITS
MIN
MAX
SYMBOL
PARAMETER
(Note 17)
TYP
(Note 17)
UNITS
kΩ
TEST CONDITIONS
R
End to End Resistance
50
U version
TOTAL
End to End Resistance
Tolerance
±20
%
Power Rating
50
±3
mW
mA
W
+25°C, each pot
I
Wiper Current
W
R
Wiper Resistance
Wiper Resistance
300
150
I
I
= ± 3mA at V
= ± 3mA at V
= 3V
= 5V
W
W
W
CC
CC
R
W
W
V
Voltage on any R or R Pin
V
V
V
V
= 0V
SS
TERM
H
L
SS
CC
Noise
-120
0.4
dBVHz Ref: 1V
Resolution
%
Absolute Linearity (Note 10)
Relative Linearity (Note 11)
Temperature Coefficient of
±1
MI
R
R
w(n)(actual) - w(n)(expected)
(Note 12) (Note 14)
±0.2
MI
(Note 12)
R
- [R ] (Note 14)
w(n) + MI
w(n + 1)
±300
ppm/C
ppm/°C
pF
R
TOTAL
Ratiometric Temp.
Coefficient
20
C /C /C
W
Potentiometer
Capacitance
10/10/25
See macro model
H
L
NOTES:
10. Absolute linearity is used to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
11. Relative linearity is used to determine actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
12. MI = RTOT / 255 or (R - R ) / 255, single pot.
H
L
13. During power-up, V
CC
> V , V , and V .
H L W
14. n = 0, 1, 2, …,255; m = 0, 1, 2, …., 254.
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X9271
D.C. Operating Characteristics Across the recommended operating conditions unless otherwise specified.
LIMITS
MIN
MAX
SYMBOL
PARAMETER
(Note 17)
TYP
(Note 17) UNITS
TEST CONDITIONS
I
I
I
V
Supply Current
400
5
µA
mA
µA
f
= 2.5MHz, SO = Open, V
= 6V
CC1
CC
SCK
Other Inputs = V
CC
(Active)
SS
= 2.5MHz, SO = Open, V
V
Supply Current
1
f
= 6V
CC2
SB
CC
(Nonvolatile Write)
SCK
Other Inputs = V
CC
SS
V
Current (Standby)
3
SCK = SI = V , Addr. = V
CS = V
CC
,
SS
CC
SS
= 6V
I
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
SS
LO
OUT
CC
V
V
V
V
V
V
x 0.7
V
+ 1
IH
CC
CC
-1
V
x 0.3
V
IL
CC
0.4
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
V
I
I
I
= 3mA
OL
OH
OH
OL
OH
OH
V
V
- 0.8
- 0.4
V
= -1mA, V
CC
+3V
CC
V
= -0.4mA, V
+3V
CC
CC
Endurance and Data Retention
MIN.
PARAMETER
Minimum Endurance
Data Retention
(Note 17)
100,000
100
UNITS
Data changes per bit per register
Years
Capacitance
MAX.
SYMBOL
TEST
(Note 17)
UNITS
pF
TEST CONDITIONS
C
C
C
(Note 15)
Input / Output Capacitance (SI)
Output Capacitance (SO)
8
8
6
V
V
= 0V
= 0V
IN/OUT
(Note 15)
OUT
pF
OUT
(Note 15)
OUT
Input Capacitance (A0, CS, WP, HOLD, and SCK)
pF
V
= 0V
IN
IN
Power-Up Timing
MIN.
MAX.
SYMBOL
PARAMETER
(Note 17)
(Note 17)
UNITS
V/ms
ms
t V
(Note 15)
V Power-up Rate
CC
0.2
50
1
r
CC
t
t
(Note 16)
(Note 16)
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
PUR
50
ms
PUW
A.C. Test Conditions
INPUT PULSE LEVELS
Input Rise and Fall Times
V
x 0.1 to V
x 0.9
CC
CC
10ns
Input and Output Timing Level
V
x 0.5
CC
NOTES:
15. This parameter is not 100% tested.
16. t
and t
are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued. These
PUW CC
PUR
parameters are periodically sampled and are not 100% tested.
17. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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X9271
Equivalent A.C. Load Circuit
SPICE MACROMODEL
5V
1462Ω
3V
1382
R
TOTAL
R
R
L
H
SO pin
SO pin
C
C
W
C
L
L
10pF
2714Ω
100pF
1217
100pF
25pF
10pF
R
W
AC Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSI/SPI Clock Frequency
SSI/SPI Clock Cycle Time
SSI/SPI Clock High Time
SSI/SPI Clock Low Time
Lead Time
2.5
SCK
CYC
WH
WL
LEAD
LAG
SU
500
200
200
250
250
50
ns
ns
ns
Lag Time
ns
SI, SCK, HOLD and CS Input Setup Time
SI, SCK, HOLD and CS Input Hold Time
SI, SCK, HOLD and CS Input Rise Time
SI, SCK, HOLD and CS Input Fall Time
SO Output Disable Time
ns
50
ns
H
2
µs
µs
ns
RI
2
FI
0
0
250
200
DIS
V
SO Output Valid Time
ns
SO Output Hold Time
ns
HO
RO
FO
SO Output Rise Time
100
100
ns
SO Output Fall Time
ns
HOLD Time
400
100
100
ns
HOLD
HSU
HH
HZ
HOLD Setup Time
ns
HOLD Hold Time
ns
HOLD Low to Output in High Z
HOLD High to Output in Low Z
100
100
10
ns
ns
LZ
T
Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs
ns
I
t
t
t
CS Deselect Time
WP, A0 Setup Time
WP, A0 Hold Time
2
0
0
µs
ns
CS
WPASU
WPAH
ns
High-voltage Write Cycle Timing
SYMBOL
PARAMETER
TYP
MAX
UNITS
t
High-voltage Write Cycle Time (Store Instructions)
5
10
ms
WR
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X9271
XDCP Timing
SYMBOL
PARAMETER
MIN
5
MAX
10
UNITS
µs
t
t
Wiper Response Time After Third (Last) Power Supply is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
WRPO
WRL
5
10
µs
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change from Low to High
May change from High to Low
Don’t Care: Changes Allowed
N/A
Will change from Low to High
Will change from High to Low
Changing: State Not Known
Center Line is High Impedance
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
LSB
MSB
ADDR
SI
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X9271
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
VWx
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
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X9271
Applications information
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
3-terminal Potentiometer;
Variable Voltage Divider
2-terminal Variable Resistor;
Variable Current
Application Circuits
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V (REG) = 1.25V (1+R /R )+I
O 2 1 adj
O
2
1
S
FIGURE 7. NONINVERTING AMPLIFIER
FIGURE 8. VOLTAGE REGULATOR
R
R
2
V
–
+
1
S
V
V
O
S
100kΩ
–
+
V
O
R
R
TL072
1
2
10kΩ
10kΩ
+12V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
RL = {R /(R +R )} V (min)
10kΩ
-12V
L
1
1
2
O
FIGURE 9. OFFSET VOLTAGE ADJUSTMENT
FIGURE 10. COMPARATOR WITH HYSTERESIS
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X9271
Application Circuits (Continued)
C
V
+
–
S
R
V
R
1
2
O
–
R
V
O
V
+
S
R
3
R
2
R
4
R
= R = R = R = 10k
2 3 4
1
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2RC)
-1/2 G +1/2
FIGURE 11. ATTENUATOR
FIGURE 12. FILTER
R
2
C
R
R
1
1
2
V
+
–
S
V
S
–
+
R
R
1
V
O
Z
IN
3
V
= G V
O
S
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
FIGURE 13. INVERTING AMPLIFIER
FIGURE 14. EQUIVALENT L-R CIRCUIT
C
R
R
1
2
–
–
+
+
R
R
}
A
}
B
Frequency R , R , C
1
2
Amplitude R , R
A
B
FIGURE 15. FUNCTION GENERATOR
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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X9271
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
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18
相关型号：
X9271UV14ZT1
Single Digitally-Controlled (XDCP™) Potentiometer; TSSOP14; Temp Range: See Datasheet
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