X9271UXXXI [XICOR]
Digital Potentiometer, CMOS,;
| 型号： | X9271UXXXI |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, CMOS, 转换器 |
| 文件： | 总23页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / SPI bus
X9271
Single Digitally-Controlled (XDCPTM) Potentiometer
FEATURES
DESCRIPTION
• 256 Resistor Taps
The X9271 integrates a single digitally controlled
• SPI Serial Interface for write, read, and transfer
operations of the potentiometer
potentiometer (XDCP) on
integrated circuit.
a
monolithic CMOS
• Wiper Resistance, 100Ω typical @ V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads SavedWiper Position on
Power Up.
= 5V
CC
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
• Standby Current < 3µA Max
• V : 2.7V to 5.5V Operation
CC
• 50KΩ, 100KΩ versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 14-Lead TSSOP, xx-Lead XBGA
• Low Power CMOS
The XDCP can be used as
a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
V
R
H
CC
Write
Read
Address
Transfer
50KΩ and 100KΩ
Power On Recall
Data
256-taps
Inc/Dec
Status
Wiper Counter
POT
Bus
SPI
Bus
Interface
Register (WCR)
Interface
and Control
Data Registers
16 Bytes
Control
R
V
R
W
SS
L
Characteristics subject to change without notice. 1 of 23
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X9271
DETAILED FUNCTIONAL DIAGRAM
V
CC
Power On Recall
WIPER
50KΩ and 100KΩ
Bank 0
256-taps
R
R
H
R
R
0
1
HOLD
COUNTER
REGISTER
(WCR)
CS
SCK
SO
L
R
R
INTERFACE
AND
CONTROL
2
3
R
W
SI
CIRCUITRY
A0
A1
Bank 1
Bank 2
Bank 3
DATA
R
R
R
R
R
R
0
1
0
1
0
1
WP
R
R
R
R
R
R
2
3
2
3
2
3
Control
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
V
SS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Control the gain in audio and home entertainment
systems
• Set the output voltage of a voltage regulator
• Provide the variable DC bias for tuners in RF
wireless systems
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the operating points in temperature control
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the operating point for sensors in industrial
systems
• Vary the frequency and duty cycle of timer ICs
• Trim offset and gain errors in artificial intelligent
systems
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
Characteristics subject to change without notice. 2 of 23
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X9271
PIN CONFIGURATION
XBGA
TSSOP
X9271
X9271
S0
A0
14
13
12
11
10
1
2
3
4
5
6
7
V
CC
R
L
NC
R
R
H
CS
W
SCK
HOLD
A1
SI
9
8
V
SS
WP
PIN ASSIGNMENTS
Pin
(TSSOP)
Pin
(XBGA)
Symbol
SO
Function
1
2
Serial Data Output.
A0
Device Address.
No Connect.
3
NC
4
CS
Chip Select.
5
SCK
SI
Serial Clock.
6
Serial Data Input.
System Ground.
Hardware Write Protect.
Device Address.
7
V
SS
8
WP
A1
9
10
11
12
13
14
HOLD
Device select. Pause the serial bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage.
R
W
R
H
R
L
V
CC
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X9271
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
Potentiometer Pins
R , R
H
L
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer.
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Supply Pins
SYSTEM SUPPLY VOLTAGE (V
) AND SUPPLY GROUND (V )
SS
CC
The V pin is the system supply voltage. The V pin
CC
SS
is the system ground.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9271.
Other Pins
HARDWARE WRITE PROTECT INPUT (WP)
HOLD (HOLD)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH at
all times. CMOS level input.
NO CONNECT.
No connect pins should be left floating. This pins are
used for Xicor manufacturing and testing purposes.
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order to
initiate communication with the X9271.
CHIP SELECT (CS)
When CS is HIGH, the X9271 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9271, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Characteristics subject to change without notice. 4 of 23
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X9271
PRINCIPLES OF OPERATION
Device Description
SERIAL INTERFACE
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R and R
H
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
(R ) output. Within each individual array only one
switch may be turned on at a time.
W
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
POWER UP AND DOWN RECOMMENDATIONS.
There are no restrictions on the power-up or power-
ARRAY DESCRIPTION
down conditions of V and the voltages applied to the
CC
The X9271 is comprised of a resistor array (see Figure
1). The array contains the equivalent of 255 discrete
resistive segments that are connected in series. The
potentiometer pins provided that V
is always more
CC
positive than or equal to V , V , and V , i.e., V ≥ V ,
H
L
W
CC
H
V , V . The V ramp rate specification is always in
L
W
CC
effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
R
H
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
(DR0)
REGISTER 1
(DR1)
PARALLEL
BUS
INPUT
8
8
E
R
BANK_0 Only
REGISTER 3
(DR3)
REGISTER 2
(DR2)
D
E
C
O
D
E
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
IF WCR = FF[H] THEN R = R
UP/DN
CLK
W
H
R
L
MODIFIED SCK
R
W
Characteristics subject to change without notice. 5 of 23
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X9271
DEVICE DESCRIPTION
Data Registers (DR3–DR0)
The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
Wiper Counter Register (WCR)
The X9271 contains a Wiper Counter Register for the
DCP potentiometer. The Wiper Counter Register can
be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0 ~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9271 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the R0 value into the WCR. The DR0 value
of Bank 0 is the default value.
WIP:Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress
Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
NV
Bit 6
NV
Bit 5
NV
Bit 4
NV
Bit 3
NV
Bit 2
NV
Bit 1
NV
Bit 0
NV
MSB
LSB
Table 3. Status Register, SR (WIP is 1-bit)
WIP
(LSB)
Characteristics subject to change without notice. 6 of 23
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X9271
DEVICE DESCRIPTION
Instructions
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device id for the X9271; this is fixed as 0101[B] (refer to
Table 4).
Register Selection (DR0 to DR3) Table
Register
RB RA Selection
Operations
0
0
1
1
0
1
0
1
0
1
2
3
Data Register Read and Write;
Wiper Counter Register
Operations
The A1-A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A1-A0 input pins. The slave address is
externally specified by the user. The X9271 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9271 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1-A0 inputs can
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write;
Wiper Counter Register
Operations
be actively driven by CMOS input signals or tied to V
Register Bank Selection (Bank 0 to Bank 3) Table
Bank
CC
or V
.
SS
P1 P0 Selection
Operations
INSTRUCTION BYTE (I[3:0])
0
0
0
Data Register Read and Write;
Wiper Counter Register
Operations
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9271 is single POT, the P0=0. The format is shown in
Table 5.
0
1
1
1
0
1
1
2
3
Data Register Read and Write
Only
Data Register Read and Write
Only
Data Register Read and Write
Only
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for data register to Wiper Counter
Register operations.
Table 4. Identification Byte Format
Internal
Slave Address
Device Type
Identifier
Set to 0
for proper operation
ID3
0
ID2
1
ID1
0
ID0
1
0
0
A1
A0
(MSB)
(LSB)
Characteristics subject to change without notice. 7 of 23
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X9271
Table 5. Instruction Byte Format
P1 and P0 are used also for register Bank Selection
for SPI Register Write and Read operations
Pot Selection (WCR Selection)
Set to P0=0 for potentiometer operations
Instruction Opcode
Register Selection
I3
I2
I1
P0
RB
RA
P1
P0
(MSB)
(LSB)
DEVICE DESCRIPTION
Instructions
Two instructions require a two-byte sequence to
complete (Figure 2). These instructions transfer data
between the host and the X9271; either between the
host and one of the data registers or directly between
the host and the Wiper Counter Register. These
instructions are:
Five of the eight instructions are three bytes in length.
These instructions are:
– Read Wiper Counter Register – read the current
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
wiper position of the potentiometer;
– Write Wiper Counter Register – change current
wiper position of the potentiometer;
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
The final command is Increment/Decrement (Figure 5
and 6). It is different from the other commands,
because it’s length is indeterminate. Once the
command is issued, the master can clock the selected
wiper up and/or down in one resistor segment steps;
thereby, providing a fine tuning capability to the host.
– Read Status - This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
For each SCK clock pulse (t
) while SI is HIGH, the
HIGH
selected wiper will move one resistor segment towards
the R terminal. Similarly, for each SCK clock pulse
H
while SI is LOW, the selected wiper will move one
resistor segment towards the R terminal.
wiper to this action will be delayed by t
. A transfer
L
WRL
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
See Instruction format for more details.
minimum of t
to complete. The transfer can occur
WR
Write in Process (WIP bit)
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and one
associated register. The Read Status Register
instruction is the only unique format (see Figure 4).
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a Write In Process bit (WIP). The
WIP bit is read with a Read Status command.
Characteristics subject to change without notice. 8 of 23
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X9271
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
0
0
0
0
0
0
1
0
1
0
A1 A0
I0
ID3 ID2 ID1 ID0
Device ID
I1
RB RA
P0
I3
P1
I2
Internal
Address
Instruction
Opcode
Register
Address
Pot/Bank
Address
These commands only valid when P1=P0=0
Figure 3. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
A1 A0
RB RA P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
I1
I3 I2
I0
Internal
Address
Instruction
Opcode
Register
Address
Pot/Bank
Address
WCR[7:0] valid only when P1=P0=0;
or
Data Register Bit [7:0] for all values of P1 and P0
Figure 4. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
X
A1 A0
I3
RB RA P1 P0
I1
I2
I0
ID3 ID2 ID1 ID0
Device ID
Don’t Care
Internal
Address
Pot/Bank
Address
Instruction
Opcode
Register
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0] valid only when P1=P0=0;
or
Data Register Bit [7:0] for all values of P1 and P0
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X9271
Figure 5. Increment/Decrement Instruction Sequence
CS
SCL
0
SI
0
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
Device ID
P1
A1 A0
RA RB
P0
I1
I3 I2
I0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Internal
Address
Pot/Bank
Address
Instruction
Opcode
Register
Address
Figure 6. Increment/Decrement Timing Limits
t
WRID
SCK
SI
VOLTAGE OUT
V
W
INC/DEC CMD ISSUED
Table 6. Instruction Set
Instruction
Instruction Set
I3 I2 I1 I0 RB RA
P
P
Operation
1
0
Read Wiper Counter
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
1/0 Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
0
0
1/0 Write new value to the Wiper Counter
Register
Read Data Register
1/0 1/0 1/0 1/0 Read the contents of the Data Register
pointed to by P1-P0 and RB-RA
Write Data Register
1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1-P0 and RB-RA
XFR Data Register to
Wiper Counter Register
1/0 1/0
0
0
Transfer the contents of the Data Register
pointed to by RB-RA (Bank 0 only) to the
Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
1
1
0
1/0 1/0
0
0
Transfer the contents of the Wiper Counter
Register to the Register pointed to by RB-RA
(Bank 0 only)
Increment/Decrement
Wiper Counter Register
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
Enable Increment/decrement of the Wiper
Counter Register
Read Status (WIP bit)
Read the status of the internal write cycle, by
checking the WIP bit.
Note: 1/0 = data is one or zero
Characteristics subject to change without notice. 10 of 23
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X9271
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by X9271 on SO)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
0
1
0
0
0
0
5
4
3
2
1
0
6
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
1
0
0
0
0
0
5
4 3 2 1 0
6
Read Data Register (DR)
Device Type
CS
Device
Addresses
0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
Identifier
Falling
Edge
0
1
0
1
0
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
0
1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0 0 A1 A0 1 1 1 0 RB RA
0
0
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X9271
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0 0 A1 A0 1 1 0 1 RB RA
0
0
Increment/Decrement Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
X X
Increment/Decrement
(Sent by Master on SDA)
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
0
0
1
0
0
0 I/D I/D
.
.
.
.
I/D I/D
Read Status Register (SR)
Device Type
Identifier
Device
Addresses
A1 A0
Instruction
Opcode
DR/Bank
Addresses
Data Byte
(Sent by X9271 on SO)
0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
(4) “X:”: Don’t Care.
Characteristics subject to change without notice. 12 of 23
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X9271
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Voltage on SCK any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
with respect to V ..................................–1V to +7V
SS
∆V = |(V –V )|...................................................... 5.5V
H
L
Lead temperature (soldering, 10 seconds)........ 300°C
I
(10 seconds)..................................................±6mA
W
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9271
Supply Voltage (V
)
(4) Limits
CC
5V ±10%
–40°C
X9271-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to End Resistance
End to End Resistance
Min.
Typ.
100
50
Max.
Units
kΩ
Test Conditions
T version
R
TOTAL
R
kΩ
U version
TOTAL
End to End Resistance
Tolerance
±20
%
Power Rating
50
±3
mW
mA
Ω
25°C, each pot
I
Wiper Current
W
R
R
Wiper Resistance
Wiper Resistance
300
150
I
I
= ± 3mA @ V = 3V
CC
W
W
Ω
= ± 3mA @ V = 5V
CC
W
W
V
Voltage on any R or R Pin
V
V
V
V
= 0V
TERM
H
L
SS
CC
SS
Noise
-120
0.4
dBV/ Hz Ref: 1V
Resolution
%
(5)
Absolute Linearity(1)
±1
MI(3)
R – R
w(n)(actual) w(n)(expected)
(5)
Relative Linearity(2)
±0.2
MI(3)
R
– [R
]
w(n + 1)
w(n) + MI
Temperature Coefficient of
±300
ppm/°C
R
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitancies
20
ppm/°C
pF
C /C /C
W
10/10/25
See Macro model
H
L
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (R – R ) / 255, single pot
H
L
(4) During power up V > V , V , and V .
CC
H
L
W
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …., 254.
Characteristics subject to change without notice. 13 of 23
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X9271
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
= 2.5 MHz, SO = Open, V =6V
I
I
I
V
supply current
(active)
400
µA
f
SCK
CC1
CC2
SB
CC
CC
Other Inputs = V
SS
V
supply current
(nonvolatile write)
1
5
3
mA
f
= 2.5MHz, SO = Open, V =6V
SCK CC
CC
Other Inputs = V
SS
V
current (standby)
µA
SCK = SI = V , Addr. = V
,
CC
SS
SS
CS = V = 6V
CC
I
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
V
V
V
V
V
x 0.7
V
+ 1
IH
CC
CC
–1
V
x 0.3
V
IL
CC
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
0.4
V
I
I
I
= 3mA
OL
OH
OH
OL
OH
OH
V
V
- 0.8
V
= -1mA, V ≥ +3V
CC
CC
- 0.4
V
= -0.4mA, V ≤ +3V
CC
CC
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Units
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Units
pF
Test Conditions
(6)
IN/OUT
C
C
C
Input / Output capacitance (SI)
Output capacitance (SO)
8
8
6
V
V
= 0V
= 0V
OUT
OUT
(6)
OUT
pF
(6)
IN
Input capacitance (A0, CS, WP, HOLD, and
SCK)
pF
V
= 0V
IN
POWER-UP TIMING
Symbol
Parameter
V Power-up rate
CC
Min.
Max.
50
Units
V/ms
ms
(6)
CC
t V
0.2
r
(7)
PUR
t
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
(7)
PUW
50
ms
A.C. TEST CONDITIONS
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing level
10ns
V
x 0.5
CC
Notes: (6) This parameter is not 100% tested
(7) t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be
PUR
PUW
CC
issued.These parameters are periodically sampled and not 100% tested.
Characteristics subject to change without notice. 14 of 23
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X9271
EQUIVALENT A.C. LOAD CIRCUIT
SPICE Macromodel
5V
1462Ω
3V
1382Ω
R
TOTAL
R
R
L
H
SO pin
SO pin
C
C
W
C
L
L
10pF
2714Ω
100pF
1217Ω
100pF
25pF
10pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.5
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
SCK
CYC
WH
WL
LEAD
LAG
SU
500
200
200
250
250
50
Lag time
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
50
H
2
RI
2
FI
0
0
250
200
DIS
V
SO output valid time
SO output hold time
HO
RO
FO
SO output rise time
100
100
SO output fall time
HOLD time
400
100
100
HOLD
HSU
HH
HZ
HOLD setup time
HOLD hold time
HOLD low to output in high Z
HOLD high to output in low Z
100
100
10
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
I
t
t
t
CS deselect time
WP, A0 setup time
WP, A0 hold time
2
0
0
CS
WPASU
WPAH
Characteristics subject to change without notice. 15 of 23
REV 1.1.2 12/8/00
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X9271
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Units
t
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
5
5
10
10
µs
µs
WRPO
WRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 16 of 23
REV 1.1.2 12/8/00
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X9271
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
LSB
MSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
Characteristics subject to change without notice. 17 of 23
REV 1.1.2 12/8/00
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X9271
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
VWx
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 18 of 23
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X9271
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj
O
2
1
S
O
2
1
2
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
10KΩ
-12V
RL = {R /(R +R )} V (min)
L
1
1
2
O
Characteristics subject to change without notice. 19 of 23
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X9271
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
frequency R , R , C
1
2
amplitude R , R
A
B
Characteristics subject to change without notice. 20 of 23
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X9271
XX-ball BGA (X9271xxxxxxx)
a
a
l
j
m
k
b
b
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
d
= Die Orientation mark
c
e
Side View (Bump Side Down)
Millimeters
Inches
Symbol
Min
Nom.
Max
Min
Nom.
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
Ball Count X Axis
Ball Count Y Axis
Pins Pitch X Axis
j
Pins Pitch Y Axis
k
l
Edge to Ball Center (Corner)
Distance Along X
Edge to Ball Center (Corner)
Distance Along Y
m
Characteristics subject to change without notice. 21 of 23
REV 1.1.2 12/8/00
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X9271
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0∞– 8∞
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 22 of 23
REV 1.1.2 12/8/00
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X9271
ORDERING INFORMATION
X9271
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
V14 = 14-Lead SOIC
xxx = xxx-Lead XBGA
Potentiometer Organization
Pot
U =
T =
50KΩ
100KΩ
PART MARK CONVENTION
xx Lead XBGA
X9271xxxx-2.7
X9271xxxx xx
X9271 xxxx
Top Mark
X9271xxxxx I-2.7
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 23 of 23
REV 1.1.2 12/8/00
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