X9258UV24I_技术文档

X9258

®

Low Noise/Low Power/2-Wire Bus/256 Taps

Data Sheet

May 6, 2005

FN8168.1

DESCRIPTION

The X9258 integrates

potentiometers (XDCP) on a monolithic CMOS

integrated circuit.

Quad Digital Controlled Potentiometers

(XDCP™)

4

digitally controlled

FEATURES

• Four potentiometers in one package

• 256 resistor taps/pot–0.4% resolution

• 2-wire serial interface

• Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current < 5µA max (total package)

• Power supplies

The digitally controlled potentiometer is implemented

using 255 resistive elements in a series array.

Between each element are tap points connected to the

wiper terminal through switches. The position of the

wiper on the array is controlled by the user through the

2-wire bus interface. Each potentiometer has

associated with it a volatile Wiper Counter Register

(WCR) and 4 nonvolatile Data Registers (DR0:DR3)

that can be directly written to and read by the user.

The contents of the WCR controls the position of the

wiper on the resistor array though the switches. Power

up recalls the contents of DR0 to the WCR.

—V

= 2.7V to 5.5V

CC

—V+ = 2.7V to 5.5V

—V- = -2.7V to -5.5V

• 100kΩ, 50kΩ total pot resistance

• High reliability

—Endurance – 100,000 data changes per bit per

register

—Register data retention – 100 years

• 24-lead SOIC, 24-lead TSSOP

• Dual supply version of X9259

The XDCP can be used as a three-terminal

potentiometer or as a two-terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

BLOCK DIAGRAM

Pot 0

V

CC

SS

R

V

/R

H0 H0

R

0

1

3

0

1

Wiper

Counter

Register

(WCR)

Wiper

Counter

Register

(WCR)

V

/R

H2 H2

Resistor

Array

Pot 2

V+

V-

V

/R

L0 L0

2

WP

2

3

V

/R

L2 L2

V

/R

SCL

SDA

A0

W0 W0

V

/R

W2 W2

Interface

and

Control

A1

8

Circuitry

A2

V

/R

A3

W1 W1

Data

V

/R

W3 W3

R

0

1

3

V

/R

H1 H1

R

Wiper

Counter

Register

(WCR)

0

1

/R

Wiper

Counter

Register

(WCR)

Resistor

Array

Pot 1

H3 H3

Resistor

Array

Pot 3

2

V

/R

L1 L1

2

3

V

/R

L3 L3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9258

PIN DESCRIPTIONS

Host Interface Pins

SERIAL CLOCK (SCL)

PIN CONFIGURATION

SOIC/TSSOP

A3

NC

A0

1

2

24

23

22

21

20

19

18

17

16

SCL

The SCL input is used to clock data into and out of the

X9258.

V

/R

W3 W3

V

/R

3

L2 L2

V

/R

H3 H3

/R

4

H2 H2

V

/R

5

L3 L3

W2 W2

SERIAL DATA (SDA)

V–

V

V+

6

SDA is a bidirectional pin used to transfer data into

and out of the device. It is an open drain output and

may be wire-ORed with any number of open drain or

open collector outputs. An open drain output requires

the use of a pull-up resistor. For selecting typical

values, refer to the guidelines for calculating typical

values on the bus pull-up resistors graph.

X9258

V

7

CC

SS

V

/R

V

/R

8

W1 W1

L0 L0

V

/R

H0 H0

9

H1 H1

V

/R

W0 W0

10

15

14

L1 L1

A1

A2

11

12

WP

13

SDA

DEVICE ADDRESS (A - A )

0

3

The Address inputs are used to set the least

significant 4 bits of the 8-bit slave address. A match in

the slave address serial data stream must be made

with the address input in order to initiate

communication with the X9258. A maximum of 16

devices may occupy the 2-wire serial bus.

PIN NAMES

Symbol

Description

SCL

Serial Clock

Serial Data

SDA

A0-A3

Device Address

Potentiometer Pins

V

/R - V /R

H0 H0 H3 H3

/R - V /R

L0 L0 L3 L3

,

Potentiometer Pins

(terminal equivalent)

V /R (V /R - V /R ), V /R (V /R

H0 H0 H3 H3 L0 L0

L3 L3

-

H

L

V

/R

- V /R

Potentiometers Pins

(wiper equivalent)

V

/R )

W0 W0 W3 W3

The V /R and V /R inputs are equivalent to the

H

L

WP

Hardware Write Protection

Analog Supplies

terminal connections on either end of a mechanical

potentiometer.

V+,V-

V

System Supply Voltage

System Ground

CC

SS

V /R (V /R

W0 W0

- V /R )

W3 W3

W

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

NC

No Connection (Allowed)

PRINCIPLES OF OPERATION

The X9258 is highly integrated microcircuit

a

incorporating four resistor arrays and their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the DCP potentiometers.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to

the Data Registers.

Analog Supplies V+, V-

Serial Interface—2-Wire

The Analog Supplies V+, V- are the supply voltages for

the DCP analog section.

The X9258 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

FN8168.1

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May 6, 2005

X9258

and provide the clock for both transmit and receive

operations. Therefore, the X9258 will be considered a

slave device in all applications.

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

data registers into the WCR. These data registers and

the WCR can be read and written by the host system.

Clock and Data Conventions

Device Addressing

Data states on the SDA line can change only during

SCL LOW periods (t

SCL HIGH are reserved for indicating start and stop

conditions.

). SDA state changes during

Following a start condition the master must output the

address of the slave it is accessing. The most

significant four bits of the slave address are the device

type identifier (refer to Figure 1 below). For the X9258

this is fixed as 0101[B].

LOW

Start Condition

All commands to the X9258 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

Figure 1. Slave Address

while SCL is HIGH (t

). The X9258 continuously

HIGH

Device Type

Identifier

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this

condition is met.

0

1

0

1

A3

A2

A1

A0

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH.

Device Address

The next four bits of the slave address are the device

address. The physical device address is defined by the

state of the A0 - A3 inputs. The X9258 compares the

serial data stream with the address input state; a

successful compare of all four address bits is required

Acknowledge

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

for the X9258 to respond with an acknowledge. The A

- A inputs can be actively driven by CMOS input

0

3

signals or tied to V

or V

.

CC

SS

Acknowledge Polling

The disabling of the inputs, during the internal

nonvolatile write operation, can be used to take

advantage of the typical 5ms nonvolatile write cycle

time. Once the stop condition is issued to indicate the

end of the nonvolatile write command the X9258

initiates the internal write cycle. ACK polling can be

initiated immediately. This involves issuing the start

condition followed by the device slave address. If the

X9258 is still busy with the write operation no ACK will

be returned. If the X9258 has completed the write

operation an ACK will be returned and the master can

then proceed with the next operation.

The X9258 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9258 will respond with a final acknowledge.

Array Description

The X9258 is comprised of four resistor arrays. Each

array contains 255 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the fixed terminals of a mechanical

potentiometer (V /R and V /R inputs).

H

L

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

(V ) output. Within each individual array only one

W

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

8 bits of the WCR are decoded to select, and enable,

one of 256 switches.

FN8168.1

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X9258

ACK Polling Sequence

Four of the nine instructions end with the transmission

of the instruction byte. The basic sequence is

illustrated in Figure 3. These two-byte instructions

exchange data between the Wiper Counter Register

and one of the data registers. A transfer from a Data

Register to a Wiper Counter Register is essentially a

write to a static RAM. The response of the wiper to this

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a data

register is a write to nonvolatile memory and takes a

minimum of t

to complete. The transfer can occur

WR

Issue Slave

Address

Issue STOP

between one of the four potentiometers and one of its

associated registers; or it may occur globally, wherein

the transfer occurs between all of the potentiometers

and one of their associated registers.

ACK

Returned?

No

Four instructions require a three-byte sequence to

complete. These instructions transfer data between

the host and the X9258; either between the host and

one of the data registers or directly between the host

and the Wiper Counter Register. These instructions

are: Read Wiper Counter Register (read the current

wiper position of the selected pot), Write Wiper

Counter Register (change current wiper position of the

selected pot), Read Data Register (read the contents

of the selected nonvolatile register) and Write Data

Register (write a new value to the selected data

register). The sequence of operations is shown in

Figure 4.

Yes

Further

Operation?

No

Yes

Issue

Instruction

Issue STOP

Proceed

Instruction Structure

The next byte sent to the X9258 contains the

instruction and register pointer information. The four

most significant bits are the instruction. The next four

bits point to one of the two pots and when applicable

they point to one of four associated registers. The

format is shown below in Figure 2.

Figure 2. Instruction Byte Format

Register

Select

I3

I2

I1

I0

R1 R0

P1 P0

Wiper Counter

Register Select

Instructions

The four high order bits define the instruction. The next

two bits (R1 and R0) select one of the four registers

that is to be acted upon when a register oriented

instruction is issued. The last bits (P1, P0) select

which one of the four potentiometers is to be affected

by the instruction.

FN8168.1

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X9258

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

S

T

O

P

The Increment/Decrement command is different from

the other commands. Once the command is issued

and the X9258 has responded with an acknowledge,

the master can clock the selected wiper up and/or

down in one segment steps; thereby, providing a fine

tuning capability to the host. For each SCL clock pulse

Similarly, for each SCL clock pulse while SDA is LOW,

the selected wiper will move one resistor segment

towards the V /R terminal. A detailed illustration of

L

the sequence and timing for this operation are shown

in Figures 5 and 6 respectively.

(t

) while SDA is HIGH, the selected wiper will

HIGH

move one resistor segment towards the V terminal.

H

Table 1. Instruction Set

Instruction Set

Instruction

I

R

P

Operation

1/0 1/0 Read the contents of the Wiper Counter Register

pointed to by P - P

3

2

1

0

1

0

1

0

Read Wiper Counter

Register

1

0

1

0

1

0

1

0

1

0

Write Wiper Counter

Register

0

1

0

1/0 1/0 Write new value to the Wiper Counter Register

pointed to by P - P

1

0

Read Data Register

1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed

to by P - P and R - R

1

0

1

0

Write Data Register

1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to

by P - P and R - R

1

0

1

0

XFR Data Register to

Wiper Counter Register

1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed

to by P - P and R - R to its associated Wiper

1

0

1

0

Counter Register

XFR Wiper Counter

Register to Data

Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Reg-

ister pointed to by P - P to the Data Register

1

0

pointed to by R - R

1

Global XFR Data

Registers to Wiper

Counter Registers

1/0 1/0

0

Transfer the contents of the Data Registers

pointed to by R - R of all four pots to their re-

spective Wiper Counter Registers

1

0

Global XFR Wiper

Counter Registers

to Data Register

Transfer the contents of both Wiper Counter

Registers to their respective data Registers

pointed to by R - R of all four pots

1

0

Increment/Decrement

Wiper Counter Register

0

1/0 1/0 Enable Increment/decrement of the ControlLatch

pointed to by P - P

1

0

Note: (1) 1/0 = data is one or zero

FN8168.1

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X9258

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

D7 D6 D5 D4 D3 D2 D1 D0

A

C

K

S

T

O

P

Figure 5. Increment/Decrement Instruction Sequence

F

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

I

D

E

C

1

S

T

O

P

I

D

N

C

1

N

C

2

N

C

n

E

C

n

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

t

WRID

SCL

SDA

Voltage Out

V

/R

W

FN8168.1

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6

X9258

Figure 7. Acknowledge Response from Receiver

SCL from

Master

1

8

9

Data Output

from Transmitter

Data Output

from Receiver

START

Acknowledge

Figure 8. Detailed Potentiometer Block Diagram Detailed Operation

Serial Data Path

V /R

H H

Serial

BUS

Input

From Interface

Circuitry

C

o

u

n

t

Register 0

Register 2

Register 1

Register 3

8

Parallel

BUS

Input

e

r

Wiper

D

e

c

Counter

Register

(WCR)

o

d

e

INC/DEC

Logic

If WCR = 00[H] then V /R = V /R

W

L

UP/DN

If WCR = FF[H] then V /R = V /R

H

W

H

V /R

L

Modified SCL

CLK

V

/R

W

All DCP potentiometers share the serial interface and

share a common architecture. Each potentiometer has

a Wiper Counter Register and four Data Registers. A

detailed discussion of the register organization and

array operation follows.

one of 256 switches along its resistor array. The

contents of the WCR can be altered in four ways: it

may be written directly by the host via the Write Wiper

Counter Register instruction (serial load); it may be

written indirectly by transferring the contents of one of

four associated Data Registers via the XFR Data

Register instruction (parallel load); it can be modified

one step at a time by the Increment/Decrement

instruction. Finally, it is loaded with the contents of its

data register zero (R0) upon power-up.

Wiper Counter Register

The X9258 contains four Wiper Counter Registers,

one for each DCP potentiometer. The Wiper Counter

Register can be envisioned as a 8-bit parallel and

serial load counter with its outputs decoded to select

FN8168.1

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X9258

The WCR is a volatile register; that is, its contents are

lost when the X9258 is powered-down. Although the

register is automatically loaded with the value in R0

upon power-up, it should be noted this may be

different from the value present at power-down.

REGISTER DESCRIPTIONS

Data Registers, (8-Bit), Nonvolatile

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

NV

(MSB)

(LSB)

Data Registers

Each potentiometer has four nonvolatile Data

Registers. These can be read or written directly by the

host and data can be transferred between any of the

four Data Registers and the WCR. It should be noted

all operations changing data in one of these registers

is a nonvolatile operation and will take a maximum of

10ms.

Four 8-bit Data Registers for each DCP. (sixteen 8-bit

registers in total).

– {D7~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four

different wiper values. The contents of Data Register

0 are automatically moved to the wiper counter

register on power-up.

If the application does not require storage of multiple

settings for the potentiometer, these registers can be

used as regular memory locations that could possibly

store system parameters or user preference data.

Wiper Counter Register, (8-Bit), Volatile

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.

(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.

(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).

(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by slave on SDA)

S

A

C

K

S

A

C

K

M S

A T

C O

K P

W W W W W W W W

P P P P P P P P

A A A A

P P

1 0

0

1

0

1

1 0 0 1 0 0

3

2

1

0

7

6 5 4 3 2 1 0

Write Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

Data Byte

(sent by master on SDA)

S

A

C

K

S

A

C

K

S S

A T

C O

K P

W W W W W W W W

P P P P P P P P

A A A A

P P

1 0

0

1

0

1

1 0 1 0 0 0

3

2

1

0

7

6 5 4 3 2 1 0

Read Data Register (DR)

S device type device

instruction DR and WCR

Data Byte

(sent by slave on SDA)

S

A

C

K

S

A

C

K

M S

T

A

R

T

identifier

addresses

opcode

addresses

A T

C O

K P

W W W W W W W W

P P P P P P P P

A A A A

R

1

R

0

P

1

P

0

1

0

1

1 0 1 1

3

2

1

0

7

6 5 4 3 2 1 0

FN8168.1

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X9258

Write Data Register (WR)

S device type

device

addresses

instruction DR and WCR

Data Byte

(sent by master on SDA)

S

A

C

K

S

A

C

K

S S

T

A

R

T

identifier

opcode

addresses

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

W W W W W W W W

P P P P P P P P

A A A A

R

1

R

0

P

1

P

0

1

0

1

1 1 0 0

3

2 1 0

7

6 5 4 3 2 1 0

XFR Data Register (DR) to Wiper Counter Register (WCR)

S device type

device

addresses

instruction DR and WCR

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

opcode

addresses

A A A A

R

1

R

0

P

1

P

0

1

0

1

1 1 0 1

3

2 1 0

XFR Wiper Counter Register (WCR) to Data Register (DR)

S device type

device

addresses

instruction DR and WCR

S

A

C

K

S S

T

A

R

T

identifier

opcode

addresses

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

A A A A

R

1

R

0

P

1

P

0

1

0

1

1 1 1 0

3

2 1 0

Increment/Decrement Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SDA)

S

A

C

K

S

A

C

K

S

T

O

P

A A A A

P

0

I/ I/

D D

I/ I/

D D

0

1

0

1

0

1

0

1

.

3

2 1 0

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

DR

addresses

S

A

C

K

S

A

C O

S

T

A A A A

R R

1 0

0

1

0

1

0

1

0 0

K

P

3

2

1

0

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S device type

device

addresses

instruction

opcode

DR

addresses

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

HIGH-VOLTAGE

WRITE CYCLE

A A A A

R R

1 0

0

1

0

1

0

0 0

3

2

1

0

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X9258

SYMBOL TABLE

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

120

WAVEFORM

INPUTS

OUTPUTS

V

CC MAX

R

=

=1.8kΩ

MIN

IOL MIN

100

80

Must be

steady

Will be

steady

t

R

=

MAX

C

BUS

May change

from Low to

High

May change

from High to

Low

Will change

from Low to

High

Will change

from High to

Low

Max.

Resistance

60

40

20

0

Min.

Resistance

Don’t Care:

Changes

Allowed

N/A

Changing:

State Not

Known

0

20 40 60 80 100 120

Bus Capacitance (pF)

Center Line

is High

Impedance

FN8168.1

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X9258

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias..................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SDA, SCL or any address input

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those

listed in the operational sections of this specification) is

not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

with respect to V ................................. -1V to +7V

SS

Voltage on V+ (referenced to V ) ........................10V

SS

Voltage on V- (referenced to V ) ........................-10V

SS

(V+) - (V-)...............................................................12V

Any V /R ...............................................................V+

H

Any V /R .................................................................V-

L

Lead temperature (soldering, 10 seconds)........ 300°C

(10 seconds)................................................±15mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

0°C

Max.

+70°C

+85°C

Device

X9258

Supply Voltage (V ) Limits

CC

Commercial

Industrial

5V ± 10%

-40°C

X9258-2.7

2.7V to 5.5V

ANALOG CHARACTERISTICS

(Over recommended operating conditions unless otherwise stated.)

Limits

Symbol

Parameter

End to end resistance tolerance

Power rating

Min.

Typ.

Max.

Unit

%

Test Conditions

±20

50

mW

mA

Ω

25°C, each pot

I

Wiper current

±7.5

250

100

+5.5

-4.5

-2.7

V+

Wiper current = ± 1mA

W

R

Wiper resistance

150

40

I

= ± 1mA @ V+ = 3V, V- = -3V

= ± 1mA @ V+ = 5V, V- = -5V

W

Wiper resistance

Ω

V+

Voltage on V+ Pin

X9258

+4.5

+2.7

-5.5

V-

V

X9258-2.7

X9258

V-

Voltage on V- Pin

V

X9258 -2.7

V

Voltage on any V /R or V /R pin

V

dBV

%

TERM

H

L

Noise

-120

0.6

Ref: 1kHz

(4)

Resolution

(1)

(3)

Absolute linearity

Relative linearity

±1

MI

V

- V

w(n)(expected)

w(n)(actual)

- [V

(2)

(3)

MI

±0.6

]

w(n) + MI

w(n + 1)

Temperature coefficient of R

±300

ppm/°C

TOTAL

Ratiometric Temperature Coefficient

C /C /C Potentiometer Capacitance

W

±20 ppm/°C

pF

10/10/25

See Circuit #3

H

L

FN8168.1

11

May 6, 2005

X9258

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

I

V

supply current (Nonvol-

1

mA

f = 400kHz, SDA = Open,

SCL

Other Inputs = V

SS

CC1

CC

atile Write)

I

V

supply current (move

100

µA

f

= 400kHz, SDA = Open,

CC2

CC

wiper, write, read)

SCL

Other Inputs = V

SS

SCL = SDA = V , Addr. = V

SS

I

V

current (standby)

5

µA

V

SB

CC

I

Input leakage current

Output leakage current

Input HIGH voltage

Input LOW voltage

Output LOW voltage

10

V

= V to V

SS CC

LI

IN

I

= V to V

SS CC

LO

OUT

V

x 0.7

V

+ 0.1

CC

IH

CC

-0.5

V

x 0.3

V

IL

CC

0.4

V

I

= 3mA

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/255 or (V /R —V /R )/255, single pot

H

L

(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.

ENDURANCE AND DATA RETENTION

Parameter

Minimum endurance

Data retention

Min.

100,000

100

Unit

Data changes per bit per register

years

CAPACITANCE

Symbol

Test

Max.

Unit

pF

Test Conditions

(5)

C

Input/output capacitance (SDA)

8

6

V

= 0V

I/O

(5)

C

Input capacitance (A0, A1, A2, A3, and SCL)

pF

V

IN

POWER-UP TIMING

Symbol

Parameter

Min.

Max.

1

Unit

(6)

t

Power-up to initiation of read operation

Power-up to initiation of write operation

ms

PUR

(6)

t

5

PUW

(7)

t

V

Power up ramp

CC

0.2

50

V/msec

R

CC

POWER UP AND DOWN REQUIREMENT

The are no restrictions on the sequencing of the bias supplies V , V+, and V- provided that all three supplies reach

CC

their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+

and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their

final value. The V

ramp rate spec is always in effect.

CC

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) t and t are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific

PUR

PUW CC

instruction can be issued. These parameters are periodically sampled and not 100% tested.

(7) Sample tested only.

FN8168.1

12

May 6, 2005

X9258

A.C. TEST CONDITIONS

Test Circuit #3 SPICE Macro Model

Input pulse levels

V

x 0.1 to V

x 0.5

x 0.9

CC

10ns

Macro Model

Input rise and fall times

Input and output timing level

R

TOTAL

V

CC

R

L

H

C

L

C

H

C

EQUIVALENT A.C. LOAD CIRCUIT

W

10pF

5V

2.7V

10pF

25pF

1533Ω

R

W

SDA Output

100pF

AC TIMING (Over recommended operating condition)

Symbol Parameter

Min.

Max.

Unit

kHz

ns

f

Clock frequency

400

SCL

t

Clock cycle time

2500

600

1300

600

100

30

CYC

t

Clock high time

HIGH

t

Clock low time

LOW

t

Start setup time

SU:STA

HD:STA

SU:STO

t

Start hold time

t

Stop setup time

t

SDA data input setup time

SDA data input hold time

SCL and SDA rise time

SCL and SDA fall time

SU:DAT

HD:DAT

t

300

900

R

t

F

t

SCL low to SDA data output valid time

SDA data output hold time

AA

t

50

DH

T

Noise suppression time constant at SCL and SDA inputs

Bus free rime (prior to any transmission)

WP, A0, A1, A2 and A3 setup time

I

t

1300

0

BUF

t

SU:WPA

t

WP, A0, A1, A2 and A3 hold time

0

HD:WPA

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol

Parameter

Typ.

Max.

Unit

t

High-voltage write cycle time (store instructions)

5

10

ms

WR

FN8168.1

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May 6, 2005

X9258

DCP TIMING

Symbol

Parameter

Min. Max. Unit

t

Wiper response time after the third (last) power supply is stable

10

µs

WRPO

t

Wiper response time after instruction issued (all load instructions)

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

WRL

t

WRID

Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS 2-WIRE INTERFACE

START and STOP Timing

(START)

(STOP)

t

F

R

SCL

SDA

t

SU:STO

SU:STA

HD:STA

t

F

R

Input Timing

t

CYC

HIGH

SCL

t

LOW

SDA

t

BUF

SU:DAT

HD:DAT

Output Timing

SCL

SDA

t

DH

AA

FN8168.1

14

May 6, 2005

X9258

DCP Timing (for All Load Instructions)

(STOP)

SCL

SDA

LSB

t

WRL

VWx

DCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address

Inc/Dec

SDA

VWx

t

WRID

Write Protect and Device Address Pins Timing

(START)

(STOP)

SCL

...

(Any Instruction)

...

SDA

...

t

SU:WPA

HD:WPA

WP

A0, A1

A2, A3

FN8168.1

15

May 6, 2005

X9258

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

+V

R

V

R

V

/R

W

I

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Application Circuits

Noninverting Amplifier

Voltage Regulator

V

+

–

S

V

V (REG)

O

317

O

IN

R

1

R

2

I

adj

R

1

2

V

= (1+R /R )V

V

(REG) = 1.25V (1+R /R )+I

R

adj 2

O

2

1

S

O

2

1

Offset Voltage Adjustment

Comparator with Hysteresis

R

2

1

V

–

+

S

V

S

O

100kΩ

–

+

V

O

TL072

R

1

2

10kΩ

+12V

V

= {R /(R +R )} V (max)

1 1 2 O

UL

LL

10kΩ

-12V

= {R /(R +R )} V (min)

1

2

O

FN8168.1

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May 6, 2005

X9258

Application Circuits (continued)

Attenuator

Filter

C

V

+

–

S

R

V

R

1

2

O

–

R

V

O

V

+

S

R

3

R

2

R

4

All R = 10kΩ

S

R

1

G

= 1 + R /R

2 1

V

= G V

S

O

fc = 1/(2πRC)

-1/2 ≤ G ≤ +1/2

Inverting Amplifier

Equivalent L-R Circuit

R

2

1

V

S

R

2

C

1

–

+

V

+

–

S

V

O

R

1

Z

IN

V = G V

O

S

1

3

G = - R /R

2

Z

= R + s R (R + R ) C = R + s Leq

2 2 1 3 1 2

IN

(R + R ) >> R

1

3

2

Function Generator

C

R

1

2

–

+

R

}

A

B

frequency ∝ R , R , C

1

2

amplitude ∝ R , R

A

B

FN8168.1

17

May 6, 2005

X9258

PACKAGING INFORMATION

24-Lead Plastic, TSSOP, Package Code V24

.026 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.303 (7.70)

.311 (7.90)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.06)

.005 (.15)

.010 (.25)

Gage Plane

(7.72)

(4.16)

0° - 8°

Seating Plane

.020 (.50)

.030 (.75)

(1.78)

(0.42)

Detail A (20X)

(0.65)

ALL MEASUREMENTS ARE TYPICAL

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8168.1

18

May 6, 2005

X9258

PACKAGING INFORMATION

24-Lead Plastic Small Outline Gull Wing Package Type S

0.393 (10.00)

0.290 (7.37)

0.299 (7.60)

0.420 (10.65)

Pin 1 Index

Pin 1

0.014 (0.35)

0.020 (0.50)

0.598 (15.20)

0.610 (15.49)

(4X) 7°

0.092 (2.35)

0.105 (2.65)

0.003 (0.10)

0.012 (0.30)

0.050 (1.27)

0.050"Typical

0.010 (0.25)

0.020 (0.50)

X 45°

0.050"

Typical

0° - 8°

0.009 (0.22)

0.013 (0.33)

0.420"

0.015 (0.40)

0.050 (1.27)

0.030" Typical

24 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8168.1

19

May 6, 2005

X9258

Ordering Information

X9258

Y

P

T

V

Limits

CC

Device

Blank = 5V ±10%

-2.7 = 2.7 to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Package

S24 = 24-Lead SOIC

V24 = 24-Lead TSSOP

Potentiometer Organization

T = 100KΩ

U= 50kΩ

S & V Package Marking

Line #1

Line #2

Line #3

Line #4

(Blank)

(Part Number)

(Date Code) (*)

(Blank)

= F 2.7V 0 to 70°C

G 2.7V -40 to +85°C

I

5V

-40 to +85°C

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8168.1

20

May 6, 2005


型号：	X9258UV24I
厂家：	Intersil
描述：	Low Noise/Low Power/2-Wire Bus/256 Taps 低噪音/低功耗/ 2 - Wire总线/ 256水龙头
文件：	总20页 (文件大小：347K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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