X9258UV24IZ_技术文档

DATASHEET

X9258

FN8168

Rev 6.00

December 15, 2011

Low Noise/Low Power/2-Wire Bus/256 Taps Quad Digital Controlled

Potentiometers (XDCP™)

The X9258 integrates 4 digitally controlled potentiometers

(XDCP™) on a monolithic CMOS integrated circuit.

Features

• Four potentiometers in one package

The digitally controlled potentiometer is implemented using

255 resistive elements in a series array. Between each

element are tap points connected to the wiper terminal

through switches. The position of the wiper on the array is

controlled by the user through the 2-wire bus interface. Each

potentiometer has associated with it a volatile Wiper Counter

Register (WCR) and 4 non-volatile Data Registers

(DR0:DR3) that can be directly written to and read by the

user. The contents of the WCR controls the position of the

wiper on the resistor array though the switches. Power-up

recalls the contents of DR0 to the WCR.

• 256 resistor taps/potentiometer................. 0.4% resolution

• 2-wire serial interface

• Wiper resistance, 40Ωtypical @ V+ = 5V, V- = -5V

• Four nonvolatile data registers for each potentiometer

• Nonvolatile storage of wiper position

• Standby current <5µA max (total package)

• Power supplies

- V

CC

= 2.7V to 5.5V

- V+ = 2.7V to 5.5V

- V- = -2.7V to -5.5V

The XDCP™ can be used as a three-terminal potentiometer

or as a two-terminal variable resistor in a wide variety of

applications including control, parameter adjustments, and

signal processing.

• 100kΩ, 50kΩtotal potentiometer resistance

• High reliability

- Endurance: 100,000 data changes per bit per register

- Register data retention . . . . . . . . . . . . . . . . . . 100 years

• 24 Ld SOIC, 24 Ld TSSOP

• Dual supply version of X9259

• Pb-free (RoHS compliant)

Block Diagram

POT 0

V

CC

SS

V

R

V

/R

R

0

2

1

3

H0 H0

0

2

1

3

WIPER

COUNTER

REGISTER

(WCR)

WIPER

COUNTER

REGISTER

(WCR)

V

/R

H2 H2

RESISTOR

ARRAY

POT 2

V+

V-

V

/R

L0 L0

WP

V

/R

L2 L2

V

/R

SCL

SDA

A0

W0 W0

V

/R

W2 W2

INTERFACE

AND

CONTROL

CIRCUITRY

A1

8

A2

V

/R

A3

W1 W1

DATA

V

/R

W3 W3

R

0

2

1

3

V

/R

H1 H1

R

WIPER

COUNTER

REGISTER

(WCR)

0

2

1

3

V

/R

WIPER

COUNTER

REGISTER

(WCR)

H3 H3

RESISTOR

ARRAY

POT 1

RESISTOR

ARRAY

POT 3

R

V

/R

L1 L1

V

/R

L3 L3

FN8168 Rev 6.00

December 15, 2011

Page 1 of 19

X9258

Ordering Information

POTENTIOMETER TEMPERATURE

PART NUMBER

(Note 2)

PART

V

LIMITS

(V)

ORGANIZATION

(kΩ)

RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

CC

MARKING

X9258US Z

X9258US ZI

X9258UV ZI

X9258TS Z

X9258TS ZI

X9258US24Z (Note 1)

X9258US24IZ (Note 1)

X9258UV24IZ

5 ±10

50

0 to +70

-40 to +85

0 to +70

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

M24.3

MDP0044

M24.3

X9258TS24Z

100

50

X9258TS24IZ (Note 1)

-40 to +85

0 to +70

M24.3

X9258US24Z-2.7 (Note 1) X9258US ZF

X9258US24IZ-2.7 (Note 1) X9258US ZG

2.7 to 5.5

M24.3

-40 to +85

0 to +70

M24.3

X9258UV24IZ-2.7

X9258UV ZG

MDP0044

M24.3

X9258TS24Z-2.7 (Note 1) X9258TS ZF

X9258TS24IZ-2.7 (Note 1) X9258TS ZG

100

-40 to +85

0 to +70

M24.3

X9258TV24IZ-2.7

X9258TV24Z-2.7

NOTES:

X9258TV ZG

X9258TV ZF

MDP0044

1. Add “T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for X9258. For more information on MSL please see tech brief TB363.

FN8168 Rev 6.00

December 15, 2011

Page 2 of 19

X9258

(24 LD SOIC, TSSOP)

TOP VIEW

Pinout

A3

NC

A0

1

2

24

23

22

21

20

19

18

17

16

SCL

V

/R

W3 W3

V

/R

3

L2 L2

V

/R

H3 H3

/R

4

H2 H2

V

/R

5

L3 L3

W2 W2

V–

V

V+

6

X9258

V

7

CC

SS

V

/R

V

/R

8

W1 W1

L0 L0

V

/R

H0 H0

9

H1 H1

V

/R

W0 W0

10

15

14

L1 L1

A1

A2

11

12

WP

13

SDA

Pin Descriptions

Host Interface Pins

SERIAL CLOCK (SCL)

Pin Names

SYMBOL

DESCRIPTION

Serial Clock

SCL

SDA

Serial Data

The SCL input is used to clock data into and out of the X9258.

A0 thru A3

Device Address

SERIAL DATA (SDA)

V

/R thru V /R

H0 H0 H3 H3

,

Potentiometer Pins

(terminal equivalent)

SDA is a bidirectional pin used to transfer data into and out of

the device. It is an open drain output and may be wire-ORed

with any number of open drain or open collector outputs. An

open drain output requires the use of a pull-up resistor. For

selecting typical values, refer to “Guidelines for Calculating

Typical Values of Bus Pull-Up Resistors” on page 10.

/R thru V /R

L0 L0 L3 L3

V

/R

thru V /R

Potentiometers Pins

(wiper equivalent)

W0 W0 W3 W3

WP

V+, V-

Hardware Write Protection

Analog Supplies

DEVICE ADDRESS (A - A )

0

3

V

System Supply Voltage

System Ground

CC

The Address inputs are used to set the least significant 4 bits

of the 8-bit slave address. A match in the slave address serial

data stream must be made with the address input in order to

initiate communication with the X9258. A maximum of 16

devices may occupy the 2-wire serial bus.

V

SS

NC

No Connection (Allowed)

Principles Of Operation

The X9258 is a highly integrated microcircuit incorporating four

resistor arrays and their associated registers and counters and

the serial interface logic providing direct communication

between the host and the DCP potentiometers.

Potentiometer Pins

V /R (V /R - V /R ), V /R (V /R - V /R

)

H

H0 H0 H3 H3 L0 L0 L3 L3

L

The V /R and V /R inputs are equivalent to the terminal

H

L

connections on either end of a mechanical potentiometer.

Serial Interface (2-Wire)

V

/R (V /R - V /R

)

W

W0 W0 W3 W3

The X9258 supports a bidirectional bus oriented protocol. The

protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The

device controlling the transfer is a master and the device being

controlled is the slave. The master will always initiate data

transfers and provide the clock for both transmit and receive

operations. Therefore, the X9258 will be considered a slave

device in all applications.

The wiper outputs are equivalent to the wiper output of a

mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to the Data

Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages for the

DCP analog section.

FN8168 Rev 6.00

December 15, 2011

Page 3 of 19

X9258

Clock and Data Conventions

Device Addressing

Data states on the SDA line can change only during SCL LOW

periods (t ). SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions.

Following a start condition the master must output the address

of the slave it is accessing. The most significant 4 bits of the

slave address are the device type identifier (refer to Figure 1).

For the X9258 this is fixed as 0101[B].

LOW

Start Condition

DEVICE TYPE

IDENTIFIER

All commands to the X9258 are preceded by the start

condition, which is a HIGH to LOW transition of SDA while SCL

is HIGH (t

). The X9258 continuously monitors the SDA

HIGH

and SCL lines for the start condition and will not respond to any

command until this condition is met.

0

1

0

1

A3

A2

A1

A0

Stop Condition

DEVICE ADDRESS

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA while SCL is HIGH.

FIGURE 1. SLAVE ADDRESS

The next 4 bits of the slave address are the device address.

The physical device address is defined by the state of the A0

thru A3 inputs. The X9258 compares the serial data stream

with the address input state; a successful compare of all

4 address bits is required for the X9258 to respond with an

Acknowledge

Acknowledge is a software convention used to provide a

positive handshake between the master and slave devices on

the bus to indicate the successful receipt of data. The

transmitting device, either the master or the slave, will release

the SDA bus after transmitting 8 bits. The master generates a

ninth clock cycle and during this period the receiver pulls the

SDA line LOW to acknowledge that it successfully received the

8 bits of data.

acknowledge. The A thru A inputs can be actively driven by

0

3

CMOS input signals or tied to V

or V .

SS

CC

Acknowledge Polling

The disabling of the inputs (during the internal nonvolatile write

operation), can be used to take advantage of the typical 5ms

nonvolatile write cycle time. Once the stop condition is issued

to indicate the end of the nonvolatile write command, the

X9258 initiates the internal write cycle. ACK polling can be

initiated immediately. This involves issuing the start condition

followed by the device slave address. If the X9258 is still busy

with the write operation, no ACK will be returned. If the X9258

has completed the write operation an ACK will be returned and

the master can then proceed with the next operation.

The X9258 will respond with an acknowledge after recognition

of a start condition and its slave address and once again after

successful receipt of the command byte. If the command is

followed by a data byte, the X9258 will respond with a final

acknowledge.

Array Description

The X9258 is comprised of four resistor arrays. Each array

contains 255 discrete resistive segments that are connected in

series. The physical ends of each array are equivalent to the

fixed terminals of a mechanical potentiometer (V /R and

H

V /R inputs).

L

At both ends of each array and between each resistor segment

is a CMOS switch connected to the wiper (V ) output. Within

W

each individual array only one switch may be turned on at a

time. These switches are controlled by the Wiper Counter

Register (WCR). The 8 bits of the WCR are decoded to select,

and enable, one of 256 switches.

The WCR may be written directly, or it can be changed by

transferring the contents of one of four associated data

registers into the WCR. These data registers and the WCR can

be read and written by the host system.

FN8168 Rev 6.00

December 15, 2011

Page 4 of 19

X9258

.

ACK Polling Sequence

REGISTER

SELECT

NONVOLATILE WRITE

COMMAND COMPLETED

ENTER ACK POLLING

I3

I2

I1

I0

R1

R0

P1

P0

WIPER COUNTER

REGISTER SELECT

INSTRUCTIONS

ISSUE

START

FIGURE 2. INSTRUCTION BYTE FORMAT

The four high order bits define the instruction. The next 2 bits

(R1 and R0) select one of the four registers that is to be acted

upon when a register oriented instruction is issued. The last

bits (P1, P0) select which one of the four potentiometers is to

be affected by the instruction.

ISSUE SLAVE

ADDRESS

ISSUE STOP

ACK

NO

RETURNED?

Four of the nine instructions end with the transmission of the

instruction byte. The basic sequence is illustrated in Figure 3.

These two-byte instructions exchange data between the Wiper

Counter Register and one of the data registers. A transfer from

a Data Register to a Wiper Counter Register is essentially a

write to a static RAM. The response of the wiper to this action

YES

FURTHER

OPERATION?

NO

will be delayed t

Register (current wiper position), to a data register is a write to

nonvolatile memory and takes a minimum of t to complete.

The transfer can occur between one of the four potentiometers

and one of its associated registers; or it may occur globally,

wherein the transfer occurs between all of the potentiometers

and one of their associated registers.

. A transfer from the Wiper Counter

WRL

YES

WR

ISSUE

INSTRUCTION

ISSUE STOP

PROCEED

Four instructions require a three-byte sequence to complete.

These instructions transfer data between the host and the

X9258; either between the host and one of the data registers or

directly between the host and the Wiper Counter Register.

These instructions are: Read Wiper Counter Register (read the

current wiper position of the selected potentiometer), Write

Wiper Counter Register (change current wiper position of the

selected potentiometer), Read Data Register (read the

contents of the selected nonvolatile register) and Write Data

Register (write a new value to the selected data register). The

sequence of operations is shown in Figure 4.

Instruction Structure

The next byte sent to the X9258 contains the instruction and

register pointer information. The four most significant bits are

the instruction. The next four bits point to one of the two

potentiometers and when applicable they point to one of four

associated registers. The format is shown in Figure 2.

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3

I2

I1 I0

R1 R0 P1 P0

A

C

K

S

T

O

P

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE

FN8168 Rev 6.00

December 15, 2011

Page 5 of 19

X9258

The Increment/Decrement command is different from the other

commands. Once the command is issued and the X9258 has

responded with an acknowledge, the master can clock the

selected wiper up and/or down in one segment steps; thereby,

providing a fine tuning capability to the host. For each SCL

Similarly, for each SCL clock pulse while SDA is LOW, the

selected wiper will move one resistor segment towards the

V /R terminal. A detailed illustration of the sequence and

L

timing for this operation are shown in Figures 5 and 6

respectively.

clock pulse (t

) while SDA is HIGH, the selected wiper will

HIGH

move one resistor segment towards the V terminal.

H

TABLE 1. INSTRUCTION SET

INSTRUCTION SET

INSTRUCTION

I

R

P

OPERATION

3

2

1

0

1

0

1

0

Read Wiper Counter Register

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1/0

0

1/0 Read the contents of the Wiper Counter Register pointed to

by P - P

1

0

Write Wiper Counter Register

Read Data Register

0

1/0 Write new value to the Wiper Counter Register pointed to by

- P

P

1

0

1/0

1/0 Read the contents of the Data Register pointed to by P - P

1 0

and R - R

1

0

Write Data Register

1/0 Write new value to the Data Register pointed to by P - P

1 0

and R - R

1

0

XFR Data Register to Wiper

Counter Register

1/0 Transfer the contents of the Data Register pointed to by

- P and R - R to its associated Wiper Counter Register

P

1

0

1

0

XFR Wiper Counter Register to

Data Register

1/0 Transfer the contents of the Wiper Counter Register pointed

to by P - P to the Data Register pointed to by R - R

1

0

1

0

Global XFR Data Registers to

Wiper Counter Registers

0

Transfer the contents of the Data Registers pointed to by

- R of all four potentiometers to their respective Wiper

R

1

0

Counter Registers

Global XFR Wiper Counter

Registers to Data Register

1

0

1

0

1/0

0

1/0

0

Transfer the contents of both Wiper Counter Registers to

their respective data Registers pointed to by R - R of all

1

0

four potentiometers

Increment/Decrement Wiper

Counter Register

1/0

1/0 Enable Increment/decrement of the Control Latch pointed to

by P - P

1

0

NOTE:

4. 1/0 = data is one or zero.

FN8168 Rev 6.00

December 15, 2011

Page 6 of 19

X9258

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0

R1 R0 P1 P0

A

C

K

D7 D6 D5 D4 D3 D2 D1 D0

A

C

K

S

T

O

P

FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE

I

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3

I2

I1 I0

R1 R0 P1 P0

A

C

K

I

D

E

C

1

S

T

O

P

I

N

C

D

E

C

N

C

1

N

C

2

n

FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE

F

I

INC/DEC

CMD

ISSUED

t

WRID

SCL

SD A

VOLTAGE OUT

V

/R

W

FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER

FN8168 Rev 6.00

December 15, 2011

Page 7 of 19

X9258

SERIAL DATA PATH

V /R

H H

SERIAL

BUS

FROM INTERFACE

CIRCUITRY

INPUT

REGISTER 0

REGISTER 1

8

PARALLEL

BUS

INPUT

WIPER

REGISTER 2

REGISTER 3

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

If WCR = 00[H] then V /R = V /R

L

W

L

UP/DN

CLK

If WCR = FF[H] then V /R = V /R

H

W

H

V /R

L

MODIFIED SCL

V

/R

W

FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM DETAILED OPERATION

All DCP potentiometers share the serial interface and share a

common architecture. Each potentiometer has a Wiper

Counter Register and four Data Registers. A detailed

discussion of the register organization and array operation

follows.

Data Registers

Each potentiometer has four nonvolatile Data Registers. These

can be read or written directly by the host and data can be

transferred between any of the four Data Registers and the

WCR. It should be noted all operations changing data in one of

these registers is a nonvolatile operation and will take a

maximum of 10ms.

Wiper Counter Register

The X9258 contains four Wiper Counter Registers, one for

each DCP potentiometer. The Wiper Counter Register can be

envisioned as a 8-bit parallel and serial load counter with its

outputs decoded to select one of 256 switches along its

resistor array. The contents of the WCR can be altered in four

ways:

If the application does not require storage of multiple settings

for the potentiometer, these registers can be used as regular

memory locations that could possibly store system parameters

or user preference data.

Register Descriptions

1. Written directly by the host via the Write Wiper Counter

Register instruction (serial load)

Data Registers, (8-bit), Nonvolatile

2. Written indirectly by transferring the contents of one of four

associated Data Registers via the XFR Data Register

instruction (parallel load)

WP7

NV

WP6

WP5

WP4

WP3

WP2

WP1

WP0

NV

3. Can be modified one step at a time by the

Increment/Decrement instruction.

(MSB)

(LSB)

4. Loaded with the contents of its data register zero (R0) upon

power-up.

Four 8-bit Data Registers for each DCP (sixteen 8-bit registers

in total).

The WCR is a volatile register; that is, its contents are lost

when the X9258 is powered-down. Although the register is

automatically loaded with the value in R0 upon power-up, it

should be noted this may be different from the value present at

power-down.

{D7~D0}: These bits are for general purpose not volatile data

storage or for storage of up to four different wiper values. The

contents of Data Register 0 are automatically moved to the

wiper counter register on power-up.

FN8168 Rev 6.00

December 15, 2011

Page 8 of 19

X9258

WCR can be loaded from any of the other Data Register or

Wiper Counter Register, (8-bit), Volatile

directly. The contents of the WCR can be saved in a DR.

WP7

V

WP6

WP5

WP4

WP3

WP2

WP1

WP0

V

Instruction Format

V

NOTES:

(MSB)

(LSB)

5. “MACK”/”SACK”: stands for the acknowledge sent by the

master/slave.

One 8-bit Wiper Counter Register for each DCP (four 8-bit

registers in total.)

6. “A3 ~ A0”: stands for the device addresses sent by the master.

7. “X”: indicates that it is a “0” for testing purpose but physically it is a

“don’t care” condition.

{D7~D0}: These bits specify the wiper position of the

respective DCP. The Wiper Counter Register is loaded on

power-up by the value in Data Register 0. The contents of the

8. “I”: stands for the increment operation, SDA held high during active

SCL phase (high).

9. “D”: stands for the decrement operation, SDA held low during active

SCL phase (high).

Read Wiper Counter Register (WCR)

S DEVICE TYPE

DEVICE

INSTRUCTION

OPCODE

WCR

WIPER POSITION

(SENT BY SLAVE ON SDA)

T

A

R

T

IDENTIFIER ADDRESSES S

ADDRESSES S

A

M S

A T

C O

K P

A

C

K

0

1

0

1

A3 A2 A1 A0

1

0

1

0

P1 P0

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

C

K

Write Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE

TYPE

IDENTIFIER ADDRESSES

DEVICE

S

A

C

K

INSTRUCTION

OPCODE

WCR

ADDRESSES

S

A

C

K

DATA BYTE

(SENT BY MASTER ON SDA)

S

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

1

0

1

0

P1 P0

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

Read Data Register (DR)

S

T

A

R

T

DEVICETYPE

IDENTIFIER ADDRESSES

DEVICE

INSTRUCTION DR AND WCR

DATA BYTE

(SENT BY SLAVE ON SDA)

S

A

C

K

OPCODE

ADDRESSES

S

A

C

K

M

S

A

C

K

T

O

P

0

1

0

1

A3 A2 A1 A0

1

0

1

R1 R0 P1 P0

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

Write Data Register (WR)

S

T

DEVICE

TYPE

HIGH-VOLTAGE

S S WRITE CYCLE

DEVICE

S INSTRUCTION DR AND WCR

S

A

C

K

DATA BYTE

(SENT BY MASTER ON SDA)

A IDENTIFIER ADDRESSES A

R

T

OPCODE

ADDRESSES

A T

C O

K P

C

K

0

1

0

1

A3 A2 A1 A0

1

0

R1 R0 P1 P0

WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0

FN8168 Rev 6.00

December 15, 2011

Page 9 of 19

X9258

XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE

TYPE

IDENTIFIER ADDRESSES

DEVICE

S

A

C

K

INSTRUCTION DR AND WCR

S

A

C

K

S

T

O

P

OPCODE

ADDRESSES

0

1

0

1

A3 A2 A1 A0

1

0

1

R1 R0 P1 P0

XFR Wiper Counter Register (WCR) to Data Register (DR)

S

T

A

R

T

DEVICE

TYPE

IDENTIFIER ADDRESSES

HIGH-VOLTAGE

WRITE CYCLE

DEVICE

S

A

C

K

INSTRUCTION DR AND WCR

S

A

C

K

S

T

O

P

OPCODE

ADDRESSES

0

1

0

1

A3 A2 A1 A0

1

0

R1 R0 P1 P0

Increment/Decrement Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER ADDRESSES

DEVICE

INSTRUCTION

OPCODE

WCR

ADDRESSES

INCREMENT/DECREMENT

(SENT BY MASTER ON SDA)

S

A

C

K

S

T

O

P

A

C

K

0

1

0

1

A3 A2 A1 A0

0

1

0

P1 P0

I/D I/D

.

I/D I/D

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER ADDRESSES

DEVICE

INSTRUCTION

OPCODE

DR

S

A

C

K

ADDRESSES

S

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

0

1

R1 R0

0

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S

T

A

R

T

DEVICE

TYPE

IDENTIFIER ADDRESSES

HIGH-VOLTAGE

WRITE CYCLE

DEVICE

S

A

C

K

INSTRUCTION

OPCODE

DR

S

A

C

K

S

T

O

P

ADDRESSES

0

1

0

1

A3 A2 A1 A0

1

0

R1 R0

0

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

Symbol Table

120

V

WAVEFORM

INPUTS

OUTPUTS

CC MAX

R

=

=1.8kΩ

MIN

IOL MIN

100

80

60

40

20

0

Must be

steady

Will be

steady

t

R

=

MAX

C

BUS

May change

from Low to

High

Will change

from Low to

High

MAXIMUM

RESISTANCE

May change

from High to

Low

Will change

from High to

Low

MINIMUM

RESISTANCE

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

0

20

40

60

80

100

120

BUS CAPACITANCE (pF)

N/A

Center Line

is High

Impedance

FN8168 Rev 6.00

December 15, 2011

Page 10 of 19

X9258

Absolute Maximum Ratings

Thermal Information

Voltage on SDA, SCL or any Address Input

Thermal Resistance (Typical)



(°C/W)



(°C/W)

JC

JA

with Respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

Voltage on V+ (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . .10V

SS

24 Lead SOIC (Notes 10, 11). . . . . . . .

24 Lead TSSOP (Notes 10, 11) . . . . . .

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

46

68

21

17

Voltage on V- (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . . -10V

SS

(V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

Any V /R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+

H

Any V /R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-

L

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15mA

W

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage Range (Typical)

X9258. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%

X9258-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

10.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

11. For  , the “case temp” location is taken at the package top center.

JC

Analog Specifications Over recommended operating conditions, unless otherwise specified.

MIN

MAX

SYMBOL

PARAMETER

End-to-end Resistance Tolerance

Power Rating

TEST CONDITIONS

(Note 12)

TYP

(Note 12) UNIT

±20

50

%

mW

mA

Ω

+25°C, each potentiometer

Wiper current = ±1mA

I

Wiper Current

±7.5

250

100

+5.5

-4.5

-2.7

V+

W

R

Wiper Resistance

I

= ± 1mA @ V+ = 3V, V- = -3V

= ± 1mA @ V+ = 5V, V- = -5V

150

40

W

R

Wiper Resistance

Ω

V+

Voltage on V+ Pin

X9258

+4.5

+2.7

-5.5

V-

V

X9258-2.7

X9258

V

V-

Voltage on V- Pin

V

X9258 -2.7

V

Voltage on any V /R or V /R Pin

V

TERM

H

L

Noise

Resolution (Note 16)

Ref: 1kHz

-120

0.6

dBV

%

Absolute Linearity (Note 13)

Relative Linearity (Note 14)

Temperature Coefficient of R

V

- V

±1

MI

(Note 15)

w(n)(actual)

w(n)(expected)

- [V

]

w(n) + MI

±0.6

MI

(Note 15)

w(n + 1)

±300

ppm/C

ppm/°C

pF

TOTAL

Ratiometric Temperature Coefficient

Potentiometer Capacitance

±20

C /C /C

W

See “Test Circuit #3 SPICE Macro

Model” on page 13

10/10/25

H

L

FN8168 Rev 6.00

December 15, 2011

Page 11 of 19

X9258

DC Operating Characteristics Over recommended operating conditions, unless otherwise specified.

MIN

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 12)

TYP

(Note 12)

UNIT

I

V

Supply Current (Nonvolatile

f = 400kHz, SDA = Open,

SCL

1

mA

CC1

CC2

CC

Write)

Other Inputs = V

SS

I

V

Supply Current (Move Wiper,

f

= 400kHz, SDA = Open,

100

µA

CC

Write, Read)

SCL

Other Inputs = V

SS

SCL = SDA = V , Addr. = V

SS

I

V

Current (Standby)

5

µA

V

SB

CC

I

Input Leakage Current

Output Leakage Current

Input HIGH Voltage

Input LOW Voltage

V

= V to V

SS CC

10

LI

IN

I

= V to V

SS CC

LO

OUT

V

x 0.7

V

CC

+ 0.1

x 0.3

IH

CC

V

-0.5

V

IL

CC

V

Output LOW Voltage

I

= 3mA

0.4

V

OL

NOTES:

12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

13. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

14. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is

a measure of the error in step size.

15. MI = R O /255 or (V /R —V /R )/255, single potentiometer.

T

H

L

16. Max = all four arrays cascaded together; typical = individual array resolutions.

Endurance and Data Retention

MIN

PARAMETER

Minimum Endurance

(Note 12)

100,000

100

UNIT

Data changes per bit per register

years

Data Retention

Capacitance

SYMBOL

MAX

PARAMETER

TEST CONDITIONS

(Note 12)

UNIT

pF

C

(Note 17) Input/Output Capacitance (SDA)

V

= 0V

8

6

I/O

C

(Note 17) Input Capacitance (A0, A1, A2, A3, and SCL)

V

pF

IN

Power-Up Timing

MIN

MAX

SYMBOL

PARAMETER

(Note 12)

UNIT

t

(Note 18) Power-up to Initiation of Read Operation

(Note 18) Power-up to Initiation of Write Operation

1

5

ms

PUR

t

PUW

t

V

(Note 19)

V Power-up Ramp

CC

0.2

50

V/ms

R

CC

NOTES:

17. This parameter is periodically sampled and not 100% tested.

18. t and t are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific instruction can be

PUR

PUW CC

issued. These parameters are periodically sampled and not 100% tested.

19. Sample tested only.

FN8168 Rev 6.00

December 15, 2011

Page 12 of 19

X9258

Equivalent AC Load Circuit

X9258

Power-Up and Power-Down Requirement

The are no restrictions on the sequencing of the bias supplies

5V

2.7V

V

, V+, and V- provided that all three supplies reach their final

CC

values within 1ms of each other. At all times, the voltages on the

potentiometer pins must be less than V+ and more than V-. The

recall of the wiper position from nonvolatile memory is not in effect

1533Ω

100pF

SDA OUTPUT

until all supplies reach their final value. The V

specification is always in effect.

ramp rate

CC

100pF

AC Test Conditions

Input Pulse Levels

V

x 0.1 to V

x 0.5

x 0.9

CC

Input Rise and Fall Times

Input and Output Timing Level

10ns

Test Circuit #3 SPICE Macro Model

V

CC

MACRO MODEL

R

TOTAL

R

L

H

C

L

C

H

C

W

10pF

25pF

R

W

AC Timing

Over recommended operating conditions, unless otherwise specified.

MIN

MAX

SYMBOL

PARAMETER

Clock Frequency

(Note 12) (Note 12)

UNIT

kHz

ns

f

400

SCL

t

Clock Cycle Time

2500

600

1300

600

100

30

CYC

t

Clock High Time

ns

HIGH

t

Clock Low Time

ns

LOW

t

Start Setup Time

ns

SU:STA

HD:STA

SU:STO

t

Start Hold Time

ns

t

Stop Setup Time

ns

t

SDA Data Input Setup Time

SDA Data Input Hold Time

ns

SU:DAT

HD:DAT

t

ns

t

SCL and SDA Rise Time (Note 20)

SCL and SDA Fall Time (Note 20)

SCL Low to SDA Data Output Valid Time

SDA Data Output Hold Time

Noise Suppression Time Constant at SCL and SDA Inputs

Bus Free Time (Prior to any Transmission)

WP, A0, A1, A2 and A3 Setup Time

WP, A0, A1, A2 and A3 Hold Time

300

900

50

ns

R

t

ns

F

t

ns

AA

DH

t

ns

T

50

ns

I

t

1300

0

ns

BUF

t

ns

SU:WPA

t

0

ns

HD:WPA

NOTE:

20. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.

FN8168 Rev 6.00

December 15, 2011

Page 13 of 19

X9258

High-Voltage Write Cycle Timing

MAX

SYMBOL

PARAMETER

TYP

(Note 12)

UNIT

t

High-Voltage Write Cycle Time (Store Instructions)

5

10

ms

WR

DCP Timing

MIN

MAX

SYMBOL

PARAMETER

(Note 12) (Note 12) UNIT

t

Wiper Response Time After the Third (Last) Power Supply is Stable

10

µs

WRPO

t

Wiper Response Time After Instruction Issued (All Load Instructions)

Wiper Response Time from an Active SCL/SCK Edge (Increment/Decrement Instruction)

WRL

t

WRID

Timing Diagrams 2-Wire Interface

Start and Stop Timing

(START)

(STOP)

t

F

R

SCL

t

SU:STO

SU:STA

HD:STA

t

F

R

SDA

Input Timing

t

CYC

HIGH

SCL

SDA

t

LOW

t

BUF

SU:DAT

HD:DAT

Output Timing

SCL

SDA

t

DH

AA

FN8168 Rev 6.00

December 15, 2011

Page 14 of 19

X9258

DCP Timing (for All Load Instructions)

(STOP)

SCL

SDA

VWx

LSB

t

WRL

DCP Timing (for Increment/Decrement Instruction)

SCL

WIPER REGISTER ADDRESS

INCREMENT/DECREMENT

WRID

SDA

VWx

t

Write Protect and Device Address Pins Timing

(START)

(STOP)

SCL

...

(ANY INSTRUCTION)

...

SDA

...

t

SU:WPA

t

HD:WPA

WP

A0, A1

A2, A3

FN8168 Rev 6.00

December 15, 2011

Page 15 of 19

X9258

Applications information

Basic Configurations of Electronic Potentiometers

V

+V

R

V

/R

W

I

FIGURE 9. THREE TERMINAL POTENTIOMETER; VARIABLE

VOLTAGE DIVIDER

FIGURE 10. TWO-TERMINAL VARIABLE RESISTOR;

VARIABLE CURRENT

Application Circuits

V

+

–

S

V

V (REG)

O

317

O

IN

R

1

R

2

I

ADJ

R

1

2

V

= (1+ R /R ) V

V

(REG) = 1.25V (1+ R /R )+ I

R

ADJ 2

O

2

1

S

O

2

1

FIGURE 11. NON-INVERTING AMPLIFIER

FIGURE 12. VOLTAGE REGULATOR

R

2

1

V

S

V

100k

–

+

S

V

–

+

O

V

O

TL072

10k

R

1

2

10k

V

= {R /(R +R )} V (MAX)

1 1 2 O

= {R /(R +R )} V (MIN)

UL

LL

1

2

O

+12V

-12V

FIGURE 14. COMPARATOR WITH HYSTERESIS

FIGURE 13. OFFSET VOLTAGE ADJUSTMENT

FN8168 Rev 6.00

December 15, 2011

Page 16 of 19

X9258

Application Circuits (Continued)

C

V

+

–

S

V

R

O

R

2

1

3

–

+

R

V

O

V

S

R

2

R

4

All R = 10k

S

R

1

V

= G V

S

G

= 1 + R /R

2 1

O

-1/2  G  +1/2

fc = 1/(2RC)

FIGURE 15. ATTENUATOR

FIGURE 16. FILTER

R

2

C

1

R

V

+

–

1

2

S

V

S

R

1

3

–

+

Z

IN

V

O

V

= G V

O

S

1

Z

= R + s R (R + R ) C = R + s Leq

2 2 1 3 1 2

IN

G = - R /R

2

(R + R ) >> R

2

1

3

FIGURE 18. EQUIVALENT L-R CIRCUIT

FIGURE 17. INVERTING AMPLIFIER

C

R

1

2

–

+

–

+

R

}

A

B

R

}

FREQUENCY  R , R , C

1

2

AMPLITUDE  R , R

A

B

FIGURE 19. FUNCTION GENERATOR

FN8168 Rev 6.00

December 15, 2011

Page 17 of 19

X9258

Thin Shrink Small Outline Package Family (TSSOP)

X9258

MDP0044

0.25 M C A B

N

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

D

A

(N/2)+1

MILLIMETERS

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A

A1

A2

b

1.20

0.10

0.90

0.25

0.15

5.00

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

5.00

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

6.50

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

7.80

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

9.70

6.40

4.40

0.65

0.60

1.00

Max

±0.05

PIN #1 I.D.

E

E1

±0.05

+0.05/-0.06

±0.10

0.20 C B A

2X

1

(N/2)

c

N/2 LEAD TIPS

B

D

TOP VIEW

E

Basic

E1

e

±0.10

Basic

0.05

H

e

L

±0.15

C

L1

Reference

Rev. F 2/07

SEATING

PLANE

NOTES:

0.10 M C A B

b

1. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

0.10 C

N LEADS

SIDE VIEW

2. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm per

side.

SEE DETAIL “X”

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

END VIEW

L1

A2

A

GAUGE

PLANE

0.25

L

A1

0° - 8°

DETAIL X

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8168 Rev 6.00

December 15, 2011

Page 18 of 19

X9258

Package Outline Drawing

M24.3

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)

Rev 2, 3/11

24

INDEX

AREA

7.60 (0.299)

7.40 (0.291)

10.65 (0.419)

10.00 (0.394)

DETAIL "A"

1

2

3

TOP VIEW

1.27 (0.050)

0.40 (0.016)

SEATING PLANE

2.65 (0.104)

2.35 (0.093)

15.60 (0.614)

15.20 (0.598)

0.75 (0.029)

x 45°

0.25 (0.010)

0.30 (0.012)

0.10 (0.004)

1.27 (0.050)

8°

0°

0.51 (0.020)

0.33 (0.013)

0.32 (0.012)

0.23 (0.009)

SIDE VIEW “A”

SIDE VIEW “B”

1.981 (0.078)

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1982.

2. Package length does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

3. Package width does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm

(0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm

(0.024 inch).

9.373 (0.369)

7. Controlling dimension: MILLIMETER. Converted inch dimensions in

(

) are not necessarily exact.

8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.

1.27 (0.050)

0.533 (0.021)

TYPICAL RECOMMENDED LAND PATTERN

FN8168 Rev 6.00

December 15, 2011

Page 19 of 19


型号：	X9258UV24IZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	Low Noise, Low Power, 2-Wire Bus, 256 Taps Quad Digital Controlled Potentiometer (XDCP™); SOIC24, TSSOP24; Temp Range: See Datasheet 光电二极管转换器电阻器
文件：	总19页 (文件大小：795K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9258UV24IZ [RENESAS]

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