X80142Q20I [INTERSIL]
Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors; 电压监控器/排序四路可编程延时与本地/远程电压监测器
| 型号： | X80142Q20I |
| 厂家： | 
Intersil |
| 描述： | Voltage Supervisor/Sequencer Quad Programmable Time Delay with Local/Remote Voltage Monitors |
| 文件： | 总18页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X80140, X80141, X80142, X80143, X80144
®
Data Sheet
January 20, 2005
FN8153.0
PRELIMINARY
Voltage Supervisor/Sequencer
Quad Programmable Time Delay with
Local/Remote Voltage Monitors
The X80140 is a voltage supervisor/sequencer with four built
in voltage monitors. This allows the designer to monitor up to
four voltages and sequence up to five events.
Features
• Quad Voltage Monitor and Sequencing
- Four independent voltage monitors
- Four time delay circuits (in circuit programmable)
- Remote delay via SMBus
- Factory programmable voltage thresholds
- Sequence up to 5 power supplies.
Low voltage detection circuitry protects the system from
power supply failure or “brown out” conditions, resetting the
system and resequencing the voltages when any of the
monitored inputs fall below the minimum threshold level. The
RESET pin is active until all monitored voltages reach proper
operating levels and stabilize for a selectable period of time.
Five common low voltage combinations are available,
however, Intersil’s unique circuits allow the any voltage
monitor threshold to be reprogrammed for special needs or
for applications requiring higher precision.
• Fault Detection Register
- Remote diagnostics of voltage fail event.
• Debounced Manual Reset Input
• Manufacturing/Configuration Memory
- 2Kbits of EEPROM
- 400kHz SMBus interface
• Available Packages
- 20-lead Quad No-Lead Frame (QFN - 5x5mm)
A manual reset input provides debounce circuitry for
minimum reset component count. Activating the manual
reset both controls the RESET output and resequences the
supplies through control of the ViGDO pins.
Applications
• General Purpose Timers
• Long Time Delay Generation
The X80140 has 2kb of EEPROM for system configuration,
manufacturing or maintenance information. This memory is
protected to prevent inadvertent changes to the contents.
• Cycle Timers / Waveform Generation
• ON/OFF Delay Timers
• Supply Sequencing for Distributed Power
• Programmable Delay Event Sequencing
• Multiple DC-DC ON/OFF Sequencing
• Voltage Window Monitoring with Reset
• ON/OFF Switches with Programmable Delay
• Voltage Supervisor with Programmable Output Delays
• Databus Power Sequencing
Pinout
5X5 QFN
TOP VIEW
• 100 ms to 5 secs Selectable Delay Switches
• ATE or Data Acquisition Timing Applications
• Datapath/Memory Timing Applications
• Data Pipeline Timing Applications
• Batch Timer/Sequencers
20 19 18 17 16
V4GDO
V4MON
1
15
WP
2
3
4
14
13
12
11
RESET
(5mm x 5mm)
V3GDO
V3MON
V1GDO
V1MON
V2GDO
SCL
5
• Adjustable Duty Cycle Applications
6
7
8
9 10
Ordering Information
PART
NUMBER
X80140Q20I
X80141Q20I
X80142Q20I
X80143Q20I
X80144Q20I
V
V
V
V
PACKAGE
QFN
REF1
REF2
REF3
REF4
4.5
3.0
2.25
0.9
1.7
0.9
0.9
0.9
4.5
3.0
3.0
2.25
2.25
2.25
2.25
0.9
0.9
0.9
0.9
QFN
QFN
QFN
2.25
QFN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X80140, X80141, X80142, X80143, X80144
Block Diagram
RESET
SDA
V
SS
CONTROL AND
FAULT
REGISTERS
SCL
WP
A0
POR
RESET LOGIC
AND DELAY
V
CC
MR
A1
EEPROM
2kbits
V
P
V
SS
OSC
VMON
LOGIC
DIVIDER
Reset
4
V1GDO
V2GDO
V1MON
V2MON
4
Select
0.1s
V
REF1
0.5s
1s
5s
V
REF2
delay1
V3GDO
V4GDO
V3MON
V4MON
delay2
delay3
V
REF3
REF4
delay4
V
Delay circuit
repeated 4 times
V
SS
V
SS
FN8153.0
January 20, 2005
2
X80140, X80141, X80142, X80143, X80144
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
ViMON pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
ViGDO pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
SDA, SCL, WP, A0, A1 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
MR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Temperature Range (Industrial). . . . . . . . . . . . . . . . . .-40°C to 85°C
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V
CC
V
pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14V
P
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Electrical Specifications (Standard Setting) Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
4.5
9
TYP
MAX
UNIT
DC CHARACTERISTICS
V
Supply Operating Range
5.5
2.5
12
V
mA
V
CC
I
Supply Current
f
= 0kHz
1.0
CC
SCL
V
EEPROM programming voltage
P
(Note 3)
I
Programming Current
10
10
15
mA
µA
µA
P
I
Input Leakage Current (MR)
V
= GND to V
CC
LI
IL
I
Output Leakage Current
(V1GDO, V2GDO, V3GDO, V4GDO, RESET)
LO
V
Input LOW Voltage (MR)
-0.5
V
x
V
IL
CC
0.3
V
Input HIGH Voltage (MR)
V
x 0.7
CC
5.5
0.4
V
V
IH
V
Output LOW Voltage
(RESET, V1GDO, V2GDO, V3GDO, V4GDO)
I
= 4.0mA
OL
OL
C
Output Capacitance
V
= 0V
OUT
8
pF
OUT
(Note 1) (RESET, V1GDO, V2GDO, V3GDO, V4GDO)
V
V1MON Trip Point Voltage (Range)
2.20
4.45
4.45
2.95
2.95
2.20
2.20
2.95
2.20
2.20
2.20
2.20
4.70
4.55
4.55
3.05
3.05
2.30
4.70
3.05
2.30
2.30
2.30
2.30
V
V
V
V
V
V
V
V
V
V
V
V
REF1
X80140
X80141
X80142
X80143
X80144
4.50
4.50
3.00
3.00
2.25
V
V2MON Trip Point Voltage
REF2
X80140
X80141
X80142
X80143
X80144
3.00
2.25
2.25
2.25
2.25
FN8153.0
3
January 20, 2005
X80140, X80141, X80142, X80143, X80144
Electrical Specifications (Standard Setting) Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
0.85
2.20
0.85
1.65
0.85
0.85
0.85
0.85
TYP
MAX
3.50
2.30
0.95
1.75
0.95
0.95
3.50
0.95
UNIT
V
V3MON Trip Point Voltage
V
REF3
X80140
X80141
X80142
X80143
X80144
2.25
0.90
1.70
0.90
0.90
V
V
V
V
V
V
V4MON Trip Point Voltage
V
REF4
All Devices
0.90
V
VREF
Voltage Reference Long Term Drift
10 years
0
-100
mV
AC CHARACTERISTICS
t
Minimum time high for reset valid
5
µs
µs
ms
ns
MR
(Note 3) on the MR pin
t
Delay from MR enable to V1GDO
1.6
55
MRE
(Note 3) HIGH
t
Internal Device Delay on power up
45
50
50
DPOR
(Note 3)
t
ViGDO turn off time
TO
(Note 3)
Electrical Specifications (Programmable Parameters) Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Delay before RESET assertion
SPOR
TPOR1 = 0 TPOR0 = 0 Factory Default
90
450
0.9
4.5
100
500
1
110
550
1.1
5.5
ms
ms
s
TPOR1 = 0 TPOR0 = 1 (Note 3)
TPOR1 = 1 TPOR0 = 0 (Note 3)
TPOR1 = 1 TPOR0 = 1 (Note 3)
5
s
t
Time Delay used in Power Sequencing
(i = 1 to 4)
DELAYi
TiD1 = 0 TiD0 = 0
TiD1 = 0 TiD0 = 1
TiD1 = 1 TiD0 = 0
TiD1 = 1 TiD0 = 1
Factory Default
(Note 3)
90
450
0.9
4.5
100
500
1
110
550
1.1
5.5
ms
ms
s
(Note 3)
(Note 3)
5
s
Equivalent A.C. Output Load Circuit
A.C. Test Conditions
Input pulse levels
5V
5V
5V
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
4.6kΩ
4.6kΩ
Input rise and fall times
Input and output timing levels
Output load
10ns
4.6kΩ
V1GDO,
V2GDO,
V3GDO,
V4GDO
V
RESET
CC
SDA
Standard output load
30pF
30pF
30pF
FN8153.0
4
January 20, 2005
X80140, X80141, X80142, X80143, X80144
Initial
Power-up
V
CC
V
REFi
t
DPOR
ViMON
t
DELAYi
t
t
TO
DELAYi
ViGDO
i = 1, 2, 3, 4
FIGURE 1. INITIAL POWER UP AND DELAY TIMING
Symbol Table
WAVEFORM INPUTS
OUTPUTS
MR
t
MR
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
ViGDO
t
DELAYi
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
RESET
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
t
t
DELAYi
MRE
+ t
SPOR
FIGURE 2. MANUAL RESET (MR)
MR
ViMON
(i= 1 to 4)
t
DELAY1
t
DELAY1
V1GDO
t
DELAY2
t
DELAY2
V2GDO
V3GDO
t
DELAY3
t
DELAY3
t
DELAY4
t
DELAY4
V4GDO
RESET
t
t
SPOR
SPOR
Any ViGDO
(1st occurance)
FIGURE 3. ViGDO, RESET TIMINGS
FN8153.0
January 20, 2005
5
X80140, X80141, X80142, X80143, X80144
Serial Interface Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS
I
Active Supply Current (V ) Read or Write
CC
V
V
SCL
= V x 0.1
CC
2.5
mA
CC1
IL
IH
to Memory or registers
= V
x 0.9,
CC
f
= 400kHz
I
Input Leakage Current (SCL, WP, A0, A1)
Output Leakage Current (SDA)
V
= GND to V
CC
15
15
µA
µA
LI
IL
I
V
= GND to V
CC
LO
SDA
Device is in Standby
V
Input LOW Voltage (SDA, SCL, WP, A0, A1)
Input HIGH Voltage (SDA, SCL, WP, A0, A1)
Schmidt Trigger Input Hysteresis
Fixed input level
-0.5
V
x 0.3
V
V
IL
CC
V
V
x 0.7
5.5
IH
CC
V
HYS
0.2
V
V
V
V
related level
0.05 x 5
CC
V
Output LOW Voltage (SDA)
AC CHARACTERISTICS
SCL Clock Frequency
Pulse width Suppression Time at inputs
I
= 4.0mA
OL
0.4
400
1.5
OL
f
kHz
ns
SCL
t
50
0.1
1.3
IN
t
(Note 1) SCL LOW to SDA Data Out Valid
µs
AA
t
(Note 1) Time the bus is free before start of new
transmission
µs
BUF
t
Clock LOW Time
1.3
0.6
µs
µs
µs
µs
ns
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
µs
pF
ms
LOW
HIGH
t
Clock HIGH Time
t
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
HD:STO
t
t
0.6
100
0
t
Data In Hold Time
t
Stop Condition Setup Time
Stop Condition Hold Time
0.6
t
0.6
t
(Note 1) Data Output Hold Time
(Note 1) SDA and SCL Rise Time
(Note 1) SDA and SCL Fall Time
50
DH
t
20 +.1Cb
20 +.1Cb
0.6
300
300
R
t
F
t
WP Setup Time
WP Hold Time
SU:WP
t
0
HD:WP
t
A0, A1 Setup Time
A0, A1 Hold Time
0.6
SU:ADR
t
0
HD:ADR
t
V
Setup Time
P
0.6
SU:VP
Cb (Note 3) Capacitive load for each bus line
(Note 2) EEPROM Write Cycle Time
400
10
t
5
WC
NOTES:
1. This parameter is based on characterization data.
2. t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
WC
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
3. This parameter is not 100% tested.
FN8153.0
6
January 20, 2005
X80140, X80141, X80142, X80143, X80144
Timing Diagrams
t
t
t
BUF
t
t
R
F
HIGH
LOW
t
BUF
SCL
t
t
t
t
t
HD:STO
SU:DAT
SU:STA
HD:DAT
SU:STO
t
HD:STA
SDA IN
t
t
DH
t
HD:DAT
AA
SDA OUT
FIGURE 4. BUS TIMING
STOP
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
t
t
HD:WP
SU:WP
WP
t
t
HD:ADR
SU:ADR
A1, A0
t
WC
t
SU:VP
V
P
FIGURE 5. WP, A0, A1, VP PIN TIMING
SCL
SDA
th
ACK
8
Bit of Last Byte
t
WC
Start
Condition
Stop
Condition
FIGURE 6. WRITE CYCLE TIMING
FN8153.0
January 20, 2005
7
X80140, X80141, X80142, X80143, X80144
Pin Configuration
X80140/1/2/3/4
20 19 18 17 16
(5mm x 5mm)
V4GDO
V4MON
1
15
WP
2
3
4
RESET
14
13
12
11
V3GDO
V3MON
V1GDO
V1MON
V2GDO
SCL
5
6
7
8
9 10
Pin Descriptions
PIN
NAME
DESCRIPTION
V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than V
1
V4GDO
REF4
REF3
REF2
and goes LOW when V4MON is greater than V
. There is user selectable delay circuitry on this pin.
REF4
2
3
V4MON
V3GDO
V4 Voltage Monitor Input. Fourth voltage monitor pin. If unused connect to V
.
CC
V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than V
and goes LOW when V3MON is greater than V . There is user selectable delay circuitry on this pin.
REF3
V3 Voltage Monitor Input. Third voltage monitor pin. If unused connect to V
4
5
V3MON
V2GDO
.
CC
V2 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V2MON is less than V
and goes LOW when V2MON is greater than V
. There is user selectable delay circuitry on this pin.
REF2
6
7
V
P
EEPROM programming Voltage.
V2MON
DNC
A1
V2 Voltage Monitor Input. Second voltage monitor pin. If unused connect to V
Do Not Connect.
.
CC
8
9
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical)
The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface.
10
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input
buffer is always active (not gated).
11
12
13
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
V1MON
V1GDO
V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to V
.
CC
V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than V
REF1
and goes LOW when V1MON is greater than V
. There is user selectable delay circuitry on this pin.
REF1
14
15
16
RESET
WP
RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive
and the power sequencing is complete. This pin will be released after a programmable delay.
Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the
device. It has an internal pull-down resistor. (>10MΩ typical)
MR
Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5µsecs. It has an
internal pull-down resistor. (>10MΩ typical)
17
18
V
Ground Input.
SS
NC
A0
No Connect. No internal connections.
19
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical)
The A0 and A1 bits allow for up to 4 X80140 devices to be used on the same SMBus serial interface.
20
V
Supply Voltage.
CC
FN8153.0
8
January 20, 2005
X80140, X80141, X80142, X80143, X80144
Each ViGDO signal remains active until its associated
Functional Description
Power On Reset and System Reset With Delay
Application of power to the X80140 activates a Power On
Reset circuit that pulls the RESET pin active. This signal, if
used, prevents the system microprocessor from starting to
operate while there is insufficient voltage on any of the
supplies. This circuit also does the following:
ViMON input rises above the threshold.
TABLE 2. VIGDO OUTPUT TIME DELAY OPTIONS
TiD1
TiD0
t
DELAYi
0
0
1
1
0
1
0
1
100ms (default)
500ms
1 secs
• It prevents the processor from operating prior to
stabilization of the oscillator.
5 secs
where i is the specific voltage monitor (i = 1 to 4).
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
Fault Detection
The X80140 contains a Fault Detection Register (FDR) that
provides the user the status of the causes for a RESET pin
active (See Table 20).
• It prevents communication to the EEPROM during
unstable power conditions, greatly reducing the likelihood
of data corruption on power up.
• It allows time for all supplies to turn on and stabilize prior
to system initialization.
At power-up, the FDR is defaulted to all “0”. The system
needs to initialize the register to 0Fh before the actual
monitoring can take place. In the event that any one of the
monitored sources fail, the corresponding bit in the register
changes from a “1” to a “0” to indicate the failure. When a
RESET is detected by the main controller, the controller
should read the FDR and note the cause of the fault. After
reading the register, the controller can reset the register bit
back to all “1” in preparation for future failure conditions.
The POR/RESET circuit is activated when all voltages are
within specified ranges and the V1GDO, V2GDO, V3GDO,
and V4GDO time-out conditions are met. The POR/RESET
circuit will then wait t
and de-assert the RESET pin.
SPOR
The POR delay may be changed by setting the TPOR bits in
register CR2. The delay can be set to 100ms, 500ms, 1
second, or 5 seconds.
TABLE 1. POR RESET DELAY OPTIONS
Flexible Power Sequencing of Multiple Power
Supplies
t
DELAY BEFORE RESET
ASSERTION
SPOR
TPOR1 TPOR0
The X80140 provides several circuits such as multiple
voltage monitors, programmable delays, and output drive
signals that can be used to set up flexible power monitoring
or sequencing schemes system power supplies. Below are
two examples:
0
0
1
1
0
1
0
1
100 milliseconds (default)
500 milliseconds
1 second
5 seconds
1. Power Up of Supplies In Parallel Using Programmable
Delays. (See Figure 7 and Figure 8).
Manual Reset
2. The X80140 monitors several power supplies, powered
by the same source voltage, that all begin power up at the
same time. Each voltage source is fed into the ViMON
inputs to the X80140. The ViMON inputs monitor the
voltage to make sure it has reached the minimum desired
level. When each voltage monitor determines that its
input is good, a counter starts. After the programmed
delay time, the X80140 sets the ViGDO signals LOW. Any
individual voltage failure can be viewed in the Fault
Detection Register.
The manual reset option allows a hardware reset of the
power sequencing pins. These can be used to recover the
system in the event of an abnormal operating condition.
Activating the MR pin for more than 5us sets all of the
ViGDO outputs and the RESET output active (LOW). When
MR is released (and if all supplies are still at their proper
operating voltage) then the ViGDO and RESET pins will be
released after their programmed delay periods. (See Figure
3.)
3. In the factory default condition, each ViGDO output is
instructed to go LOW 100ms after the input voltage
reaches its threshold. However, each ViGDO delay is
individually selectable as 100ms, 500ms, 1s and 5s. The
delay times are changed via the SMBus during calibration
of the system.
Quad Voltage Monitoring
X80140 monitors 4 voltage inputs. When the ViMON (i=1-4)
input is detected to be above the input threshold, the output
ViGDO (i = 1 to 4) goes inactive (LOW). The ViGDO signal is
de-asserted after a delay of 100ms. This delay can be
changed on each ViGDO output individually with bits in
register CR3. The delay can be 100ms, 500ms, 1s and 5s.
FN8153.0
9
January 20, 2005
X80140, X80141, X80142, X80143, X80144
Power
Supplies
Can Choose Different
Delays for each
Voltage Monitor
5V
V1MON
Programmable
3.3V
2.5V
1.2V
t
On/Off
On/Off
On/Off
DELAY1
100ms
500ms
1 sec
Delay
V1GDO
5 secs
V4MON
X80140/41/42/43/44
Programmable
Delay
t
DELAY4
V4GDO
V4MON
µC
V
CC1
V4GDO
IRQ RESET
V3GDO
V3MON
V
Programmable
Delay
CC2
t
SPOR
FPGA
V2GDO
V2MON
RESET
V
V
CC1
CC2
Timing
not to scale
V1GDO
V1MON
FIGURE 8. PARALLEL POWER CONTROL - TIMING
ASIC
CC1
RESET
MR
V
V
CC2
FIGURE 7. EXAMPLE APPLICATION OF PARALLEL POWER
CONTROL
4. Power Up of Supplies Via Relay Sequencing Using
Voltage Monitors (see Figure 10 and Figure 9).
5. Several power supplies and their respective power up
start times can be controlled using the X80140 such that
each of the power supplies will start in a relay sequencing
fashion. In the following example, the 1st supply is
allowed to power up when the input regulated supply
reaches an acceptable threshold. Subsequent supplies
power up after the prior supply has reached its operating
voltage. This configuration ensures that each subsequent
power supply turns on after the preceding supplies
voltage output is valid. Again, the X80140 offers
programmable delays for each voltage monitor and this
delay is selectable via the SMBus during calibration of the
system.
FN8153.0
January 20, 2005
10
X80140, X80141, X80142, X80143, X80144
Power
Supply
5V
On/Off
12V
µC
V
V
CC1
RESET
1.2V
Power
CC2
Supply
On/Off
FPGA
ASIC
V
V
Power
Supply
3.3V
On/Off
CC1
CC2
Power
Supply
2.5V
On/Off
X80140/41/42/43
V
CC1
V4GDO
V4MON
V
CC2
V3GDO
V3MON
V
CC
V2GDO
V2MON
V1MON V1GDO
RESET
MR
5V
FIGURE 9. EXAMPLE OF RELAY POWER SUPPLY SEQUENCING
Timing Not
To Scale
100ms
500ms
1sec
V1MON
V1MON
(12V)
threshold
5sec
Example: Five Independent
Power Supplies in relay timing
Programmable
Delay
t
DELAY1
Power Supply
#2 ON
V1GDO
Power Supply
#2 OUTPUT
V2MON
100ms
500ms
1sec
threshold
(5V)
5sec
Programmable
Delay
t
DELAY2
Power Supply
#3 ON
V2GDO
Power Supply
#3 OUTPUT
V3MON
100ms
500ms
1sec
threshold
(1.2V)
5sec
Programmable
Delay
t
DELAY3
Power Supply
#4 ON
V3GDO
Power Supply
#4 OUTPUT
V4MON
threshold
100ms
500ms
1sec
(3.3V)
5sec
Programmable
Delay
t
DELAY4
V4GDO
Power Supply
#5 OUTPUT
(2.5V)
t
SPOR
RESET
FIGURE 10. RELAY SEQUENCING OF DC-DC SUPPLIES (TIMING)
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January 20, 2005
X80140, X80141, X80142, X80143, X80144
WEL: Write Enable Latch
Control Registers and Memory
A write enable latch (WEL) bit controls write accesses to the
nonvolatile registers and the EEPROM memory array in the
X80140. This bit is a volatile latch that powers up in the LOW
(disabled) state. While the WEL bit is LOW, writes to any
address (registers or memory) will be ignored. The WEL bit
is set by writing a “1” to the WEL bit and zeroes to the other
bits of the control register 0 (CR0). It is important to write
only 00h or 80h to the CR0 register.
The user addressable internal control, status and memory
components of the X80140 can be split up into three parts:
• Control Register (CR)
• Fault Detection Register (FDR)
• EEPROM array
Registers
The Control Registers and Fault Detection Register are
summarized in Table 4. Changing bits in these registers
change the operation of the device or clear fault conditions.
Reading bits from these registers provides information about
device configuration or fault conditions. Reads and writes
are done through the SMBus serial port.
Once set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits of the
control register) or until the part powers up again.
Note, a write to FDR does not require that WEL=1.
BP1 and BP0: Block Protect Bits
All of the Control Register bits are nonvolatile (except for the
WEL bit), so they do not change when power is removed.
The Block Protect Bits, BP1 and BP0, determines which
blocks of the memory array are write protected. A write to a
protected block of memory is ignored. The block protect bits
will prevent write operations to one of four segments of the
array.
The values of the Register Block can be read at any time by
performing a random read (see Serial Interface) at the
specific byte address location. Only one byte is read by each
register read operation.
PROTECTED ADDRESSES
(SIZE)
ARRAY LOCK
None (Default)
Upper 1/4
Upper 1/2
All
Bits in the registers can be modified by performing a single
byte write operation directly to the address of the register
and only one data byte can change for each register write
operation.
0
0
1
1
0
1
0
1
None (Default)
C0h - FFh (64 bytes)
80h - FFh (128 bytes)
00h - FFh (256 bytes)
EEPROM Array
The X80140 contains a 2kbit EEPROM memory array. This
array can contain information about manufacturing location
and dates, board configuration, fault conditions, service
history, etc. Access to this memory is through the SMBus
serial port. Read and write operations are similar to those of
the control registers, but a single command can write up to
16 bytes at one time. A single read command can return the
entire contents of the EEPROM memory.
WPEN: Write Protect Enable
The Write Protect pin and Write Protect Enable bit in the
CR1 register control the Programmable Hardware Write
Protect feature. Hardware Protection is enabled when the
WP pin is HIGH and WPEN bit is HIGH and disabled when
WP pin is LOW or the WPEN bit is LOW. When the chip is
Hardware Write Protected, non-volatile writes to all control
registers (CR1, CR2, and CR) are disabled including BP bits,
the WPEN bit itself, and the blocked sections in the memory
Array. Only the section of the memory array that is not block
protected can be written.
Register and Memory Protection
In order to reduce the possibility of inadvertent changes to
either a control register of the contents of memory, several
protection mechanisms are built into the X80140. These are
a Write Enable Latch, Block Protect bits, a Write Protect
Enable bit and a Write Protect pin.
Non Volatile Programming Voltage (V )
P
Nonvolatile writes require that a programming voltage be
applied to the VP for the duration of a nonvolatile write
operation.
TABLE 3. WRITE PROTECT CONDITIONS
MEMORY ARRAY
NOT BLOCK
MEMORY ARRAY
WRITES TO
WEL
LOW
HIGH
HIGH
HIGH
WP
X
WPEN
X
PROTECTED
BLOCK PROTECTED
Writes Blocked
CR1, CR2, CR3
PROTECTION
Hardware
Software
Writes Blocked
Writes Enabled
Writes Enabled
Writes Enabled
Writes Blocked
Writes Enabled
Writes Enabled
Writes Blocked
LOW
X
X
Writes Blocked
Writes Blocked
Writes Blocked
LOW
HIGH
Software
HIGH
Hardware
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January 20, 2005
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X80140, X80141, X80142, X80143, X80144
TABLE 4. REGISTER ADDRESS MAP
BIT
BYTE
MEMORY
TYPE
ADDR. NAME
CONTROL/STATUS
7
6
0
0
5
0
0
4
0
3
0
2
0
0
1
0
0
0
0
0
00H
01H
CR0
CR1
Write Enable
WEL
WPEN
Volatile
EEPROM Block
Control
BP1
BP0
EEPROM
02H
03H
FF
CR2
CR3
FDR
POR Timing
0
T4D1
0
0
T4D0
0
0
T3D1
0
0
T3D0
0
TPOR1
T2D1
TPOR0
T2D0
0
0
EEPROM
EEPROM
Volatile
ViGDO Time Delay
T1D1
V20S
T1D0
V10S
Fault Detection
Register
V40S
V30S
TABLE 5. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY
CONTROL
/STATUS
LOCATION(S)
REGISTER BITS
OPERATION
DESCRIPTION (SEE FUNCTIONAL FOR DETAILS)
SOFTWARE CONTROL BITS
EEPROM Write Enable
WEL
CR0
7
WEL = 1 enables write operations to the control registers and
EEPROM.
WEL = 0 prevents write operations.
EEPROM Write Protect
EEPROM Block Protect
WPEN
CR1
CR1
7
WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and
the EEPROM.
BP1
BP0
4:3
BP1=0, BP0=0 : No EEPROM memory protected.
BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected
BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected.
BP1=1, BP0=1 : All of EEPROM memory protected.
RESET Time Delay
TPOR1
TPOR0
CR2
3:2
TPOR1=0, TPOR0=0 : RESET delay = 100ms
TPOR1=0, TPOR0=1 : RESET delay = 500ms
TPOR1=1, TPOR0=0 : RESET delay = 1s
TPOR1=1, TPOR0=1 : RESET delay = 5s
V1GDO Time Delay
V2GDO Time Delay
V3GDO Time Delay
V4GDO Time Delay
T1D1
T1D0
CR3
CR3
CR3
CR3
1:0
3:2
5:4
7:6
TiD1=0, TiD0=0 : ViGDO delay = 100ms
TiD1=0, TiD0=1 : ViGDO delay = 500ms
TiD1=1, TiD0=0 : ViGDO delay = 1s
TiD1=1, TiD0=1 : ViGDO delay = 5s
T2D1
T2D0
T3D1
T3D0
T4D1
T4D0
STATUS BITS
1st Voltage Monitor
2nd Voltage Monitor
3rd Voltage Monitor
4th Voltage Monitor
V1OS
V2OS
V3OS
V4OS
FDR
FDR
FDR
FDR
0
1
2
3
V1OS = 0 : V1GDO pin has been asserted (must be preset to 1).
V2OS = 0 : V2GDO pin has been asserted (must be preset to 1).
V3OS = 0 : V3GDO pin has been asserted (must be preset to 1).
V4OS = 0 : V4GDO pin has been asserted (must be preset to 1).
FN8153.0
January 20, 2005
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X80140, X80141, X80142, X80143, X80144
The device does not acknowledge any instructions following
Bus Interface Information
Interface Conventions
a non-volatile write operation, unless the V pin has the
P
recommended programming voltage applied for the duration
of the write cycle.
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the devices in this family operate as slaves in all
applications.
In the read mode, the device transmits eight bits of data,
releases the SDA line, then monitors the line for an
acknowledge. If an acknowledge is detected and no STOP
condition is generated by the master, the device continues
transmitting data. The device terminates further data trans-
missions if an acknowledge is not detected. The master
must then issue a STOP condition to return the device to
Standby mode and place the device into a known state.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a STOP condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a STOP condition.
SCL
SDA
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions. See Figure 11.
Start
Stop
FIGURE 11. VALID START AND STOP CONDITIONS
Serial START Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met. On power up, the SCL pin
must be brought LOW prior to the START condition.
SCL from
Master
1
8
9
Data Output from
Transmitter
Data Output from
Receiver
Serial STOP Condition
Start
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH followed by a HIGH to LOW on SCL. After
going LOW, SCL can stay LOW or return to HIGH. The
STOP condition also places the device into the Standby
power mode after a read sequence.
Acknowledge
FIGURE 12. ACKNOWLEDGE RESPONSE FROM RECEIVER
Device Addressing
Addressing Protocol Overview
Serial Acknowledge
Depending upon the operation to be performed on each of
these individual parts, a 1, 2 or 3 Byte protocol is used. All
operations however must begin with the Slave Address Byte
being clocked into the SMBus port on the SCL and SDA
pins. The Slave address selects the part of the device to be
addressed, and specifies if a Read or Write operation is to
be performed.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, releases the bus after transmitting eight
bits. During the ninth clock cycle, the receiver pulls the SDA
line LOW to acknowledge that it received the eight bits of
data. See Figure 12.
The device responds with an acknowledge after recognition
of a START condition and if the correct Device Identifier and
Select bits are contained in the Slave Address Byte. If a write
operation is selected, the device responds with an
acknowledge after the receipt of each subsequent eight bit
word. The device acknowledges all incoming data and
address bytes, except for the Slave Address Byte when the
Device Identifier and/or Select bits are incorrect.
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte. This byte consists of three parts:
• The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
FN8153.0
14
January 20, 2005
X80140, X80141, X80142, X80143, X80144
The Device Type Identifier MUST be set to 1010 in order
to select the device.
BYTE WRITE
For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master
access to any one of the words in the array. After receipt of
the Word Address Byte, the device responds with an
acknowledge, and awaits the next eight bits of data. After
receiving the 8 bits of the Data Byte, the device again
responds with an acknowledge. The master then terminates
the transfer by generating a STOP condition, at which time
the device begins the internal write cycle to the nonvolatile
memory. During this internal write cycle, the device inputs
are disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance.
• The next two bits (SA3 - SA2) are slave address bits. The
bits received via the SMBus are compared to A0 and A1
pins and must match or the communication is aborted.
• The next bit, SA1, selects the device memory sector.
There are two addressable sectors: the memory array and
the control, fault detection and remote shutdown registers.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed. When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation
(Refer to Figure 13).
A write to a protected block of memory will suppress the
acknowledge bit.
EXTERNAL
DEVICE
ADDRESS
DEVICE TYPE
IDENTIFIER
Memory
Select
READ /
WRITE
PAGE WRITE
The device is capable of a page write operation. See Figure
14. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit an
unlimited number of 8-bit bytes. After the receipt of each
byte, the device will respond with an acknowledge, and the
address is internally incremented by one. The page address
remains constant. When the counter reaches the end of the
page, it “rolls over” and goes back to ‘0’ on the same page.
See Figure 15.
SA7
SA6
0
SA3 SA2
SA5
1
SA4
0
SA1
SA0
1
A1
A0
MS R/W
INTERNAL
INTERNALLY ADDRESSED
DEVICE
ADDRESS (SA1)
0
1
EEPROM Array
Control Register,
Fault Detection Register
This means that the master can write 16 bytes to the page
starting at any location on that page. If the master begins
writing at location 10, and loads 12 bytes, then the first 6
bytes are written to locations 10 through 15, and the last 6
bytes are written to locations 0 through 5. Afterwards, the
address counter would point to location 6 of the page that
was just written. If the master supplies more than 16 bytes of
data, then new data overwrites the previous data, one byte
at a time.
BIT SA0
OPERATION
WRITE
0
1
READ
FIGURE 13. SLAVE ADDRESS FORMAT
The master terminates the Data Byte loading by issuing a
STOP condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle.
Serial Write Operations
Before any write operations can be performed, a
programming supply voltage (V ) must be supplied. This
P
voltage is only needed for programming, but the nonvolatile
registers and EEPROM locations cannot be programmed
without it.
STOP AND WRITE MODES
STOP conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte plus
the subsequent ACK signal. If a STOP is issued in the
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array will
not be effected.
In order to successfully complete a write operation to either a
Control Register or the EEPROM array, the Write Enable
Latch (WEL) bit must first be set and either the WP pin or the
WPEN bit must be LOW.
Writes to the WEL bit do not cause a high voltage write
cycle, so the device is ready for the next operation
immediately after the STOP condition.
ACKNOWLEDGE POLLING
The disabling of the inputs during high voltage cycles can be
used to take advantage of the typical 5ms write cycle time.
Once the STOP condition is issued to indicate the end of the
FN8153.0
15
January 20, 2005
X80140, X80141, X80142, X80143, X80144
master’s byte load operation, the device initiates the internal
cycle then no ACK will be returned. If the device has
completed the write operation, an ACK will be returned and
the host can then proceed with the read or write operation.
See Figure 18.
high voltage cycle. Acknowledge polling can be initiated
immediately. To do this, the master issues a START
condition followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the high voltage
(1 to n to 16)
S
S
t
o
p
t
Signals from
Byte
Address
Slave
Data
(1)
Data
(n)
a
the Master
Address
r
t
SDA Bus
0
1 0 1 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
FIGURE 14. PAGE WRITE OPERATION
7 Bytes
5 Bytes
address pointer
address
address
= 6
address
n-1
ends here
10
Addr = 7
FIGURE 15. WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 10
S
S
S
t
o
p
t
Byte
Address
t
Slave
Address
Slave
Address
Signals from
the Master
a
r
t
a
r
t
1 0 1
0
SDA Bus
1
1 0 1 0
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
FIGURE 16. RANDOM ADDRESS READ SEQUENCE
S
t
S
Slave Address
t
Signals from
the Master
a
r
o
p
t
SDA Bus
1
1
0 1 0
A
C
K
Signals from
the Slave
Data
FIGURE 17. CURRENT ADDRESS READ SEQUENCE
FN8153.0
16
January 20, 2005
X80140, X80141, X80142, X80143, X80144
CURRENT ADDRESS READ
Internally the device contains an address counter that
Byte Load Completed by
Issuing STOP.
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
Enter ACK Polling
Issue START
Upon receipt of the Slave Address Byte with the R/W bit set
to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond with
an acknowledge during the ninth clock and then issues a
STOP condition. See Figure 17 or the address,
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
Returned?
acknowledge, and data transfer sequence.
YES
Operational Notes
The device powers-up in the following state:
High Voltage Cycle
Complete. Continue
Command Sequence?
• The device is in the low power standby state.
Issue STOP
• The WEL bit is set to ‘0’. In this state it is not possible to
write to the device.
NO
YES
• SDA pin is the input mode.
Continue Normal Read
or Write Command
Sequence
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The WEL bit must be set to allow write operations.
PROCEED
• The proper clock count and bit sequence is required prior
to the STOP bit in order to start a nonvolatile write cycle.
FIGURE 18. ACKNOWLEDGE POLLING SEQUENCE
• The WP pin, when held HIGH, prevents all writes to the
array and all the Register.
Serial Read Operations
• A programming voltage must be applied to the V pin prior
P
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current Address Reads, Random Reads, and
Sequential Reads.
to any programming sequence.
RANDOM READ
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the START condition and the Slave Address Byte, receives
an acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another START condition and the
Slave Address Byte with the R/W bit set to one. This is
followed by an acknowledge from the device and then by the
eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
STOP condition. See Figure 16 for the address,
acknowledge, and data transfer sequence.
FN8153.0
17
January 20, 2005
X80140, X80141, X80142, X80143, X80144
Packaging Information
20-Lead Quad Flat No Lead Package (Package Code: Q20)
5mm x 5mm Body with 0.65mm Lead Pitch
A3
A1
Pin 1 Indent
b
E
E2
e
D2
L
D
A
NOTES:
DIMENSIONS IN MILLIMETERS
1. The package outline drawing is compatible with
SYMBOLS
MIN
0.70
0.00
0.25
0.19
4.90
3.70
4.90
3.70
—
NOM
0.75
0.02
0.30
0.20
5.00
3.80
5.00
3.80
0.65
0.40
—
MAX
0.80
0.05
0.35
0.25
5.10
3.90
5.10
3.90
—
JEDEC MO-220; variations: WHHC-2, except
dimensions D2 and E2.
A
A1
b
2. The terminal #1 identifier is a laser marked feature
A3
D
D2
E
E2
e
L
0.35
0.45
0.08
y
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8153.0
18
January 20, 2005
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