X80203 [INTERSIL]
Power Supply Swquencer with Power-up System Mnitoring; 电源Swquencer与电系统Mnitoring
| 型号： | X80203 |
| 厂家： | 
Intersil |
| 描述： | Power Supply Swquencer with Power-up System Mnitoring |
| 文件： | 总16页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X80200, X80201, X80202, X80203, X80204
®
Data Sheet
January 21, 2005
FN8154.0
Power Supply Sequencer with Power-up
System Monitoring
The X80200 power sequencer provides a flexible approach
for handling difficult system power-up conditions. The
X80200 includes control of up to three voltage supplies and
can be cascaded to control additional supplies. The device
contains independent undervoltage lockout for each
controlled voltage.
Features
• Sequence three voltage supplies independently
- Core and Logic I/O VCC power sequencer for processor
supplies
- Power up and power down control
- Voltage monitors have undervoltage lockout
- Internal charge pump drives external N-channel FET
switches
- Cascadable to sequence more than 3 supplies
- Time based or voltage based sequencing
The three voltage control circuits allow sequencing for
primary, core, and I/O voltages. The core and I/O supplies
are linked together with a comparator or a timer allowing a
tight coupling between these two supplies. The sequencing
may be either voltage based or time based.
• Status register bits monitor gate output status
• SMBus compatible Interface
• Slave address identification for up to 8 power sequencers
(24 supplies) on the same bus
The X80200 contains separate charge pumps to control
external N-channel power FETs for each of the supplies. The
charge pumps provide the high gate control voltage
necessary for efficient operation of the FET switches.
• Surface mount 20-pin TSSOP Package
Applications
• Distributed Power Supply Designs
The X80200 turns on the primary voltage to the system
when the voltage source is steady. This primary FET switch
turn-on can be delayed with an external RC circuit. For the
secondary voltage sources, the device has a built-in “core-
up-first and core-down-last” sequencing logic which is ideal
for high performance processors, DSPs and ASICs.
• Multi-voltage systems
• Multiprocessor systems
• Embedded Processor Applications
• Digital Signal Processors, FPGAs, ASICs, Memory
Controllers
The serial bus can be used to monitor the status or turn off
each of the external power switches. The X80200 has 3
slave address bits that allow up to 8 devices to be connected
to the same bus.
• N + 1 Redundant Power Supplies
• Support for SSI – Server System Infrastructure
Specifications
Pinout
• -48V Hotswap Power Backplane/Distribution
• Card Insertion Detection and Power
• Power Sequencing DC-DC Supplies
• Databus Power Interfacing
20 LD TSSOP
TOP VIEW
SETV
REF
A0
1
2
3
4
5
6
20
19
18
17
VDDL
VDDM
VDDH
• Custom Industrial Power Backplanes
GND
A1
VFB
16
DNC
• Other: ATE, Data Acquisition, Mass Storage, Servers,
Data com, Wireless Basestations
A2
GATE_M
GATE_H
GATE_L
ENS
15
14
13
12
NC
7
8
Ordering Information
SDA
SCL
9
PART NUMBER UVLO
UVLO
UVLO
0.9
PACKAGE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
H
M
L
10
READY
11
GATEH_EN
X80200V20I
X80201V20I
X80202V20I
X80203V20I
X80204V20I
4.5
4.5
3.0
3.0
3.0
3.0
2.25
2.25
2.25
0.9
0.9
1.7
0.9
0.9
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X80200, X80201, X80202, X80203, X80204
Functional Diagram
VDDH
18
VFB
17
DNC
16
GATE_M
15
GATE_H
14
CHARGE
PUMP_M
13
12
GATE_L
ENS
UVLO
H
OSC
CHARGE
PUMP_H
19
VDDM
UVLO
M
CHARGE
PUMP_L
VDDL 20
UVLO
L
SETV
REF
1
2
+
–
CORE-UP-FIRST
11
10
GATEH_EN
READY
CORE-DOWN-LAST
2-WIRE
STATUS REGISTER
REMOTE SHUTDOWN REGISTER
A0
3
INTERFACE
9
SCL
4
GND
5
6
7
8
A1
A2
NC
SDA
Pin Descriptions
PIN
NAME
DESCRIPTION
1
SETV
Set Voltage. This pin is used for voltage based power sequencing of supplies VDDM and VDDL.
If unused connect to ground.
2
REF
Reference voltage. This pin is used for voltage based sequencing. The voltage on this pin is compared to the voltage on the
VFB pin and provides the threshold for turn on of the GATE_M output. Either a voltage source or external resistor divider can
be used to provide the reference. If time based sequencing is used this pin should be tied to VDDH.
3
4
A0
GND
A1
Slave address pin assignment. It has an Internal pull down resistor. (>10MΩ typical)
Voltage Ground.
5
Slave address pin assignment. It has an Internal pull down resistor. (>10MΩ typical)
Slave Address pin assignment. It has an Internal pull down resistor. (>10MΩ typical)
No internal connections.
6
A2
7
NC
8
SDA
SCL
READY
Serial bus data input/output pin.
9
Serial bus clock input pin.
10
READY Output Pin: This open-drain output pin goes LOW while VDDH is below UVLO and remains LOW for t after
PURST
H
VDDH goes above UVLO . READY goes HIGH after t
.
H
PURST
11 GATEH_EN GATE_H Enable. When this pin is HIGH and VDDH > UVLO the charge pump of the GATE_H pin turns on and the output
H
drives HIGH. When this pin is LOW, the charge pump is disabled and the GATE_H output is LOW. An external RC time delay
can be connected between the enable signal and this pin to delay the GATE_H turn on.
12
13
ENS
Enable Sequence. This pin is used for time-based power sequencing of supplies VDDM and VDDL. If unused, connect to ground.
GATE_L
GATE_L Output: This output is connected to the gate of an (external) Power Switch “L”. The GATE_L pin is driven HIGH when
charge pump L is enabled and pulled LOW when the charge pump is disabled.
14
15
GATE_H GATE_H Output: This output is connected to the gate of a (external) Power Switch “H”. The GATE_H pin driven HIGH when
charge pump H is enabled and pulled LOW when the charge pump is disabled.
GATE_M GATE_M Output: This output is connected to the gate of a (external) Power Switch “M”. The GATE_M pin driven HIGH when
charge pump M is enabled and pulled LOW when the charge pump is disabled.
16
17
DNC
VFB
Do not connect (must be left floating).
Voltage Feedback Pin. This input pin is used with voltage based power sequencing to monitor the level of a previously turned-
on supply. If unused, connect to ground.
18
19
20
VDDH
VDDM
VDDL
Primary supply voltage (typically 5V).
Monitored Supply Voltage “M” input.
Monitored Supply Voltage “L” input.
FN8154.0
2
X80200, X80201, X80202, X80203, X80204
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on given pin (Power Sequencing Functions):
All V
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Power Sequencing Control Circuits Over the recommended operating conditions unless otherwise specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS – Undervoltage Lockout Comparators
V
Supply Operating Range
Supply Operating Range
Supply Operating Range
Supply Current
3.05
0.95
0.95
5.5
5.5
5.5
V
V
DDH
V
DDM
V
V
DDL
DDH
DDH
I
I
V
V
= 5.5V
= 3.1V
2.5
mA
µA
DDH
DDH
Supply Current
200
UVLO
Undervoltage lockout for VDDH
H
X80200
X80201
X80202
X80203
X80204
4.425
4.425
2.95
4.5
4.5
3.0
3.0
3.0
4.575
4.575
3.05
V
V
V
V
V
2.95
3.05
2.95
3.05
UVLO
Undervoltage lockout for VDDM
Undervoltage lockout for VDDL
M
X80200
X80201
X80202
X80203
X80204
2.2
2.2
3.0
2.25
2.25
2.25
0.9
3.05
2.3
V
V
V
V
V
2.2
2.3
2.2
2.3
0.875
0.925
UVLO
L
X80200
X80201
X80202
X80203
X80204
0.875
0.875
1.65
0.9
0.9
1.7
0.9
0.9
30
0.925
0.925
1.75
V
V
V
0.875
0.875
0.925
0.925
V
V
V
UVLO
comparator Hysteresis
H,M,L
mV
HYS
DC CHARACTERISTICS – Gates and Others
V
Voltage Input Valid High for
ENS, SETV, GATEH_EN
VDDH x
0.7
VDDH + 0.5
VDDH x 0.3
0.4
V
V
V
IH
V
Voltage Input Valid Low for
ENS, SETV, GATEH_EN
-0.5
IL
V
Output LOW Voltage
(SDA, READY)
OL
FN8154.0
3
X80200, X80201, X80202, X80203, X80204
Power Sequencing Control Circuits Over the recommended operating conditions unless otherwise specified (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
9.0
7.0
7.0
6.0
0
TYP
10
8
MAX
11.0
9.0
UNIT
V
GATE_H, GATE_M
V
V
= 5.5V
V
GATE_ON
DDH
DDH
GATE_L
GATE_H, GATE_M
GATE_L
= 3.1V
8
9.0
V
7.0
8.0
V
I
Gate Voltage Drive (OFF) for GATE_H,
GATE_M, GATE_L
0.1
V
GATE_OFF
GATE_ON
GATE_OFF
Gate Current Drive (ON) for GATE_H,
GATE_M, GATE_L
(Note 1)
20
9
35
10
45
11
µA
mA
I
Gate Sinking Current Drive (OFF) for
GATE_H, GATE_M, GATE_L
V
V
= 5.5V, V
= 0V,
DDM
DDH
DDL
= 0V, GATEH_EN = 0,
GATE_H = 5.5, GATE_L = 5.5,
GATE_M = 5.5 (Note 1)
V
VFB comparator
(Note 1) 25°C
15
10
20
25
mV
ms
HYST
AC CHARACTERISTICS
t
Delayed READY Output
V
V
= 5.5V
= 3.1V
12
40
15
80
PURST
DDH
DDH
(READY output delayed after VDDH rises
above UVLO )
H
t
V
V
V
V
V
V
V
V
= 5.5V, C
= 3.1V, C
= 5.5V
= 0
= 0
600
700
750
900
6
µs
ms
µs
DELAY_UP
DDH
DDH
DDH
DDH
DDH
DDH
DDH
DDH
GATE
GATE
t
800
900
6
DELAY_DOWN
= 3.1V
ms
µs
t
GATE_H, GATE_M, GATE_L
turn-off time
= 5.5V, (Note 1)
= 3.1V, (Note 1)
= 5.5V, (Note 1)
= 3.1V, (Note 1)
40
80
0.7
5
OFF
µs
t
GATE_H, GATE_M, GATE_L
turn-on time
0.5
2
0.6
ms
ms
µs
ON
t
V
V
Rise Time
Fall Time
(Note 1)
(Note 1)
1.0
1.0
R
DDH
DDH
t
µs
F
GATE_L
GATE_M
VDDH
t
DELAY_DOWN
t
t
F
t
R
DELAY_UP
GATE_H, M, L
t
t
ON
OFF
UVLO
H
VDDH
t
PURST
READY
FN8154.0
4
X80200, X80201, X80202, X80203, X80204
Serial bus Interface Electrical Characteristics
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
Signal Input Low Voltage
0.8
IL
V
Signal Input High Voltage
2.0
V
IH
V
Signal Output Low Voltage
Capacitive Load per bus segment
(Note 1), I
(Note 1)
≥ 4mA
pullup
0.4
V
OL
C
400
pF
BUS
Capacitance
SYMBOL
PARAMETER
Output Capacitance (SDA)
Input Capacitance (SCL)
TEST CONDITIONS
MAX
UNIT
C
V
V
= 0V, (Note 1)
OUT
8
6
pF
pF
OUT
C
= 0V, (Note 1)
IN
IN
NOTE:
1. Guaranteed by device characterization.
Equivalent AC Output Load Circuit for
VDDH = 5V
AC Test Conditions
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
VDDH
Input rise and fall times
Input and output timing levels
Output load
10ns
V
CC
2.06kΩ
Standard output load
SDA, READY
30pF
Symbol Chart
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8154.0
5
X80200, X80201, X80202, X80203, X80204
Bus Interface AC Timing
SMBUS
2-WIRE BUS
TEST
SYMBOL
PARAMETER
CONDITION
MIN
10
MAX
MIN
MAX
UNITS
kHz
µs
f
Clock Frequency
Clock Cycle Time
Clock High Time
Clock Low Time
Start Set-up Time
Start Hold Time
Stop Set-up Time
100
400
SCL
t
10
2.5
0.6
1.3
0.6
0.6
0.6
100
0
CYC
t
4.0
4.7
4.7
4.0
4.0
250
300
50
µs
HIGH
t
µs
LOW
t
µs
SU:STA
HD:STA
SU:STO
t
µs
t
µs
t
SDA Data Input Set-up Time
SDA Data Hold Time
ns
SU:DAT
t
ns
HD:DAT
t
SCL and SDA Rise Time: TR = (V
IHMIN
- 0.15) to
ILMAX
(Note 1)
(Note 1)
1000
300
300
300
ns
R
(V
+0.15)
t
SCL and SDA Fall Time: TF = (V
ILMAX
- 0.15) to
IHMIN
ns
F
(V
- 0.15)
t
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
(Note 1)
(Note 1)
(Note 1)
(Note 1)
550
300
50
4.7
0
1100
250
0
1100
ns
ns
ns
µs
ns
ns
AA
t
DH
T
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 Set-up Time
50
1.3
0
I
t
BUF
SU:A
HD:A
t
t
A0, A1, A2 Hold Time
0
0
Timing Diagrams
t
t
BUF
t
t
R
HIGH
LOW
t
t
BUF
F
SCL
t
t
t
t
t
SU:DAT
SU:STA
HD:DAT
SU:STO
HD:STO
t
t
HD:STA
SDA IN
t
t
DH
AA
HD:DAT
SDA OUT
FIGURE 1. BUS TIMING
START
SCL
CLK 1
CLK 9
SLAVE ADDRESS BYTE
SDA IN
t
t
HD:A
SU:A
A2, A1, A0
FIGURE 2. ADDRESS PIN TIMING
FN8154.0
6
X80200, X80201, X80202, X80203, X80204
In the absence of an externally provided ENS signal, the
Principles of Operation
Power Sequencing Control (PSC)
ENS pin can be connected in a number of different ways.
• ENS can connect to the VDDH pin. In this case, the
GATE_H and GATE_L outputs are enabled at the same
time. GATE_H could be delayed by using an external RC
timer between READY and GATEH_EN to provide a
sequence where VDDL is the first supply voltage applied
to the system.
The Intersil X80200 supports a variety of sequencing
applications. The sequencing can be voltage-based or time-
based. Some examples are shown in Figure , Figure , and
Figure in the Applications section. The X80200 allows for
designs that can control the power sequencing of up to three
voltage supplies. For systems with more than three supplies,
the X80200 may be cascaded.
• ENS can connect to a delayed READY signal, so that the
VDDL voltage follows the VDDH voltage by a fixed time.
Basic Functions
• ENS can connect to the system side of the VDDH FET, so
the VDDL voltage will follow immediately after the primary
supply is applied to the system.
VDDH is the primary voltage for the X80200. Once VDDH
rises above the primary undervoltage lockout level (UVLO )
H
for time t
, the READY output goes HIGH indicating
PURST
See "Functional Description" on page 7 for details on timing
and ramp-up.
that the supply power is good. By connecting READY
directly to GATEH_EN, the GATE_H output goes high
immediately, turning on the power FET connected in series
with VDDH. The system primary voltage may be delayed by
using an external RC circuit between READY and
GATEH_EN.
VOLTAGE-BASED POWER SEQUENCING
In this configuration, the drain of the “L” MOSFET is
connected to the VFB input of the X80200, the ENS pin is
tied to ground and a resistor divider provides a reference
voltage to the REF pin.
VDDH must be stable before VDDM and VDDL supplies are
monitored and power sequencing begins.
A LOW to HIGH transition of the SETV pin turns on the
GATE_L output. This turns on the “L” MOSFET. Once the
drain of this FET reaches the REF level, GATE_M turns on.
Since the trigger for the GATE_M output is selected by a
threshold level, the user has the ability to specify relative
core and I/O voltage sequencing.
The second supply voltage (I/O supply) is monitored by the
VDDM pin. VDDM must be greater than the I/O supply
undervoltage lockout level (UVLO ) prior to any activation of
the GATE_M output. The VDDM voltage is used to turn on
the charge pump that drives the GATE_M output.
M
System Monitoring and Remote Shutdown
The third supply (core supply) is monitored by the VDDL pin.
VDDL must be greater than the core supply undervoltage
The X80200 Status Register contains fault detection bits that
indicate the status of the GATE_H, GATE_M, and GATE_L
pins. These bits are Stat_GATEH, Stat_GATEM, and
Stat_GATEL. The status register can be read via 2-wire bus.
This feature allows for system monitoring of the power
sequencing of supplies.
lockout level (UVLO ) prior to any activation of the GATE_L
L
output. The VDDL voltage is used to turn on the charge
pump that drives the GATE_M output.
Power Sequencing Functions
X80200 provides two options for power sequencing. In time
based sequencing, the ENS (Enable Sequence) input
signals that the core and I/O voltages are to turn on with a
fixed time relationship. In voltage based sequencing, the
SETV (Set Voltage) initiates turn-on of the core voltage. The
I/O voltage remains off until the core voltage reaches a set
threshold.
The system can turn off the FETs by writing to the Remote
Shutdown Register through the 2-wire interface. There are
three turn-off selections. See "Remote Shutdown Register
(RSR) (Volatile)" on page 10 for more details.
Functional Description
Voltage Inputs. The X80200 has three voltage monitors for
power sequencing: the VDDH (primary voltage), VDDM (I/O
voltage), and VDDL (core voltage). These voltage monitors
operate independently of each other.
In both cases the X80200 uses a core-voltage first and core
voltage-last power up/down algorithm.
TIME-BASED POWER SEQUENCING
A rising edge (LOW to HIGH) transition of the ENS pin turns
on the charge pump that drives the GATE_L output.
PRIMARY VOLTAGE VDDH
This voltage is the primary voltage for the device and is
required before X80200 can power sequence VDDM and
VDDL. As VDDH powers up, it is compared to an internal
A falling edge (HIGH to LOW) transition of the ENS signal
turns off the charge pump that drives the GATE_M output.
This technique provides a “forced” core-voltage-first power
up and core-voltage-last power down algorithm. The ENS
signal does not control the ramp up/down rates of the
GATE_M or GATE_L outputs.
UVLO reference. This undervoltage lockout level is preset
H
at the factory. For information on this setting, see Ordering
Information. For custom programmed levels, contact Intersil.
FN8154.0
7
X80200, X80201, X80202, X80203, X80204
The READY output pin reflects the condition of the VDDH
input. READY is LOW as long as VDDH is below UVLO
time, the GATE_M charge pump turns ON. Again the slew
rate is dependent on the load connected to GATE_M output.
H
and remains LOW for a period of t
after VDDH
PURST
The falling edge transition on the ENS pin (HIGH to LOW)
turns off the charge pump that drives the GATE_M output.
crosses UVLO , see Figure 4. Once VDDH rises above
H
UVLO and remains stable for t
, the READY output
PURST
H
After a t
time period, the GATE_L charge
DELAY_DOWN
turns ON. If READY connects directly to the GATEH_EN pin,
then the GATE_H charge pump turns on immediately. The
turn on of the Gate_H charge pump can be delayed by using
an external filter (RC filter) connected between the READY
and GATEH_EN pins.
pump turns OFF.
ENS
When VDDH drops below the UVLO threshold, READY
H
goes inactive immediately. For more details on this turn-off
mechanism, See "Power Supply Failure Conditions" on
page 9.
t
DELAY_DOWN
GATE_L
t
DELAY_UP
SECONDARY VOLTAGES VDDM AND VDDL
The VDDM and VDDL voltage inputs each have their own
undervoltage lockout settings, UVLO , and UVLO ,
M
L
respectively. Each undervoltage lockout level is preset at the
factory. For information on these settings, See Ordering
Information. For custom programmed levels, contact Intersil.
GATE_M
FIGURE 3. TIME BASED SEQUENCING OF GATE_M AND
GATE_L
The GATE_M and GATE_ L charge pumps are OFF as long
as VDDM, and VDDL are below their respective UVLO trip
points. When READY is active and VDDM and VDDL go
above their UVLO thresholds, the GATE_M and GATE_L
charge pumps can be turned ON when activated as part of
the power sequence desired. If VDDL or VDDM drop below
the UVLO level the charge pumps turn off. For more details
on this turn-off mechanism, See "Power Supply Failure
Conditions" on page 9.
UVLO
H
VDDH
t
PURST
Sequence Delay Logic. This block contains the logic
circuits that implement the power-up and power-down
sequencing of the VDDH (GATE_H), VDDM (GATE_M), and
VDDL (GATE_L) voltages. The sequencing protocol has a
built-in “core-first-up and core-down-last” algorithm. On
power-up the GATE_L signal turns on first, followed by
GATE_M signal. During the power-down, the GATE_M turns
off first and the GATE_L signal follows.
READY
FIGURE 4. VDDH/READY SEQUENCING
Voltage Based Power Sequencing (SETV Option)
Using the SETV pin allows for a voltage based sequencing
of the GATE_L and GATE_M outputs. SETV is an edge
triggered input signal. A LOW to HIGH transition on SETV
immediately turns ON the charge pump for GATE_L. The
GATE_L output then starts ramping up. In this configuration,
the drain of the MOSFET “L” connects to the VFB pin and
this voltage is compared to an external reference applied to
the REF pin. The comparator turns on the charge pump for
GATE_M once the voltage on VFB exceeds the voltage on
REF. (See Figure 5.)
The sequencing of the power supplies is primarily controlled
and regulated via the SETV and the ENS (enable sequence)
pins.
All charge pumps are designed to ramp up their respective
gates at the same slew rate for the same load.
Time Based Power Sequencing (ENS option)
The ENS (Enable Sequence) pin controls the start of the
ramp up/ramp down sequence for GATE_M and GATE_L in
the time domain. (See Figure 3.)
The voltage sequencing comparator has a 30mV hysteresis,
so the GATE_M output does not oscillate as the core voltage
powers up.
A High to Low transition of SETV turns OFF charge pump M
ENS is an edge-triggered input. A rising edge (LOW to
HIGH) on the ENS input turns on the charge pump that
drives the GATE_L output. The slew rate of the GATE_L
output depends on the external MOSFET and any load
and GATE_M is pulled low. After a t
time
DELAY_DOWN
period, charge pump L turns off and GATE_L is pulled low.
connected to it. (See Electrical Table). After a t
DELAY_UP
FN8154.0
8
X80200, X80201, X80202, X80203, X80204
VDDH
FAILS
VDDM
FAILS
VDDL
FAILS
SETV
VDDH
VDDM
t
GATE_L
DELAY_DOWN
REF
REF
VDDL
FET “L”
DRAIN
(VFB)
GATE_H
GATE_M
GATE_L
GATE_M
FIGURE 5. VOLTAGE BASED SEQUENCING OF GATE_M
AND GATE_L
t
DELAY_DOWN
Power Supply Failure Conditions
Should there be a power failure of VDDH, GATE_H,
GATE_M and GATE_L charge pumps are all turned OFF
FIGURE 6. GATE CONTROL DURING INDIVIDUAL POWER
FAIL CONDITIONS
when VDDH falls below the UVLO threshold.
H
Should there be a failure of the VDDM supply, the GATE_M
Remote Monitoring Functions
charge pump turns off when VDDM falls below the UVLO
M
threshold. After a t
time period, the GATE_L
The X80200 can monitor the status of the GATE_H,
GATE_M, and GATE_L charge pump control signals. This
allows an indirect way to monitor system voltages. The
volatile status bits: Stat_GATEH, Stat_GATEM, and
Stat_GATEL indicate the status of GATE_H, GATE_M and
GATE_L output control signals, respectively. If the bit is a “1”,
then the charge pump is being turned on. If the bit is a “0”,
the output is turned off. Since the bits reflect the internal
control signal and not the state of the output, external
loading that prevents the charge pump from reaching the
desired FET gate drive voltage will not be detected by
reading the register.
DELAY_DOWN
charge pump turns OFF.
Should there be a failure of the VDDL supply, the GATE_L
and GATE_M charge pumps both turn off when VDDL falls
below the UVLO threshold.
L
These status bits can be read via the 2-wire serial bus. Refer
to Status Register section for more information on how to
read this register.
Several X80200 devices can be used to monitor many
system voltages on different system cards on a backplane.
Each X80200 has 3 slave address pins allowing up to 8
X80200 to be used on the same bus.
X80200 provides the user the ability to remotely turn-off the
gates through software. (See "Remote Shutdown Register
(RSR) (Volatile)" on page 10 for more information.)
FN8154.0
9
X80200, X80201, X80202, X80203, X80204
Register Information
Remote Shutdown Register (RSR) (Volatile)
The Register Block is organized as follows:
RSR
GATE
DATA SHUTDOWN
SEQUENCE
• Status Register (SR) (1 Byte). Located at address 00h.
01
GATE_M,
GATE_L
GATE_M turns off, then after time
DELAY_DOWN
• Remote Shut Down Register (RSR) (1 Byte). Located at
address FFh.
t
GATE_L turns off.
02
03
GATE_H
Immediate turn off of GATE_H
Status Register (Volatile)
GATE_H,
GATE_M,
GATE_L
GATE_H and GATE_M turn off, then after
7
6
5
4
3
2
1
0
time t
GATE_L turns off.
DELAY_DOWN
0
0
0
0
STAT_
GATEH
STAT_
GATEM
STAT_
GATEL
WEL
00
no override
X80200 returns to previous condition,
assuming all supplies are good, GATE_H
and GATE_L turn on, then GATE_M turns
on according to the chosen sequence
mode.
The Status Register provides the user a mechanism for
checking the status of GATE_H, GATE_M and GATE_L.
These bits are volatile and are read only.
The X80200 provides the user with a software shutdown of
GATE_H, GATE_L and GATE_M. This over-rides the normal
output control.
The gate status values in the Status Register can be read at
any time by performing a random read operation. Only one
byte is returned by each read operation. The master should
supply a stop condition following the output byte to be
consistent with the bus protocol.
A write operation with data 01h to the RSR will immediately
turn off GATE_M followed by GATE_L. The GATE_L turn off
is delayed by t
.
DELAY_DOWN
STAT_GATEH: GATEH Status Flag (volatile)
A write operation with data 02 to the RSR will turn off
GATE_H.
STAT_GATEH will be set to ‘1’ when the GATE_H charge
pump is turned on. It will be reset to ‘0’ when the GATE_H
charge pump is turned off.
A write operation with data 03 to RSR will shutdown all
gates. GATE_H turn off at the same time as GATE_M.
STAT_GATEM: GATEM Status Flag (volatile)
GATE_L turns off after a delay of t
.
DELAY_DOWN
STAT_GATEM will be set to ‘1’ when GATE_M charge pump
is turned on. It will be reset to ‘0’ when the GATE_M charge
pump is turned off.
A write operation with data 00h to the RSR will remove the
software override function. Assuming all supplies are good,
the X80200 will return to the previous state by first turning on
GATE_H and GATE_L. Then, GATE_M is turned on
according to the power sequencing mode chosen.
STAT_GATEL: GATEL Status Flag (volatile)
STAT_GATEL will be set to ‘1’ when GATE_L charge pump
is turned on. It will be reset to ‘0’ when the GATE_L charge
pump is turned off.
Bits 7, 6, 5, 4, 3 and 2 of the Remote Shutdown Register
should always be set to ‘0’.
The status register also contains a WEL bit that controls
write operations to the Shutdown Register. Bits 7, 6, 5, and 4
should always be set to ‘0’.
The data in the RSR can be read by performing a random
read operation to the RSR. The data in the RSR powers up
in ‘0’ state.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the Remote Shutdown
Register (RSR). This bit is a volatile latch that powers up in
the LOW (disabled) state. While the WEL bit is LOW, writes
to the RSR will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1” to the
WEL bit and zeroes to the other bits of the status register.
Bus Interface Information
Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the devices in this family operate as slaves in all
applications.
FN8154.0
10
X80200, X80201, X80202, X80203, X80204
SERIAL CLOCK AND DATA
Word Address
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. (See Figure 7.)
The next 8 bits following the slave byte, BA7–BA0,
determine the portion of the device accessed. If all ‘0’s, then
Status Register (SR) is selected. If all ‘1’s, then the Remote
Shutdown Register (RSR) is selected.
Serial Acknowledge
SCL
SDA
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data. (See Figure 9.)
DATA
DATA STABLE
DATA STABLE
CHANGE
FIGURE 7. VALID DATA CHANGES ON THE SDA BUS
SERIAL START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. (See Figure 8.)
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will acknowledge all incoming data
and address bytes, except for the Slave Address Byte when
the Device Identifier and/or Select bits are incorrect.
SERIAL STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH, followed by a HIGH to LOW transition on SCL. After
going LOW, SCL can stay LOW or return to HIGH. (See
Figure 8.)
SCL FROM
1
8
9
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
SCL
SDA
START
ACKNOWLEDGE
FIGURE 9. ACKNOWLEDGE RESPONSE FROM RECEIVER
START
STOP
Write Operation
FIGURE 8. VALID START AND STOP CONDITIONS
For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master
access to the registers. After receipt of the Word Address
Byte, the device responds with an acknowledge, and awaits
the next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a stop
condition. (See Figure 11, See Figure 1 for bus timing.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte. This byte consists of three parts:
• The Device Type Identifier which consists of the most
significant four bits of the Slave Address. The Device Type
Identifier MUST be set to 1010 in order to select the
device.
In order to perform a write operation to Remote Shutdown
Register, the Write Enable Latch (WEL) bit must first be set.
• The next 3 bits (SA3 - SA1) are slave address bits. These
bits are compared to the status of the input pins A2–A0.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined in
the bits SA2 - SA1). When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation.
FN8154.0
11
X80200, X80201, X80202, X80203, X80204
Read Operation
A Read operation is initiated in the same manner as a write
operation with the exception that the R/W bit of the Slave
Address Byte is set to one.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• The WEL bit is set to ‘0’. It is not possible to write to the
device.
Prior to issuing the Slave Address Byte with the R/W bit set to
one, the master must first perform a “dummy” write operation.
The master issues the start condition and the Slave Address
Byte, receives an acknowledge, then issues the Word Address
Byte. After acknowledging receipt of the Word Address Byte,
the master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is followed
by an acknowledge from the device and then by the data byte
containing the register contents. The master terminates the
read operation by responding with a no-acknowledge and then
issuing a stop condition. The ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
• The WEL bit must be set to allow write operations.
• SDA pin is the input mode.
• The data in the RSR powers up in ‘0’ state.
See Figure 12 for the address, acknowledge, and data
transfer sequence. See Figure 1 for bus timing.
SLAVE ADDRESS
INTERNAL
DEVICE TYPE
READ/
WRITE
DEVICE
IDENTIFIER
ADDRESS
SA7 SA6
SA3 SA2
SA5 SA4
SA1
SA0
0
1
0
1
A2
A1
A0 R/W
BIT SA0
OPERATION
WRITE
0
1
READ
WORD ADDRESS
BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SR
RSR
DATA BYTE
D7 D6
D5
D4
D3
D2
D1
D0
FIGURE 10. ADDRESS FORMAT
FN8154.0
12
X80200, X80201, X80202, X80203, X80204
S
T
SIGNALS FROM
THE MASTER
S
T
SLAVE
DEVICE
ID
A
R
T
WORD
ADDRESS
ADDRESS
O
P
DATA
SDA BUS
0
0
A2 A1 A0
1
0
1
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIGURE 11. BYTE WRITE SEQUENCE
S
T
S
S
T
SIGNALS FROM
SLAVE
ADDRESS
T
A
R
T
DEVICE
ID
WORD
SLAVE
ADDRESS
DEVICE
ID
THE MASTER
A
R
T
ADDRESS
O
P
SDA BUS
1
0 1 0
1
0 1 0
0
A2 A1 A0
1
A2 A1 A0
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
DATA
FIGURE 12. READ SEQUENCE
Application Section
DC-DC
#1
SYSTEM
PRIMARY
COMPONENTS &
BOARD SUPPLIES
H (OPTIONAL)
M
I/O VOLTAGES
I/O SUPPLY
DC-DC
#2
µP/
ASICs/
FPGA
CORE VOLTAGES
DC-DC
#3
CORE SUPPLY
L
X80200
VFB
VDDH
GATE_H
GATE_M
GATE_L
ENS
VCORE
V I/O
Primary
5V
3.3V
2.7V
2.5V
2.0V
1.8V
1.25V
0.9V
5V
VDDM
REF
3.3V
2.5V
1.35V
1.25V
SETV
VDDL
A0
PULL UP
OPTIONAL
RC DELAY
TO SET
GATEH_EN
READY
ADDRESS HIGH
A2
GND
SDA SCL
SMBus
SMBus
FIGURE 13. TELECOM BACKPLACE/SYSTEM POWER SUPPLY VOLTAGE BASED POWER SEQUENCING
FN8154.0
13
X80200, X80201, X80202, X80203, X80204
DC-DC
#1
SYSTEM
PRIMARY
COMPONENTS &
BOARD SUPPLIES
H (OPTIONAL)
I/O VOLTAGES
PGOOD1
I/O SUPPLY
DC-DC
#2
M
µP/
ASICs/
FPGA
CORE VOLTAGES
DC-DC
#3
CORE SUPPLY
L
PGOOD2
VCORE
V I/O
Primary
5V
3.3V
2.7V
2.5V
2.0V
1.8V
1.25V
0.9V
5V
3.3V
2.5V
1.35V
1.25V
VFB
VDDH
GATE_H
VDDM
REF
GATE_M
GATE_L
ENS
OPTION
SETV
FORCED
SEQUENCING
VDDL
A0
PULL UP
TO SET
OPTIONAL
DELAY
GATEH_EN
READY
ADDRESS HIGH
A2
GND
SDA SCL
SMBus
SMBus
FIGURE 14. TELECOM BACKPLACE/SYSTEM POWER SUPPLY TIME BASED POWER SEQUENCING
FN8154.0
14
X80200, X80201, X80202, X80203, X80204
POWER SEQUENCING (TIME BASED MODE)
USING POWER GOOD SIGNALS
PRIMARY
H (OPTIONAL)
V I/O
DC-DC
#1
SYSTEM
COMPONENTS &
BOARD SUPPLIES
DC-DC
#2
I/O SUPPLY
PGOOD1
M
7,8,55-57
V
µP/
ASICs/
FPGA
V
ID4:ID0
ID4:IDO
VRM
10
PWRGD
VCORE
POWER
SUPPLY
CORE SUPPLY
53 OUTEN
VCORE V I/O Primary
3.3V
2.7V
2.5V
2.0V
1.8V
1.25V
0.9V
5V
5V
3.3V
2.5V
1.35V
1.25V
X80200
VFB
VDDH
GATE_H
GATE_M
GATE_L
ENS
VDDM
REF
5 SCL
NC
OPTIONAL
FORCED
SDA
9
SETV
SEQUENCING
VDDL
A0
PULL UP
OPTION
DELAY
TO SET
ADDRESS HIGH
GATEH_EN
A2
READY
GND
SDA SCL
SMBus
SMBus
FIGURE 15. POWER SEQUENCING OF VRM SUPPLIES
FN8154.0
15
X80200, X80201, X80202, X80203, X80204
Packaging Information
20-Lead Plastic, TSSOP, Package Code V20
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.260 (6.6)
.041 (1.05)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8154.0
16
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