X60250 [INTERSIL]
Micro Power Programmable Voltage Reference; 微功耗可编程电压参考
| 型号： | X60250 |
| 厂家： | 
Intersil |
| 描述： | Micro Power Programmable Voltage Reference |
| 文件： | 总16页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X60250
®
Data Sheet
September 14, 2005
FN8146.1
PROGRAMMABLE VOLTAGE
REFERENCE APPLICATIONS
Micro Power Programmable Voltage
Reference
• Sensor Bias
FEATURES
• Variable DAC reference
• Linear Voltage Regulators
• DC/DC converters
• Voltage comparators
• Motor controllers
• 1.25V 1.0%, 20ppm/°C Tempco Reference
• Adjustable to ±0.25% Over the 0 to 1.25V Range
• 8 bit, 100kΩ XDCP on-chip
• Programmable Resolution of 4.9mV (255 steps)
• Extra Matched 100kΩ Resistor Available for
Increased Resolution Over a Smaller Range
• 2.7V to 5.5V Supply Range
• Amplifier biasing
DESCRIPTION
• 2-Wire Interface for Programming Reference
Setting
• Low Supply Current: 12µA in Normal Mode
• 8-pin TSSOP Package
• Programmable Reference
• NV Memory
The Intersil X60250 combines
a
temperature
compensated voltage reference with a Intersil Digitally
Controlled Potentiometer (XDCP) to provide a precision
adjustable reference with a range of 0.0V to 1.25V. The
device includes a serial bus interface to enable in-circuit
programming of the reference voltage.
• Pb-Free Plus Anneal Available (RoHS Compliant)
The XDCP contains a resistor chain with 255 taps to
provide 8 bits of digital adjustment to the reference
voltage. Non-volatile storage retains the digital wiper
setting, for permanent reference programming. An
additional matched 100kΩ resistor is available to
increase resolution of the output voltage while retaining
accuracy.
IC BLOCK DIAGRAM
VCC
VREFOUT
Pwr On Recall
1.25V
Reference
100K
VOUT
EE
PROM
R1
SCL
SDA
Serial
Interface
100kΩ
Digital Wiper
Control
GND
VREFL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X60250
Ordering Information
OUTPUT VOLTAGE
PART NUMBER
X60250V8I
X60250V8IZ (Note)
PART MARKING
(V)
RESOLUTION
8 bits
TEMP RANGE (°C)
-40 to 85
PACKAGE
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
60250 I
1.250
1.250
60250I Z
8 bits
-40 to 85
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
TSSOP
V
REFL
1
8
SCL
SDA
GND
V
2
3
4
7
6
5
CC
V
REFOUT
V
R
1
OUT
PIN ASSIGNMENTS
TSSOP
Symbol
VREFL
VCC
Description
1
2
3
4
5
6
7
8
DCP and auxiliary resistor reference input
Positive Power Supply
Bandgap Reference Output
DCP Wiper Output
VREFOUT
VOUT
R1
Auxiliary resistor input
Ground
GND
SDA
Serial Data Input/Output
Serial Clock Input
SCL
FN8146.1
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September 14, 2005
X60250
ABSOLUTE MAXIMUM RATINGS
COMMENTS
Supply Voltage Range...................................-1V to 7V
Bias Temperature Range .................... -40°C to +85°C
Storage Temperature Range............. -65°C to +150°C
Absolute Maximum Ratings indicate limits beyond
which permanent damage to the device and impaired
reliability may occur. These are stress ratings provided
for information only and functional operation of the
device at these or any other conditions beyond those
indicated in the operational sections of this specification
are not implied.
Voltage on V
pin .............................0V to V
REF(LOW)
CC
Voltage on all other pins ................-0.3V to V +0.3V
CC
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
For guaranteed specifications and test conditions, see
Electrical Characteristics.
Min
-40°C
2.7V
Max
+85°C
5.5V
Temperature
The guaranteed specifications apply only for the test con-
ditions listed. Some performance characteristics may de-
grade when the device is not operated under the listed
test conditions.
Supply Voltage
ELECTRICAL CHARACTERISTICS
(Over operating conditions unless otherwise specified. I
= 12.5 µA, R = N/C (Floating).)
OUT
1
ANALOG PARAMETERS
Limits
(1)
Symbol
Parameter
Min. Typ.
Max.
Unit
Test Conditions
Power Supply
VCC
IQ
Supply Voltage Range
2.7
3.0
15
5.5
V
Supply Current
VCC = 2.7V
VCC = 3V
20
60
µA
RL=0, VREFL, VOUT, RAUX = floating
VCC = 5.5V Write
IQ(NV)
Non-Volatile Supply Current
VCC = 2.7V
1100
1300
µA
RL=0, VREFL, VOUT, RAUX = floating
VCC = 3V
VCC = 5.5V
600
Reference Output Voltage
DC Parameters
VREFOUT Output Voltage
1.237
GND
1.250
1.263
VREFOUT
V
V
TA = 25°C
VREFL
DCP and auxilliary resistor
reference input
(2, 5)
(6)
TCOref
Temperature coefficient of
20
66
70
ppm/°C
dB
VREF output voltage
PSRR
IOUT
Power Supply Rejection
55
Output Current
Sourcing
Sinking
(2)
400
2.5
µA
1
1
(2)
ROUT
ISC
Output Impedance
Ω
Given by ROUT = (∆VREF/∆IOUT)
Short Circuit Current
Sourcing
Sinking
5
0
mA
µF
At 5.5V
CL
Load Capacitance
0.001
0.003
Reference output stable for all CL up
to specifications (2)
FN8146.1
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September 14, 2005
X60250
ANALOG PARAMETERS (CONTINUED)
Limits
(1)
Symbol
Parameter
Min. Typ.
Max.
Unit
Test Conditions
AC Parameters
VN
Output Voltage Noise
100
200
µVP-P 0.1Hz to 10Hz (2)
µVRMS 10Hz to 10kHz (2)
Power-on Response
Line Ripple Rejection
250
60
µs
1% Settling (2)
V
DD = 3V ±100mV, f = 120 Hz (2)
dB
Reference DCP
Resolution
8
bits
RTOT
RW
End to end resistance
85
100
115
kΩ
Wiper Resistance
VCC = 2.7V
VCC = 3V
(2)
5000
1200
Ω
600
±0.2
±0.1
±300
±20
Absolute Linearity (INL)
Relative Linearity (DNL)
LSB
LSB
RTOT Temperature Coeff.
ppm/°C
ppm/°C
Ratiometric Temp. Coeff.
RAUX (Auxiliary Resistor)
RTOT
End to end resistance
85
100
±300
0.1
115
kΩ
RTOT Temperature Coeff.
ppm/°C RL=0, VREFL, VOUT, RAUX = floating
DCP Matching Tolerance
%
DCP Matching Temp. Coeff.
±20
ppm/°C
DIGITAL PARAMETERS
Limits
(1)
Symbol
ILI
Parameter
Min.
Typ.
Max.
Unit
µA
µA
V
Test Conditions
VIN = GND to VCC
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Capacitance
Output Low Voltage
Output High Voltage
Output Load
2
2
ILO
VOUT = GND to VCC
VIL
0
VCC x 0.2
VCC
VIH
CIN
VOL
VOH
CL
VCC x 0.7
V
5
pF
0
10
%VDD IOL = 100 µA (2)
%VDD IOH = 100 µA (2)
90
100
100
pF
(2)
EEPROM PARAMETERS (Erase at V = 5.0 V min, T = 25°C)
CC
Parameter
Min.
Units
Write Cycle Endurance
100,000
Cycles per bit
CAPACITANCE
Symbol
CIN/OUT
CIN
Test
Max.
Units
pF
Test Conditions
VOUT = 0V (2)
VIN = 0V (2)
Input/Output capacitance (SDA)
Input capacitance (SCL)
8
6
pF
FN8146.1
September 14, 2005
4
X60250
A.C. TEST CONDITIONS
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
10ns
Input rise and fall times
Input and output timing threshold level
External load at pin SDA
V
CC x 0.5
2.3kΩ to VCC and 100 pF to VSS
AC SPECIFICATIONS
Symbol
Parameter
Min.
0
Max. Unit
fSCL
tIN
SCL Clock Frequency
400
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
Pulse width Suppression Time at inputs (2)
SCL LOW to SDA Data Out Valid (2)
50
tAA
0.1
0.9
tBUF
Time the bus must be free before a new transmission can start (2)
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Clock LOW Time
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
0.6
0.6
Data In Setup Time
100
0
Data In Hold Time
Stop Condition Setup Time (2)
Data Output Hold Time (2)
0.6
50
tR
SDA and SCL Rise Time (2, 3)
SDA and SCL Fall Time (2, 3)
Capacitive load for each bus line (2, 3)
20 +.1Cb
20 +.1Cb
300
300
400
tF
Cb
TIMING DIAGRAMS
Bus Timing
tBUF
tR
tF
tHIGH
tLOW
tBUF
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STO
tHD:STA
SDA IN
tAA tDH
tHD:DAT
SDA OUT
FN8146.1
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September 14, 2005
X60250
WRITE CYCLE TIMING
SCL
8th Bit of Last Byte
ACK
SDA
tWC
Stop
Start
Condition
Condition
POWER-UP TIMING
Symbol
Parameter
VCC Power-up rate (2)
Min.
0.2
Max.
Unit
∆VCC/∆t
50
V/ms
tPUR
tPUW
Time from Power-up to Read (2)
Time from Power-up to Write (2)
1
5
ms
ms
NONVOLATILE WRITE CYCLE TIMING
Symbol
Parameter
Write Cycle Time (4)
Min.
Typ.
Max.
10
Unit
tWC
5
ms
Notes: (1) Typical values are for TA = 25°C and VCC = 3.0V
(2) This parameter is guaranteed by characterization.
(3) Cb = total capacitance of one bus line in pF.
(4) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile
write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
(5) Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in
V
OUT is divided by the temperature range; in this case, -40°C to +85°C = 125°C. TCOref = [Max V(VREF) - Min V(VREF)] ×
106 / (1.25V × 125°C)
FN8146.1
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September 14, 2005
X60250
FUNCTIONAL DESCRIPTION
wiper currents and thus only a small output voltage error.
If the X60250 is used with the wiper connected to V
to produce a current source, care must be taken to avoid
exceeding the maximum output current of the reference
(typically 400µA).
REFL
The X60250 combines a micropower precision reference
with an 8-bit, 256 tap digitally controlled 100kΩ
potentiometer (DCP) which allows nonvolatile setting of
an output reference voltage. When normally configured
with the V
pin tied to ground, the device provides an
REFL
Power-Up considerations
output range of 0V to 1.25V with 4.90mV resolution.
The X60250 contains EEPROM nonvolatile storage cells
which are recalled during power-up. This recall process
The device can also be configured with an optional
100kΩ series resistor to ground, which effectively halves
the output voltage range while doubling the resolution.
works best with power supply (V ) ramping that is
CC
monotonic and free of excessive glitches (<100mV
disturbances give best results). The ramp rate spec
should be adhered to, although the most sensitive part of
Grounding the R pin while floating the V
pin places
1
REFL
the device in this mode. Output voltage setting accuracy
can be as high as 0.10% while permitting adjustment
from 0.625V to 1.25V (2.45mV resolution).
recall is between V = 1.0V and 2.5V. Effort should be
CC
made to make sure the device receives a power-up ramp
between those voltage levels that meet the ramp rate
spec and have no glitches.
Reference Section
The reference is designed to provide an accurate, low
tempco voltage source while requiring less than 12µA
(typical) of supply current. This supply current is for the
reference section only. Keep in mind that the DCP will
increase supply current draw by VREF/RTOTAL
(typically 1.25/100k or 12.5µA). The total current drawn
by the adjustable reference circuit will be less than 25µA
(typically).
Recall of the stored wiper position happens in < 1ms
from V reaching 2.5V. Note that any excursions of V
CC
CC
below 2.5V, although temporary, can cause the wiper to
be loaded with the midpoint value (80h) until V
recovers to its normal voltage.
CC
Register Organization
There are 2 nonvolatile registers and 1 volatile register
available for storage and recall via the serial bus. They
contain the current wiper position, a general purpose
data register and a status register.
The reference output has a typical impedance of 1Ω and
can provide up to 400µA of load current. It is intended to
drive the resistive load of the DCP, which is a minimum
of 85kΩ, but can also be used to drive off chip circuitry
provided the loading does not exceed the 400µA
maximum. Also, highly capacitive loads can make the
reference oscillate, so no more than 2000pF should be
The wiper register is nonvolatile and is at address 0h and
contains 8 bits, with the 00h setting corresponding to the
tap position nearest V
, and the FFh setting nearest
REFL
to V
.
REFOUT
placed directly on the output of the V
pin.
REFOUT
The general purpose register is nonvolatile and is at
address 1h, and contains 8 bits for use as scratchpad
memory or serial number information.
The reference output produces about 200µV RMS of
noise (10kHz bandwidth) due to its micropower design.
This is easily reduced in normal applications, as shown in
the applications section for optimizing circuits for
reducing output noise levels.
The Status register is volatile and is at address 7h. It has
one active bit, D3, which is the WEL bit. This bit must be
set to 1 berfore any nonvolatile writes are performed to
the other registers. See the register information on the
next page.
DCP Section
The 256 tap DCP has an 8-bit nonvolatile wiper control
register which controls which tap is selected. The
register is changed by performing a serial data write to its
address (0h, see Serial Interface section). The resulting
wiper position will produce an output voltage at V
,
OUT
depending on whether the DCP V
is grounded or the
REFL
R
pin is grounded. The wiper consists of CMOS
1
transistors and has a finite resistance, typically 600Ω at
V
V
= 5V (this parameter increases with decreasing
). The wiper resistance will produce errors in
CC
CC
reference circuits due to I-R drops if current flows
through the wiper. However, typically these circuits will
have the wiper connected to a high impedance
comparator or amplifier input which results in very small
FN8146.1
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September 14, 2005
X60250
X60250 REGISTER BIT MAP
Addr
D7
D6
D5
D4
D3
D2
D1
D0
0
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
(MSB)
1
7
D7
(MSB)
D6
0
D5
0
D4
0
D3
D2
0
D1
0
D0 (LSB)
0
0
WEL
REGISTER DESCRIPTIONS
Reg
Nonvolatile Description
0
1
7
Y
Y
N
VOUT wiper setting
General Purpose data storage register
Status register
REGISTER 0 (NONVOLATILE)
This register is used to hold the DCP wiper position, which is given by:
Code
---------------
×
V
= V
(with V
= GND)
REFL
OUT
REF
255
REGISTER 1 (NONVOLATILE)
This 8 bit register is used for general storage such as date code, temp setting, etc.
STATUS REGISTER
Bit
Value Description
D - D4
D3
0
0 - 1
Must remain 0
WEL bit
Must be programmed to "1" for Reg 0 or 1 EEPROM
write. When accessing, only WEL bit may be changed
Must remain 0
D2 - D0
0
FN8146.1
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September 14, 2005
X60250
X60250 BUS INTERFACE INFORMATION
Figure 1. Slave Address, Word Address, and Data Bytes - Write Mode
Slave Address*
Device Identifier
Slave Address Byte
0
A0
D0
0
0 / 1
0
0
1
0
1
Byte 0
Byte Address
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
Byte 1
Data Byte
Byte 2
Figure 2. Slave Address, Word Address, and Data Bytes - Read Mode
Slave Address*
Device Identifier
Slave Address Byte
1
D0
D0
0
0
0 / 1
0
1
0
1
Byte 0
Data Byte
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
Byte 1
Data Byte
Byte 2
FN8146.1
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September 14, 2005
X60250
X60250 BUS INTERFACE INFORMATION
Pin Descriptions
Slave Address, Address Byte, and Data Byte
V
REFOUT
The byte communication format for the serial bus is
shown in Figure 1 on the previous page. The first byte,
BYTE 0, defines the device identifier, 0101 in the upper
half; and the device slave address in the low half of the
byte. The slave address is set to 0. The next byte,
BYTE 1, is the Address Byte. The Address Byte
identifies a unique address for the Status or Control
Registers as shown in the Register Descriptions table.
The following byte, Byte 2, is the byte used for READ
and WRITE operations.
Reference voltage output.
The 1.25V bandgap
reference output (V ) is available at this pin for
REF
application to other circuits. Maximum output current is
400µA. The V pin also connects to the Rh
REFOUT
terminal of the 256-tap DCP.
V
OUT
DCP Wiper Output. This pin functions as the wiper of the
DCP, and can be used as a variable voltage source for
voltages between GND and V
. Since it is connected
REF
to the DCP resistor, any loads on this pin must be high
impedance for best performance.
Start Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. On power-
up, the SCL pin must be brought LOW prior to the
START condition. See Figure 3.
R
1
Auxiliary Resistor Input. The R pin is connected to one
1
end of a 100kΩ resistor (R ) which closely matches the
1
DCP resistance. The other end of R is tied to the R
1
REFL
terminal of the DCP. When R is grounded and V
is
1
REFL
left open, the output voltage range of V
will be from
OUT
Stop Condition
V
/2 to V
, and the effective resolution (mV/step) of
REF
REF
the Reference control is doubled. R should be left open
if not used.
1
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH followed by a HIGH to LOW
transistion on SCL. After going LOW, SCL can stay LOW
or return to HIGH. See Figure 3.
GND
This pin is common for the V
signal inputs.
output and for control
REF
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 4. The device will
respond with an acknowledge after recognition of a start
condition and if the correct Device Identifier and Select
bits are contained in the Slave Address Byte. If a write
operation is selected, the device will respond with an
acknowledge after the receipt of each subsequent eight
bit word. The device will acknowledge all incoming data
and address bytes, except for:
SDA
Serial Data Input/Output. Bidirectional pin used for serial
data transfer. As an output, it is open drain and may be
wire-ored with any number of open drain or open
collector outputs. A pullup resistor is required and the
value is dependent on the speed of the serial data bus
and the number of outputs tied together.
SCL
Serial Clock Input. Accepts a clock signal for clocking
serial data into and out of the device.
V
REFL
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
DCP and Auxiliary Resistor Input. This pin is connected
to one end of the 256-tap DCP, and also to one end of
the 100kΩ auxiliary resistor. When connected to ground,
– The 2nd Data Byte of a Status Register Write Oper-
ation (only 1 data byte is allowed)
V
range will be from 0V to V
. When left open
OUT
REF
and R is connected to ground, the voltage at this pin will
1
be from V
/2 to V
.
REF
REF
FN8146.1
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September 14, 2005
X60250
V
Figure 3. Valid Start and Stop Conditions
CC
Positive Power Supply. Connect to a voltage supply in
the range of 2.7V < V < 5.5V, with minimum noise and
ripple. For best performance, bypass with a 0.1µF
capacitor to ground.
CC
SCL
SDA
Start
Stop
Figure 4. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Change
Data Stable
Data Stable
FN8146.1
September 14, 2005
11
X60250
Figure 6. Byte Write Sequence
S
t
Signals from
the Master
S
t
o
p
Slave
Address*
Device
ID
a
r
Byte
Address 0
Data
t
SDA Bus
1 0 1
0
0/1
0
0
0
A
C
K
A
C
K
A
C
K
Signals From
The Slave
*Note: The X60250 will respond to either 000 or 001 slave addresses.
Byte Write
A write to a protected block of memory is ignored, but will
still receive an acknowledge. At the end of the write
command, the X60250 will not initiate an internal write
cycle, and will continue to okay commands.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array.
Upon receipt of each address byte, the X60250 responds
with an acknowledge. After receiving the address bytes
the X60250 awaits the eight bits of data. After receiving
the 8 data bits, the X60250 again responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition. The X60250 then begins an
internal write cycle of the data to the nonvolatile memory.
During the internal write cycle, the device inputs are
disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance.
See Figure 6.
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and its associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X60250 resets itself without performing the
write. The contents of the array are not affected.
Figure 7. Random Address Read Sequence
S
S
Signals from the
t
a
r
S
Slave
Address
Device
ID
t
a
r
Byte
Address 0
Slave
Address
Device
ID
Master
t
o
p
t
t
SDA Bus
1 0 1
0
0/1
0
0
0
1 0 1
0
0
0
0
1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Random Address Read
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 7. The X60250 then goes
into standby mode after the stop and all bus activity will
be ignored until a start is detected. This operation loads
the new address into the address counter. The next
Current Address Read operation will read from the newly
loaded address. This operation could be useful if the
master knows the next address it needs to read, but is
not ready for the data.
Random read operation allows the master to access any
location in the X60250. Prior to issuing the Slave
Address Byte, the master must first perform a “dummy”
write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues the
word address bytes. After acknowledging receipt of each
word address byte, the master immediately issues
another start condition and the slave address byte. This
is followed by an acknowledge from the device and then
by the eight bit data word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. Refer to Figure 7 for
the address, acknowledge, and data transfer sequence.
FN8146.1
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September 14, 2005
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TYPICAL PERFORMANCE CHARACTERISTIC CURVES
VRefout vs Temperature (2 representative units)
IREFOOUT vs VREFOUT
1.25120
1.25070
1.25020
1.24970
1.24920
1.24870
1.24820
1.24770
1.24720
1.24670
1.24620
1.2550
1.2540
1.2530
1.2520
1.2510
1.2500
1.2490
1.2480
1.2470
1.2460
1.2450
Refout
+25 deg C
-40 deg C
+85 deg C
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
IREFOUT (mA)
Temperature (C)
VRefout vs Vcc
Icc vs Vcc
1.257E+0
1.256E+0
1.255E+0
1.254E+0
1.253E+0
1.252E+0
1.251E+0
1.250E+0
1.249E+0
50.00E-6
45.00E-6
40.00E-6
35.00E-6
30.00E-6
25.00E-6
20.00E-6
15.00E-6
10.00E-6
Refout (-40C)
Refout (25C)
Refout (85C)
Icc (-40C)
Icc (25C)
Icc (85C)
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
Vcc (V)
Vcc (V)
Vref Output Voltage Noise, 0.1Hz to 10Hz
V
Output Noise Spectrum
REF
10
9
8
7
6
5
4
3
2
1
0
Filter = 1 zero at 0.1Hz
2 poles at 10Hz
Vertical = 50µV/div
Horizontal = 1 sec/div
10
100
1000
10000
Frequency
DNL
INL
0.50
0.40
0.30
0.20
0.10
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
0.50
0.40
0.30
0.20
0.10
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
0
50
100
150
200
250
0
50
100
150
Tap Position
200
250
Tap Position
FN8146.1
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TYPICAL PERFORMANCE CHARACTERISTIC CURVES (Continued)
Power On Settling Time
APPLICATIONS INFORMATION
Figure 9. Using Auxilliary Resistor
VREFOUT
Standard Reference configurations
Figure 8 shows the device connections to produce a 0
to 1.250V adjustable reference with 8 bits of resolution.
VOUT
R1
0.625V to 1.25V
Range
V
will be grounded in this case. Figure 9 has
1.25V
Reference
REFL
100K
device connections to produce a 0.625V to 1.250V
reference with 8 bits of resolution, with R grounded.
1
This configuration effectively doubles the output voltage
control resolution, increasing the accuracy of the
desired reference output voltage. Since the auxiliary
resistor is matched to the DCP resistor, temperature
drift is minimized.
100K
VREFL
GND
Figure 8. Standard Configuration
VREFOUT
Reducing Output Noise
The output noise voltage of the reference is typically
200µV rms in the 10kHz bandwidth. An advantage of the
adjustable reference configuration is the ease in filtering
Adjusted
VOUT
Reference
1.25V
Reference
Voltage
0.0 to 1.25V Range
100K
this noise. Simply adding a capacitor to the V
pin will
OUT
R1
produce a single pole filter with a corner frequency of:
1
--
F
=
× π × R
× C
DCP FILTER
CORNER
2
100K
R
will vary with tap position and wiper resistance. If
DCP
the approximate tap position of the DCP is known, it can
be used to calculate this resistance as follows:
VREFL
GND
255 – tapw
tapw
#
#
||
-----------------------------
-------------
R
=
× R
× R
+ R
WIPER
DCP
TOTAL
TOTAL
255
255
For example, with V = 5V, tap # = 127 (corresponding
CC
to V
= 0.623V), C
= 0.1µF, using typical values:
OUT
FILTER
R
= 25K + 0.6K = 25.6kΩ
DCP
F
= 62Hz
CORNER
FN8146.1
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September 14, 2005
X60250
Since this is a single pole rolloff, the actual noise
Higher Reference Voltages
bandwidth is 1.57 times this, or 97Hz. This should
reduce typical output noise to about 45µV rms. Note that
if the wiper is set to the highest tap positon (tap# = 255)
If a reference voltage higher than 1.25V is required, then
an opamp can be added to amplify the V
voltage.
OUT
There are many micropower opamps available, such as
the LMV341, which can produce an output at very close
to either supply rail. Figure 11 shows a circuit for a 0V to
5.0V adjustable reference, which has 8 bits of control.
Note that if the auxiliary resistor is connected to ground
to give a V
of 1.25V, the resulting R
= R
or
OUT
DCP
WIPER
600Ω, and the filter bandwidth will now be 2.6kHz,
increasing noise significantly. If tap positions near
V
will be used, then a series resistor R
should
REFOUT
OUT
be added to better control noise bandwidth.
instead of V
, then the output voltage range will be
REFL
2.5V to 5.0V, but resolution will double. Total current
draw from that circuit will be 156µA (typically, with
Figure 10. Reducing Output Noise
V
= 5V) including reference and opamp circuitry.
OUT
VREFOUT
Note that due to V supply variations, the output may
CC
ROUT
(optional)
not span up to 5.00V which would result in missing codes
at the top end of the DCP range.
VOUT
Filtered
Reference
Voltage
1.25V
Reference
100K
Figure 11. Increasing Reference Output Voltage
R1
CFILTER
VREFOUT
+5V
5
100K
R1
20K
0 to
1
3
6
+
5.0V
4
1.25V
Reference
LMV341
100K
–
VREFL
2
GND
CFILTER
100K
100K
33K
VREFL
GND
FN8146.1
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September 14, 2005
X60250
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
(7.72)
(4.16)
Detail A (20X)
(1.78)
(0.42)
.031 (.80)
.041 (1.05)
(0.65)
All Measurements Are Typical
See Detail “A”
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN8146.1
16
September 14, 2005
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