X68257DMB [XICOR]
EEPROM, 32KX8, 120ns, Parallel, CMOS, CDIP28, HERMETIC SEALED, CERDIP-28;
| 型号： | X68257DMB |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 32KX8, 120ns, Parallel, CMOS, CDIP28, HERMETIC SEALED, CERDIP-28 |
| 文件： | 总14页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
68XX Microcontroller Family Compatible
256K
X68257
32,768 x 8 Bit
E2 Micro-Peripheral
FEATURES
DESCRIPTION
2
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500µA Standby Maximum
• Software Data Protection
• Toggle Bit Polling
The X68257 is an 32K x 8 E PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X68257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chipmicrocontrollersoperatinginexpandedmul-
tiplexed mode without the need for additional interface
circuitry.
—Early End of Write Detection
• Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
• 28-Lead PDIP Package
• 28-Lead SOIC Package
• 32-Lead PLCC Package
FUNCTIONAL DIAGRAM
CE, CE
R/W
CONTROL
LOGIC
SOFTWARE
DATA
E
PROTECT
SEL
X
L
A
T
C
H
E
S
D
E
C
O
D
E
A –A
8
14
32K x 8
2
AS
E PROM
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D –A/D
0
7
6539 ILL F02.2
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
6539-1.7 9/16/96 T0/C1/D2 SH
Characteristics subject to change without notice
1
X68257
PIN DESCRIPTIONS
PIN CONFIGURATION
Address/Data (A/D –A/D )
0
7
PDIP
SOIC
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on R/W, SEL, and
CE.
A
A
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
14
12
CC
2
R/W
AS
SEL
CE
3
A
13
4
A
8
A
9
5
Addresses (A –A )
8
14
NC
NC
NC
NC
NC
6
A
11
HighorderaddressesflowintothedevicewhenAS=V
and are latched when AS goes LOW.
IH
X68257
7
E
8
A
10
Chip Enable (CE)
9
CE
The Chip Enable input must be LOW to enable all read/
write operations. WhenCE is HIGH, AS is LOW, and CE
is LOW, the X68257 is placed in the low power standby
mode.
10
11
12
13
14
A/D
7
A/D
0
A/D
1
A/D
2
A/D
A/D
A/D
A/D
6
5
4
3
V
Chip Enable (CE)
SS
Chip Enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
6539 FHD F01.3
PLCC
Program Store Enable (SEL)
When the X68257 is to be used in a 68XX-based
system, SEL is tied to V
.
SS
3
2
1 32 31
4
30
29
Read/Write (R/W)
SEL
CE
NC
NC
NC
NC
NC
NC
A
8
A
9
5
6
7
8
9
When the X68257 is to be used in a 68XX-based
system, R/W is tied directly to the microcontroller’s R/W
output.
28
27
26
25
24
23
22
21
A
11
NC
E
Address Strobe (AS)
X68257
10
A
10
Addressesflowthroughthelatchestoaddressdecoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
11
12
13
CE
A/D
7
A/D
6
A/D
0
PIN NAMES
14 15 16 17 18 19 20
Symbol
AS
A/D –A/D
Description
Address Strobe
6539 FHD F01A.5
Address Inputs/Data I/O
Address Inputs
Enable Input
0
7
A –A
8
14
E
R/W
CE, CE
Read/Write Input
Chip Enable
SEL
Device Select—Connect to V
Ground
SS
V
SS
CC
V
Supply Voltage
No Connect
NC
6539 PGM T01.2
2
X68257
PRINCIPLES OF OPERATION
DEVICE OPERATION
The X68257 is a highly integrated peripheral device for
awidevarietyofsingle-chipmicrocontrollers.TheX68257
provides 32K-bytes of 5V E PROM which can be used
Motorola 68XX operation requires the microcontroller
AS, E, and R/W outputs to be tied to the X68257 AS, E,
and R/W inputs respectively.
2
either for program storage, data storage, or a combina-
tion of both, in systems based upon Von Neumann
(68XX) architectures. The X68257 incorporates the
interfacecircuitrynormallyneededtodecodethecontrol
signals and demultiplex the address/data bus to provide
a “seamless” interface.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of the R/W output
determines the operation to be performed, with the E
signal acting as a data strobe.
IfR/W isHIGHandCEisHIGH(readoperation)datawill
be output on A/D –A/D after E transitions HIGH. If
0
7
The interface inputs on the X68257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip micro-
controller.
R/W is LOW and CE is HIGH (write operation) data
present at A/D –A/D will be strobed into the X68257 on
0
7
the HIGH to LOW transition of E.
2
TheX68257featurestheindustrystandard5VE PROM
characteristics such as byte or page mode write and
Toggle Bit Polling.
Typical Application
U?
30
U?
XTAL
31
32
33
34
35
36
37
38
11
12
12
15
16
17
18
19
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
29
EXTAL
39
RESET
41
IRQ
40
XIRQ
8
PA0
7
PA1
6
16
15
14
13
12
11
10
9
25
24
21
23
2
PA2
5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A8
PA3
4
A9
PA4
3
A10
A11
A12
A13
A14
CE
PA5
2
PA6
1
26
1
PA7
VCC
20
25
5
MODA
24
CE
MODB
26
28
3
4
AS
AS
SEL
42
27
PD0
43
R/W
R/W
PD1
44
27
22
PD2 MISO
45
E
E
PD3 MOSI
46
X68257
17
18
19
20
PD4 SCK
47
PE0
PE1
PE2
PE3
PD5 SS
22
21
VRH
VRL
68HC11
6539 ILL F03.2
3
X68257
MODE SELECTION
CE
E
R/W
Mode
I/O
Power
V
X
X
X
Standby
Standby
Read
High Z
High Z
Standby (CMOS)
Standby (TTL)
Active
SS
LOW
HIGH
HIGH
X
HIGH
HIGH
LOW
D
OUT
IN
Write
D
Active
6539 PGM T02.2
PAGE WRITE OPERATION
Regardlessofthemicrocontrolleremployed,theX68257
supports page mode write operations. This allows the
microcontroller to write from 1 to 128 bytes of data to the
X68257. Eachindividualwritewithinapagewriteopera-
tion must conform to the byte write timing requirements.
The rising edge of E starts a timer delaying the internal
programming cycle 100µs. Therefore, each successive
write operation must begin within 100µs of the last byte
written.Thefollowingwaveformsillustratethesequence
and timing requirements.
Page Write Timing Sequence for E Controlled Operation
OPERATION
BYTE 1
BYTE 0
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
CE
AS
A
A
A
A
A
A
A
IN
D
D
D
D
D
IN
A/D –A/D
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0
7
An
An
An
An
An
ADDR
Next Address
A –A
8
14
E
R/W
t
t
WC
BLC
6539 FHD F07.1
Note: (1) For each successive write within a page write cycle A –A must be the same.
14
7
4
X68257
Toggle Bit Polling
subsequent attempts to read the device. When the
internalcycleiscomplete,thetogglingwillceaseandthe
device will be accessible for additional read or write
operations.
Becausethetypicalwritetimingislessthanthespecified
5ms, Toggle Bit Polling has been provided to determine
the early end of write. During the internal programming
cycle I/O will toggle from “1” to “0” and “0” to “1” on
6
Toggle Bit Polling E Control
OPERATION
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
X68257 READY FOR
NEXT OPERATION
I/O6=X
I/O6=X
CE
AS
A
A
A
A
A
A
D
D
D
D
D
OUT
A/D –A/D
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
0
7
An
An
An
An
An
ADDR
A –A
8
14
E
R/W
6539 FHD F08.2
5
X68257
Software Data Protection
SYMBOL TABLE
Software Data Protection (SDP) is employed to protect
the entire array against inadvertent writes. To write to
the X68257, a three-byte command sequence must
precede the byte(s) being written.
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
All write operations, both the command sequence and
anydatawriteoperationsmustconformtothepagewrite
timing requirements.
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Writing with SDP
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
WRITE AA
TO 5555
N/A
Center Line
is High
Impedance
WRITE 55
TO 2AAA
WRITE A0
TO 5555
PERFORM BYTE
OR PAGE WRITE
OPERATIONS
WAIT t
WC
EXIT ROUTINE
6539 FHD F09.1
6
X68257
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reli-
ability.
Respect to V
.................................. –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
+70°C
+85°C
+125°C
X68257
5V ±10%
6539 PGM T04.1
–40°C
–55°C
6539 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
CE = V , All I/O’s = Open,
I
I
I
V
V
V
Current (Active)
60
mA
CC
CC
CC
CC
IL
Other Inputs = V , AS = V
CC
IH
Current (Standby)
Current (Standby)
500
6
µA
CE = V , All I/O’s = Open,Other
SS
SB1(CMOS)
SB2(TTL)
LI
Inputs = V
– 0.3V, AS = V
SS
CC
mA
CE = V , All I/O’s = Open, Other
IH
Inputs = V , AS = V
IH
IL
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
IN
= V to V
SS CC
V
OUT
= V to V , E = V
LO
(1)
SS
CC
IL
V
V
V
V
–1
2
0.8
lL
(1)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
+ 0.5
V
IH
CC
0.4
V
I
I
= 2.1mA
OL
OL
2.4
V
= –400µA
OH
OH
6539 PGM T05.1
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Test
Max.
Units
Conditions
(2)
C
C
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
V
= 0V
= 0V
I/O
I/O
(2)
IN
V
IN
6539 PGM T06
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(2)
t
Power-Up to Read
Power-Up to Write
1
5
ms
ms
PUR
(2)
t
PUW
6539 PGM T07
Notes: (1) V min. and V max. are for reference only and are not tested.
IL IH
(2) This parameter is periodically sampled and not 100% tested.
7
X68257
A.C. CONDITIONS OF TEST
TEST CIRCUIT
Input Pulse Levels
0V to 3V
5V
Input Rise and
Fall Times
10ns
1.92KΩ
Input and Output
Timing Levels
OUTPUT
1.37KΩ
1.5V
6539 PGM T08.1
100pF
6539 FHD F04.2
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
E Controlled Read Cycle
Symbol
PW
Parameter
Min.
Max.
Units
Address Strobe Pulse Width
Address Setup Time
Address Hold Time
Data Access Time
Data Hold Time
80
20
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASH
ASL
t
t
t
t
t
AHL
ACC
DHR
CSL
120
0
7
CE Setup Time
PW
E Pulse Width
150
30
20
20
EH
t
t
t
t
t
Enable Setup Time
E Hold Time
ES
EH
R/W Setup Time
E LOW to High Z Output
E HIGH to Low Z Output
RWS
(3)
HZ
(3)
LZ
50
0
ns
6539 PGM T09.1
E Controlled Read Cycle
CE
t
t
EH
CSL
PW
t
t
ASH
ES
EH
AS
t
t
AHL
ASL
A
D
A/D –A/D
IN
OUT
0
7
t
t
t
ACC
DHR
HZ
A –A
A –A
8
8
14
14
t
RWS
R/W
E
t
EH
PW
EH
6539 FHD F05.2
Note: (3) This parameter is periodically sampled and not 100% tested.
8
X68257
E Controlled Write Cycle
Symbol
Parameter
Min.
Max.
Units
PW
Address Strobe Pulse Width
Address Setup Time
Address Hold Time
Data Setup Time
80
20
30
50
30
7
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
µs
ASH
t
t
t
t
t
ASL
AHL
DSW
DHW
CSL
Data Hold Time
CE Setup Time
PW
E Pulse Width
120
EH
t
t
t
t
t
Write Cycle Time
Enable Setup Time
R/W Setup Time
5
WC
ES
30
20
20
0.5
RWS
EH
E Hold Time
6539 FHD F05.2
Byte Load Time (Page Write)
100
BLC
6539 PGM T10
E Controlled Write Cycle
CE
t
t
EH
t
CSL
PW
ASH
t
ES
EH
AS
t
t
AHL
ASL
A
D
A/D –A/D
IN
IN
0
7
t
t
DSW
DHW
A –A
A –A
8
8
14
14
t
t
EH
RWS
R/W
E
PW
EH
6539 FHD F06.2
Note: (4) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
WC
9
X68257
WR Controlled Write Cycle
Symbol
Parameter
Min.
Max.
Units
t
t
t
t
t
t
t
t
t
t
t
ALE Pulse Width
80
20
30
50
30
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
LHLL
AVLL
LLAX
DVWH
WHDX
ELLL
WLWH
WRS
WRH
BLC
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Chip Enable Setup Time
WR Pulse Width
WR Setup Time
WR Hold Time
Byte Load Time (Page Write)
Write Cycle Time
120
30
20
0.5
100
5
(7)
WC
6539 PGM T11
WR Controlled Write Timing Diagram
OPERATION
BYTE 1
BYTE 0
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
CE
AS
A
A
A
A
A
A
A
IN
D
D
D
D
D
IN
A/D –A/D
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0
7
An
An
An
An
An
ADDR
Next Address
A –A
8
14
E
R/W
t
t
WC
BLC
6539 FHD F07.1
Note: (7) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
10
X68257
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.470 (37.34)
1.400 (35.56)
0.557 (14.15)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
REF.
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
TYP. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F04
11
X68257
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.299 (7.59)
0.290 (7.37)
0.419 (10.64)
0.394 (10.01)
0.020 (0.508)
0.014 (0.356)
0.713 (18.11)
0.697 (17.70)
0.105 (2.67)
0.092 (2.34)
BASE PLANE
SEATING PLANE
0.012 (0.30)
0.003 (0.08)
0.050 (1.270)
BSC
0.050" TYPICAL
0.0200 (0.5080)
X 45°
0.0100 (0.2540)
0.050"
TYPICAL
0.013 (0.32)
0.008 (0.20)
0° – 8°
0.42" MAX
0.0350 (0.8890)
0.0160 (0.4064)
0.030" TYPICAL
28 PLACES
FOOTPRINT
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F17
12
X68257
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.030" TYPICAL
32 PLACES
0.050"
0.420 (10.67)
TYPICAL
0.050"
TYPICAL
0.510"
TYPICAL
0.400"
0.050 (1.27) TYP.
0.300"
REF
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
13
X68257
ORDERING INFORMATION
X68257
X
X
Temperature Range
Device
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 28-Lead Plastic DIP
S = 28-Lead SOIC
J = 32-Lead PLCC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475;4,450,402;4,486,769;4,488,060;4,520,461;4,533,846;4,599,706;4,617,652;4,668,932;4,752,912;4,829,482;4,874,967;4,883,976;
4,980,859; 5,012,132; 5,003,197; 5,023,694. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailure
of the life support device or system, or to affect its satety or effectiveness.
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