LCL8052ACPD [INTERSIL]
Precision 4 1/2 Digit, A/D Converter; 精密4 1/2位， A / D转换器
| 型号： | LCL8052ACPD |
| 厂家： | 
Intersil |
| 描述： | Precision 4 1/2 Digit, A/D Converter |
| 文件： | 总23页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICL8052A/ICL71C03,
ICL8068A/ICL71C03
TM
heet
May 2001
File Number 3081.2
1
Precision 4 / Digit, A/D Converter
2
Features
itle
L80
AA/
L71
3,
L80
A/IC
1C0
The ICL8052A or ICL8068A/lCL71C03 chip pairs with their
multiplexed BCD output and digit drivers are ideally suited
for the visual display DVM/DPM market. The outstanding
• Typically Less Than 2µV
Noise (200.00mV Full Scale,
P-P
lCL8068A
• Accuracy Guaranteed to 1 Count Over Entire 20,000
Counts (2.0000V Full Scale)
1
4 / digit accuracy, 200.00mV to 2.0000V full scale
2
capability, auto-zero and auto-polarity combine with true
ratiometric operation, almost ideal differential linearity and
time-proven dual slope conversion. Use of these chip pairs
eliminates clock feedthrough problems, and avoids the
critical board layout usually required to minimize charge
injection.
• Guaranteed Zero Reading for 0V Input
• True Polarity at Zero Count for Precise Null Detection
• Single Reference Voltage Required
• Over-Range and Under-Range Signals Available for Auto-
Ranging Capability
bjec
ecis
When only 2000 counts of resolution are required, the 71C03
1
• All Outputs TTL Compatible
can be wired for 3 / digits and give up to 30 readings/sec.,
2
making it ideally suited for a wide variety of applications.
• Medium Quality Reference, 40ppm (Typ) on Board
• Blinking Display Gives Visual Indication of Over Range
The ICL71C03 is an improved CMOS plug-in replacement for
the lCL7103 and should be used in all new designs.
/2
git,
D
nver
)
utho
)
• Six Auxiliary Inputs/Outputs are Available for Interfacing to
UARTs, Microprocessors or Other Complex Circuitry
Part Number Information
• 5pA Input Current (Typ) (8052A)
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
14 Ld PDIP
lCL8052ACPD
ICL8068ACDD
lCL8068ACJD
lCL71C03ACPl
0 to 70
0 to 70
0 to 70
0 to 70
E14.3
14 Ld CERDIP
14 Ld CERDIP
28 Ld PDIP
F14.3
F14.3
E28.6
eyw
s
tersi
Pinouts
rpor
on,
ICL8052A/ICL8068A
(CERDIP, PDIP)
TOP VIEW
ICL71C03 (PDIP)
TOP VIEW
alog
V+
1
1
2
3
4
5
6
7
8
9
28 BUSY
1
4 / / 3 /
27
26
25
24
23
22
21
20
19
D
D
D
D
B
B
B
B
D
(LSD)
gital
nver
,
D,
crop
esso
2
2
1
2
3
4
8
4
2
1
5
POL
RUN/HOLD
COMP IN
V-
COMP OUT
1
2
3
4
5
6
7
14 INT OUT
-1.2V
13 +BUFF IN
12 +INT IN
11 -INT IN
V-
(MSB)
REF CAP
REF BYPASS
GND
REFERENCE
REF. CAP. 1
REF. CAP. 2
V
10 -BUFF IN
(LSB)
(MSD)
REF
erfa
ANALOG IN 10
ANALOG GND 11
CLOCK IN 12
REF OUT
9
8
BUFF OUT
V+
18 STROBE
17 A-Z IN
ICL8052A/
ICL8068A
REF SUPPLY
ta
quis
16
UNDER-RANGE 13
OVER-RANGE 14
A-Z OUT
15 DIGITAL GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright © Intersil Americas Inc. 2001
1
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Functional Block Diagram
0.22µF
10kΩ
90kΩ
100kΩ
+15V -15V
SEVEN-
SEGMENT
DECODER
-BUF IN BUF OUT -INT IN INT OUT
REF
OUT
8
7
1
10
BUFFER
9
11
INTEG.
14
COMP.
6
3
INT.
REF.
-
-
A1
+
A2
-
300pF
D
D
D
D
D
1
5
4
3
2
+
A3
10kΩ
3
19
24
25
26
27
ICL8052A/8068A
+
B
1
20
21
22
-1.2V
5
+INT IN 12
2
MSD
LSD
1kΩ
+BUF IN 13
B
2
COMP
OUT
B
B
MULTIPLEXER
10µF
3
4
10µF (TYP)
REF
1µF (TYP)
23
REF
CAP 1
AZ OUT
AZ IN
CAP 2
COMP IN
16
17
5
8
9
LATCH
LATCH
LATCH
LATCH
LATCH
REF
7
4
ZERO
ANALOG
INPUT
2
5
CROSSING
DETECTOR
SW3
COUNTERS
10kΩ
0.1µF
10
11
1
6
CONTROL LOGIC
ICL71C03
ANALOG
GND
1
15
6
4
12
2
14
13
18
28
RUN/
HOLD
CLOCK 4 1/2 DIGIT/ OVER UNDER STROBE BUSY
IN RANGE RANGE
3 1/2 DIGIT
+5V
-15V
FIGURE 1.
2
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Absolute Maximum Ratings
Thermal Information
o
o
ICL8052A, ICL8068A
Thermal Resistance (Typical, Note 5)
θ
( C/W)
θ
( C/W)
JA
JC
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Differential Input Voltage
CERDIP Package. . . . . . . . . . . . . . . . .
14 Ld PDIP Package . . . . . . . . . . . . . .
28 Ld PDIP Package . . . . . . . . . . . . . .
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300 C
75
100
65
20
N/A
N/A
o
(8068A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
(8052A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Output Short Circuit Duration All Outputs (Note 2) . . . . . . Indefinite
ICL71C03
o
o
Power Supply Voltage (GND to V+). . . . . . . . . . . . . . . . . . . . . . 6.5V
Negative Supply Voltage (GND to V-) . . . . . . . . . . . . . . . . . . . . -17V
Analog Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Digital Input Voltage (Note 4) . . . . . . . . .(GND - 0.3V) to (V+ + 0.3V)
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage.
o
3. Short circuit may be to ground or either supply. Rating applies to 70 C ambient temperature.
4. Input voltages may exceed the supply voltages provided the input current is limited to 100µA.
5. Connecting any digital inputs or outputs to voltages greater then V+ or less than GND may cause destructive device latchup. For this reason it
is recommended that the power supply to the ICL71C03 be established before any inputs from sources not on that supply are applied.
6. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
TEST
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.2
0.1
0.1
0.1
2.5
0.25
4.2
4.99
400
1200
2
MAX
UNITS
mA
µA
µA
µA
V
Clock In, Run/Hold, 4 1/2 / 3 1/2
I
V
V
V
V
= 0
-
0.6
INL
IN
IN
IN
IN
I
= +5V
= 0
-
10
INH
Comp. In Current
I
-
10
INL
I
= +5V
-
10
INH
Threshold Voltage
All Outputs
V
-
-
-
INTH
V
I
I
I
= 1.6mA
= -1mA
= -10µA
0.40
V
OL
OH
OH
OL
OH
OH
B , B , B , B , D , D , D , D , D
5
V
2.4
4.9
-
-
V
1
2
4
8
1
2
3
4
Busy, Strobe, Over-Range, Under-Range Polarity
Switches 1, 3, 4, 5, 6
Switch 2
V
-
V
r
r
-
Ω
DS(ON)
DS(ON)
-
-
Ω
Switch Leakage (All)
+5V Supply Range
I
-
-
6
pA
V
D(OFF)
V+
4
5
-15V Supply Range
V-
I+
I-
-5
-
-15
1.1
0.8
40
-18
3
V
+5V Supply Current
f
f
= 0
= 0
mA
mA
pF
kHz
CLK
CLK
-15V Supply Current
Power Dissipation Capacitance
Clock Frequency (Note 6)
NOTE:
-
3
C
vs Clock Frequency
-
-
PD
DC
2000
1200
7. This specification relates to the clock frequency range over which the ICL71C03A will correctly perform its various functions. See the “Max Clock
Frequency” section under Component Value Selection for limitations on the clock frequency range in a system.
3
ICL8052A/ICL71C03, ICL8068A/ICL71C03
o
ICL8068A Electrical Specifications V
=
15V, T = 25 C, Unless Otherwise Specified
A
SUPPLY
TEST
PARAMETER
EACH OPERATIONAL AMPLIFIER
Input Offset Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
I
V
V
V
V
= 0V
= 0V
-
-
20
80
65
mV
pA
dB
dB
OS
CM
CM
CM
CM
Input Current (Either Input) (Note 7)
Common-Mode Rejection Ratio
150
IN
CMRR
=
=
10V
2V
70
-
90
-
-
Non-Linear Component of Common-Mode Rejection
Ratio (Note 8)
110
Large Signal Voltage Gain
Slew Rate
A
R
= 50kΩ
L
20,000
-
-
-
-
-
V/V
V/µs
MHz
mA
V
SR
-
-
-
6
2
5
Unity Gain Bandwidth
Output Short-Circuit Current
COMPARATOR AMPLIFIER
Small-Signal Voltage Gain
Positive Output Voltage Swing
Negative Output Voltage Swing
VOLTAGE REFERENCE
Output Voltage
GBW
I
SC
A
R
= 30kΩ
L
-
-
-
-
-
V/V
V
VOL
+V
12
13
O
O
-V
-2.0
-2.6
V
V
R
1.60
1.75
5
1.90
-
V
O
Output Resistance
-
Ω
O
o
Temperature Coefficient
Supply Voltage (V++ -V-)
Supply Current Total
TC
-
40
-
-
ppm/ C
V
10
-
16
14
V
SUPPLY
I
8
mA
SUPPLY
o
ICL8052A Electrical Specifications V
=
15V, T = 25 C, Unless Otherwise Specified
A
SUPPLY
TEST
PARAMETER
EACH OPERATIONAL AMPLIFIER
Input Offset Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
I
V
V
V
V
= 0V
= 0V
-
-
20
2
75
10
-
mV
pA
dB
dB
OS
CM
CM
CM
CM
Input Current (Either Input) (Note 7)
Common-Mode Rejection Ratio
IN
CMRR
=
=
10V
2V
70
-
90
110
Non-Linear Component of Common-Mode Rejection
Ratio (Note 8)
-
Large Signal Voltage Gain
Slew Rate
A
R
= 50kΩ
L
20,000
-
6
-
-
-
-
V/V
V/µs
MHz
mA
V
SR
-
-
-
Unity Gain Bandwidth
GBW
1
Output Short-Circuit Current
COMPARATOR AMPLIFIER
Small-Signal Voltage Gain
Positive Output Voltage Swing
Negative Output Voltage Swing
VOLTAGE REFERENCE
Output Voltage
I
20
SC
A
R
= 30kΩ
L
-
-
-
-
-
V/V
V
VOL
+V
12
13
O
O
-V
-2.0
-2.6
V
V
R
1.60
-
1.75
5
1.90
-
V
O
Output Resistance
Ω
O
4
ICL8052A/ICL71C03, ICL8068A/ICL71C03
o
ICL8052A Electrical Specifications V
=
15V, T = 25 C, Unless Otherwise Specified (Continued)
SUPPLY
A
TEST
PARAMETER
Temperature Coefficient
Supply Voltage (V++ -V-)
Supply Current Total
NOTES:
SYMBOL
CONDITIONS
MIN
TYP
40
-
MAX
-
UNITS
o
TC
-
ppm/ C
V
10
-
16
14
V
SUPPLY
I
6
mA
SUPPLY
o
8. The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature, T . Due
J
to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction
temperature rises above the ambient temperature as a result of internal power dissipation, P . T = T + R
resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
P , where R is the thermal
θJA θJA
D
J
A
D
9. This is the only component that causes error in dual-slope converter.
System Electrical Specifications: ICL8068A/ICL71C03
o
V++ = +15V, V+ = +5V, V- = -15V, T = 25 C, f
Set for 3 Readings/Sec.
A
CLK
ICL8068A/ICL71C03
ICL8068A/ICL71C03
(NOTE 9)
(NOTE 10)
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
-000.0
TYP
MAX
000.0
UNITS
Zero Input Reading
V
= 0V,
-000.0
000.0
+000.0
000.0
Digital
IN
Full Scale = 200mV
Reading
Ratiometric Error (Note 11)
V
= V
0.999
1.000
0.2
1.001
0.9999
1.0000
0.5
1.0001
Digital
Reading
IN
REF
Full Scale = 2V
Linearity Over Full Scale (Error of
Reading from Best Straight Line)
-2V ≤ V ≤ +2V
IN
-
-
1
-
-
-
1
-
Counts
Differential Linearity (Difference between -2V ≤ V ≤ +2V
0.01
0.01
Counts
IN
Worst Case Step of Adjacent Counts and
Ideal Step)
Rollover Error (Difference in Reading for -V ≅ +V ≈ 2V
IN IN
Equal Positive & Negative Voltage Near
Full Scale)
-
-
0.2
3
1
-
-
-
0.5
2
1
-
Counts
Noise (P-P Value Not Exceeded 95% of
Time)
V
= 0V,
µV
IN
Full Scale = 200mV
Leakage Current at Input
V
= 0V
-
-
200
1
300
5
-
-
100
0.5
200
2
pA
IN
IN
o
Zero Reading Drift (Note 12)
V
= 0V,
µV/ C
o
o
0 C ≤ T ≤ 50 C
A
o
Scale Factor Temperature Coefficient
(Note 12)
V
= 2V,
-
3
15
-
2
5
ppm/ C
IN
o
o
0 C ≤ T ≤ 50 C
Ext. Ref. 0ppm/ C
A
o
System Electrical Specifications: ICL8052A/ICL71C03
o
V++ = +15V, V+ = +5V, V- = -15V, T = 25 C, f
Set for 3 Reading/Sec.
A
CLK
ICL8052A/ICL71C03
ICL8052A/A/ICL71C03
(NOTE 9)
(NOTE 10)
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Zero Input Reading
V
= 0V,
-0.000
0.999
-
0.000
+0.000
1.001
1
-0.000
0.000
0.000
Digital
Reading
IN
Full Scale = 2V
Ratiometric Error (Note 11)
V
= V
1.000
0.2
0.9999
-
1.0000
0.5
1.0001
1
Digital
Reading
IN
REF
Full Scale = 2V
Linearity Over Full Scale (Error of
Reading from Best Straight Line)
-2V ≤ V ≤ +2V
IN
Counts
5
ICL8052A/ICL71C03, ICL8068A/ICL71C03
System Electrical Specifications: ICL8052A/ICL71C03
o
V++ = +15V, V+ = +5V, V- = -15V, T = 25 C, f
Set for 3 Reading/Sec. (Continued)
A
CLK
ICL8052A/ICL71C03
ICL8052A/A/ICL71C03
(NOTE 9)
(NOTE 10)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Differential Linearity (Difference between -2V ≤ V ≤ +2V
-
0.01
-
-
0.01
-
Counts
IN
Worst Case Step of Adjacent Counts and
Ideal Step)
Rollover Error (Difference in Reading for -V ≅ +V ≈ 2V
IN IN
-
0.2
1
-
0.5
1
Counts
Equal Positive & Negative Voltage Near
Full Scale)
Noise (Peak-To-Peak Value Not
Exceeded 95% of Time)
V
= 0V,
IN
Full Scale = 200mV,
Full Scale = 2V
-
20
50
-
-
-
-
-
-
µV
30
3
Leakage Current at Input
Zero Reading Drift
V
= 0V
-
-
5
1
30
5
-
-
10
2
pA
IN
IN
o
V
= 0V,
0.5
µV/ C
o
o
0 C To 70 C
o
Scale Factor Temperature Coefficient
V
= 2V,
-
3
15
-
2
5
ppm/ C
IN
o
o
0 C To 70 C,
Ext. Ref. 0ppm/ C
o
NOTES:
1
10. Tested in 3 / digit (2,000 count) circuit shown in Figure 5, clock frequency 12kHz. Pin 2 71C03 connected to GND.
2
1
11. Tested in 4 / digit (20,000 count) circuit shown in Figure 5, clock frequency 120kHz. Pin 2 71C03A open.
2
12. Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
o
13. The temperature range can be extended to 70 C and beyond if the Auto-Zero and Reference capacitors are increased to absorb the high
temperature leakage of the 8068A.
Zero phase, and the integrator will generate a ramp whose
Detailed Description
slope is proportional to V . At the end of this phase, the
IN
Analog Section
sign of the ramp is latched into the polarity F/F.
Figure 2 shows the equivalent Circuit of the Analog Section
of both the ICL71C03/8052A and the ICL71C03/8068A in
the 3 different phases of operation. IF the RUN/HOLD pin is
Deintegrate Phase II (Figures 2C and 2D)
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switch 6 or 5. If the input signal is positive, switch 6 is closed
left open or tied to V+, the system will perform conversions
1
at a rate determined by the clock frequency: 40,0002 at 4 /
1
2
and a voltage which is V
more negative than during
digit and 4002 at 3 / digit clock periods per cycle (see
2
REF
Auto-Zero is impressed on the BUFFER INPUT. Negative
Inputs will cause +2(V ) to be applied to the BUFFER
Figure 3 for details of conversion timing).
REF
Auto-Zero Phase I (Figure 2A)
INPUT via switch 5. Thus, the reference capacitor generates
the equivalent of a (+) or (-) reference from the single
reference voltage with negligible error. The reference voltage
returns the output of the integrator to the zero-crossing point
established in Phase I. The time, or number of counts,
required to do this is proportional to the input voltage. Since
the Deintegrate phase can be twice as long as the Input
Integrate Phase, the input voltage required to give a full
During the Auto-Zero, the input of the buffer is connected to
through switch 2, and switch 3 closes a loop around
V
REF
the integrator and comparator, the purpose of which is to
charge the auto-zero capacitor until the integrator output
does not change with time. Also, switches 1 and 2 recharge
the reference capacitor to V
.
REF
Input Integrate Phase II (Figure 2B)
scale reading is 2V
.
REF
During Input Integrate the auto-zero loop is opened and the
ANALOG INPUT is connected to the BUFFER INPUT
through switch 4 and C
. If the input signal is zero, the
REF
buffer, integrator and comparator will see the same voltage
that existed in the previous state (Auto-Zero). Thus, the
integrator output will not change but will remain stationary
during the entire Input Integrate cycle. If V is not equal to
IN
zero, and unbalanced condition exists compared to the Auto
6
ICL8052A/ICL71C03, ICL8068A/ICL71C03
C
R
INT
INT
V
(+1.000V)
2
REF
BUFFER
INTEGRATOR
COMPARATOR
-
-
5
4
1µF
ZERO
CROSSING
DETECTOR
A1
+
A2
+
-
A3
+
C
REF
V
IN
1
6
C
STRAY
C
AZ
3
FIGURE 2A. PHASE I AUTO-ZERO
R
C
INT
INT
V
(+1.000V)
2
REF
BUFFER
INTEGRATOR
COMPARATOR
-
-
5
4
1µF
ZERO
CROSSING
DETECTOR
A1
+
A2
+
-
A3
+
C
REF
V
1
IN
6
C
STRAY
C
AZ
POLARITY
FF
3
FIGURE 2B. PHASE II INTEGRATE INPUT
R
C
INT
INT
V
(+1.000V)
2
REF
BUFFER
INTEGRATOR
COMPARATOR
-
-
5
4
1µF
ZERO
CROSSING
DETECTOR
A1
+
A2
+
-
A3
+
C
REF
V
1
IN
6
C
STRAY
C
AZ
POLARITY
FF
3
FIGURE 2C. PHASE III + DEINTEGRATE
R
C
INT
INT
V
(+1.000V)
2
REF
BUFFER
INTEGRATOR
COMPARATOR
-
-
5
4
1µF
ZERO
CROSSING
DETECTOR
A1
+
A2
+
-
A3
+
C
REF
V
1
IN
6
C
STRAY
C
AZ
POLARITY
FF
3
FIGURE 2D. PHASE III - DEINTEGRATE
FIGURE 2. ANALOG SECTION OF EITHER ICL8052A OR ICL8068A WITH ICL71C03
7
ICL8052A/ICL71C03, ICL8068A/ICL71C03
COUNTS
PHASE I
10,001
1,001
PHASE II
10,000
1,000
PHASE III
20,001
1
4 / DIGIT
2
1
3 / DIGIT
2,001
2
POLARITY
DETECTED
ZERO CROSSING
OCCURS
INTEGRATOR
OUTPUT
ZERO CROSSING
DETECTED
AZ PHASE I
INT PHASE II
DEINT PHASE III
AZ
CLOCK
INTERNAL LATCH
BUSY OUTPUT
AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO V
IN
CONFIGURATION
FIGURE 3. CONVERSION TIMING
Zero-Crossing Flip-Flop
Figure 4 shows the problem that the zero-crossing F/F is
designated to solve.
CLOCK
PULSE
FEEDTHROUGH
The integrator output is approaching the zero-crossing point
where the count will be latched and the reading displayed.
For a 20,000 count instrument, the ramp is changing
approximately 0.50mV per clock pulse (10V Max integrator
output divided by 20,000 counts). The clock pulse
TRUE ZERO
CROSSING
FALSE ZERO
CROSSING
feedthrough superimposed upon this ramp would have to be
less than 100mV peak to avoid causing significant errors.
FIGURE 4. INTEGRATOR OUTPUT NEAR ZERO-CROSSING
The flip-flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by clock
pulses are not recognized. Of course, the flip-flop delays the
true zero-crossing by one count in every instance, and if a
correction were not made, the display would always be one
count too high. Therefore, the counter is disabled for one
clock pulse at the beginning of phase 3. This one count
delay compensates for the delay of the zero crossing flip-
flop, and allows the correct number to be latched into the
display. Similarly, a one count delay at the beginning of
phase 1 gives an overload display of 0000 instead of 0001.
No delay occurs during phase 2, so that true ratiometric
readings result.
Detailed Description
Digital Section
The 71C03 includes several pins which allow it to operate
conveniently in more sophisticated systems. These include:
4-1/2 / 3-1/2 (PIN 2)
When high (or open) the internal counter operates as a full
1
4 / decade counter, with a complete measurement cycle
2
requiring 40,002 counts. When held low, the least significant
decade is cleared and the clock is fed directly into the next
decade. A measurement cycle now requires only 4,0002
clock pulses. All 5 digit drivers are active in either case, with
1
each digit lasting 200 counts with Pin 2 high (4 / digit) and
2
1
20 counts for Pin 2 low (3 / digit).
2
8
ICL8052A/ICL71C03, ICL8068A/ICL71C03
RUN/HOLD (PIN 4)
BUSY (PIN 28)
When high (or open) the A/D will free-run with equally
spaced measurement cycles every 40,0002/4,002 clock
pulses. If taken low, the converter will continue the full
measurement cycle that it is doing and then hold this reading
as long as Pin 4 is held low. A short positive pulse (greater
then 300ns) will now initiate a new measurement cycle
beginning with up to 10,001/1,001 counts of auto zero. Of
course if the pulse occurs before the full measurement cycle
(40,002/4,002 counts) is completed, it will not be recognized
and the converter will simply complete the measurement it is
doing. An external indication that full measurement cycle
has been completed is that the first STROBE pulse (see
below) will occur 101/11 counts after the end of this cycle.
Thus, if RUN/HOLD is low and has been low for at least
101/11 counts, converter is holding and ready to start a new
measurement when pulsed high.
BUSY goes high at the beginning of signal integrate and
stays high until the first clock pulse after zero-crossing (or
after end of measurement in the case of an OVER-RANGE).
The internal latches are enabled (i.e., loaded) during the first
clock pulse after BUSY and are latched at the end of this
clock pulse. The circuit automatically reverts to auto-zero
when not BUSY so it may also be considered an A-Z signal.
A very simple means for transmitting the data down a single
wire pair from a remote location would be to AND BUSY with
clock and subtract 10,001/1,001 counts from the number of
pulses received - as mentioned previously there is one “NO-
count” pulse in each Reference Integrate cycle.
OVER-RANGE (PIN 4)
This pin goes positive when the input signal exceeds the
range (20,000/2,000) of the converter. The output F-F is set
at the end of BUSY and is reset to zero at the beginning of
Reference Integrate in the next measurement cycle.
STROBE (PIN 18)
This is a negative-going output pulse that aids in transferring
the BCD data to external latches, UARTs or
UNDER-RANGE (PIN 13)
This pin goes positive when the reading is 9% of range or
less. The output F-F is set at the end of BUSY (if the new
reading is 1800/180 or less) and is reset a the beginning of
Signal Integrate of the next reading.
microprocessors. There are 5 negative-going STROBE
pulses that occur once and only once for each measurement
cycle starting 101/11 pulses after the end of the full
measurement cycle. Digit 5 (MSD) goes high at the end of
the measurement cycle and stays on for 201/21 counts. In
the center of this digit pulse (to avoid race conditions
POLARITY (PIN 3)
This pin is positive for a positive input signal. It is valid even for a
zero reading. In other words, +0000 means the signal is
positive but less than the least significant bit. The converter can
be used as null detector by forcing equal (+) and (-) readings.
The null at this point should be less than 0.1 LSB. This output
becomes valid at the beginning of Reference Integrate and
remains correct until it is revalidated for the next measurement.
between changing BCD and digit drives) the first STROBE
1
pulse goes negative for / clock pulse width. Similarly, after
2
Digit 5, Digit 4 goes high (for 200/20 clock pulses) and
100/10 pulses later the STROBE goes negative for the
second time. This continues through Digit 1 (LSD) when the
fifth and last STROBE pulse is sent. The digit drive will
continue to scan (unless the previous signal was over-range)
but no additional STROBE pulses will be sent until a new
measurement is available.
DIGIT DRIVES (PINS 19, 24, 25, 26, AND 27)
Each digit drive is a positive-going signal which lasts for
200/20 clock pulses. The scan sequence is D (MSD), D ,
5
4
D , D , and D (LSD). All five digits are scanned even when
3
2
1
1
operating in the 3 / digit mode, and this scan is continuous
2
unless and OVER-RANGE occurs. Then all Digit drives are
blanked from the end of the STROBE sequence until the
beginning of Reference Integrate, at which time D will start
5
the scan again. This gives a blinking display as a visual
indication of OVER-RANGE.
BCD (PINS 20, 21, 22 AND 23)
The Binary coded decimal bit B , B , B , and B are positive
8
4
2
1
logic signals that go on simultaneously with the Digit driver.
9
ICL8052A/ICL71C03, ICL8068A/ICL71C03
INTEGRATOR
OUTPUT
AUTO
ZERO
10,001
/ 1,001
COUNTS
SIGNAL
INTEG.
10,000
REFERENCE
INTEGRATE
20,001 / 2,001
/ 1,000
COUNTS
COUNTS MAX
FULL MEASUREMENT CYCLE
40,002/4,002 COUNTS
BUSY
OVER-RANGE
WHEN APPLICABLE
UNDER-RANGE
WHEN APPLICABLE
EXPANDED SCALE BELOW
DIGIT SCAN
D
5
4
3
FOR OVER-RANGE
D
D
D
D
2
1
†FIRST D OF AZ AND REF INT
5
ONE COUNT LONGER
1000†/100 COUNTS
STROBE
SIGNAL
REFERENCE
INTEGRATE
INTEGRATE
AUTO ZERO
DIGIT SCAN
FOR OVER-RANGE
D
5
D
4
D
3
D
2
D
1
FIGURE 5. TIMING DIAGRAM FOR OUTPUTS
Component Value Selection
10,000(4-1/2 Digit)
1000(3-1/2 Digit)
× Clock Period × (20µA)
= -------------------------------------------------------------------------------------------------------------------------
For optimum performance of the analog section, care must
be taken in the selection of values for the integrator capacitor
and resistor, auto-zero capacitor, reference voltage, and
conversion rate. These values must be chosen to suit the
particular application.
C
INT
Integrator Output Voltage Swing
A very important characteristic of the integrating capacitor is
that it has low dielectric absorption to prevent roll-over or
ratiometric errors. A good test for dielectric absorption is to
use the capacitor with the input tied to the reference.
Integrating Resistor
This ratiometric condition should be read half scale 1.0000,
and any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at
reasonable cost. Polystyrene and polycarbonate capacitors
may be used in less critical applications.
The integrating resistor is determined by the full scale input
voltage and the output current of the buffer used to charge
the integrator capacitor. This current should be small
compared to the output short circuit current such that
thermal effects are kept to a minimum and linearity is not
affected. Values of 5µA to 40µA give good results with a
nominal of 20µA. The exact value may be chosen by:
Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system, with a larger value capacitor giving
less noise. The reference capacitor should be large enough
such that stray capacitance to ground from its nodes is
negligible.
Full Scale Voltage (See Note)
R
= ------------------------------------------------------------------------------
INT
20µA
NOTE: If gain is used in the buffer amplifier, then:
(BufferGain) (Full Scale Voltage)
R
= -------------------------------------------------------------------------------------------
INT
When gain is used in the buffer amplifier the reference
capacitor should be substantially larger than the auto-zero
capacitor. As a rule of thumb, the reference capacitor should
be approximately the gain times the value of the auto-zero
capacitor. The dielectric absorption of the reference cap and
auto-zero cap are only important at power-on or when the
circuit is recovering from an overload. Thus, smaller or
cheaper caps can be used here if accurate readings are not
required for the first few seconds of recovery.
20µA
Integrating Capacitor
The product of integrating resistor and capacitor is selected
to give 9V swing for full scale inputs. This is a compromise
between possibly saturating the integrator (at +14V) due to
tolerance buildup between the resistor, capacitor and clock
and the errors a lower voltage swing could induce due to
offsets referred to the output of the comparator. In general,
the value of C
is given by:
INT
10
ICL8052A/ICL71C03, ICL8068A/ICL71C03
10-50K
+15V -15V
100kΩ
-BUF IN BUF OUT -INT IN INT OUT
REF
OUT
8
7
1
10
BUFFER
9
11
INTEG.
14
COMP.
6
3
INT.
REF.
300pF
-
-
COMP
OUT
A1
+
A2
-
+
A3
10kΩ
ICL8068A
2
+
-1.2V
5
+BUF IN 13
-15V
+INT IN 12
1kΩ
TO ICL7104
FIGURE 6. ADDING BUFFER GAIN TO ICL8068A
bandwidth product of 300MHz. The comparator output
follows the integrator ramp with a 3µs delay, and at a clock
frequency of 160kHz (6µs period) half of the first reference
integrate clock period is lost in delay. This means that the
meter reading will change from 0 to 1 with 50µV input, 1 to 2
with 150µV, 2 to 3 at 250µV, etc. This transition at midpoint is
considered desirable by most users. However, if the clock
frequency is increased appreciably above 160kHz, the
instrument will flash “1” on noise peaks even when the input
is shorted.
Reference Voltage
The analog input required to generate a full scale output is:
= 2V
V
.
REF
IN
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. For this reason, it
is recommended that an external high quality reference be
used where ambient temperature is not controlled or where
high-accuracy absolute measurements are being made.
Buffer Gain
At the end of the auto-zero interval, the instantaneous noise
voltage on the auto-zero capacitor is stored and subtracted
from the input voltage while adding to the reference voltage
during the next cycle. The result of this is that the noise
voltage is effectively somewhat greater than the input noise
voltage of the buffer itself during integration. By introducing
some voltage gain into the buffer, the effect of the auto-zero
noise (referred to the input) can be reduced to the level of
the inherent buffer noise. This generally occurs with a buffer
gain of between 3 and 10. Further increase in buffer gain
merely increases the total offset to be handled by the auto-
zero loop, and reduces the available buffer and integrator
swings, without improving the noise performance of the
system. The circuit recommended for doing this with the
ICL8068A/ICL71C03 is shown in Figure 6.
For many dedicated applications where the input signal is
always on one polarity, the dealy of the comparator need not
be limitation. Since the non-linearity and noise do not
increase substantially with frequency, clock rates of up to
approximately 1MHz may be used. For a fixed clock
frequency, the extra count or counts caused by comparator
delay will be a constant and can be subtracted out digitally.
The minimum clock frequency is established by leakage on
the auto-zero and reference caps. With most devices,
measurement cycles as long as 10 seconds give no
measurable leakage error.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
1
40kHz, 33 / kHz, etc, should be selected. For 50Hz
3
2
rejection, oscillator frequencies of 250kHz, 166 / kHz,
ICL8052A vs ICL8068A
3
125kHz, 100kHz, etc. would be suitable. Note that 100kHz
(2.5 readings/second) will reject both 50Hz and 60Hz.
The ICL8052A offers significantly lower input leakage
currents than the ICL8068A, and may be found preferable in
systems with high input impedances. However, the
ICL8068A has substantially lower noise voltage, and is the
device of choice for systems where noise is a limiting factor,
particularly in low signal level conditions.
The clock used should be free from significant phase or
frequency jitter. A simple two-gate oscillator and one based
on CMOS 7555 timer are shown in the Applications section.
The multiplexed output means that if the display takes
significant current from the logic supply, the clock should
have good PSRR.
Max Clock Frequency
The maximum conversion rate of most dual-slope A/D
converters is limited by frequency response of the
comparator. The comparator in this circuit is no exception,
even though it is entirely NPN with an open-loop, gain-
11
ICL8052A/ICL71C03, ICL8068A/ICL71C03
The auto-zero cap should be 1µF for all scales and the
Applications
reference capacitor should be 1µF times the gain of the
buffer amplifier. At this value if the input leakages of the
8052A/8068A are equal, the droop effects will cancel giving
zero offset. This is especially important at high temperature.
Specific Circuits Using the 8068A/71C03
8052A/A71C03
1
Figure 7 shows the complete circuit for a 4 / digit
2
( 200mV full scale) A/D converter with LED readout using
the internal reference of the 8068A/52A. If an external
reference is used, the reference supply (pin 7) should be
connected to ground and the 300pF reference cap deleted.
The circuit also shows a typical RC input filter. Depending on
Some typical component values are shown in Table 1. For
1
3 / digit conversion, use 12kHz clock.
2
V++ = +15V, V+ = 5V, V- = -15V
1
1
Clock Freq. = 120kHz (4 / Digit) or 12kHz (3 / Digit)
2
2
TABLE 1.
the application, the time-constant of this filter can be made
1
faster, slower, or the filter deleted completely. The / digit
2
SPECIFICATION
Full Scale V
VALUE
UNITS
mV
LED is driven from the 7-segment decoder, with a zero
20
200
10
2000
IN
reading blanked by connecting a D signal to RBI input of
5
Buffer Gain
(RB1 + RB2)
-----------------------------------
RB2
100
(See
Note)
1
V/V
the decoder.
A voltage translation network is connected between the
comparator output of the 8068A/52A and the auto-zero input
of the 71C03. The purpose of this network is to assure that,
during auto-zero, the output of the comparator is at or near the
threshold of the 71C03 logic (+2.5V) while the auto-zero
R
C
C
C
V
100
0.22
1.0
10
100
0.22
1.0
100
0.22
1.0
kΩ
µF
µF
µF
mV
µV
INT
INT
AZ
capacitor is being charged to V
(+100mV for a 200mV
REF
10
1.0
REF
REF
instrument). Otherwise, even with 0V in, some reference
integrate period would be required to drive the comparator
output to the threshold level. This would show up as an
equivalent offset error. Once the divider network has been
selected, the unit-to-unit variation should contribute less than
a tenth of a count error. A second feature is the back-to-back
diodes, used to lower the noise. In the normal operating mode
they offer a high impedance and long integrating time
constant to any noise pulses charging the auto-zero cap. At
startup or recovery from an overload, their impedance is low
to large signals so that the cap can be charged up in one
auto-zero cycle. The buffer gain does not have to be set
precisely at 10 since the gain is used in both the integrate and
deintegrate phase. For scale factors other then 200mV the
gain of the buffer should be changed to give a 2V buffer
output. For 2.0000V full scale this means unity gain and for
20,000mV (1µV resolution) a gain of 100 is necessary. Not all
8068As can operate properly at a gain of 100 since their offset
should be less than 10mV in order to accommodate the auto-
zero circuitry. However, for devices selected with less than
10mV offset, the noise performance is reasonable with
approximately 1.5µV near full scale. On all scales less than
200mV, the voltage translation network should be made
adjustable as an offset trim.
10
100
10
1000
100
1
Resolution (4 / Digit)
1
2
NOTE: Comment on offset limitations above. Buffer gain does not
improve ICL8052A noise performance adequately.
12
ICL8052A/ICL71C03, ICL8068A/ICL71C03
+5V
150Ω
5
4
3
2
1
7447
150Ω
150Ω
a
b
c
d
e
f
4.7kΩ
B
1
2
3
B
B
B
4
g
RBI
ICL71C03
+5V
V+
1
BUSY 28
1
2
3
4
5
6
7
47kΩ
1
4 / / 3 /
(LSD) D 27
1
2
2
POLARITY
RUN/HOLD
COMP IN
D
D
D
26
25
24
2
3
4
1.0µF
-15V
V-
(MSB) B 23
8
ICL8068A
INT OUT 14
2 COMP OUT +BUFF IN 13
0.22µF
REFERENCE
REF. CAP. 1
REF. CAP. 2
ANALOG IN
ANALOG GND
CLOCK IN
B
B
22
21
20
4
2
1
10µF
-15V
1 V-
8
10kΩ
SIGNAL
INPUT
9
(LSB) B
300µF
36
kΩ
10
11
12
13
14
(MSD) D 19
5
3 REF CAP
+INT IN 12
0.1µF
STROBE 18
A-Z IN 17
4 REF BYPASS -INT IN 11
10
kΩ
100
kΩ
5 GND
-BUFF IN 10
UNDER-RANGE
OVER-RANGE
16
A-Z OUT
10µF
1kΩ
6 REF OUT
BUFF OUT
V++
9
8
300
kΩ
DIGITAL GND 15
90kΩ
10kΩ
CLOCK
IN
7 REF SUPPLY
-15V
120kHz = 3
READINGS/SEC
+15V
1
NOTE: For 3 / digit, tie pin 2 low and change clock to 12kHz.
2
1
FIGURE 7. ICL8052A (8068A)/71C03A 4 / DIGIT A/D CONVERTER
2
a
a
V+
+5V
POL
3kΩ
DM8880
PROG
A
g
g
0V
RBI BI D
+5V
HI VOLTAGE BUFFER DI 505
47kΩ
5kΩ
0.02µF
0.02
µF
2.5kΩ
0.02
µF
GATES
ARE
7409
0.02
µF
0.02
µF
POL
D
D
D
D
D
B
B
B
B
5
4
3
2
1
8
4
2
1
8052A/
8068A
71C03A
FIGURE 8. ICL8052A-8068A/71C03A PLASMA DISPLAY CIRCUIT
13
ICL8052A/ICL71C03, ICL8068A/ICL71C03
A suitable circuit for driving a plasma-type display is shown
driver circuit could be ganged to the one shown if required.
This would be useful if additional annunciators were needed.
in Figure 8. The high voltage anode driver buffer is made by
Dionics. The 3 AND gates and caps driving “Bl” are needed
for interdigit blanking of multiple-digit display elements, and
can be omitted if not needed. The 2K and 3K resistors set
the current levels in the display. A similar arrangement can
be used with “Nixie” tubes.
1
Figure 10 shows the complete circuit for a 4 /2 digit
( 2.000V) A/D, again using the internal reference of the
8052A/8068A.
Figure 11 shows a more complicated circuit for driving LCD
displays. Here the data is latched into the ICM7211 by the
STROBE signal and “Overrange” is indicated by blanking the
4 digits. A clock oscillator circuit using the ICM7555 CMOS
timer is shown. Some other suitable clock circuits are
suggested in Figures 12 and 13. The 2-gate circuit should
use CMOS gates to maintain good power supply rejection.
Nixie is a registered trademark of Burroughs Corporation.
Analog and Digital Grounds
Extreme care must be taken to avoid ground loops in the
layout of 8068A or 8052A/71C03A circuits, especially in high
sensitivity circuits. It is most important that return currents
from digital loads are not fed into the analog ground line.
Both of the above circuits have considerable current flowing
in the digital ground returns from drivers, etc. A
A problem sometimes encountered with the
8052A/68A/71C03 A/D is that of gross over-voltage applied
in the input. Voltage in excess of 2.000V may cause the
integrator output to saturate. When this occurs, the integrator
can no longer source (or sink) the current required to hold
the summing junction (Pin 11) at the voltage stored on the
auto zero capacitor. As a result, the voltage across the
integrator capacitor decreases sufficiently to give a false
voltage reading. This problem can also show up as large-
signal instability on overrange conditions. A simple solution
to this problem is to use junction FET transistors across the
integrator capacitor to source (or sink) current into the
summing junction and prevent the integrator amplifier from
saturating, as shown in Figure 14.
recommended connection sequence for the ground lines is
shown in Figure 9.
Other Circuits for Display Applications
Popular LCD displays can be interfaced to the Output of the
ICL71C03 with suitable display drivers, such as the
ICM7211A as shown in Figure 10. A standard CMOS 4000
1
series LCD driver circuit is used for displaying the / digit,
2
the polarity, and the “over-range” flag. A similar circuit can be
used with the ICM7212A LED driver. Of course, another full
REF
VOLTAGE
BUFF
OUT
EXTERNAL
REFERENCE
(IF USED)
ANALOG SUPPLY
BYPASS CAPACITORS
+15V
-15V
BUFF
-IN
(IF USED)
V
PIN 11
ICL71C03
AN GND
PIN 5
REF
I/P
FILTER
CAP
+
ICL8052A/68A
AN GND
V
C
IN
-
AZ
ANALOG
SUPPLY
RETURN
8068A PIN 2
COMPARATOR
BOARD
EDGE
DIGITAL
SUPPLY
RETURN
DIGITAL
LOGIC
DIG GND
ICL7104
PIN 2
DEVICE PIN
+5V SUPPLY BYPASS CAPACITOR(S)
FIGURE 9. GROUNDING SEQUENCE
14
ICL8052A/ICL71C03, ICL8068A/ICL71C03
1
4 / DIGIT LCD DISPLAY
2
28 SEGMENTS
- D
D
1
4
+5V
116 151412 5
CD4054A
3
2
4
6
BACKPLANE
7
8 1311 10 9
0V
ICM7211A
5 BP
ICL71C03
+5V
V+
1
2
BUSY 28
31 D
1
41/2 / 31/2
POL
D
D
D
D
B
B
B
B
D
27
26
25
24
23
22
21
20
19
1
2
3
4
8
4
2
1
5
32 D
2
3
33 D
34 D
3
4
R/H
4
2, 3, 4
6 - 26
37 - 40
COMP IN
V-
5
30 B
29 B
28 B
27 B
-15V
6
3
2
1
0
OPTIONAL
CAPACITOR
REF
7
+5V
OSC 36
V+ 1
REF. CAP. 1
REF. CAP. 2
INPUT
8
1µF
100kΩ
22-100pF
9
10
11
12
13
14
INPUT
35 V-
0.1µF
ANALOG GND
CLOCK
UR
STROBE 18
A-Z IN 17
+5V
0V
A-Z OUT 16
DIG GND 15
OR
0V
CLOCK IN (120kHz = 3 READINGS/SEC)
1.0µF
-15V
1
2
3
4
5
6
7
14
13
0.22µF
300µF
36kΩ
12
11
10
9
ICL8052A
8068A
300kΩ
100kΩ
-15V
5kΩ
10kΩ
+15V
8
10µF
ANALOG GND
FIGURE 10. DRIVING LCD DISPLAYS
15
ICL8052A/ICL71C03, ICL8068A/ICL71C03
+5V
1
4 / DIGIT LCD DISPLAY
2
28 SEGMENTS
- D
D
1
4
1
/
CD4030
2
BACKPLANE
ICM7211A
5 BP
+5V
ICL71C03(A)
2
V+
1
1
2
BUSY 28
1
1
CD4081
CD4071
/ CD4030
4
4 / / 3 /
2
D
D
D
D
B
B
B
B
D
27
26
25
24
23
22
21
20
19
1
2
3
4
8
4
2
1
5
31 D
32 D
1
2
POL
R/H
3
4
33 D
34 D
3
4
2, 3, 4
6 - 26
37 - 40
COMP IN
V-
5
-15V
6
30 B
29 B
28 B
27 B
3
2
1
OPTIONAL
REF
7
CAPACITOR
+5V
OSC 36
V+ 1
REF. CAP. 1
REF. CAP. 2
INPUT
8
1µF
100kΩ
22-100pF
9
0
CD4071
10
11
12
13
14
INPUT
0.1µF
35 V-
ANALOG GND
CLOCK
UR
STROBE 18
A-Z IN 17
0V
+5V
A-Z OUT 16
DIG GND 15
+5V
1
+5V
/
CD4030
4
OR
4.7kΩ
0V
0V
1
2
3
4
V-
V+
8
7
6
5
ICM7555
OUT
1.0µF
10 TO 15kΩ
ADJUST TO
= 120kHz
+5V
RESET
-15V
300µF
F
1
2
3
4
5
6
7
14
13
12
11
10
9
CL
0.22µF
100kΩ
300pF
36kΩ
ICL8052A
8068A
0V
300kΩ
-15V
+15V
5kΩ
10kΩ
8
10µF
ANALOG GND
1
FIGURE 11. 4 / DIGIT LCD DPM WITH DIGIT BLANKING ON OVERRANGE
2
16
ICL8052A/ICL71C03, ICL8068A/ICL71C03
+5V
16kΩ
1kΩ
56kΩ
2
3
8
+
7
0.22µF
LM311
1
-
30kΩ
4
f
= 0.45/RC
R
OSC
16kΩ
37.5kΩ
390pF
C
100pF
FIGURE 12. CMOS OSCILLATOR
FIGURE 13. LM311 OSCILLATOR
D
D
S
S
2N5461
2N5458
0.22µF
100K
+15V -15V
-BUF IN BUF OUT -INT IN INT OUT
REF
OUT
8
7
1
10
BUFFER
9
11
INTEG.
14
COMP.
6
3
INT.
REF.
300pF
-
-
COMP
OUT
A1
+
A2
-
REF
COMP
+
A3
8052A/
8068A
2
+
-1.2V
5
+BUF IN 13
+INT IN 12
TO ICL71C03
FIGURE 14. GROSS OVERVOLTAGE PROTECTION CIRCUIT
Circuits to interface the 71C03(A) directly with three popular
microprocessors are shown in Figures 17, 18 and 19. The
main differences in the circuits are that the IM6100 with its
12-bit word capability can accept polarity, over-range, under-
range, 4 bits of BCD and 5 digits simultaneously where the
8080/8048 and the MC6800 groups with 8-bit words need to
have polarity, over-range and under-range multiplexed onto
the Digit 5 word - as in the UART circuits. In each case the
microprocessor can instruct the A/D when to begin a
measurement and when to hold this measurement.
Interfacing with UARTs and
Microprocessors
Figure 15 shows a very simple interface between a free-
running 8068A/8052A/71C03A and a UART. The five
STROBE pulses start the transmission of the five data words.
The digit 5 word is 0000XXXX, digit 4 is 1000XXXX, digit 3 is
0100XXXX, etc. Also, the polarity is transmitted indirectly by
using it to drive the Even Parity Enable Pin (EPE). If EPE of
the receiver is held low, a parity flag at the receiver can be
decoded as a positive signal, no flag as negative. A complex
arrangement is shown in Figure 14. Here the UART can
instruct the A/D to begin a measurement sequence by a word
on RRI. The Busy signal resets the Data Ready Reset (DRR).
Again STROBE starts the transmit sequence. A quad 2 input
multiplexer is used to superimpose polarity, over-range, and
Application Notes
NOTE #
DESCRIPTION
AN016 “Selecting A/D Converters”
AN017 “The Integrating A/D Converter”
AN018 “Do’s and Don’ts of Applying A/D Converters”
AN023 “Low Cost Digital Panel Meter Designs”
under-range onto the D word since in this instance it is
5
known that B = B = B = 0.
2
4
8
For correct operation it is important that the UART clock be
fast enough that each word is transmitted before the next
STROBE pulse arrives. Parity is locked into the UART at
load time but does not change in this connection during an
output stream.
AN028 “Build an Auto-Ranging DMM Using the 8052A/7103A
A/D Converter Pair,” by Larry Goff
17
ICL8052A/ICL71C03, ICL8068A/ICL71C03
SERIAL OUTPUT
TO RECEIVING UART
TRO
UART
IM6402/3
EPE
1
TBRL
TBR
2
3
4
5
6
7
8
D
D
D
D
B
B
B
B
8
4
3
2
1
1
2
4
NC
D
STROBE
5
71C03/A
POL
RUN/HOLD
+5V
FIGURE 15. SIMPLE ICL71C03/71C03A TO UART INTERFACE
TRO
RRI
DRR
UART
IM6402/3
DR
EPE
1
TBRL
TBR
2
3
4
5
6
7
8
1Y
2Y
2A
3Y
ENABLE
3B
74C157
1A
3A SELECT 1B
2B
D
D
D
D
B
B
B
B
8
POL OVER UNDER
4
3
2
1
1
2
4
D
5
71C03/A
STROBE
RUN/HOLD
BUSY
+5V
10kΩ
100pF
FIGURE 16. COMPLEX ICL71C03/7103A TO UART INTERFACE
18
ICL8052A/ICL71C03, ICL8068A/ICL71C03
12
12
12
1
1
80C95
80C95
15
15
READ 1
IM6101
IM6100
D
D
D
D
D
B
B
B
B POL OVER
4 8
1
2
3
4
5
1
2
STROBE
RUN/HOLD
SENSE 1
WRITE 1
71C03/A
7
FIGURE 17. IM6100 TO ICL71C03A/71C03A INTERFACE
EN
1Y
2Y
PA0
PA1
PA2
PA3
74C157
EN
1Y
2Y
PA0
PA1
PA2
PA3
3Y
74C157
1B 2B 3BSEL1A 2A 3A
8080,
8085,
ETC.
3Y
1B 2B 3BSEL1A 2A 3A
8255
MC680X
OR
MCS650X
D
B
B
B
B
(MODE 1)
5
8
4
2
1
1
D
D
PA4
PA5
PA6
PA7
MC6820
71C03
D
B
B
B
B
D
D
2
3
4
5
8
4
2
1
D
D
RUN/
HOLD STROBE
PA4
PA5
1
2
71C03
D
D
PA6
PA7
STB PB0
A
RUN/
HOLD STROBE
3
4
CA1 CA2
FIGURE 18. ICL71C03 TO MC6800, MCS650X INTERFACE
FIGURE 19. ICL71C03 TO MCS-48, -80, -85 INTERFACE
19
ICL8052A/ICL71C03, ICL8068A/ICL71C03
ICL71C03 with ICL8052A/8068A Integrating A/D Converter Equations
The ICL71C03 does not have an internal crystal or RC
oscillator. It has a clock input only.
Integrator Output Voltage
(t
)(I
)
INT INT
V
= -------------------------------
INT
C
INT
Integration Period
10, 000
V
(Typ) = 9V
INT
t
= -------------------- (4-1/2 Digit)
INT
f
CLOCK
Output Count
1, 000
V
t
= -------------------- (3-1/2 Digit)
IN
INT
f
Count = 10, 000 × -------------- (4-1/2 Digit)
CLOCK
V
REF
Integration Clock Period
= 1/f
V
IN
Count = 1, 000 × -------------- (3-1/2 Digit)
t
V
CLOCK
CLOCK
REF
1
1
NOTE: The 4 / digit mode’s LSD will be output as a zero in the 3 /
2
60/50Hz Rejection Criterion
/t or t /t = Integer
2
digit mode.
t
INT 60Hz INT 50Hz
Output Type:
Optimum Integration Current
= 20µA
4 Nibbles BCD with Polarity and Over-range.
I
INT
Power Supply: 15V, +5V
Full Scale Analog Input Voltage
V++ = +15V
V- = -15V
V+ = +5V
V
(Typ) = 200mV to 2.0V = 2V
REF
INFS
Integrate Resistor
V
≅ 1.75V
REF
REF
If V
(BufferGain) × V
INFS
= ------------------------------------------------------------
not used, float output pin.
R
INT
I
INT
Auto Zero Capacitor Values
Integrate Capacitor
0.01µF < C < 1µF
AZ
(t
)(I
)
INT INT
C
= -------------------------------
Reference Capacitor Value
INT
V
INT
C
= (Buffer Gain) x C
AZ
REF
AUTO ZERO
(COUNTS)
INTEGRATE
DEINTEGRATE
(COUNTS)
(FIXED COUNT)
1
(4 / DIGIT)
2
30,001 - 10,001
3,001 - 1,001
10,000
1,000
1 - 20,001
1 - 2,001
1
(3 / DIGIT)
2
TOTAL CONVERSION TIME (t
)
CONV
(IN CONTINUOUS MODE)
1
t
= 40,002 * t
(4 / DIGIT MODE)
2
CONV
CLOCK
1
t
= 4,002 * t
(3 / DIGIT MODE)
CONV
CLOCK
2
FIGURE 20. INTEGRATOR OUTPUT
20
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N
E1
INDEX
AREA
INCHES
MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.735
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
18.66
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.775
-
4.95
0.558
1.77
0.355
19.68
-
-
A2
A
-C-
-
SEATING
PLANE
L
C
L
B1
C
8
D1
B1
-
eA
A1
A
D1
e
D
5
eC
B S
C
B
eB
D1
E
5
0.010 (0.25) M
C
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
14
14
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
dicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be perpen-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
21
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
AREA
1
2
3
N/2
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
BASE
PLANE
A2
A
-C-
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
35.1
5
eC
B S
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
B
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
28
28
JEDEC seating plane gauge GS-3.
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
22
ICL8052A/ICL71C03, ICL8068A/ICL71C03
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C
D
A - B
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
E
0.220
5.59
5
e
S
b
eA/2
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
C
A - B
D
aaa
C
A - B
D
S
M
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
14
14
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
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23
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