ISL99227BFRZ-T [INTERSIL]
ISL99227 with 3.3V compatible tri-state PWM input;
| 型号： | ISL99227BFRZ-T |
| 厂家： | 
Intersil |
| 描述： | ISL99227 with 3.3V compatible tri-state PWM input |
| 文件： | 总17页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Smart Power Stage (SPS) Module with Integrated High
Accuracy Current and Temperature Monitors
ISL99227, ISL99227B
Features
The ISL99227, ISL99227B are Smart Power Stages (SPS)
compatible with Intersil’s ISL68xxx/69xxx Digital Multiphase
(DMP) controllers and phase doubler (ISL6617A), respectively.
The ISL99227, ISL99227B have integrated high accuracy
current and temperature monitors that can be fed back to the
controller and doubler to complete a multiphase DC/DC
system. They simplify design and increase performance by
eliminating the DCR sensing network and associated thermal
compensation. Light-load efficiency is supported via a
dedicated LFET control pin. An industry leading thermally
enhanced 5x5 PQFN package allows minimal overall PCB real
estate.
• Input range: +4.5V to +18V
• Supports 60A DC current
• ISL99227 with 3.3V compatible tri-state PWM input
• ISL99227B with 5.0V compatible tri-state PWM input
• Downslope current sensing
• ±3% accuracy current monitor (IMON) with REFIN input
• 8mV/°C temperature monitor with OT flag
• Dedicated low-side FET control input
• Comprehensive fault protection for high system reliability
- High-side FET short and overcurrent protection
- Over-temperature protection
The ISL99227, ISL99227B feature a 3.3V compatible, 5.0V
compatible tri-state PWM input that, working together with
Intersil’s multiphase PWM controllers, will provide a robust
solution in the event of abnormal operating conditions. The
ISL99227, ISL99227B also improve system performance and
reliability with integrated fault protection of UVLO,
- V and V Undervoltage Lockout (UVLO)
CC
IN
• Open-drain fault reporting output
• Up to 2MHz switching frequency
over-temperature and overcurrent. An open-drain fault
reporting pin simplifies the handshake between SPS and
Intersil controllers and can be used to disable the controller
during start-up and fault conditions.
• Pb-free (RoHS compliant), 32 Ld 5x5 PQFN
Applications
• High frequency and high efficiency VRM and VRD
• Core, graphic and memory regulators for microprocessors
• High density VR for server, networking and cloud computing
• POL DC/DC converters and video gaming consoles
Related Literature
• TB363 “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
+12V
+5V
BOOT
PHASE
VIN
VCC
PVCC
LGCTRL
SHOOT-
THROUGH
PROTECTION
PWM
IMON
REFIN
PWM
CS#n
L
OUT
V
OUT
SW
ISL68xxx/
ISL69xxx
CONTROLLER
CSRTN#n
PVCC
TMON
SMART
CONTROL
TEMP
EN
FAULT#
C
OUT
ISL99227
GND
GND
GND
FIGURE 1. ISL99227 SIMPLIFIED APPLICATION BLOCK DIAGRAM
October 27, 2016
FN8684.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL99227, ISL99227B
Typical Application Circuit with ISL99227
+3.3V
VCCS
ISL99227
VCCS
VCC
5V
5V
VCC
PVCC
VIN
5V
LGCTRL
FAULT#
TMON
PWM
VIN
BOOT
PHASE
SW
TEMPVCORE
VSENVCORE
PWM1
CS1
RGNDVCORE
ENVCORE
IMON
CSRTN1
REFIN
GND
PGVCORE
ISL99227
ISL69127
5V
5V
VCC
PVCC
VIN
5V
LGCTRL
FAULT#
TMON
PWM
VIN
BOOT
PHASE
SW
VCORE
SVDATA
SVCLK
PWM2
CS2
IMON
nSVALERT
nVRHOT
REFIN
GND
CSRTN2
nPINALERT
PWM3-5
CS3-5
N PHASES
PMSDA
PMSCL
CSRTN3-5
nPMALERT
ISL99227
VCC
5V
5V
5V
PVCC
VIN
LGCTRL
FAULT#
TMON
PWM
VIN
CFP
BOOT
PHASE
SW
PWM6
CS6
VIN
IMON
CSRTN6
REFIN
GND
VINSEN
ISL99227
VCC
PVCC
VIN
5V
5V
5V
LGCTRL
FAULT#
TMON
PWM
VIN
BOOT
PHASE
SW
PGVSA
ENVSA
TEMPVSA
PWMVSA
CSVSA
IMON
RGNDVSA
VSENVSA
CSRTNVSA
REFIN
GND
VSA
VCCS
GND
ADDRESS
CONFIG
FIGURE 2. TYPICAL APPLICATION CIRCUIT WITH ISL99227 (ISL99227B 5V PWM IS NOT COMPATIBLE WITH ISL69127)
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ISL99227, ISL99227B
Typical Application Circuit with ISL99227B and ISL6617A
+3.3V
ISL99227B
5V
5V
VCC
PVCC
5V
VCCS
LGCTRL
PWM
VIN
VIN
BOOT
PHASE
SW
IMON
REFIN
TMON
FAULT#
VCCS
VCC
ISL6617A
PWMA
GND
CSENA
CSRTNA
VSENVCORE
RGNDVCORE
PWM
PWM1
CSRTNB
CSENB
ISL99227B
PWMB
5V
5V
VCC
PVCC
5V
ISL69128
LGCTRL
PWM
VIN
VIN
CS1
BOOT
PHASE
SW
IMON
REFIN
TMON
FAULT#
CSRTN1
GND
LOAD
PWM2-5
CS2-5
N PHASES
CSRTN2-5
TEMPVCORE
ENVCORE
ISL99227B
5V
5V
VCC
PVCC
5V
LGCTRL
PWM
VIN
VIN
BOOT
PHASE
SW
IMON
REFIN
TMON
FAULT#
ISL6617A
PWMA
GND
CSENA
CSRTNA
PWM6
PWM
CSRTNB
CSENB
ISL99227B
PWMB
5V
5V
VCC
PVCC
5V
LGCTRL
PWM
VIN
VIN
CS6
BOOT
PHASE
SW
IMON
CSRTN6
VCCS
REFIN
TMON
FAULT#
GND
FIGURE 3. TYPICAL APPLICATION CIRCUIT WITH ISL99227B (COMPATIBLE WITH ISL6617A 5V PWM OUTPUT)
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ISL99227, ISL99227B
Functional Block Diagram
PVCC
VIN
PHASE
BOOT
VIN
UVLO
VIN
POR
BOOT
SWITCH
CONTROL
HFET
OCH
CSH
-
2.5V
LDO
2.5V
+
90A
HS
GH
VCC-BOOT LEVEL
SHIFTER
VCC
POR
DRIVER
VCC
UVLO
VCC
GH_BLANK
CONTROL
20k
SW
V
PWM
UGH
-
PWMH
LOGIC
+
33.5k (for 3.3V)
16.5k (for 5.0V)
DEAD TIME AND
SHOO T-THRO UG H
LOGIC
V(T )
J
CAL
PWM
LFET
GL
-
AND
REFIN
IMON
PWML
100mV
PVCC
CSL
V
LGH
16.5k
+
LEV
SHFT
LS
AGND-PGND
LEVEL SHIFTER
DRIVER
HFET
SHORT
+
GL_BLANK
CONTROL
-
PHASE
GL
2.5V
OCH
V (T ) = 0.6V + 8mV * T
J
J
1µs
PULSE
OCH
OT
OT
V(T )
J
+
V(T
MAX
)
TEMP
SENSE
FAULT#
-
T
J
OR
FUNCTION
REFIN + 1.2V
+
-
VCC
POR
POR
VIN
LGCTRL TMON
NC
GND
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM
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ISL99227, ISL99227B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
CURRENT
RATING
PWM INPUT TAPE AND REEL
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
(°C)
(V)
3.3
3.3
3.3
5.0
(UNITS)
ISL99227IRZ-T
ISL99227HRZ-T
ISL99227FRZ-T
27I
-40 to +85
-10 to +100
-40 to +125
-40 to +125
60A
60A
60A
60A
3k
32 Ld 5x5 PQFN Double Cooling
32 Ld 5x5 PQFN Double Cooling
32 Ld 5x5 PQFN Double Cooling
32 Ld 5x5 PQFN Double Cooling
L32.5x5V
L32.5x5V
L32.5x5V
L32.5x5V
27H
27F
3k
3k
ISL99227BFRZ-T 27B
3k
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil plastic packaged products are RoHS compliant by EU exemption 7A and employ special Pb-free material sets, molding compounds/die
attach materials, and 100% matte tin plate plus anneal (e3) termination finish which is compatible with both SnPb and Pb-free soldering operations.
Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL99227, ISL99227B. For more information on MSL, please see tech
brief TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
CURRENT
RATING PWM THERMAL OCP
P2P
PART #
(A)
(V)
FLAG
FLAG IMON TMON
PACKAGE
COMPATIBLE
USED WITH
5.0V PWM POWER STAGE FAMILY
ISL99125B
ISL99135B
ISL99227B
25
35
60
5.0
5.0
5.0
No
No
No
No
No
No
No 24 Ld 3.5x5 QFN ISL99135B Analog Controllers: ISL633x, ISL636x, ISL637x,
ISL95829, ISL9585x
No 24 Ld 3.5x5 QFN ISL99125B
Digital Hybrid Controllers: ISL68201, ISL6388/98
Full Digital Controller: ZL8802
Phase Doublers: ISL6617, ISL6617A (see Figure 3 on
page 3)
Yes
Yes Yes
Yes 32 Ld 5x5 PQFN N/A
3.3V PWM POWER STAGE FAMILY
ISL99140
ISL99227
40
60
3.3
3.3
Yes
Yes
No
No
No 40 Ld 6x6 QFN
N/A
Full Digital Controllers: ISL68/69xxx (see Figure 2 on
page 2), ZL8802
Digital Hybrid Controllers: ISL68201, ISL6388/98
(3.3V PWM Setting)
Yes Yes
Yes 32 Ld 5x5 PQFN N/A
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ISL99227, ISL99227B
Pin Configuration
ISL99227, ISL99227B
(32 LD PQFN)
TOP VIEW
24
32 31 30 29 28 27 26 25
23 VIN
LGCTRL
VCC
1
2
3
4
5
6
7
8
VIN
34
GND
33
22
21
VIN
VIN
PVCC
GND
NC
GND
GND
GND
GND
20
19
18
17
GND
35
GND
GND
GND
9
10 11 12 13 14 15 16
Pin Descriptions
PIN #
PIN NAME
DESCRIPTION
1
LGCTRL Lower gate control signal input. LO = GL low (LFET off). HI = Normal operation (GL and GH strictly obey PWM). This pin should
be driven with a logic signal, or externally tied high if not required; it should NOT be left floating.
2
3
VCC
+5V logic bias supply. Place a high quality low ESR ceramic capacitor (~1µF/X7R) in close proximity from this pin to GND.
PVCC
+5V gate drive bias supply. Place a high quality low ESR ceramic capacitor (~1µF/X7R) in close proximity from this pin to
GND.
4, 6, 7, 8, 17,
18, 19, 20, 29
33, 35
GND
All GND pins are internally connected. Pins 4 and 29 should be connected directly to the nearby GND paddles on package
bottom. Figure 15 on page 14 shows GND paddles should be connected to the system GND plane with as many vias as
possible to maximize thermal and electrical performance.
5
NC
No connect (this is a low-side gate driver output (GL), optional to monitor for system debugging).
Switching junction node between HFET source and LFET drain. Connect directly to output inductor.
9, 10, 11, 12,
13, 14, 15, 16
SW
21, 22, 23, 27,
34
VIN
Input of power stage (to drain of HFET). Place at least 2 ceramic capacitors (10µF or higher, X5R or X7R) in close proximity
across VIN and GND. Pin 27 should NOT be used for decoupling. For optimal performance, place as many vias as possible
in the bottom side VIN paddle.
24
25
PHASE Return of boot capacitor. Internally connected to SW node so no external routing required for SW connection.
BOOT Floating bootstrap supply pin for the upper gate drive. Place a high quality low ESR ceramic capacitor (0.1µF~0.22µF/X7R)
in close proximity across BOOT and PHASE pins.
26
FAULT# Open-drain output pin. Any fault (overcurrent, over-temperature, shorted HFET, or POR/UVLO) will pull this pin to ground. This
pin may be connected to the controller Enable pin or used to signal a fault at the system level.
28
30
PWM
ISL99227: PWM input of gate driver, compatible with 3.3V tri-state PWM signal. ISL99227B for 5V PWM.
REFIN Input for external reference voltage for IMON signal. This voltage should be between 0.8V and 1.6V. Connect REFIN to the
appropriate current sense input of the controller. Place a high quality low ESR ceramic capacitor (~ 0.1µF) in close proximity
from this pin to GND.
31
32
IMON Current monitor output, referenced to REFIN. IMON will be pulled high (to REFIN + 1.2V) to indicate an HFET shorted or
overcurrent fault. Connect the IMON output to the appropriate current sense input of the controller. No more than 56pF
capacitance can be directly connected across IMON and REFIN pins. With a 100Ω series resistor, up to 470pF may be used.
TMON Temperature monitor output. For multiphase, the TMON pins can be connected together as a common bus; the highest voltage
(representing the highest temperature) will be sent to the PWM controller. TMON will be pulled high (to 2.5V) to indicate an
over-temperature fault. No more than 470pF total capacitance can be directly connected across the TMON and GND pins;
with a series resistor, a higher capacitance load is allowed, such as 1kΩ for 100nF load.
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ISL99227, ISL99227B
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC, PVCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Input Supply Voltage (VIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V
Thermal Resistance
32 Ld 5x5 PQFN
Double Cooling Package (Notes 4, 5, 7). . . .
(°C/W)
10.7
(°C/W)
4
JA
JC
PHASE, SW Voltage (V
V
). . . . . . . . . . . . . . . . . . -0.3V to 25V
PH-GND, SW-GND
GND - 10V (<20ns Pulse Width, 10µJ)
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 36V
Other I/O Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
BOOT Voltage (V
BOOT-GND
ESD Ratings
Human Body Model (Tested per JEDEC-JS-001-2014) . . . . . . . . . . .2.5kV
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 250V
Latch-Up (Tested per JESD-78E; Class 2, Level A). . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Operating Junction Temperature Range
IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
FRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage, V , PVCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
CC
Input Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V
IN
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on an Intersil SPS evaluation board. Refer to Tech Brief TB379 for general thermal metric
JA
info.
5. For , the “case temp” location is the center of the package underside.
JC
Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating
temperature range, T = -40°C to +125°C.
J
MIN
MAX
PARAMETER
POWER RATING
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNIT
Maximum Instant Power Dissipation
Maximum Continuous Power Dissipation
THERMAL RESISTANCE
T
= +25°C, 150A, (Note 7)
100
W
W
A
T
= +25°C, = 10°C/W, T = +150°C, (Note 7)
JA
12.5
A
J
Thermal Resistance Junction to PCB
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient
VCC SUPPLY CURRENT
Intersil SPS evaluation board, (Note 7)
5.2
10.7
9.3
°C/W
°C/W
°C/W
JB
JA
JA
Intersil SPS evaluation board, (Note 7), 0 LFM
Intersil SPS evaluation board, (Note 7), 400 LFM
Logic Standby Current
IVCC
IPVCC
IVCC
PWM = Open
PWM = Open
PWM = 300kHz
PWM = 300kHz
4.75
100
4.75
15
mA
µA
Gate Drive Standby Current
Logic Operational Current
mA
mA
Gate Drive Operational Current
POWER-ON RESET AND ENABLE
VCC Rising POR Threshold
VCC Falling POR Threshold
VCC POR Hysteresis
IPVCC
3.86
3.58
280
125
4.0
4.20
V
V
3.20
3.4
mV
µs
V
VCC POR Delay to Operation
VIN Rising POR Threshold
197
4.2
VIN Falling POR Threshold
VIN POR Hysteresis
3.5
V
445
mV
3.3V PWM INPUT FOR ISL99227 (See “TIMING DIAGRAM” Figure 5 on page 9)
Sink Impedance
33.5
16.5
kΩ
kΩ
Source Impedance
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ISL99227, ISL99227B
Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating
temperature range, T = -40°C to +125°C. (Continued)
J
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
1.11
0.87
2.13
1.95
(Note 6) UNIT
Tri-State Lower Gate Falling Threshold
Tri-State Lower Gate Rising Threshold
Tri-State Upper Gate Rising Threshold
Tri-State Upper Gate Falling Threshold
Tri-State Shutdown Window
V
V
V
V
V
= 5V
= 5V
= 5V
= 5V
= 5V
V
V
V
V
CC
CC
CC
CC
CC
1.3
1.8
V
5V PWM INPUT FOR ISL99227B (See “TIMING DIAGRAM” on Figure 5 on page 9)
Sink Impedance
16.5
16.5
1.51
1.14
3.24
3.02
kΩ
kΩ
V
Source Impedance
Tri-State Lower Gate Falling Threshold
Tri-State Lower Gate Rising Threshold
Tri-State Upper Gate Rising Threshold
Tri-State Upper Gate Falling Threshold
Tri-State Shutdown Window
V
V
V
V
V
= 5V
= 5V
= 5V
= 5V
= 5V
CC
CC
CC
CC
CC
V
V
V
1.6
2.8
V
SWITCHING TIME
GH Turn-On Propagation Delay
GH Turn-Off Propagation Delay
GL Turn-On Propagation Delay
GL Turn-Off Propagation Delay
GL Exit Tri-State Propagation Delay
GH Exit Tri-State Propagation Delay
PWML to Tri-State Shutdown Hold-Off Time
PWMH to Tri-State Shutdown Hold-Off Time
CURRENT MONITOR
t
See Figure 5 (GL Low to GH High)
See Figure 5 (PWM Low to GH Low)
See Figure 5 (GH Low to GL High)
See Figure 5 (PWM High to GL Low)
See Figure 5 (Tri-state to GL High)
See Figure 5 (Tri-state to GH High)
See Figure 5 (PWM Low to GL Low)
See Figure 5 (PWM High to GH Low)
8
ns
ns
ns
ns
ns
ns
ns
ns
PDHU
t
t
40
8
PDLU
PDHL
t
23
25
35
40
50
PDLL
t
PDTSL
PDTSU
t
t
TSSHDL
TSSHDU
t
REFIN Voltage Range
0.8
1.2
±2
1.6
V
%
%
%
ns
A
IMON Current Gain Accuracy
(Intersil SPS Validation Board, V = 5V)
10A, T = +90°C
J
CC
≥10A, T = +40°C to +125°C
±3
J
≥10A, T = +20°C to +125°C
±4
J
Downslope Blanking Time
HFET Overcurrent Trip
160
90
V
= 5V
CC
IMON-REFIN at OCP
1.1
1.2
1.3
V
TEMPERATURE MONITOR
Over-Temperature Rising Threshold
Over-Temperature Falling Threshold
Over-Temperature Hysteresis
Temperature Coefficient
TMON Voltage at +25°C Temperature
TMON High at Over-Temperature
FAULT PIN
140
125
15
°C
°C
°C
8
mV/K
V
V (T ) = 0.6V + (8mV*T )
0.80
2.5
J
J
2.3
2.7
V
Output Low Voltage
5mA
0.18
16
0.26
V
Leakage Current
nA
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ISL99227, ISL99227B
Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply across the operating
temperature range, T = -40°C to +125°C. (Continued)
J
MIN
MAX
PARAMETER
BOOTSTRAP DIODE
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6) UNIT
Forward Voltage Drop
ON-Resistance
5mA
0.09
16
V
R
Ω
F
LGCTRL PIN
Rising Threshold
Falling Threshold
MOSFETs
Logic high; (normal: obeys PWM)
Logic low; (forces GL low; LFET off)
1.29
1.01
1.60
V
V
0.70
High-Side MOSFET (HFET) r
3.84
0.76
mΩ
mΩ
DS(ON)
Low-Side MOSFET (LFET) r
DS(ON)
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. These ratings vary with PCB layout and operating condition, and limited by SPS temperature and thermal shutdown trip point.
PWM
t
t
PDLU
PDHU
t
TSSHDU
t
PDTSU
t
PDTSL
t
FU
GH
GL
t
RU
t
PDHL
t
RL
t
FL
t
t
TSSHDL
PDLL
t
t
PDUFLR
PDLFUR
FIGURE 5. TIMING DIAGRAM (INTERNAL SIGNALS)
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ISL99227, ISL99227B
Typical Performance Characteristics PVCC = 5V, T = +25°C, unless otherwise stated.
A
98
96
94
92
90
88
86
84
82
80
98
96
94
92
90
88
86
84
82
80
Exclude 5V Losses
Include 5V Losses
Exclude 5V Losses
Include 5V Losses
0
30
60
90
120 150 180 210 240
0
30
60
90
120 150 180 210 240
LOAD (A)
LOAD (A)
FIGURE 7. 1.2V V
OUT
POWER STAGE EFFICIENCY (V = 12V;
IN
FIGURE 6. 1.8V V
OUT
POWER STAGE EFFICIENCY (V = 12V;
IN
f
= 500kHz; L = 0.18µH/0.17mΩ/FP1008-180-R;
f
= 500kHz; L = 0.18µH/0.17mΩ/FP1008-180-R;
SW
OUT
SW
OUT
AUTO-PHASE ENABLED IN 6-PHASE OPERATION)
AUTO-PHASE ENABLED IN 6-PHASE OPERATION)
96
94
92
90
88
86
84
82
80
96
94
92
90
88
86
84
82
80
0.80V
0.90V
1.00V
1.20V
1.35V
1.50V
1.80V
2.50V
400kHz
500kHz
600kHz
700kHz
800kHz
0
10
20
30
40
50
60
0
10
20
30
40
50
60
LOAD (A)
LOAD (A)
FIGURE 8. POWER STAGE EFFICIENCY (V = 12V; f
IN
= 500kHz;
FIGURE 9. POWER STAGE EFFICIENCY (V = 12V; V
IN
= 1.8V;
SW
OUT
L
= 0.18µH/0.17mΩ/FP1008-180-R; INCLUDE
L
= 0.18µH/0.17mΩ/FP1008-180-R; INCLUDE
OUT
OUT
INDUCTOR AND ISL99227, ISL99227B LOSSES)
INDUCTOR AND ISL99227, ISL99227B LOSSES)
16
14
12
10
8
14
12
10
8
400kHz
500kHz
600kHz
700kHz
800kHz
0.80V
0.90V
1.00V
1.20V
1.35V
1.50V
1.80V
2.50V
6
6
4
4
2
2
0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
LOAD (A)
LOAD (A)
FIGURE 10. ISL99227, ISL99227B POWER DISSIPATION (V = 12V;
IN
FIGURE 11. ISL99227, ISL99227B POWER DISSIPATION (V = 12V;
IN
f
= 500kHz; L
= 0.18µH/0.17mΩ/FP1008-180-R)
V = 1.8V; L
= 0.18µH/0.17mΩ/FP1008-180-R)
SW
OUT
OUT OUT
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ISL99227, ISL99227B
Tri-State PWM Input
Operation
The ISL99227 supports a 3.3V PWM tri-level input and is
compatible with Intersil’s digital multiphase controllers as well
as other control IC’s utilizing 3.3V PWM logic. Use the ISL99227B
for 5V PWM logic, like ISL6617A doubler with 5V PWM logic
output (see Table 1 on page 5). Should the pin be pulled into and
remain in the tri-state window for a set hold-off time, the driver
will force both MOSFETs to their off states. When the PWM signal
moves outside the shutdown window, the driver immediately
resumes driving the MOSFETs according to the PWM commands.
The ISL99227, ISL99227B are optimized drivers and power
stage solutions for high density synchronous DC/DC power
conversion. They include high performance GH and GL drivers, an
NFET controlled to function as a bootstrap diode and MOSFET
pair optimized for high switching frequency buck voltage
regulators. They also include advanced power management
features listed as follows:
1. Accurate current and thermal reporting outputs.
2. Fault protections of HFET overcurrent, HFET short,
over-temperature, VCC UVLO and VIN UVLO.
This feature is utilized by Intersil’s PWM controllers as a method
of forcing both MOSFETs off. Should the PWM input be left
floating, the pin will be pulled into the tri-state window internally
and thus force both MOSFETs to a safe off state.
Power-On Reset (POR)
During initial start-up, the V voltage rise is monitored. Once the
rising V voltage exceeds 3.86V (typical) for 125µs, then normal
CC
operation of the driver is enabled. The PWM signals are passed
through to the gate drivers, the TMON output is valid and the
IMON-REFIN output starts at zero, and becomes valid on the first
CC
Although the PWM input can sustain a voltage as high as V
the ISL99227 is not compatible with a controller (such as the
ISL63xx family) that actively drives its mid-level in tri-state higher
than 1.7V.
,
CC
GL signal. If V drops below the falling threshold of 3.58V
(typical), operation of the driver is disabled. The PVCC voltage is
CC
Bootstrap Function
The ISL99227, ISL99227B feature an internal NFET that is
controlled to function as a bootstrap diode. A high quality
ceramic capacitor should be placed in close proximity across the
BOOT and PHASE pins. The bootstrap capacitor can range
between 0.1µF~0.22µF (0402~0603 and X5R~X7R) for normal
buck switching applications.
not monitored as it should to be from the same supply as V
.
CC
V
POR is also monitored. When both V and V reach above
CC IN
IN
their POR trip points, it enables HFET overcurrent protection.
Both V and V POR are gated to the FAULT# pin, which goes
CC IN
high once both V and V are above their POR levels after
CC IN
125µs and no other faults occur.
Current Monitoring
Shoot-Through Protection
LFET current is monitored and a signal proportional to that
current is the output on the IMON pin (relative to the REFIN pin).
The IMON and REFIN pins should be connected to the appropriate
current sense input pin of the controller. This method does not
Prior to POR, the undervoltage protection function is activated
and both GH and GL are held active low (HFET and LFET off). After
POR (the Rising Thresholds; see “Electrical Specifications” on
page 8) and a 125µs delay, the PWM and LGCTRL signals are
used to control both high-side and low-side MOSFETs, as shown
in Table 2.
require external R
or DCR sensing of the inductor current.
SENSE
Figure 12 depicts the low-side current sense concept. After the
falling edge of the PWM, there are two delays; one that
represents the expected propagation delay from PWM to GH/SW
and a second blanking delay to allow time for the transition to
settle; typical total time is ~350ns. The IMON output
The ISL99227, ISL99227B’s dead time control is optimized for
high efficiency and guarantees that simultaneous conduction of
both FETs cannot occur.
approximates the actual I waveform.
L
Should the driver have no bias voltage applied (either V or
CC
PVCC missing) and be unable to actively hold the MOSFETs off,
an integrated 20kΩ resistor from the upper MOSFET
IL x IMONGAIN
gate-to-source will aid in keeping the HFET device in its off state.
This can be especially critical in applications where the input
IMON
voltage rises prior to the ISL99227, ISL99227B V and PVCC
CC
supplies.
SW
TABLE 2. GH AND GL OPERATION TRUTH TABLE
PWM
LGCTRL
GH
0
GL
0
HFET, LFET
Both off
LFET on
HFET on
LFET off
HFET on
COMMENT
GL
GH
3-state
X
1
1
0
0
PWM
0
1
0
1
0
1
Normal
Normal
GL low
Normal
1
0
ONdly
OFFdly
0
0
FIGURE 12. LFET CURRENT SAMPLE DIAGRAM
1
0
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ISL99227, ISL99227B
The HFET current is NOT monitored in the same way, so no valid
Shorted HFET Protection
measured current is available while PWM is high (including the
short delays before and after). During this time, the IMON will
output the last valid LFET current before the sampling stopped.
On start-up after POR, the IMON will output zero (relative to
REFIN, which represents zero current) until the switching begins
and then the current can be properly measured.
In case of a shorted HFET, the SW node will have excessive
positive voltage present even when the LFET is turned on. The
ISL99227, ISL99227B monitor the SW node during periods when
the LFET is on (GL is high) and should that voltage exceed 100mV
(typical), the HFET short fault is declared. The ISL99227,
ISL99227B will pull the IMON pin high and the FAULT# will be
pulled low. However, the fault will be latched; VCC POR is needed
to reset it. GH will be gated low (ignore PWM = high), thus the
ISL99227, ISL99227B will still respond to PWM tri-state and
logic low.
The high-side FET current is separately monitored for OC
conditions; see the following “Overcurrent Protection” section.
Overcurrent Protection
Figure 13 shows the timing diagram of an overcurrent fault.
There is a comparator monitoring the HFET current while it is on
Thermal Monitoring
(GH high; also requires V POR above its trip point). If the current
The ISL99227, ISL99227B monitor their internal temperature
and provides a signal proportional to that temperature on the
TMON pin. TMON has a voltage of 600mV at 0°C and reflects
temperature at 8mV/°C. The TMON output is valid 125µs after
VCC POR.
IN
is higher than 90A (typical; not user-programmable), then an OC
fault is detected. The GH will be forced low, even if PWM is still
high; this effectively shortens the PWM (and GH) pulse width, to
limit the current. The IMON pin is pulled up to REFIN + 1.2V,
which will be detected by the controller as an overcurrent fault.
The controller is then expected to force PWM to tri-state (gates
off both FETs), which signals the SPS that the fault has been
acknowledged. The fault clears ~1µs after PWM enters tri-state.
The IMON flag is released after the delay. The driver will then
normally respond to the PWM inputs. If the PWM tri-state signal
is not received after the fault, then the fault stays asserted and
the IMON pin remains high.
TMON PIN
600mV+8mV/C* TEMP
FAULT
OVER-TEMP
REPORTING
Note that if the controller does NOT acknowledge, the IMON flag
will stay high indefinitely, which will also hold GH low.
CONFIGURATION
If OC is detected, the FAULT# pin is also pulled low; the timing on
the FAULT# pin will follow that of the IMON pin.
FIGURE 14. OVER-TEMPERATURE FAULT
ILIM
Figure 14 shows a simplified functional representation. The top
section includes the sensor and the output buffer. The bottom
section includes the protection sensing that will pull the output
high. The TMON pin is configured internally such that a user can
tie multiple pins together externally and the resulting TMON bus
will assume the voltage of the highest contributor (representing
the highest temperature).
HFET
CURRENT
0
No GH allowed
GH
Follow PWM low to
support OV following
OC
GL
Thermal Protection
DMP enters PWM
Should the internal temperature exceed the over-temperature
trip point (+140°C typical), the TMON pin will be pulled high (to
~2.5V), and the FAULT# pin will be pulled low. No other action is
taken on-chip. Both the TMON and FAULT# pins will remain in the
fault mode until the junction temperature drops below +125°C
(typical); at that point, the TMON and FAULT# pins resume normal
operation.
mid-state to
acknowledge fault
PWM
IMON - REFIN
FAULT#
1.2V
RESUME NORMAL OP
(IF RECOVERS)
FAULT CLEAR
DELAY 1µs
FIGURE 13. OVERCURRENT FAULT TIMING DIAGRAM
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ISL99227, ISL99227B
FAULT Reporting
PCB Layout Considerations
Proper PCB layout will reduce noise coupling to other circuits,
improve thermal performance and maximize the efficiency. The
following is meant to lead to an optimized layout:
Overcurrent and shorted HFET detections will pull the IMON pin to
a high (fault) level, such that the PWM controller should quickly
recognize it as out of the normal range. Over-temperature
detection will pull the TMON pin to a high (fault) level, such that
the PWM controller should quickly recognize it as out of the
normal range.
• Place multiple 10µF or greater ceramic capacitors directly on
the device between VIN and GND as indicated in Figure 15 on
page 14. This is the most critical decoupling and reduced
parasitic inductance in the power switching loop. This will
reduce overall electrical stress on the device as well as reduce
coupling to other circuits. Best practice is to place the
decoupling capacitors on the same PCB side as the device. For
a design with tight space requirements, these decoupling
capacitors can be placed under the device, i.e., bottom layer,
as shown in Figure 17 on page 15.
All of the above faults, plus the VCC and VIN POR (UVLO)
conditions, will also pull down the FAULT# pin. This can be used
by the controller (or system) as a fault detection and can also be
used to disable the controller through its Enable pin.
The fault reporting and respective SPS response are summarized
in Table 3.
TABLE 3. FAULT REPORTING SUMMARY
• Connect GND to the system GND plane with a large via array as
close to the GND pins as design rules allow. This improves
thermal and electrical performance.
FAULT
EVENT
OC
IMON
HIGH
TMON FAULT#
RESPONSE
N/A
LOW GH gated off. The controller
should acknowledge and force its
PWM to tri-state to keep both
HFET and LFET off. The fault is
cleared ~1µs after PWM enters
tri-state, otherwise, it stays
• Place PVCC, VCC and BOOT-PHASE decoupling capacitors at
the IC pins as shown in Figure 15 on page 14.
• Note that the SW plane connecting the ISL99227, ISL99227B
and inductor must carry full load current and will create
resistive loss if not sized properly. However, it is also a very
noisy node that should not be oversized or routed close to any
sensitive signals. Best practice is to place the inductor as close
to the device as possible and thus minimizing the required
area for the SW connection. If one must choose a long route of
either the VOUT side of the inductor or the SW side, choose the
quiet VOUT side. Best practice is to locate the ISL99227,
ISL99227B as close to the final load as possible and thus
avoid noisy or lossy routes to the load.
asserted. (If system OVP occurs,
the controller may send PWM low
to turn on LFET).
Shorted IMON
HFET Latched
HIGH
N/A
FAULT# GH gated off, until fault latch is
Latched cleared by VCC POR. GL follows
LOW PWM.
OT
N/A
HIGH
LOW GH and GL follow PWM.
VCC
IMON-
TMON
Not
Valid
LOW Switching stops while in UVLO.
Once above VCC POR, after
125µs: GH and GL follow PWM;
the FAULT# pin is released; TMON
is valid; IMON-REFIN is valid after
GL first goes low.
• The IMON and IREF network and their vias should not sit on the
top of the VIN plane, a keep out area is recommended, as
shown in Figure 17 on page 15.
UVLO REFIN =
0V
• The PCB is the best thermal heatsink material than any top
side cooling materials. The PCB always has enough vias to
connect VIN and GND planes. Insufficient vias will yield lower
efficiency and very poor thermal performance.
VIN
UVLO
OC not
valid
N/A
LOW GH and GL follow PWM.
Figures 16 and 17 show a multiphase PCB layout example for
dual footprint, a device compatible with ISL99227. For a
reference design file, please contact Intersil’s Application
support at www.intersil.com/en/support.html.
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ISL99227, ISL99227B
TABLE 4. AVAILABLE EVALUATION BOARDS
PEAK EFFICIENCY
(%)
SMBus/
PMBus/I C
2
EVALUATION BOARDS
ISL69127-61P-EV1Z
ISL69125-31P-EV2Z
DESCRIPTION
95.7% at 60A
94.5% at 30A
Yes
Yes
6+1 Dual Output VR13 Evaluation Board for V
and VSA Applications
CORE
3+1 Dual Outputs DDR4 Evaluation Board for VR13 Memory Applications
FIGURE 15. SINGLE-PHASE PCB LAYOUT FOR MINIMIZING CURRENT LOOPS
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ISL99227, ISL99227B
FIGURE 16. MULTIPHASE PCB LAYOUT EXAMPLE TOP LAYER FOR DUAL FOOTPRINT, A DEVICE COMPATIBLE WITH ISL99227
FIGURE 17. MULTIPHASE PCB LAYOUT EXAMPLE BOTTOM LAYER
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ISL99227, ISL99227B
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN8684.2
CHANGE
October 27, 2016
Updated Ordering Information table on page 5 to show all Released parts.
Added “for dual footprint, a device compatible with ISL99227” on page 13
Updated Figures 16 and 17 for dual footprint on page 15
September 28, 2016
August 30, 2016
FN8684.1
FN8684.0
Updated POD to revision 2 which added additional dimensions to the typical recommended land pattern
and bottom views, and eliminated Note 6 which repeated the sentiments in the first line of Note 5.
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL99227, ISL99227B
For the most recent package outline drawing, see L32.5x5V.
Package Outline Drawing
L32.5x5V
32 LEAD DOUBLE COOLING QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2 9/16
SEE DETAIL “X”
2X
MILLIMETERS
0.10 C A
A
0.08 C
7
A
D
SYMBOL
MIN
0.56
0.00
NOM
0.61
MAX
0.66
0.05
PIN 1 INDEX AREA
A1
A2
5
A (Note 7)
A1
-
A2
0.20 REF.
0.25
b (Note 4)
0.20
0.30
D
5.00 BSC
1.50
Q2
Q1
P2
D2-1
1.45
1.95
4.25
1.55
2.05
4.35
E
D2-2
2.00
D2-3
4.30
e
0.50 BSC
5.00 BSC
1.15
E
B
E2-1
1.10
1.80
1.10
1.20
1.90
1.20
E2-2
1.85
C
P1
E2-3
1.15
SIDE VIEW
TOP VIEW
K1
0.55 BSC
0.15 BSC
0.40
K2
8
(Nd4-1)x e
REF.
L
L1
0.35
0.25
3.95
0.75
2.05
1.30
0.45
0.35
4.05
1.15
2.15
1.40
0.30
0.2 REF
D2-2
0.2
C
P1
4.00
D2-1
0.2
0.00 MIN
0.05 MAX
5
P2
-
PIN 1
Q1
2.10
L
INDEX AREA
DETAIL "X"
Q2
1.35
1
23
N (Note 3)
Nd1 (Note 3)
Nd2 (Note 3)
Nd3 (Note 3)
Nd4 (Note 3)
32
E2-1
8 (PIN1~PIN8)
8 (PIN9~PIN16)
7 (PIN17~PIN23)
9 (PIN24~PIN32)
3.25
e
2.950
NOTES:
8
17
1.50
1. Use millimeters as the primary measurement.
L
2. Dimensioning and tolerances conform to
ASME Y14.5M-1994.
(Nd2-1)x e
REF.
D2-3
0.20
3. N is the number of terminals.
L
L1
Nd1 and Nd3 is the number of terminals in Y-direction
and Nd2 and Nd4 is the number of terminals in
X-direction.
BOTTOM VIEW
(4.80)
(4.00)
4. Dimension b applies to plated terminal and is
measured between 0.20mm and 0.25mm from
terminal tip.
(22x 0.60)
(2.00)
(0.40)
5. The configuration of the pin #1 identifier is optional,
but must be located within the zone indicated. The pin
#1 identifier may be either a mold or mark feature.
(32x 0.204)
(1.50)
(1.325)
6. Package warpage MAX 0.08mm.
(2x 1.15)
(0.40)
(0.25)
7. Applied only for terminals.
(3x 3.50)
(4.80)
8. Tiebar shown (if present) is a non-functional feature.
(1.35)
(0.70)
(1.85)
(2.075)
(27x 0.50)
(1.25)
(3.00)
(3.75)
TYPICAL RECOMMENDED LAND PATTERN
FN8684.2
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