ISL9G1260EG3 [ETC]
TRANSISTOR | IGBT | N-CHAN | 600V V(BR)CES | 20A I(C) | TO-247 ; 晶体管| IGBT | N -CHAN | 600V V（ BR ） CES | 20A I（C ） | TO- 247\n
| 型号： | ISL9G1260EG3 |
| 厂家： | 
ETC |
| 描述： | TRANSISTOR | IGBT | N-CHAN | 600V V(BR)CES | 20A I(C) | TO-247
|
| 文件： | 总11页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
Data Sheet
January 2001
File Number 5019
600V, SMPS II LGC Series N-Channel IGBT
Features
[ /Title
(ISL9
G1260
EG3,
ISL9G
1260E
P3,
ISL9G
1260E
S3)
The ISL9G1260EG3, ISL9G1260EP3 and ISL9G1260ES3
are Low Gate Charge (LGC) SMPS II IGBTs combining the
fast switching speed of the SMPS IGBTs with lower gate
charge and avalanche capability (UIS). These LGC devices
shorten delay times, and reduce the power requirement of
the gate drive. These devices are ideally suited for high
voltage switched mode power supply applications where low
conduction loss, fast switching times and UIS capability are
essential. SMPS II LGC devices have been specially
designed for:
• >100kHz Operation at 390V,12A
• 200kHz Operation at 390V, 9A
• 600V Switching SOA Capability
o
• Typical Fall Time. . . . . . . . . . . . . . . . . .72ns at T = 125 C
J
• Low Gate Charge. . . . . . . . . . . . . . . . .23nC at V = 15V
GE
• UIS Rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150mJ
• Low Conduction Loss
Symbol
• Power Factor Correction (PFC) Circuits
• Full Bridge Topologies
• Half Bridge Topologies
• Push-Pull Circuits
• Uninterruptible Power Supplies
• Zero Voltage and Zero Current Switching Circuits
/Subjec
t
C
(600V,
SMPS
II LGC
Series
N-
Chann
el
IGBT)
/Autho
r ()
/Keyw
ords
(Intersi
l
Corpor
ation,
semico
nducto
r,
G
Formerly Developmental Type TA49367.
E
Ordering Information
PART NUMBER
ISL9G1260EG3
ISL9G1260EP3
ISL9G1260ES3
PACKAGE
BRAND
G1260EG3
TO-247
TO-220AB
TO-263AB
G1260EP3
G1260ES3
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the TO-263AB variant in tape and reel, e.g.,
ISL9G1260ES3T.
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
E
C
G
E
C
G
COLLECTOR
(FLANGE)
COLLECTOR
(FLANGE)
600V,
SMPS
II LGC
Series
N-
JEDEC TO-263AB
COLLECTOR
(FLANGE)
G
E
Chann
el
IGBT,
INTERSIL CORPORATION IGBT PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS
4,364,073
4,598,461
4,682,195
4,803,533
4,888,627
4,417,385
4,605,948
4,684,413
4,809,045
4,890,143
4,430,792
4,620,211
4,694,313
4,809,047
4,901,127
4,443,931
4,631,564
4,717,679
4,810,665
4,904,609
4,466,176
4,639,754
4,743,952
4,823,176
4,933,740
4,516,143
4,639,762
4,783,690
4,837,606
4,963,951
4,532,534
4,641,162
4,794,432
4,860,080
4,969,027
4,587,713
4,644,637
4,801,986
4,883,767
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified
C
ALL TYPES
UNITS
Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BV
600
V
CES
Collector Current Continuous
o
At T = 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
50
20
A
A
A
V
V
C25
o
At T = 110 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
C110
Collector Current Pulsed (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
108
CM
GES
GEM
Gate to Emitter Voltage Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
20
Gate to Emitter Voltage Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
o
30
Switching Safe Operating Area at T = 150 C, Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . SSOA
J
60A at 600V
150mJ at 12A
100mJ at 12A
167
o
Single Pulse Avalanche Energy at T = 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
C
Singlle Pulse Reverse Avalanche Energy at T = 25 C . . . . . . . . . . . . . . . . . . . . . . . . . E
C
Power Dissipation Total at T = 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
C
AS
o
ARV
o
W
D
o
o
Power Dissipation Derating T > 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.33
W/ C
C
o
Operating and Storage Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Lead Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Tech Brief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
o
o
300
260
C
C
L
PKG
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. Pulse width limited by maximum junction temperature.
o
Electrical Specifications T = 25 C, Unless Otherwise Specified
J
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
-
UNITS
V
Collector to Emitter Breakdown Voltage
Emitter to Collector Breakdown Voltage
Collector to Emitter Leakage Current
BV
BV
I
I
= 250µA, V
= 0V
600
-
CES
ECS
C
C
GE
= 10mA, V
= 0V
15
-
-
V
GE
o
I
V
= 600V
T = 25 C
J
-
-
-
-
100
2
µA
mA
V
CES
CE
o
T = 125 C
J
o
Collector to Emitter Saturation Voltage
V
I
V
=12A,
T = 25 C
J
-
1.95
1.7
6.5
-
2.7
2.0
7.0
250
-
CE(SAT)
C
GE
= 15V
o
T = 125 C
-
V
J
Gate to Emitter Threshold Voltage
Gate to Emitter Leakage Current
Switching SOA
V
I
= 250µA, V = 600V
CE
4.5
-
V
GE(TH)
C
I
V
=
GE
20V
o
nA
A
GES
SSOA
T = 150 C, R = 10Ω, V
= 15V
60
-
J
G
GE
L = 100µH, V = 600V
CE
Pulsed Avalanche Energy
Gate to Emitter Plateau Voltage
On-State Gate Charge
E
I
I
I
= 12A, L = 2.1mH, V = 50V
DD
150
-
-
-
mJ
V
AS
CE
V
= 12A, V = 300V
CE
-
-
-
-
-
-
-
-
-
-
9.0
23
GEP
C
Q
= 12A,
= 300V
V
= 15V
30
36
-
nC
nC
ns
ns
ns
ns
µJ
µJ
µJ
g(ON)
C
GE
GE
V
CE
V
= 20V
o
28
Current Turn-On Delay Time
Current Rise Time
t
IGBT and Diode at T = 25 C
I
V
V
16
d(ON)I
J
= 12A
CE
t
14
-
rI
= 390V
= 15V
CE
GE
Current Turn-Off Delay Time
Current Fall Time
t
42
-
d(OFF)I
R
= 10Ω
G
t
18
-
fI
L = 200µH
Test Circuit - Figure 20
Turn-On Energy (Note 2)
Turn-On Energy (Note 2)
Turn-Off Energy (Note 3)
E
E
E
55
-
ON1
ON2
OFF
170
100
-
-
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
o
Electrical Specifications T = 25 C, Unless Otherwise Specified (Continued)
J
PARAMETER
Current Turn-On Delay Time
Current Rise Time
SYMBOL
TEST CONDITIONS
MIN
TYP
22
MAX
-
UNITS
ns
o
t
IGBT and Diode at T = 125 C
-
-
-
-
-
-
-
-
d(ON)I
J
I
V
V
= 12A
= 390V
= 15V
CE
CE
GE
t
15
-
ns
rI
d(OFF)I
Current Turn-Off Delay Time
Current Fall Time
t
80
100
85
ns
R
= 10Ω
L = 200µH
Test Circuit - Figure 20
G
t
72
ns
fI
Turn-On Energy (Note 2)
Turn-On Energy (Note 2)
Turn-Off Energy (Note 3)
E
E
E
55
-
µJ
ON1
ON2
OFF
230
225
-
280
300
0.75
µJ
µJ
o
Thermal Resistance Junction To Case
NOTES:
R
C/W
θJC
2. Values for two Turn-On loss conditions are shown for the convenience of the circuit designer. E
is the turn-on loss of the IGBT only. E
ON2
ON1
is the turn-on loss when a typical diode is used in the test circuit and the diode is at the same T as the IGBT. The diode type is specified in
J
Figure 20.
3. Turn-Off Energy Loss (E
) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending
OFF
at the point where the collector current equals zero (I = 0A). All devices were tested per JEDEC Standard No. 24-1 Method for Measurement
CE
of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss.
Typical Performance Curves Unless Otherwise Specified
50
70
V
= 15V
o
o
GE
T
= 150 C, R = 10Ω, V = 15V
GE
J
G
T
= 150 C
J
60
50
40
30
20
10
0
40
30
20
10
0
25
50
75
100
125
150
0
100
V
200
300
400
500
600
700
o
T
, CASE TEMPERATURE ( C)
, COLLECTOR TO EMITTER VOLTAGE (V)
C
CE
FIGURE 1. DC COLLECTOR CURRENT vs CASE
TEMPERATURE
FIGURE 2. MINIMUM SWITCHING SAFE OPERATING AREA
1000
140
120
100
80
24
20
16
12
8
T
o
C
o
V
= 390V, R = 10Ω, T = 125 C
CE
G
J
V
= 15V
GE
75 C
I
SC
V
= 12V
GE
100
f
f
P
= 0.05 / (t
+ t
d(ON)I
)
MAX1
d(OFF)I
= (P - P ) / (E
= CONDUCTION DISSIPATION
(DUTY FACTOR = 50%)
+ E
)
t
SC
MAX2
D
C
ON2
OFF
C
60
o
R
= 0.75 C/W, SEE NOTES
o
ØJC
T
= 125 C, R = 10Ω, L = 200µH, V
= 390V
10
J
G
CE
4
40
10
10
11
12
13
14
15
1
5
20
30
V
, GATE TO EMITTER VOLTAGE (V)
I
, COLLECTOR TO EMITTER CURRENT (A)
GE
CE
FIGURE 3. OPERATING FREQUENCY vs COLLECTORTO
EMITTER CURRENT
FIGURE 4. SHORT CIRCUIT WITHSTAND TIME
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
Typical Performance Curves Unless Otherwise Specified (Continued)
18
16
14
12
10
8
18
16
14
12
10
8
DUTY CYCLE < 0.5%, V
= 12V
PULSE DURATION = 250µs
GE
DUTY CYCLE < 0.5%, V
= 15V
PULSE DURATION = 250µs
GE
o
T
= 150 C
J
o
T
= 25 C
J
6
6
o
o
T
= 25 C
T
= 150 C
J
J
4
4
o
2
o
2
T
= 125 C
J
T
= 125 C
J
0
0
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.5
2.0
2.5
1.0
V
, COLLECTOR TO EMITTER VOLTAGE (V)
V
, COLLECTOR TO EMITTER VOLTAGE (V)
CE
CE
FIGURE 5. COLLECTOR TO EMITTER ON-STATE VOLTAGE
FIGURE 6. COLLECTOR TO EMITTER ON-STATE VOLTAGE
400
275
R
= 10Ω, V
= 390V
G
CE
R
= 10Ω, V
= 390V
G
CE
250
350
300
250
200
150
100
50
o
225
200
T
= 125 C, V
= 12V, V = 15V
GE
J
GE
175
150
125
100
75
o
T
= 125 C, V
= 12V OR 15V
J
GE
50
o
25
0
o
T
6
= 25 C, V
= 12V, V
10
= 15V
J
GE
GE
T
= 25 C, V
8
= 12V OR 15V
J
GE
0
0
2
4
6
10
12
14
0
2
4
8
12
14
I
, COLLECTOR TO EMITTER CURRENT (A)
I
, COLLECTOR TO EMITTER CURRENT (A)
CE
CE
FIGURE 7. TURN-ON ENERGY LOSS vs COLLECTORTO
EMITTER CURRENT
FIGURE 8. TURN-OFF ENERGY LOSS vs COLLECTORTO
EMITTER CURRENT
24
35
R
= 10Ω, V = 390V
CE
R
= 10Ω, V
= 390V
G
G
CE
30
25
20
15
10
5
22
20
18
16
14
12
10
o
o
T
= 25 C OR T = 125 C, V
= 12V
GE
o
J
J
T
= 25 C, V
= 12V
J
GE
o
T
= 125 C, V
= 12V
= 15V
J
GE
o
= 25 C, V
T
= 15V
GE
J
o
T
= 125 C, V
J
GE
o
o
T
= 25 C OR T = 125 C, V
= 15V
J
J
GE
0
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
I
, COLLECTOR TO EMITTER CURRENT (A)
I
, COLLECTOR TO EMITTER CURRENT (A)
CE
CE
FIGURE 9. TURN-ON DELAYTIME vs COLLECTORTO
EMITTER CURRENT
FIGURE 10. TURN-ON RISETIME vs COLLECTORTO
EMITTER CURRENT
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
Typical Performance Curves Unless Otherwise Specified (Continued)
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
R
= 10Ω, V = 390V
CE
R
= 10Ω,
V
= 390V
G
G
CE
o
V
= 15V,T = 125 C
J
GE
o
T
= 125 C, V = 12V OR 15V
GE
J
o
V
= 12V,T = 125 C
J
GE
o
V
= 15V,T = 25 C
J
GE
o
= 25 C, V
T
= 12V OR 15V
GE
J
o
V
= 12V,T = 25 C
GE
J
2
4
6
8
10 12 14 16 18 20 22 24
0
2
4
6
8
10
12
14
I
, COLLECTOR TO EMITTER CURRENT (A)
I
CE
, COLLECTOR TO EMITTER CURRENT (A)
CE
FIGURE 11. TURN-OFF DELAYTIME vs COLLECTORTO
EMITTER CURRENT
FIGURE 12. FALLTIME vs COLLECTORTO EMITTER
CURRENT
16
o
175
I
= 1mA, R = 25Ω, T = 25 C
G(REF)
L
J
DUTY CYCLE < 0.5%, V
= 10V
PULSE DURATION = 250µs
CE
14
12
10
8
150
125
100
75
o
V
= 600V
CE
T
= 25 C
J
o
T
= -55 C
J
o
T
= 125 C
J
V
= 400V
V
= 200V
CE
CE
6
50
4
2
25
0
0
0
2
4
6
8
10 12 14 16 18 20 22 24
, GATE CHARGE (nC)
6
7
8
9
10
11
12
13
14
15
16
Q
G
V
, GATE TO EMITTER VOLTAGE (V)
GE
FIGURE 13. TRANSFER CHARACTERISTIC
FIGURE 14. GATE CHARGE WAVEFORMS
10
o
1.4
1.2
T
= 125 C, V
= 390V, V
GE
= 15V
J
CE
V
= 10Ω,
CE
= 390V
R
G
E
= E
ON2
+ E
TOTAL
OFF
E
= E
ON2
+ E
OFF
TOTAL
1.0
0.8
0.6
I
I
I
= 24A
= 12A
= 6A
CE
CE
CE
I
= 24A
CE
1
0.4
0.2
I
I
= 12A
= 6A
CE
CE
0.1
3
0
25
10
1000
100
, GATE RESISTANCE (Ω)
50
75
100
125
150
R
o
G
T
, CASE TEMPERATURE ( C)
C
FIGURE 15. TOTAL SWITCHING LOSS vs CASE
TEMPERATURE
FIGURE 16. TOTAL SWITCHING LOSS vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
Typical Performance Curves Unless Otherwise Specified (Continued)
1400
1200
1000
800
600
400
200
0
2.4
2.3
2.2
2.1
2.0
1.9
1.8
FREQUENCY = 1MHz
DUTY CYCLE < 0.5%, V
PULSE DURATION = 250µs,T = 25 C
= 15V
GE
o
J
C
IES
I
= 18A
CE
I
I
= 12A
= 6A
CE
C
OES
CE
C
RES
0
20
40
60
80
100
10
11
12
13
14
15
16
V
, COLLECTOR TO EMITTER VOLTAGE (V)
CE
V
, GATE TO EMITTER VOLTAGE (V)
GE
FIGURE 17. CAPACITANCE vs COLLECTORTO EMITTER
VOLTAGE
FIGURE 18. COLLECTORTO EMITTER ON-STATEVOLTAGE
vs GATE TO EMITTER VOLTAGE
0
10
0.5
0.2
0.1
t
1
-1
10
P
0.05
D
t
0.02
0.01
2
DUTY FACTOR, D = t / t
1
2
X R
PEAK T = (P X Z
) + T
J
D
θJC
θJC C
SINGLE PULSE
-2
10
-5
-4
10
-3
10
-2
10
-1
10
0
1
10
10
10
t , RECTANGULAR PULSE DURATION (s)
1
FIGURE 19. IGBT NORMALIZED TRANSIENT THERMAL RESPONSE, JUNCTION TO CASE
Test Circuit and Waveforms
ISL9H1260EP3
90%
OFF
10%
V
GE
E
ON2
E
L = 200µH
V
CE
R
= 10Ω
G
90%
10%
d(OFF)I
I
+
-
CE
t
t
rI
ISL9G1260EP3
V
= 390V
t
DD
fI
t
d(ON)I
FIGURE 20. INDUCTIVE SWITCHING TEST CIRCUIT
FIGURE 21. SWITCHING TEST WAVEFORMS
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
Handling Precautions for IGBTs
Operating Frequency Information
Insulated Gate Bipolar Transistors are susceptible to
gate-insulation damage by the electrostatic discharge of
energy through the devices. When handling these devices,
care should be exercised to assure that the static charge
built in the handler’s body capacitance is not discharged
through the device. With proper handling and application
procedures, however, IGBTs are currently being extensively
used in production by numerous equipment manufacturers in
military, industrial and consumer applications, with virtually
no damage problems due to electrostatic discharge. IGBTs
can be handled safely if the following basic precautions are
taken:
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating device
performance for a specific application. Other typical
frequency vs collector current (I ) plots are possible using
CE
the information shown for a typical unit in Figures 5, 6, 7, 8, 9
and 11. The operating frequency plot (Figure 3) of a typical
device shows f
or f ; whichever is smaller at each
MAX1
MAX2
point. The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
f
is defined by f
MAX1
= 0.05/(t ).
+ t
MAX1
d(OFF)I d(ON)I
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs or by the insertion into conductive material such
as “ECCOSORBD LD26” or equivalent.
are possible. t
and t are defined in Figure 21.
d(OFF)I
d(ON)I
Device turn-off delay can establish an additional frequency
limiting condition for an application other than T
.
JM
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
f
is defined by f
MAX2
= (P - P )/(E
OFF
+ E
). The
ON2
MAX2
D
C
allowable dissipation (P ) is defined by P = (T - T )/R
The sum of device switching and conduction losses must
not exceed P . A 50% duty factor was used (Figure 3) and
the conduction losses (P ) are approximated by
P
.
D
D
JM θJC
C
3. Tips of soldering irons should be grounded.
D
4. Devices should never be inserted into or removed from
circuits with power on.
C
= (V
x I )/2.
CE
C
CE
5. GateVoltage Rating - Never exceed the gate-voltage
E
and E are defined in the switching waveforms
OFF
rating of V
. Exceeding the rated V can result in
ON2
GEM
GE
permanent damage to the oxide layer in the gate region.
shown in Figure 21. E
is the integral of the instantaneous
ON2
power loss (I
CE
integral of the instantaneous power loss (I x V ) during
turn-off. All tail losses are included in the calculation for
x V ) during turn-on and E
CE OFF
is the
6. GateTermination - The gates of these devices are
essentially capacitors. Circuits that leave the gate
open-circuited or floating should be avoided. These
conditions can result in turn-on of the device due to
voltage buildup on the input capacitor due to leakage
currents or pickup.
CE CE
E
; i.e., the collector current equals zero (I = 0).
CE
OFF
7. Gate Protection - These devices do not have an internal
monolithic Zener diode from gate to emitter. If gate
protection is required an external Zener is recommended.
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
TO-247
3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE
A
INCHES
MIN
MILLIMETERS
TERM. 4
ØP
E
SYMBOL
MAX
0.190
0.051
0.070
0.105
0.026
0.820
0.625
MIN
4.58
MAX
4.82
NOTES
ØS
A
b
0.180
0.046
0.060
0.095
0.020
0.800
0.605
-
Q
1.17
1.29
2, 3
ØR
b
b
1.53
1.77
1, 2
1
2
D
2.42
2.66
1, 2
c
0.51
0.66
1, 2, 3
D
E
e
20.32
15.37
20.82
15.87
-
-
L
1
b1
b2
0.219 TYP
0.438 BSC
0.090
5.56 TYP
11.12 BSC
4
4
5
-
L
c
e
1
b
J
0.105
0.640
0.155
0.144
0.220
0.205
0.270
2.29
2.66
16.25
3.93
3.65
5.58
5.20
6.85
1
L
0.620
0.145
0.138
0.210
0.195
0.260
15.75
3.69
3.51
5.34
4.96
6.61
1
2
3
3
2
1
J
e
1
L
1
-
BACK VIEW
1
ØP
Q
e1
-
ØR
-
ØS
-
NOTES:
1. Lead dimension and finish uncontrolled in L .
1
2. Lead dimension (without solder).
3. Add typically 0.002 inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.250 inches (6.35mm) from bottom
of dimension D.
5. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of dimension D.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
TO-263AB SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
E
A
INCHES
MIN
MILLIMETERS
A
1
SYMBOL
MAX
0.180
0.052
0.034
0.055
-
MIN
4.32
MAX
4.57
1.32
0.86
1.39
-
NOTES
H
1
A
0.170
0.048
0.030
0.045
0.310
0.018
0.405
0.395
-
4, 5
4, 5
4, 5
2
TERM. 4
A
1.22
1
b
0.77
D
L
b
b
1.15
1
2
7.88
L
2
c
0.022
0.425
0.405
0.46
0.55
10.79
10.28
4, 5
-
L
1
D
E
e
10.29
10.04
-
1
3
0.100 TYP
0.200 BSC
2.54 TYP
5.08 BSC
7
b
b1
c
e
e
7
1
J
1
e1
H
0.045
0.055
0.105
0.195
0.110
0.070
-
1.15
1.39
2.66
4.95
2.79
1.77
-
-
1
0.450
(11.43)
TERM. 4
J
0.095
0.175
0.090
0.050
0.315
2.42
4.45
2.29
1.27
8.01
-
1
L
-
L
L
L
4, 6
3
1
2
3
L
3
0.350
(8.89)
2
b
2
0.700
(17.78)
NOTES:
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-263AB outline dated 2-92.
2. L and b dimensions established a minimum mounting surface
3
2
0.150
(3.81)
for terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
3
1
0.080 TYP (2.03)
0.062 TYP (1.58)
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L is the terminal length for soldering.
1
7. Position of lead to be measured 0.120 inches (3.05mm) from bottom
of dimension D.
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
8. Controlling dimension: Inch.
9. Revision 10 dated 5-99.
4.0mm
1.5mm
1.75mm
DIA. HOLE
USER DIRECTION OF FEED
2.0mm
C
TO-263AB
L
24mm TAPE AND REEL
24mm
16mm
COVER TAPE
40mm MIN.
ACCESS HOLE
30.4mm
13mm
330mm
100mm
GENERAL INFORMATION
1. 800 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
24.4mm
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A
INCHES
MIN
MILLIMETERS
E
ØP
SYMBOL
MAX
0.180
0.052
0.034
0.055
0.019
0.610
0.160
0.410
0.030
MIN
4.32
1.22
0.77
1.15
0.36
14.99
-
MAX
4.57
NOTES
A
1
A
0.170
0.048
0.030
0.045
0.014
0.590
-
-
Q
H
1
A
1.32
-
1
b
0.86
3, 4
TERM. 4
D
b
1.39
2, 3
1
o
45
E
1
c
0.48
2, 3, 4
D
1
D
15.49
4.06
-
-
L
1
D
1
b1
b
E
0.395
-
10.04
-
10.41
0.76
-
L
E
-
c
1
e
0.100 TYP
0.200 BSC
2.54 TYP
5.08 BSC
5
5
-
o
60
e
1
2
e
e1
3
1
J
1
H
0.235
0.255
0.110
0.550
0.150
0.153
0.112
5.97
6.47
2.79
13.97
3.81
3.88
2.84
1
1
J
0.100
0.530
0.130
0.149
0.102
2.54
13.47
3.31
6
-
L
L
2
-
1
ØP
Q
3.79
2.60
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L .
1
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bot-
tom of dimension D.
7. Controlling dimension: Inch.
8. Revision 2 dated 7-97.
©2001 Fairchild Semiconductor Corporation
ISL9G1260EG3, ISL9G1260EP3, ISL9G1260ES3 Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
PACMAN™
POP™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
Star* Power™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
FAST
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
UltraFET
VCX™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOTASSUMEANY LIABILITYARISING OUT OF THEAPPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H1
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