ISL99202IRTAZ-T [INTERSIL]
60mW, Capfree, Stereo Headphone Amplifier; 为60mW ，无电容，立体声耳机放大器
| 型号： | ISL99202IRTAZ-T |
| 厂家： | 
Intersil |
| 描述： | 60mW, Capfree, Stereo Headphone Amplifier |
| 文件： | 总11页 (文件大小：553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL99202
¬
Data Sheet
May 29, 2009
FN6758.0
60mW, Capfree, Stereo Headphone
Amplifier
Features
• Supports 16Ω to 600Ω Speaker Impedance
• Ground Referenced: No Output Coupling Capacitors
• Audiophile Quality Sound THD of 0.01%, SNR of 102dB
• PSRR < -90dB, No Need for LDO
The ISL99202 is a stereo, capfree headphone amplifier. The
wide operating voltage of 2.4V to 5.5V makes it versatile
enough to be used in mobile battery powered applications
powered by 2 AA or Single cell Li-Ion batteries as well as
3.3/5V power supply available notebook computers.
• Wide Operating Voltage of 2.4V to 5.5V
• < 3mA Quiesent Current and 0.1µA Shutdown Current
• State of the Art Pop and Click Suppression
• Pb-Free (RoHS Compliant)
The ISL99202 has robust RF immunity, which makes it
ideally suited for today’s mobile applications.
It has audiophile quality SNR and THD specifications and
Click/Pop suppression.
The ISL99202 comes with Comprehensive Protection
features, which include undervoltage and short-circuit
protection and thermal shutdown.
Applications
• Mobile Phones
• MP3 Players
The ISL99202 lowest power consumption in the industry is
achieved by low I and current shutdown.
qq
The product is available in 12 Ld TQFN and 0.4mm pitch
12 ball WLCSP.
Ordering Information
PACKAGE
GAIN SETTING
TEMP. RANGE
(°C)
Tape & Reel
(Pb-Free)
PART NUMBER
PART MARKING
202A
(dB)
PKG. DWG. #
ISL99202IIAZ-T* (Notes 1, 3)
ISL99202IIBZ-T* (Notes 1, 3)
ISL99202IRTAZ (Notes 2, 3)
-1.5V/V
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
12 Ball 3x4 WLCSP Array W3x4.12
12 Ball 3x4 WLCSP Array W3x4.12
202B
202A
Adjustable
-1.5V/V
12 Ld TQFN
12 Ld TQFN
12 Ld TQFN
12 Ld TQFN
12 Ld TQFN
12 Ld TQFN
L12.3x3Z
L12.3x3Z
L12.3x3Z
L12.3x3Z
L12.3x3Z
L12.3x3Z
ISL99202IRTAZ-T* (Notes 2, 3) 202A
ISL99202IRTAZ-TK* (Notes 2, 3) 202A
-1.5V/V
-1.5V/V
ISL99202IRTBZ (Notes 2, 3)
202B
Adjustable
Adjustable
Adjustable
ISL99202IRTBZ-T* (Notes 2, 3) 202B
ISL99202IRTBZ-TK* (Notes 2, 3) 202B
*Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach
materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
3. Contact factory for ordering details.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL99202
Pinouts
ISL99202
(12 LD TQFN)
TOP VIEW
ISL99202
(12 BALL WLCSP)
TOP VIEW
3
2
1
VDD
CP
PGND
SDB
CN
CP
PGND
CN
1
2
3
9
8
7
SVSS
INR
THERMAL
PAD
OUTL
INR
PVSS
SGND
OUTR SVSS SGND
INL
D
A
B
C
Pin Descriptions
PIN NUMBER
TQFN
WLCSP
B3
PIN NAME
DESCRIPTION
1
2
CP
PGND
CN
Charge pump positive terminal
Charge pump Ground
Charge pump negative terminal
Charge pump output
Active low shutdown input
Left channel input
C3
3
D3
4
D2
PVSS
SDB
5
C2
6
D1
INL
7
C1
SGND
INR
Analog ground
8
B2
Right channel input
9
B1
SVSS
OUTR
OUTL
VDD
Amplifier negative supply
Right channel output
Left channel output
10
11
12
A1
A2
A3
Positive power supply
NOTE: Exposed Pad is connected to PGND and SGND
FN6758.0
May 29, 2009
2
ISL99202
Absolute Maximum Ratings (Reference to GND)
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5)
θ
(°C/W)
θ
(°C/W)
JC
JA
INR, INL, CP, SDB . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
+ 0.3V
DD
TQFN Package . . . . . . . . . . . . . . . . . .
WLCSP Package . . . . . . . . . . . . . . . . .
54
90
8
N/A
Maximum Junction Temperature (Plastic Package) -65°C to +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Dissipation Ratings
Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Supply Voltage (VDD Pin) . . . . . . . . . . . . . . . . . . . . . 5.5V
Operating Supply Voltage (VDD Pin). . . . . . . . . . . . . . . . 2.4V to 5V
Derating Factor
12 LD 3x3 TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . .14.7mW/°C
12 Ball 3x4 Array WLCSP . . . . . . . . . . . . . . . . . . . .10.1mW/°C
Power Rating T
A
12 Ld 3x3 TQFN
+25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.84W
+70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.12W
+85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.96W
12 Ball 3x4 Array WLCSP
+25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.79W
+70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.33W
+85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.18W
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. For theta θ the "case temp." location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Typical Values are Tested at V = 5V, T = +25°C and R = 32Ω. All Maximum and Minimum Values Are
DD
A
L
Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature Range,
Unless Otherwise Noted.
PARAMETER
OUTPUT POWER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Output Power (QFN)
P
R = 32Ω, THD = 1%
30
25
63
70
mW
mW
mW
mW
%
OUT
OUT
L
R = 16Ω
L
Output Power (CSP)
P
R =32Ω
63
L
R =16Ω
70
L
Total Harmonic Distortion + Ratio
THD+N
R
R
R
= 1kΩ, V
= 32Ω, P
= 16Ω, P
= 1.5V , f = 1kHz
RMS
0.003
0.01
0.02
L
L
L
OUT
OUT
OUT
= 50mW, f = 1kHz
= 35mW, f = 1kHz
%
%
PROTECTION
Thermal Shutdown
OTP
OCP
160
15
°C
°C
mA
V
Thermal Shutdown Hysteresis
Overcurrent Protection
Undervoltage Shutdown
LOGIC INPUTS (SDB)
Input Voltage High
200
2.4
V
1.4
2.4
V
V
INH
Input Voltage Low
V
0.9
5.5
INL
POWER SUPPLY
Supply Voltage Range
V
V
DD
FN6758.0
May 29, 2009
3
ISL99202
Electrical Specifications Typical Values are Tested at V = 5V, T = +25°C and R = 32Ω. All Maximum and Minimum Values Are
DD
A
L
Established Under the Recommended Operating Supply Voltage Range and Ambient Temperature Range,
Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
= 2.5V to 5.0V at 217Hz
MIN TYP MAX UNITS
Power Supply Rejection Ratio
PSRR
V
V
V
V
96
88
76
3
dB
dB
dB
mA
µA
DD
DD
DD
DD
= 2.5V to 5.0V at 1kHz
= 2.5V to 5.0V at 20kHz
= 5.0V
Quiescent Current
Shutdown Current
GAIN CONTROL
Voltage Gain
I
4.6
1.1
qq
I
SDB = GND , V
= 5.0V
DD
0.1
SDB
A
-1.55 -1.50 -1.45
V/V
%
V
±0.15
0.005
0.01
Ch to Ch Gain Tracking
Total Harmonic Distortion + Ratio
THD+N
SNR
SR
R
R
R
= 1kΩ, V
= 32Ω, P
= 16Ω, P
= 1.5V , f = 1kHz
RMS
%
L
L
L
OUT
OUT
OUT
= 50mW, f = 1kHz
= 35mW, f = 1kHz
%
0.04
%
NOISE PERFORMANCE
Signal to Noise Ratio
R = 1kΩ, V
= 1.5V
, BW = 22Hz to 20kHz
RMS
102
105
100
113
0.5
dB
dB
L
OUT
R = 1kΩ, V
= 1.5V
, BW = 22Hz to 20kHz, A-weighted
L
OUT
RMS
R = 32Ω, P
= 35mW, BW = 22Hz to 20kHz
dB
L
OUT
OUT
R = 32Ω, P
= 35mW, BW = 22Hz to 20kHz, A-weighted
dB
L
Slew Rate
VµS
pF
Capacitve Drive
C
100
-76
L
Crosstalk (QFN, CSP)
Charge Pump Oscillation Frequency
Click and Pop Level
xtalk
R
R
= 16Ω, P
= 15mW, f = 10kHz
OUT
dB
L
L
f
400
500
-67
600
kHz
dB
soc
K
= 32Ω, Peak voltage, Awtg. 32 sam/sec
CP
V
= 3.0V
DD
Power Supply Rejection Ratio
PSRR
217Hz
1kHz
96
88
dB
dB
dB
mA
µA
mV
mW
mW
%
20kHz
76
Quiescent Current
I
2.4
3.6
1.1
1
qq
Shutdown Current
I
SDB = GND
0.1
SDB
Output Offset Voltage
Output Power at 32Ω Load
Output Power at 16Ω Load
VOS
-1
0.05
54
R
R
R
R
R
= 32Ω, THD = 1%
= 16Ω, THD = 1%
L
L
L
L
L
56
Total Harmonic Distortion + Noise Ratio THD+N
= 1kΩ, V
= 32Ω, P
= 16Ω, P
= 1.5V
, f = 1kHz
RMS
0.005
0.01
0.02
OUT
OUT
OUT
= 50mW, f = 1kHz
= 35mW, f = 1kHz
%
%
FN6758.0
May 29, 2009
4
ISL99202
Block Diagram
VDD
SDB LOGIC
CLICK AND POP
SUPPRESSION
SDB
PVSS
OUTR
POSITIVE VOLTAGE
REGULATOR
BIAS AND REFERENCE
INR
-
AMPR
+
OVERCURRENT
PROTECTION
SGND
SVSS
+
OUTL
PGND
AMPL
-
INL
DYNAMICALLY
ADJUSTED
VOLTAGE
REGULATOR
CLOCK GENERATOR
PVSS
CP
CN
Typical Performance Curves
100
100
10
V
R
= 3V
= 16Ω
V
R
= 3V
DD
L
DD
= 32Ω
10kHz
L
10
1.0
0.1
1.0
0.1
20Hz
10kHz
20Hz
0.01
0.001
0.01
1kHz
1kHz
0.001
1
10
OUTPUT POWER (mW)
100
1
10
OUTPUT POWER (mW)
100
FIGURE 1. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
FIGURE 2. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
FN6758.0
May 29, 2009
5
ISL99202
Typical Performance Curves (Continued)
100
10
100
V
R
= 5V
V
R
= 3V
DD
= 32Ω
DD
= 32Ω
10kHz
10kHz
L
L
10
1.0
1.0
20Hz
20Hz
0.1
0.1
0.01
0.01
0.001
1kHz
1kHz
0.001
1
10
OUTPUT POWER (mW)
100
1
10
OUTPUT POWER (mW)
100
FIGURE 3. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
FIGURE 4. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs OUTPUT POWER
10
10
V
= 5V
V
= 3V
DD
= 16Ω
DD
R
R
= 16Ω
L
L
1.0
0.1
1.0
0.1
P
= 20mW
P
= 10mW
OUT
OUT
0.01
0.01
P
= 40mW
OUT
P
= 5mW
OUT
1k
0.001
0.001
10
100
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
10
10
V
= 3V
DD
V
= 5V
DD
R
= 32Ω
L
R
= 32Ω
L
1.0
0.1
1.0
0.1
P
= 50mW
OUT
P
= 15mW
= 10mW
OUT
0.01
0.01
P
= 30mW
OUT
P
OUT
0.001
0.001
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
FIGURE 7. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE RATIO
vs FREQUENCY
FN6758.0
May 29, 2009
6
ISL99202
Typical Performance Curves (Continued)
0
-30
-40
R
= 32Ω
L
V
= 5V
DD
R
= 16Ω
L
-20
-40
-50
-60
-60
V
= 5V
RIGHT TO LEFT
DD
-80
-70
-80
-100
-120
V
= 3V
DD
LEFT TO RIGHT
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 9. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
FIGURE 10. CROSSTALK vs FREQUENCY
70
90
80
70
60
50
40
30
20
10
0
R
= 16 (STEREO INPUT)
R
= 32 (STEREO INPUT)
L
L
60
50
40
30
20
10
0
5
15
25
35
45
55
65
5
15
25
35
45
55
65
75
85
95
OUTPUT POWER (mW)
OUTPUT POWER (mW)
FIGURE 11. POWER DISSIPATION vs OUTPUT POWER
FIGURE 12. POWER DISSIPATION vs OUTPUT POWER
90
80
70
60
50
40
30
R
= 32Ω
NO LOAD INPUTS GND
L
THD + N = 10%
THD + N = 1%
255
f
= 1kHz
IN
205
155
105
55
5
2.4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.9
3.4
3.9
4.4
4.9
5.4
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 13. SHUTDOWN CURRENT vs SUPPLY VOLTAGE
FIGURE 14. OUTPUT POWER vs SUPPLY VOLTAGE
FN6758.0
May 29, 2009
7
ISL99202
Typical Performance Curves (Continued)
100
0.100
0.095
0.090
0.085
0.080
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
R
f
= 16Ω
V
f
= 5V
L
DD
= 1kHz
90
80
70
60
50
40
30
= 1kHz
IN
IN
THD + N = 10%
THD + N = 10%
THD + N = 1%
THD + N = 1%
2.5
3.0
3.5
4.0
4.5
5.0
5.5
10
100
1k
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (Ω)
FIGURE 15. OUTPUT POWER vs SUPPLY VOLTAGE
FIGURE 16. OUTPUT POWER vs LOAD RESISTANCE
0.080
V
f
= 3V
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
NO LOAD INPUTS GND
INPUT GND
DD
= 1kHz
3.6
IN
THD + N = 10%
3.4
3.2
3.0
THD + N = 1%
2.8
2.6
2.4
2.4
2.9
3.4
3.9
4.4
4.9
5.4
5.9
10
100
1k
LOAD RESISTANCE (Ω)
SUPPLY VOLTAGE (V)
FIGURE 17. OUTPUT POWER vs. LOAD RESISTANCE
FIGURE 18. SUPPLY CURRENT vs. SUPPLY VOLTAGE
FIGURE 19. CHARGE PUMP RESPONSE FOR SDB GOING
HIGH
FIGURE 20. CHARGE PUMP RESPONSE FOR SDB GOING
LOW
FN6758.0
May 29, 2009
8
ISL99202
Typical Application Circuit
ISL99202
INL
LEFT
-
AUDIO INPUT
1µ
OUTL
+
+
-
INR
OUTR
RIGHT
AUDIO INPUT
1µ
current in quiescent state. The ISL99202 is tested and
trimmed to have very low offset voltages (typically 50µV).
Detailed Description
The ISL99202 incorporates a novel proprietary architecture
to eliminate the large output capacitors associated with
single supply headphone amplifiers. Traditional charge
pump based architectures that eliminated the output
capacitors required additional power to operate the charge
pump, which made them ill-suited for portable battery
powered applications. The ISL99202 architecture eliminates
the need for large output capacitors while consuming
industry’s lowest quiescent and shutdown currents.
RF Immunity
Most portable applications for ISL99202 are subject to RF
radiation from a myriad of sources, like Wi-Fi networks or
cellular phone networks. Though these signals are not in the
audio band, they can interfere with the audio signals through
complex non-linear mechanisms, aliasing or demodulations
to create audio band noise. The ISL99202 architecture
prevents this coupling into audio band to achieve superior
audio performance.
Capfree Architecture
At the core of the Capfree architecture is a dynamically
adjusted negative voltage regulator. By continuously
monitoring the output power requirements, it adjusts the
energy delivery circuitry. The feedback system ensures that
overhead power required to deliver audio at the headphone
speaker is always optimized for lower power dissipation.
Protection Circuitry
The ISL99202 has comprehensive protection circuitry, which
protects the part due to undervoltage, over-temperature and
overcurrent. There is hysteresis built into over-temperature
and undervoltage, while the overcurrent is designed to limit
the output current in case of accidental short circuit or low
impedance headphone load connection.
Integrated LDO
A high precision LDO integrated into the power path of the
amplifier accounts for a 92dB PSRR. This eliminates the
need for a dedicated LDO used in some systems resulting in
BOM/cost savings.
References
Intersil Technical Brief 451: “PCB Assembly Guidelines for
Intersil Wafer Level Chip Scale Package Devices”
http://www.intersil.com/data/tb/TB451.pdf
Offset Cancellation Circuitry
Intersil Technical Brief 389: “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
http://www.intersil.com/data/tb/tb389.pdf
The DC offset is a very important parameter. It is a principal
contributor to Click and Pop. In the cast Capfree
architecture, the DC offset can also be a source of DC
FN6758.0
May 29, 2009
9
ISL99202
Package Outline Drawing
L12.3x3Z
12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE
FOR ISL99202 USE ONLY WITH REDUCED e-PAD SIZE TO 1.4mm ON LAND PATTERN
Rev 0, 10/08
3.00
0 . 5
BSC
A
6
B
12
10
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
9
7
1
3
0.10
M C A B
0.15
(4X)
4
0.25 +0.07 / -0.05
6
4
12X 0 . 4 ± 0 .
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 75
BASE PLANE
SEATING PLANE
0.08
( 2 . 8 TYP )
C
SIDE VIEW
0 . 6
5
C
0 . 2 REF
0 . 50
0 . 25
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to JEDEC STD MO-229.
3. Unless otherwise specified, tolerance : Decimal ± 0.0
4. Dimension b applies to the metallized terminal and is measured
between 0.20mm and 0.32mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6758.0
May 29, 2009
10
ISL99202
Wafer Level Chip Scale Package (WLCSP 0.4mm Ball Pitch)
W3x4.12
3x4 ARRAY 12 BALL WAFER LEVEL CHIP SCALE PACKAGE
D
SYMBOL
MILLIMETERS
0.445 Min 0.495 Nom 0.545 Max
0.190 ±0.025
A
A1
A2
b
E
0.305 ±0.025
0.270 ±0.030
PIN 1 ID
D
1.695 ±0.020
TOP VIEW
D1
E
0.400 BASIC
1.295 ±0.020
E1
e
0.400 BASIC
0.400 BASIC
SD
SE
0.200 BASIC
A2
A
A1
0 BASIC
NUMBER OF BUMPS: 12
b
Rev. 0 12/08
SIDE VIEW
NOTES:
1. All Dimensions are in Millimeters.
b
SD
3
2
1
SE
D
C
B
A
e (D1)
BOTTOM VIEW
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6758.0
May 29, 2009
11
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