ISL97522IRZ-T [INTERSIL]
4-Channel TFT-LCD Supply; 4通道的TFT -LCD供应
| 型号： | ISL97522IRZ-T |
| 厂家： | 
Intersil |
| 描述： | 4-Channel TFT-LCD Supply |
| 文件： | 总20页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97522
®
Data Sheet
December 13, 2006
FN7445.0
4-Channel TFT-LCD Supply
Features
The ISL97522 represents a 4-channel supply control IC for
use in large panel TFT-LCD displays. Supporting inputs from
4.5V to 13V, the ISL97522 includes a boost controller to
• 4.5V to 13V input
• Boost controller for A
VDD
• Regulated LDOs for V
and V
ON
achieve the required A
output voltage. Both V
and
are generated using off-chip charge-pumps which are
OFF
• Buck controller for logic output
• V slicing circuit
VDD
ON
V
OFF
then post regulated using on-board LDO controllers.
ON
The logic supply is generated using an internal non-
synchronous buck controller. This controller runs at 180° out
• Fully fault-protected
of phase with the A
VDD
supply to minimize input noise.
• Programmable sequence
• 1MHz switching frequency
• 38 Ld QFN package
The A
, V
, and V
outputs are automatically
, and V . By using an optional
VDD OFF ON
sequenced as A
, V
VDD OFF ON
external series transistor with A
(Q1), the start-up
VDD
sequence can be adjusted to VOFF, A
• Pb-free plus anneal available (RoHS compliant)
and then V . A
ON
VDD
slicing circuit is also included to reduce LCD flicker.
V
ON
Applications
The ISL97522 also incorporates a fault protection circuit that
can disable the IC and turn off all outputs when an output
short is detected. (Note that to protect A
external transistor is required).
• LCD-TVs (up to 50”+)
• LCD monitors (15”+)
• Industrial/medical LCD displays
a single
VDD
Ordering Information
Pinout
PART NUMBER
(Note)
PART
MARKING
TAPE & PACKAGE
REEL (Pb-Free) DWG. #
PKG.
ISL97522
(38 LD QFN)
TOP VIEW
ISL97522IRZ-TK ISL 97522IRZ
ISL97522IRZ-T ISL 97522IRZ
13”
(1k pcs)
38 Ld QFN L38.5x7B
38 Ld QFN L38.5x7B
13”
(4k pcs)
DRVN
DELB
FBN
1
2
3
4
5
6
7
8
9
31 FBP
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
30 VREF
29 ACGND
28 NC
VCC1
FBB
27 DRVP
26 NC
ISADJB
ILADJB
CINTB
DRVB
THERMAL
PAD
25 VDCP
24 VDC
23 ISADJL
22 CINTL
21 ILADJL
20 PBL
PGNDB 10
VHIB 11
NC 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97522
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Maximum Pin Voltages, all pins except below . . . . . . . . . . . . . . 6.5V
VIN,EN,ENL,LX,VHIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V
VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V
VDRVP, VSINB, SRC, COM, DRN . . . . . . . . . . . . . . . . . . . . . . .36V
VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V
Thermal Resistance
θ
(°C/W)
33
θ
(°C/W)
4.5
JA
JC
38 Ld QFN Package (Notes 1, 2). . . . .
Operating Conditions
Input Voltage Range, V . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 13V
IN
Boost Output Voltage Range, A
. . . . . . . . . . . . . . +15V to +25V
VDD
V
V
Output Range, V . . . . . . . . . . . . . . . . . . . . . . . +15V to +32V
ON
ON
Output Range, V
. . . . . . . . . . . . . . . . . . . . . . . .-15V to -5V
ON
OFF
Input Capacitance, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2x10µF
IN
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Output Capacitance, C
. . . . . . . . . . . . . . . . . . . . . . . . . .4x10µF
OUT
Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V
= 5V, A
VDD
= 15V, V
ON
= 20V, V
= -9V, V = 3V, Over Temperature from -40°C to +85°C
LOGIC
IN
OFF
PARAMETER
GENERAL
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
V
Input Voltage
4.5
13.2
V
mA
mA
kHz
V
IN
I
Sum Quiescent Current into Vin
EN = 0, ENL = 0
EN = ENL = 1, switching
3
S
15
F
Oscillator Frequency
Reference Voltage
850
1000
1.215
1.215
1100
1.235
1.237
OSC
V
T
= +25°C
= +25°C
1.192
1.190
REF
A
V
A
VDD
V
Feedback Reference Voltage
T
1.195
1.193
0.85
1.208
1.208
0.9
1.221
1.223
0.95
25
V
V
FBB
A
V
FBB Fault Trip Point
Minimum Duty Cycle
Maximum Duty Cycle
Boost Efficiency
V
falling
V
F_FBB
FBB
D
19
%
MIN
D
80
86
%
MAX
Eff
90
%
I
FBB Input Bias Current
Line Regulation
25
nA
%/V
%
FBB
R
C
C
= 2.2nF, V = 4.5V to12V, I =100mA
0.01
0.03
0.25
0.25
LINEB
INT
INT
IN
O
R
Load Regulation
= 2.2nF, V = 5V, I
= 100mA to
LOADB
IN AVDD
350mA
R
Gate Drive on Resistance
Pull-up
3.6
1.9
Ω
Ω
ONB
Pull-down
FN7445.0
December 13, 2006
2
ISL97522
Electrical Specifications
V
= 5V, A
VDD
= 15V, V
ON
= 20V, V
= -9V, V = 3V, Over Temperature from -40°C to +85°C
LOGIC
IN
DESCRIPTION
Peak Drive Current
OFF
PARAMETER
CONDITION
MIN
TYP
600
900
15
MAX
UNIT
mA
mA
µA
I
Source
Sink
PEAKB
I
I
I
I
Output Current
R
= 30kΩ
= 30kΩ
10
10
25
25
ISADJB
ILADJB
SADJB
LADJB
SADJB
LADJB
Output Current
R
17
µA
V
LDO
ON
V
FBP Regulation Voltage
I
I
= 0.2mA,T = +25°C
1.176
1.174
0.82
1.2
1.2
0.87
150
0.5
4
1.224
1.226
0.92
V
V
FBP
DRVP
DRVP
A
= 0.2mA
falling
V
FBP Fault Trip Point
V
V
F_FBP
FBP
FBP
I
FBP Input Bias Current
V
= 1.35V
nA
%
FBP
R
V
Load Regulation
ON
I(V ) = 0mA to 20mA
ON
0.75
2
LOADP
I
I
DRVP Sink Current Max
DRVP Leakage Current
V
V
= 1.1V, V
= 1.5V, V
= 25V
= 35V
2
mA
µA
DRVP
FBP
FBP
DRVP
DRVP
0.3
L_DRVP
V
LDO
OFF
V
FBN Regulation Voltage
I
I
= 0.2mA,T = +25°C
0.186
0.183
0.45
0.213
0.213
0.5
0.24
0.243
0.55
V
V
FBN
DRVN
DRVN
A
= 0.2mA
rising
V
FBN Fault Trip Point
V
V
V
F_FBN
FBN
FBN
I
FBNInput Bias Current
= 0.2V
40
nA
%
FBN
R
V
Load Regulation
OFF
I(V
) = 0mA to 20mA
OFF
0.4
0.85
5
LOADN
I
I
DRVN Source Current Max
DRVN Leakage Current
V
V
= 0.3V, V
= -6V
2
4
mA
µA
DRVN
FBN
FBN
DRVN
= -20V
DRVN
= 0V, V
0.4
L_DRVN
V
LOGIC
V
FBL Regulation Voltage
T
= 25°C
1.178
1.176
1.2
1.2
20
1.222
1.224
V
V
FBL
A
D
D
Minimum Duty Cycle
Maximum Duty Cycle
Logic Buck Efficiency
FBL Input Bias Current
%
MIN
85
%
MAX
EFF
90
%
L
IFBL
20
nA
%/V
%
I
I
V
V
Line Regulation
Load Regulation
C
= 2.2nF, V = 5V to 12V
IN
0.03
0.1
3.6
1.9
600
900
15
0.25
0.5
LINEL
LOGIC
LOGIC
INT
INT
C
= 2.2nF, I = 100mA to 450mA
LOGIC
LOADL
R
Gate Drive on Resistance
Pull-up
Pull-down
Source
Sink
Ω
ONL
Ω
I
Peak Drive Current
mA
mA
µA
µA
PEAKL
I
I
I
I
Output Current
Output Current
R
R
= 30kΩ
ISADJL
ILADJL
SADJB
LADJB
SADJB
LADJB
= 30kΩ
17
V
-SLICE CIRCUIT
ON
I
CTL
CTL Input Leakage Current
CTL = A
or V
IN
-1
1
µA
ns
LEAK
GND
t rise
CTL to OUT Rising Prop Delay
1kΩ from DRN to 8V, V
= 0V to 3V step,
CTL
100
D
no load on OUT, measured from V
= 1.5V
CTL
to OUT = 20%
FN7445.0
December 13, 2006
3
ISL97522
Electrical Specifications
V
= 5V, A
VDD
= 15V, V
ON
= 20V, V
= -9V, V = 3V, Over Temperature from -40°C to +85°C
LOGIC
IN
OFF
PARAMETER
t fall
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
CTL to OUT Falling Prop Delay
1kΩ from DRN to 8V, V = 3V to 0V step,
100
ns
D
CTL
no load on OUT, measured from V
= 1.5V
CTL
to OUT = 80%
V
SRC Input Voltage Range
SRC Input Current
30
1.25
250
14
V
mA
µA
Ω
SRC
ISRC
Start-up sequence not completed
Start-up sequence completed
Start-up sequence completed
Start-up sequence completed
Start-up sequence not completed
0.2
150
5
R
R
R
SRC
DRN
COM
SRC On Resistance
ON
ON
ON
DRN On Resistance
30
60
Ω
COM to GND On Resistance
400
1000
1800
Ω
SEQUENCING
t
t
t
t
t
Turn On Delay
Soft-start Time
C
= 0.22µF
= 0.22µF
= 0.22µF
= 0.22µF
= 0.22µF
30
2
ms
ms
ms
ms
ms
ON
DLY
DLY
DLY
DLY
DLY
C
C
C
C
SS
Delay Between A
Delay Between V
Delay Between V
and V
OFF
10
17
10
DEL1
DEL2
DEL3
VDD
and V
ON
OFF
and Delayed
OFF
V
BOOST
I
I
DELB Pull-Down Current or Resistance
when Enabled by the Start-Up
Sequence
V
> 0.9V
35
50
65
2
µA
DELB_ON
DELB
DELB
V
< 0.9V
1.2
1.6
KΩ
DELB Pull-Down Current or Resistance VDELB < 20V
when Disabled
500
nA
DELB_OFF
FAULT DETECTION
T
Fault Time Out
C
= 0.22µF
DLY
50
ms
°C
FAULT
OT
Over-temperature Threshold
140
LOGIC
V
V
Logic High Threshold
Logic Low Threshold
Logic Low Bias Current
Logic High Bias Current
2.2
16
V
V
HI
0.8
30
LO
I
I
0.1
23
µA
µA
LOW
HIGH
FN7445.0
December 13, 2006
4
ISL97522
Typical Performance Curves
100
90
0
-0.2
-0.4
-0.6
-0.8
-1
V
= 12V, A
= 17V
VDD
IN
80
V
= 5V, A
= 12V
VDD
70
IN
V
= 5V, A
= 12V
VDD
IN
60
50
40
30
20
10
0
V
= 12V, A
= 17V
IN
VDD
-1.2
-1.4
-1.6
-1.8
0
500
1000
1500
(mA)
2000
2500
0
500
1000
1500
2000
2500
I
I
(mA)
AVDD
AVDD
FIGURE 2. BOOST AVDD LOAD REGULATION
FIGURE 1. BOOST AVDD EFFICIENCY
100
90
17.04
17.02
17
80
70
V
= 17V
O
V
= 5V, V
= 3V
LOGIC
IN
16.98
16.96
16.94
16.92
16.9
60
50
40
30
20
10
0
V
= 12V, V
= 3V
LOGIC
IN
16.88
0
500
1000
I
1500
(mA)
2000
2500
0
2
4
6
8
10
12
14
16
V
(V)
LOGIC
IN
FIGURE 4. BUCK V
EFFICIENCY
FIGURE 3. BOOST AVDD LINE REGULATION
LOGIC
0
19.75
19.74
19.73
19.72
19.71
19.7
-0.2
V
= 20V
ON
V
= 5V, V
= 3V
LOGIC
IN
-0.4
-0.6
-0.8
-1
V
= 12V, V
LOGIC
= 3V
IN
19.69
19.68
19.67
19.66
-1.2
0
500
1000
1500
(mA)
2000
2500
0
5
10
15
(mA)
20
25
I
LOGIC
I
VON
FIGURE 5. BUCK V
LOAD REGULATION
FIGURE 6. V
LOAD REGULATION
ON
LOGIC
FN7445.0
December 13, 2006
5
ISL97522
Typical Performance Curves (Continued)
-8.875
-8.880
V
= -9V
CH1 = COM (10V/DIV)
OFF
-8.885
-8.890
-8.895
-8.900
-8.905
CH2 = CTL (2V/DIV)
0
5
10
15
20
25
I
(mA)
VOFF
FIGURE 7. V
OFF
LOAD REGULATION
FIGURE 8. 4ms/DIV V
SLICE CIRCUIT OPERATION
ON
CDLY
EN
CDLY
A
VDD
A
VDD
V
OFF
V
LOGIC
V
ON
FIGURE 9. START-UP SEQUENCE
FIGURE 10. START-UP SEQUENCE
A
(BOOST)
VDD
V
(BOOST MODE)
LOGIC
I
IN
I
IN
FIGURE 11. IN RUSH CURRENT
FIGURE 12. IN RUSH CURRENT
FN7445.0
December 13, 2006
6
ISL97522
Typical Performance Curves (Continued)
V
(BUCK MODE)
LOGIC
A
(BUCK)
VDD
I
IN
I
IN
FIGURE 13. IN RUSH CURRENT
FIGURE 14. IN RUSH CURRENT
FN7445.0
December 13, 2006
7
ISL97522
Pin Descriptions
PIN #
PIN NAME
PIN DESCRIPTION
Negative LDO base drive; open drain of an internal P-Channel MOSFET.
1
2
DRVN
DELB
Active low control output for optional delay control for external A P-Channel FET; when fault is detected, this pin
VDD
goes to high.
3
FBW
VCC1
FBB
Negative LDO voltage feedback input pin; regulates to 0.2V nominal.
Supply input, connect to V
4
.
IN
5
A
regulator voltage feedback input pin; regulates to 1.2V nominal.
VDD
6
ISADJB
ILADJB
CINTB
DRVB
PGNDB
VHIB
NC
Current feedback adjust for A
.
VDD
7
With a resistor connected from this pin to GND sets the current limit of the external N-channel FET for A
VDD.
8
A
integrator output, connect 2.2nF to analog GND.
VDD
Gate driver output for the external N-Channel switch.
Power GND for A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
.
VDD
Internal Drive of Boost controller, Connect to VDCP.
ISINB
VIN
Sense the drain voltage of the external N-channel FET and connected to the internal current limit comparator.
Main supply input.
EN
Enable pin; high enable, low disabled.
VHIL
V
V
boost strap mode.
switch connection.
LOGIC
LOGIC
LX
DRVL
PGNDP
FBL
Gate driver output for external N-channel switch.
Power GND.
V
regulator voltage feedback pin; regulates to 1.2V nominal.
LOGIC
With resistor connected from this pin to GND sets the current limit of the external N-channel FET.
integrator output, connect 2.2nF to analog GND.
ILADJL
CINTL
ISADJL
VDC
V
LOGIC
Current feedback adjust for V
.
LOGIC
Positive supply for all internal analog circuits.
VDCP
NC
Positive supply for external N-Channel FET gate drives.
DRVP
NC
Positive LDO base drive; open drain of an internal N-Channel MOSFET.
ACGND
VREF
FBP
Low noise signal ground.
Bandgap voltage bypass terminal; bypass with a 0.1µF to analog GND; can be used as charge pump reference.
Positive LDO voltage feedback input pin; regulates to 1.2V nominal.
CC2
Supply input, connect to V .
IN
CDLY
CTL
With a capacitor connect from this pin to GND, sets the delay time for start-up sequence and fault detection timeout.
Input control for switch output.
ENL
Enable pin for V
high enable; low disabled.
LOGIC
DRN
Lower reference voltage for switch output.
COM
Switch output; when CTL = 1, COM is connected to SRC through a 15Ω resistor, when CT: = 0, COM is connected
to DRN through a 30Ω resistor.
38
SRC
Upper reference voltage for switch output.
FN7445.0
December 13, 2006
8
ISL97522
Typical Application Diagram
D11
D21
V
N
V
P
C11
C24
C25
0.1µF
0.1µF
0.1µF
D1
V
BOOST
L1 6.8µH
15V
Q3
V
A
VDD
IN
C16
0.01µF
C9
0.01µF
C2
FX3
R9
1MΩ
I
ON
R8
300k
R2
140k
10µFX2
V
ISINB
IN
VSW
C30
4.7NF
R10 10kΩ
DRVB
C1
CINTB
Q1
BOOST
I
R20 30k
R19 30k
SADJB
CONTROLLER
R1
I
FBB
LADJB
12k
V
VHIB
DCP
V
-8V
DCP
V
C23
4.7µF
Q21
N
INTERNAL
SUPPLY
V
OFF
V
DC
R3
3k
DRVN
FBN
C20
4.7µF
R22
104k
C24
4.7µF
V
LDO
LDO
OFF
POWER ON
SEQUENCING
CDLY
R21 20k
Q11
V
REF
C7
220nF
C25
1µF
25V
V
P
EN
V
ON
R4
3k
C15
1µF
R29
10k
DRVP
FBP
R12
237k
V
ON
VCC2
R23
1k
R11
12k
CTL
SRC
COM
DRN
V
CONTROL
INPUT
R22
68k
V
SLICE
TO GATE DRIVER
R21
ON
DELB
FAULT
PROTECTION
V
SW
C32
100nF
L2
Q2
IN
V
LOGIC
VCCL
ENL
CLOCK/
TIMING
6.8µF
R12
210k
DRVL
LX
C3
D2
10µFX4F
R28
10k
PGNDB
PGNDP
ACGND
FBL
VHIL
R13
118k
BUCK
CONTROLLER
C28
0.47µ
R15 30k
ISADJL
CINTL
C27
4.7nF
R17 2kΩ
ILADJL
R16 30k
FN7445.0
December 13, 2006
9
ISL97522
A
Converter
Applications Information
VDD
The main boost converter is a current mode PWM controller
operating at a fixed frequency. The 1MHz switching
frequency enables the use of low profile inductor and
multilayer ceramic capacitors, which results in a compact,
low-cost power system for LCD panel design.
The ISL97522 provides a multiple output power supply
solution for TFT-LCD applications. The system consists of a
high efficiency boost controller, two low cost linear-regulator
controllers (V
and V
) and a buck reglator (V
).
LOGIC
ON
OFF
Table 1 below lists the recommended components.
The A
VDD
converter can operate in continuous or
TABLE 1. RECOMMENDED COMPONENTS
discontinuous inductor current mode. The ISL97522 is
designed for continuous current mode, but it can also
operate in discontinuous current mode at light load. In
continuous current mode, current flows continuously in the
inductor during the entire switching cycle in steady state
operation. The voltage conversion ratio in continuous current
mode is given by (in boost mode):
DESIGNATION
DESCRIPTION
C1, C2, C3
10µF, 16V, X7R ceramic capacitor (1206)
TDK C3216X7R1C106M
C20
C15
D1
4.7µF, 16V X5R ceramic capacitor (1206)
TDK C3216X5R1A475K
1µF, 25V X7R ceramic capacitor (1206)
TDK C3216X7R1E105K
A
1
VDD
(EQ. 1)
---------------
-------------
=
V
1 – D
IN
1A 20V low leakage schottky rectifier (CASE
457-04) ON SEMI MBRM120ET3
where D is the duty cycle of switching MOSFET.
D11, D12, D21 200mA 30V schottky barrier diode (SOT-23)
Fairchild BAT54S
Figure 15 shows the function diagram of the boost controller.
It uses a summing amplifier architecture consisting of GM
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
L1
6.8mH 4.6A inductor
Coilcraft DO3316P-682ML
Q1,Q2
6.3A 30V single N-Channel logic level
PowerTrench MOSFET (SOT-23)
Fairchild FDC655AN
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 200kΩ is
Q3
-2A -30V single P-Channel logic level
PowerTrench MOSFET (SuperSOT-3)
Fairchild FDN360P
Q11
Q21
200mA 40V PNP amplifier (SOT-23)
Fairchild MMBT3906
200mA 40V NPN amplifier (SOT-23)
Fairchild MMBT3904
recommended. The boost converter output voltage is
determined by the following equation:
R
+ R
2
R
1
1
(EQ. 2)
--------------------
A
=
× V
VDD
FBB
FN7445.0
December 13, 2006
10
ISL97522
V
IN
V
REF
REFERENCE
GENERATOR
OSCILLATOR
SLOPE
COMPENSATION
OSC
V
BOOST
PWM
LOGIC
CONTROLLER
DRVB
Σ
BUFFER
I
I
SADJ
FBB
GM
AMPLIFIER
SIN
CINTB
CURRENT
AMPLIFIER
SHUTDOWN
& STARTUP
CONTROL
CURRENT
LIMIT REF
GENERATOR
I
LADJ
UVLO
COMPARATOR
CURRENT LIMIT
COMPARATOR
FIGURE 15. FUNCTION DIAGRAM OF THE BOOST CONTROLLER
The internal current limit circuitry is shown in Figure 16. The
circuit senses the voltage across the R when the
DS(ON)
MOSFET is on; then compare it to the internal voltage
reference to realize the current limit. The internal voltage
reference is generated by a 10mA current and any additional
V
DD
LX
I
SINB
10µA
current set at I
pin flowing through an 8kΩ resistor.
The voltage reference is based on the following equation:
LADJB
-
LOGIC
CONTROLLER
V
⎛
⎜
⎝
⎞
ILADJB
R
1
-----------------------
(EQ. 3)
V
=
+ 10μA × 8K
⎟
+
THRESHOLD
V
⎠
REF
DRVB
1k
8k
Where V
Where V
is the voltage at pin I .
LADJ
ILADJB
I
LADJB
is the voltage at pin I
SAD
.
ISAD
R
1
V
= V
– V
– 1K × I
BE SAD
ISAD
REF
FIGURE 16. CURRENT LIMIT BLOCK DIAGRAM
V
ISAD
R1
(EQ. 4)
-----------------
I
=
SAD
Hence the maximum output current is determined by the
following equation:
Where V ≈ 0.7V
BE
V
ΔI
V
IN
V
O
⎛
⎜
⎝
THRESHOLD
L
⎞
⎠
(EQ. 5)
--------------------------------------- --------
---------
I
=
–
×
OMAX
The external resistor R should be chosen in the order of
1
100K to generate µA of current.
R
2
DSON
Where ΔI is the peak to peak inductor ripple current, and is
L
set by:
V
D
f
S
IN
(EQ. 6)
--------- ----
ΔI
=
×
L
L
FN7445.0
December 13, 2006
11
ISL97522
f
is the switching frequency; D is the duty cycle.
Boost Inductor
S
A 6.8µH inductor is recommended. The inductor must be
able to handle the following average and peak current:
V
– V
IN
V
O
O
(EQ. 7)
-----------------------
D =
I
O
(EQ. 8)
-------------
I
I
=
LAVG
1 – D
To overcome the variation in external LX driver R
, an
DS(ON)
input is provided (ILADJ) to accommodate 5 different bands
of R by using 5 different selection resistors. Internally,
ΔI
L
(EQ. 9)
--------
+
= I
LPK
LAVG
DS(ON)
2
the ILADJ resistor adjusts two things:
BOOST MOSFET
1.the current limit;
Due to the parasitic inductance of the trace, the MOSFET
will experience spikes higher that the output voltage when
the MOSFET turns off. Thus, a MOSFET with enough
voltage margin is needed.
2.the current feedback being used.
This keeps the dc-dc loop stable and the current limit the
same over a wide range of external drive FETs.
The R
of the MOSFET is critical for power dissipation
and current limit. A MOSFET with low R is desired to
DS(ON)
Alternatively, the current limit can be changed for the same
FET by varying the resistor. This would affect the stability of
the system somewhat (because the current feedback
changes) but be selected appropriately to accommodated
the change. The integrator loop should keep the load
regulation within limits as long as it doesn't run out of
dynamic adjustment range when current feedback gets
larger than intended. This could be determined by
DS(ON)
get high efficiency and output current, but very low R
DS(ON)
will reduce the loop stability. A MOSFET with 20mΩ to 50mΩ
is recommended. Some recommended MOSFETs
R
DS(ON)
are shown in Table 2.
TABLE 2. RECOMMENDED MOSFETs
PART
measuring how close to the upper clamp limit the voltage on
the Cint pin voltage gets under maximum load current.
NUMBER MANUFACTURER
FEATURE
FDC655AN
FDS4488
Fairchild
Semiconductor
6.3A, 30V, R
= 23mΩ
DS(ON)
Here are the resistor settings on ILADJ which select the five
R
ranges:
Fairchild
7.9A, 30V, R
= 22mΩ
DS(ON)
DS(ON)
Semiconductor
1/ 0ohms (Cfb factor 1, "Cfb" are the relative current
feedback factors)
Si7844DP
SI6928DQ
Vishay
Vishay
10A, 30V, R
20A, 30V, R
= 22mΩ
= 30mΩ
DS(ON)
DS(ON)
2/ 30K (Cfb factor 1/1.8)
3/ 83K (Cfb factor 1/3.3)
4/ 182K (Cfb factor 1/5.7)
5/ >370K (Cfb factor 1/10)
Rectifier Diode
A high-speed diode is desired due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The rectifier
diode must meet the output current and peak inductor
current requirements.
1/ sets maximum internal current feedback and minimum
ILimit, used for low Ron fets.
5/ sets minimum internal current feedback and maximum
ILimit, used for large Ron fets.
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage consists
of two components: the voltage drop due to the inductor ripple
current flowing through the ESR of output capacitor, and the
charging and discharging of the output capacitor.
The Current limit factors should be the inverse of the Cfb
values.
Input Capacitor
The input capacitor is used to supply the current to the
V
– V
I
O
1
f
S
O
IN
(EQ. 10)
----------------------- --------------- ----
V
= I
× ESR +
LPK
×
×
converter. It is recommended that C be larger than 10µF.
RIPPLE
IN
V
C
O
OUT
The reflected ripple voltage will be smaller with larger C
.
IN
The voltage rating of input capacitor should be larger than
maximum input voltage.
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
FN7445.0
December 13, 2006
12
ISL97522
controller function diagrams are shown in Figures 17,
PI mode C
(C ) and R )
(R
INT 23
INT 10
and 18, respectively.
The IC is designed to operate with a minimum C capacitor
of 4.7nF and a minimum C (effective) = 10µF.
23
A
VDD
ISINB
0.1µF
2
Note that, for high voltage A
ceramic capacitors (C ) reduces their effective capacitance
, the voltage coefficient of
VDD
LDO_ON
0.9V
2
greatly; a 16V 10µF ceramic can drop to around 3µF at 15V.
PG_LDOP
+
CP (TO 36V)
0.1µF
36V
ESD
CLAMP
To improve the transient load response of A
VDD
in PI mode,
-
R
BP
3kΩ
a resistor may be added in series with the C capacitor. The
23
larger the resistor the lower the overshoot but at the expense
of stability of the converter loop - especially at high currents.
DRVP
FBP
V
(TO 35V)
ON
R
R
P1
P2
With L = 10µH, A
VDD
= 15V, C = 4.7nF, C (effective)
23
2
C
ON
should have a capacitance of greater than 10µF. R
(R )
INT
7
+
-
GMP
can have values up to 5kΩ for C (effective) up to 20µF and
2
up to 10K for C (effective) up to 30µF.
2
1 : Np
Larger values of R
A
(R ) may be possible if maximum
7
INT
load currents less than the current limit are used. To
VDD
ensure A
stability, the IC should be operated at the
VDD
maximum desired current and then the transient load
response of A should be used to determine the
FIGURE 17. V
FUNCTION BLOCK DIAGRAM
ON
VDD
maximum value of R
Calculation of the Linear Regulator Base-Emitter
Resistors ( R and R
INT
)
BN
BP
For the pass transistor of the linear regulator, low frequency
Operation of the DELB Output Function
An open drain DELB output is provided to allow the boost
output voltage, developed at C (see application diagram),
to be delayed via an external switch (Q3) to a time after the
gain (Hfe) and unity gain freq. (f ) are usually specified in the
datasheet. The pass transistor adds a pole to the loop transfer
function at f = f /Hfe. Therefore, in order to maintain phase
margin at low frequency, the best choice for a pass device is
often a high frequency low gain switching transistor. Further
improvement can be obtained by adding a base-emitter resistor
T
2
p
T
V
supply and negative V
charge pump supply
OFF
BOOST
have achieved regulation during the start-up sequence
shown in Figure 21. This then allows the A and V
VDD ON
supplies to start-up from 0V instead of the normal offset
R
(R , R , R in the Functional Block Diagram), which
BE BP BL BN
voltage of V -V (D ) if Q3 were not present.
IN DIODE
1
increase the pole frequency to: f = f *(1+ Hfe *re/R )/Hfe,
p
T
BE
where re = KT/qIc. So choose the lowest value R in the
design as long as there is still enough base current (I ) to
B
When DELB is activated by the start-up sequencer, it sinks
50µA allowing a controlled turn-on of Q3 and charge-up of
C . C can be used to control the turn-on time of Q3 to
BE
support the maximum output current (I ).
C
9
16
reduce inrush current into C . The potential divider formed
9
We will take as an example the V
ON
linear regulator. If a
Fairchild MMBT3906 PNP transistor is used as the external pass
by R and R can be used to limit the V voltage of Q3 if
9
8
GS
required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.
transistor, Q11 in the application diagram, then for a maximum V
operating requirement of 50mA the data sheet indicates HFE_min =
30.
ON
The base-emitter saturation voltage is: Vbe_max = 0.7V.
The voltage at DELB is monitored by the fault protection
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
For the ISL97522, the minimum drive current is:
I_DRVP_min = 2mA.
The minimum base-emitter resistor, R , can now be
BP
ramp will be initiated on the C
capacitor (C ).
7
calculated as:
DEL
Linear-Regulator Controllers (V , V
)
R
_min = V _max/(I_DRVP_min - Ic/Hfe_min) =
BP BE
ON OFF
0.7V/(2mA - 50mA/30) = 2.1kΩ
The ISL97522 includes two independent linear-regulator
controllers, in which one is a positive output voltage (V ),
ON
linear-regulator
This is the minimum value that can be used - so, we now
choose a convenient value greater than this minimum value;
say 3KΩ. Larger values may be used to reduce quiescent
current, however, regulation may be adversely affected, by
and one is negative. The V
and V
OFF
ON
supply noise if R is made too high in value.
BP
FN7445.0
December 13, 2006
13
ISL97522
Set-Up LDOs Output Voltage
Refer to Typical Application Diagram, the output voltages of
ISINB
0.1µF
V
, V
, and V
are determined by Equations 11
ON OFF
LOGIC
and 12:
CP (TO -26V)
0.1µF
R
⎛
⎞
⎟
⎠
12
(EQ. 11)
---------
V
V
= V
× 1 +
⎜
ON
FBP
LDO_OFF
R
⎝
V
11
REF
PG_LDON
0.4V
-
+
R
22
R
N2
(EQ. 12)
---------
= V
+
× (V
– V
)
REF
OFF
FBN
FBN
R
21
FBN
Charge Pump
To generate an output voltage higher than A
multi stages of charge pumps are needed. The number of
stage is determined by the input and output voltage. For
positive charge pump stages:
1 : Nn
R
N1
, single or
VDD
V
(TO -20V)
OFF
-
+
DRVN
C
OFF
GMN
R
BN
36V
ESD
CLAMP
3kΩ
V
+ V
– V
CE INPUT
– 2 × V
F
OUT
V
(EQ. 13)
-------------------------------------------------------------
≥
N
POSITIVE
INPUT
FIGURE 18. V
FUNCTION BLOCK DIAGRAM
where V
is the dropout voltage of the pass component of
the linear regulator. It ranges from 0.3V to 1V depending on
OFF
CE
The V
ON
power supply is used to power the positive supply
the transistor. V is the forward-voltage of the charge pump
rectifier diode.
F
of the row driver in the LCD panel. The DC/DC consists of an
external diode-capacitor charge pump powered from the
switch node (LXB) of the A
The number of negative charge pump stages is given by:
converter, followed by a low
VDD
dropout linear regulator (LDO_ON). The LDO_ON regulator
uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz)
V
+ V
CE
– 2 × V
F
OUTPUT
(EQ. 14)
------------------------------------------------
≥
N
NEGATIVE
V
INPUT
To achieve high efficiency and low material cost, the lowest
number of charge pump stages, which can meet the above
requirements, is always preferred.
transconductance amplifier capable of 5mA output current,
which is sufficient for up to 50mA or more output current
under the low dropout condition (forced beta of 10). Typical
V
voltage supported by the ISL97522 ranges from +15V
ON
Charge Pump Output Capacitors
to +36V. A fault comparator is also included for monitoring
the output voltage. The undervoltage threshold is set at
16.7% below the 1.2V reference.
A ceramic capacitor with low ESR is recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by Equation 15.
The V
OFF
power supply is used to power the negative
supply of the row driver in the LCD panel. The DC/DC
consists of an external diode-capacitor charge pump
I
OUT
(EQ. 15)
------------------------------------------------------
C
≥
OUT
2 × V
× f
OSC
RIPPLE
powered from the switch node (LXB) of the A
VDD
converter,
followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the
pass element. The onboard LDO controller is a wide band
(>10MHz) transconductance amplifier capable of 5mA
output current, which is sufficient for up to 50mA or more
output current under the low dropout condition (forced beta
Where f
is the switching frequency.
SOC
High Charge Pump Output Voltage (>36V)
Applications
In the applications where the charge pump output voltage is
over 36V, an external npn transistor need to be inserted into
between DRVP pin and base of pass transistor Q3 as shown
in Figure 19; or the linear regulator can control only one
stage charge pump and regulate the final charge pump
output as shown in Figure 20.
of 10). Typical V
voltage supported by the ISL97522
OFF
ranges from -5V to -25V. A fault comparator is also included
for monitoring the output voltage. The undervoltage
threshold is set at 20% above the 1.0V reference level.Set-
Up LDOs Output Voltage.
FN7445.0
December 13, 2006
14
ISL97522
The following equation gives the boundary between
discontinuous and continuous boost operation. For continuous
operation (LX switching every clock cycle) we require that:
CHARGE PUMP
OUTPUT
VDD
V
IN
OR A
I(A
_load) > D*(1-D)*V /(2*L*F
IN
)
OSC
VDD
3kΩ
where the duty cycle, D = (A
VDD
- V )/A
IN VDD
Q3
DRVP
NPN
CASCODE
TRANSISTOR
For example, with V = 5V, F
IN OSC
12V we find continuous operation of the boost converter can
be guaranteed for:
= 1.0MHz and A
=
VDD
V
ON
ISL97522
L = 10µH and I(A
) > 61mA
) > 89mA
VDD
L = 6.8µH and I(A
L = 3.3µH and I(A
FBP
VDD
) > 184mA
VDD
Buck Converter
The buck converter is the step down converter, which
supplies the current to the logic circuit of the LCD system. In
the continuous current mode, the relationship between input
voltage and output voltage is as following:
FIGURE 19. CASCODE NPN TRANSISTOR CONFIGURATION
FOR HIGH CHARGE PUMP OUTPUT VOLTAGE
(>36V)
LX
0.1µF
V
LOGIC
A
(EQ. 16
VDD
-------------------
= D
0.1µF
V
IN
3kΩ
0.1µF
0.1µF
DRVP
Q3
V
ON
Where D is the duty cycle of the switching MOSFET.
Because D is always less than 1, the output voltage of buck
converter is lower than input voltage.
0.47µF
(>36V)
0.1µF
ISL97522
0.22µF
The Feedback Resistors
FBP
The buck converter output voltage is determined by the
following equation:
R
+ R
13
(EQ. 17)
12
--------------------------
V
=
× V
FBL
FIGURE 20. THE LINEAR REGULATOR CONTROLS ONE
STAGE OF CHARGE PUMP
LOGIC
R
13
Where R12 and R13 are the feedback resistors of buck
converter to set the output voltage Current drawn by the
resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
potential for noise being coupled into the feedback pin. A
resistor network in the order of 300Ω is recommended.
Discontinuous/Continuous Boost Operation and
its Effect on the Charge Pumps
The ISL97522 V
and V
architecture uses LX
OFF
ON
switching edges to drive diode charge pumps from which
LDO regulators generate the V and V supplies. It can
ON
OFF
be appreciated that should a regular supply of LX switching
edges be interrupted, for example during discontinuous
Buck Converter Input Capacitor
operation at light A
VDD
affect the performance of V
boost load currents, then this may
and V regulation -
The capacitor should support the maximum AC RMS current
which happens when D = 0.5 and maximum output current.
ON
OFF
depending on their exact loading conditions at the time.
(EQ. 18)
I
(C ) = D ⋅ (1 – D) ⋅ I
O
To optimize V /V regulation, the boundary of
acrms IN
ON OFF
discontinuous/continuous operation of the boost converter
can be adjusted, by suitable choice of inductor given V
,
Where I is the output current of the buck converter.
IN
current loading, to
O
V
, switching frequency and the A
OUT VDD
be in continuous operation.
FN7445.0
December 13, 2006
15
ISL97522
Buck Inductor
minimum load can be adjusted by the feedback resistors
to FBL.
An inductor value in the range 3.3-10µH is recommended for
the buck converter. Besides the inductance, the DC
resistance and the saturation current should also be
considered when choosing buck inductor. Low DC
resistance can help maintain high efficiency, and the
saturation current rating should be at least maximum output
current plus half of ripple current.
The bootstrap capacitor can only be charged when the
higher side MOSFET is off. If the load is too light which can
not make the on time of the low side diode be sufficient to
replenish the boot strap capacitor, the MOSFET can’t turn
on. Hence there is minimum load requirement to charge the
bootstrap capacitor properly.
Buck MOSFET
Start-Up Sequence
Figure 21 shows a detailed start-up sequence waveform. For
The principle to select Buck MOSFET is similar to that of
Boost. The voltage of stress of buck converter should be
maximum input voltage plus reasonable margin, and the
current rating should be over the maximum output current.
a successful power-up, there should be six peaks at V
.
CDLY
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
The r
20mΩ to 50mΩ.
of this MOSFET should be in the range from
DS(ON)
If EN is L, the device is powered down. If EN is H, and the
input voltage (V ) exceeds 2.5V, an internal current source
IN
starts to charge C
to an upper threshold using a fast
DLY
ramp followed by a slow ramp. If EN is low at this point, the
ramp will be delayed until EN goes high.
Rectifier Diode (Buck Converter)
A Schottky diode is recommended due to fast recovery and
low forward voltage. The reverse voltage rating should be
higher than the maximum input voltage. The average current
should be as the following equation,
C
DLY
The first four ramps on C
(two up, two down) are used to
DLY
initialize the fault protection switch and to check whether
there is a fault condition on C or V . If a fault is
DLY REF
(EQ. 19)
I
= (1 – D)*I
O
detected, the outputs and the input protection will turn off
AVG
and the chip will power down.
Where I is the output current of buck converter.
O
If no fault is found, C
CDLY
continues ramping up and down
until the sequence is completed.
Output Capacitor (Buck Converter)
During the second ramp, the device checks the status of
Four 10µF or two 22µF ceramic capacitors are
V
and over temperature.
REF
recommended for this part. The overshoot and undershoot
will be reduced with more capacitance, but the recovery time
will be longer.
Initially the boost is not enabled so V
rises to V -
IN
BOOST
through the output diode. Hence, there is a step at
V
V
DIODE
during this part of the start-up sequence. If this step
BOOST
PI Loop Compensation (Buck Converter)
is not desirable, an external PMOS FET can be used to delay
the output until the boost is enabled internally. The delayed
The buck converter of ISL97522 can be compensated by a
RC network connected from CINTL pin to ground. C27 =
4.7nF and R17= 2k RC network is used in the demo board.
The larger value resistor can lower the transient overshoot,
however, at the expense of stability of the loop.
output appears at A
.
VDD
V
soft-starts at the beginning of the third ramp. The
BOOST
soft-start ramp depends on the value of the C
capacitor.
DLY
of 220nF, the soft-start time is ~2ms.
For C
DLY
turns on at the start of the fourth peak. At the fifth
The stability can be optimized in a similar manner to that
described in the section on "PI Loop Compensation (Boost
Converter)”.
V
OFF
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q3 to generate a delayed V output.
BOOST
Bootstrap Capacitor (C28)
V
V
is enabled at the beginning of the sixth ramp. A
, DELB and V
OFF ON
,
ON
VDD
are checked at end of this ramp.
This capacitor is used to provide the supply to the high driver
circuitry for the buck MOSFET. The bootstrap supply is
formed by an internal diode and capacitor combination. A
1µF is recommended for ISL97522. A low value capacitor
can lead to overcharging and in turn damage the part.
Vlogic’s start-up is controlled by ENL. When ENL is L, Vlogic
is off, and when ENL is H, V is on.
LOGIC
If the load is too light, the on-time of the low side diode may
be insufficient to replenish the bootstrap capacitor voltage. In
this case, if V -V
< 1.5V, the internal MOSFET pull-up
device may be unable to turn-on until V falls. Hence,
IN BUCK
LOGIC
there is a minimum load requirement in this case. The
FN7445.0
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ISL97522
V
CDLY
EN
ENL
V
LOGIC
V
REF
V
BOOST
t
ON
t
OS
V
OFF
t
DEL1
DELAYED
V
BOOST
t
DEL2
V
ON
V
SLICE
ON
START-UP SEQUENCE
TIMED BY C
DLY
FIGURE 21. ISL97522 START-UP SEQUENCE
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ISL97522
Fault Protection
Component Selection for Start-Up Sequencing and
Fault Protection
The C capacitor is typically set at 220nF and is required
During the startup sequence, prior to BOOST soft-start,
V
is checked to be within ±20% of its final value and the
REF
REF
to stabilize the V
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
output. The range of C
is from
REF
REF
22nF to 1µF and should not be more than five times the
capacitor on C to ensure correct start-up operation.
DEL
capacitor is typically 220nF and has a usable
If C
DELAY
is shorted low, then the sequence will not start,
is shorted H, the first down ramp will not
The C
DEL
while if C
range from 47nF minimum to several microfarads - only
DELAY
occur and the sequence will not complete.
limited by the leakage in the capacitor reaching µA levels.
Once the start-up sequence is completed, the chip
C
should be at least 1/5 of the value of C
(See
the fault time-out will be
DEL
above). Note with 220nF on C
REF
continuously monitors C
, DELB, FBP, FBL, FBN, V
DLY
REF
DEL
and FBB for faults. During this time, the voltage on the C
capacitor remains at 1.15V until either a fault is detected, or
the EN pin is pulled low.
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1µF will give a fault time-out
period of typically 230ms).
DLY
A fault on C
, V or temperature will shut down the
DELAY REF
Fault Sequencing
chip immediately. If a fault on any other output is detected,
will ramp up linearly with a 5µA (typical) current to
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
The ISL97522 has an advanced fault detection system
which protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
C
DELAY
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
the voltage on the C
capacitor returns to 1.15V.
DLY
Typical fault thresholds for FBP, FBL, FBN and FBB are
included in the tables. DELB fault threshold is typically 0.6V.
C
and C have an internal current-limited clamp to
INTL
INTB
keep the voltage within their normal ranges. If they are
shorted low, the regulators will attempt to regulate to 0V.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of 140°C, the device will shut
down.
If any of the regulated outputs (AVDD, V , V
ON OFF
or
V
) are driven above their target levels the drive
LOGIC
circuitry will switch off until the output returns to its expected
value.
Layout Recommendation
If AVDD and V
are excessively loaded, the current
LOGIC
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
limit will prevent damage to the chip. While in current limit,
the part acts like a current source and the regulated output
will drop. If the output drops below the fault threshold, a
ramp will be initiated on C
is sustained, the chip will be disabled on completion of the
and, provided that the fault
DELAY
There are some general guidelines for layout:
ramp.
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
In some circumstances, (depending on ambient temperature
and thermal design of the board), continuous operation at
current limit may result in the over-temperature threshold
being exceeded, which will cause the part to disable
immediately.
2. Place V
, V
REF DC
and V bypass capacitors close to
DCP
the pins.
All I/O also have ESD protection, which in many cases will
also provide overvoltage protection, relative to either ground
3. Minimize the length of traces carrying fast signals and
high current.
or V . However, these will not generally operate unless
abs max ratings are exceeded.
DD
4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
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ISL97522
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for feedback resistor networks (R , R
,
1
11
R
) and the V
capacitor, C , the C capacitor
41
REF
25 DELAY
C and the integrator capacitor C , C
.
7
30 27
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
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ISL97522
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L38.5x7B (One of 10 Packages in MDP0046)
38 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
SYMBOL
MIN
0.80
0.00
NOMINAL
0.90
MAX
1.00
0.05
NOTES
B
A
A1
D
-
0.02
-
1
2
3
5.00 BSC
3.50 REF
7.00 BSC
5.50 REF
0.40
-
PIN #1
I.D. MARK
D2
E
-
E
-
E2
L
-
0.35
0.23
0.45
0.27
-
2X
0.075 C
b
0.25
-
2X
0.075 C
c
0.20 REF
0.50 BSC
38 REF
7 REF
-
TOP VIEW
e
-
N
4
0.10 M C A B
b
ND
NE
6
12 REF
5
L
PIN #1 I.D.
Rev 0 5/06
3
NOTES:
1
2
3
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
(E2)
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
5
NE
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
(D2)
BOTTOM VIEW
0.10 C
e
C
(c)
2
SEATING
PLANE
A
C
0.08 C
(L)
SEE DETAIL "X"
N LEADS
& EXPOSED PAD
A1
DETAIL X
N LEADS
SIDE VIEW
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN7445.0
December 13, 2006
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