ISL97536 [INTERSIL]
Monolithic 1A Step-Down Regulator with Low Quiescent Current; 单片1A降压型稳压器具有低静态电流
| 型号： | ISL97536 |
| 厂家： | 
Intersil |
| 描述： | Monolithic 1A Step-Down Regulator with Low Quiescent Current |
| 文件： | 总9页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97536
®
Data Sheet
October 5, 2006
FN6279.0
Monolithic 1A Step-Down Regulator with
Low Quiescent Current
Features
2
• Less than 0.15in footprint for the complete 1A converter
• Components on one side of PCB
The ISL97536 is a synchronous, integrated FET 1A
step-down regulator with internal compensation. It operates
with an input voltage range from 2.5V to 6V, which
accommodates supplies of 3.3V, 5V, or a Li-Ion battery
• Max height 1.1mm MSOP10
• 100ms Power-On-Reset output (POR)
• Internally-compensated voltage mode controller
• Up to 95% efficiency
source. The output can be externally set from 0.8V to V
with a resistive divider.
IN
The ISL97536 features PWM control with a 1.4MHz typical
switching frequency. The typical no load quiescent current is
only 500µA. Additional features include a 100ms Power-On-
Reset output, <1µA shutdown current, short-circuit
protection, and over-temperature protection.
• <1µA shutdown current
• 500µA quiescent current
• Hiccup mode overcurrent and over-temperature protection
• Pb-free plus anneal available (RoHS compliant)
The ISL97536 is available in the 10 Ld MSOP package,
2
making the entire converter occupy less than 0.15in of PCB
Applications
area with components on one side only. The 10 Ld MSOP
package is specified for operation over the full -40°C to
+85°C temperature range.
• PDA and pocket PC computers
• Bar code readers
Ordering Information
• Cellular phones
• Portable test equipment
• Li-Ion battery powered devices
• Small form factor (SFP) modules
PART
NUMBER
PART
MARKING REEL
TAPE &
PKG.
PACKAGE DWG. #
ISL97536IUZ
(Note)
7536Z
-
10 Ld MSOP MDP0043
(Pb-free)
ISL97536IUZ-TK 7536Z
(Note)
13”
10 Ld MSOP MDP0043
Pinout and Typical Application Diagram
(1k pcs) (Pb-free)
ISL97536
(10 LD MSOP)
TOP VIEW
ISL97536IUZ-T 7536Z
(Note)
13”
10 Ld MSOP MDP0043
(2.5k pcs) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
R *
2
100kΩ
1
2
3
4
5
SGND
PGND
LX
FB 10
C
R *
4
1
124kΩ
VO
POR
EN
9
8
7
6
C
10µF
C
2
1
470pF
POR
L
1
10µF
1.8µH
V
(1.8V@600mA)
O
VIN
EN
R
3
V
(2.5V-6V)
S
100Ω
VDD
RSI
RSI
R
C
3
0.1µF
6
100kΩ
R
R
4
5
100kΩ
100kΩ
* V = 0.8V * (1 + R /R )
O
1
2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97536
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
V
, V , PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
IN DD
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
130
JA
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V + +0.3V)
SYNC, EN, V , FB to SGND. . . . . . . . . . . . . -0.3V to (V + +0.3V)
IN
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
IN
MSOP10 Package . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V
= V = V
IN
= 3.3V, C1 = C2 = 10µF, L = 1.8µH, V = 1.8V (as shown in Typical Application Diagram),
EN O
DD
= -40°C to +85°C unless otherwise specified.
T
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
DC CHARACTERISTICS
V
Feedback Input Voltage
790
800
810
250
6
mV
nA
V
FB
I
Feedback Input Current
Input Voltage
FB
V
V
V
, V
2.5
2
IN DD
IN,OFF
IN,ON
Minimum Voltage for Shutdown
Maximum Voltage for Start-up
Supply Current
V
V
V
falling, T = +25°C only
2.2
2.4
500
3
V
IN
IN
IN
A
rising, T = +25°C only
2.2
V
A
I
= V
= 5V
DD
400
0.1
70
µA
µA
mΩ
mΩ
A
DD
EN = 0, V = V
IN
= 5V
DD
R
R
PMOS FET Resistance
NMOS FET Resistance
Current Limit
V
= 5V, T = +25°C
DS(ON)-PMOS
DS(ON)-NMOS
LMAX
DD
DD
A
V
= 5V, T = +25°C
45
A
I
1.5
145
130
T
Over-temperature Threshold
Over-temperature Hysteresis
EN, RSI Current
T rising
T falling
°C
°C
µA
V
OT,OFF
OT,ON
T
I
, I
EN RSI
V
V
V
V
V
, V
EN RSI
= 0V and 3.3V
-1
0.8
86
1
V
V
V
, V
EN1 RSI1
EN, RSI Rising Threshold
EN, RSI Falling Threshold
= 3.3V
= 3.3V
rising
2.4
DD
DD
, V
V
EN2 RSI2
Minimum V for POR, WRT Targeted
FB
95
70
%
POR
FB
V
Value
FB
falling
%
FB
V
POR Voltage Drop
I
= 3.3mA
35
mV
OLPOR
SINK
AC CHARACTERISTICS
F
PWM Switching Frequency
Minimum RSI Pulse Width
Soft-Start Time
1.25
80
1.4
25
1.6
50
MHz
ns
PWM
t
t
t
Guaranteed by design
RSI
650
100
µs
SS
Power On Reset Delay Time
120
ms
POR
FN6279.0
October 5, 2006
2
ISL97536
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
2
SGND
PGND
LX
Negative supply for the controller stage
Negative supply for the power stage
3
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
Power supply for the controller stage
Resets POR timer
5
VDD
RSI
6
7
EN
Enable
8
POR
VO
Power on reset open drain output
Output voltage sense
9
10
FB
Voltage feedback input; connected to an external resistor divider between V and SGND for variable
O
output
Block Diagram
100Ω
V
V
DD
O
INDUCTOR SHORT
0.1µF
+
-
10pF
V
IN
C4 124k
470pF
CURRENT
SENSE
FB
5M
-
+
PWM
COMPEN-
SATION
+
-
PWM
P-DRIVER
100k
COMPARATOR
1.8µH
LX
RAMP
GENERA-
TOR
PFM
ON-TIME
CONTROL
CONTROL
LOGIC
1.8V
0 TO 1A
CLOCK
EN
EN
SOFT-
START
+
-
10µF
10µF
PWM
N-DRIVER
COMPARATOR
UNDER-
VOLTAGE
LOCKOUT
+
5V
PGND
POR
BANDGAP
REFERENCE
–
+
-
100k
TEMPERATURE
SENSE
SYNCHRONOUS
RECTIFIER
POR
SGND
RSI
POR
FN6279.0
October 5, 2006
3
ISL97536
Performance Curves and Waveforms
All waveforms are taken at V = 3.3V, V = 1.8V, I = 600mA with component values shown on page 1 at room ambient temperature, unless
IN
O
O
otherwise noted.
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
V
= 3.3V
O
V
= 2.5V
O
V
= 2.5V
O
V
= 1.8V
V
O
V
= 1.8V
O
= 1.2V
O
V
= 1.2V
O
0
0
200
400
600
(mA)
800
1000
0
200
400
600
(mA)
800
1000
I
I
O
O
FIGURE 2. EFFICIENCY vs I AT 3.3V
FIGURE 1. EFFICIENCY vs I AT 5V V
O
O
IN
0
200
400
600
800
1000
1200
0.2
0
200.2
400.2
600.2
800.2 1000.2 1200.2
= 3.3V
0
V
O
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
V
= 2.5V
O
V
= 1.8V
O
V
= 2.5V
O
V
= 1.8V
O
V
= 1.2V
O
V
= 1.2V
O
-1.2
-1.2
I
(mA)
I
(mA)
O
O
FIGURE 3. LOAD REGULATION vs I AT 5V V
FIGURE 4. LOAD REGULATION vs I AT 3.3V V
O IN
O
IN
2
3
4
5
6
12
10
8
-0.05
-0.1
-0.15
-0.2
6
4
2
0
V
= 1.2V
-0.25
-0.3
O
V
= 1.8V
O
-0.35
3.5
4
4.5
5
2.5
3
V
(V)
IN
V
(V)
S
FIGURE 6. NO LOAD QUIESCENT CURRENT
FIGURE 5. LINE REGULATION vs V
IN
FN6279.0
October 5, 2006
4
ISL97536
Performance Curves and Waveforms (Continued)
All waveforms are taken at V = 3.3V, V = 1.8V, I = 600mA with component values shown on page 1 at room ambient temperature, unless
IN
O
O
otherwise noted.
LX
(2V/DIV)
V
OUT
I
L
(0.5A/DIV)
V
IN
∆V
O
(10mV/DIV)
I
IN
0.5µs/DIV
FIGURE 8. PWM STEADY-STATE OPERATION (I = 600mA)
O
FIGURE 7. START-UP AT I = 600mA
O
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
(2V/DIV)
LX
(2V/DIV)
I
L
(0.5A/DIV)
I
L
(0.5A/DIV)
20ns/DIV
0.2µs/DIV
FIGURE 9. EXTERNAL SYNCHRONIZATION TO 2MHz
FIGURE 10. EXTERNAL SYNCHRONIZATION TO 12MHz
I
O
I
(200mA/DIV)
O
(200mA/DIV)
∆V
O
∆V
(100mV/DIV)
O
(100mV/DIV)
50µs/DIV
100µs/DIV
FIGURE 12. LOAD TRANSIENT RESPONSE
(30mA TO 600mA)
FIGURE 11. LOAD TRANSIENT RESPONSE (22mA TO 600mA)
FN6279.0
October 5, 2006
5
ISL97536
Performance Curves and Waveforms (Continued)
All waveforms are taken at V = 3.3V, V = 1.8V, I = 600mA with component values shown on page 1 at room ambient temperature, unless
IN
O
O
otherwise noted.
1
0.6
0.2
0
100
12MHz
1.4MHz
12MHz
80
60
40
20
1.4MHz
5MHz
5MHz
-0.2
-0.6
0
0
0
200
400
600
(mA)
800
1K
1.2K
200
400
600
(mA)
800
1K
1.2K
I
O
I
O
FIGURE 13. EFFICIENCY vs I
FIGURE 14. LOAD REGULATION
O
PG
0.5
0.3
0.1
12MHz
I
L
1.4MHz
-0.1
-0.3
-0.5
V
O
5MHz
1K
0
200
400
600
(V)
800
1.2K
V
IN
FIGURE 16. OVERCURRENT SHUTDOWN
FIGURE 15. LINE REGULATION @ 500mA
PG
I
L
V
O
FIGURE 17. OVERCURRENT HICCUP MODE
FN6279.0
October 5, 2006
6
ISL97536
average power dissipation is reduced, thereby reducing the
likelihood of damage current and thermal conditions in the IC.
Applications Information
Product Description
700µ ⋅ V
IN
⎛
⎞
(EQ. 1)
The ISL97536 is a synchronous, integrated FET 1A
step-down regulator which operates from an input of 2.5V to
6V. The output voltage is user-adjustable with a pair of
external resistors.
tHICCUP ≈ --------------------------- + 216µ
⎝
⎠
3
Thermal Shutdown
Once the junction reaches about 145°C, the regulator shuts
down. Both the P-channel and the N-channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will cool down. Once the
junction temperature drops to about 130°C, the regulator will
perform a normal restart.
The internally-compensated controller makes it possible to
use only two ceramic capacitors and one inductor to form a
complete, very small footprint 1A DC:DC converter.
PWM Operation
In PWM switching mode, the P-channel MOSFET and
N-channel MOSFET always operate complementary. When
the P-channel MOSFET is on and the N-channel MOSFET
off, the inductor current increases linearly. The input energy
is transferred to the output and also stored in the inductor.
When the P-channel MOSFET is off and the N-channel
MOSFET on, the inductor current decreases linearly, and
energy is transferred from the inductor to the output. Hence,
the average current through the inductor is the output
current. Since the inductor and the output capacitor act as a
low pass filter, the duty cycle ratio is approximately equal to
Thermal Performance
The ISL97536 is available in a fused-lead MSOP10.
Compared with regular MSOP10 package, the fused-lead
package provides lower thermal resistance. The θ is
JA
+100°C/W on a 4-layer board and +125°C/W on 2-layer
board. Maximizing the copper area around the pins will
further improve the thermal performance.
RSI/POR Function
When powering up, the open-collector Power-On-Reset
V
divided by V .
IN
output holds low for about 100ms after V reaches the
O
O
preset voltage. When the active-HI reset signal RSI is
issued, POR goes to low immediately and holds for the
same period of time after RSI comes back to LOW. The
output voltage is unaffected. (Please refer to the timing
diagram). When the function is not used, connect RSI to
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 40µF ceramic and
inductor is 1.5µH to 2.2µH.
ground and leave open the pull-up resister R at POR pin.
4
The POR output also serves as a 100ms delayed Power
Good signal when the pull-up resister R is installed. The
RSI pin needs to be directly (or indirectly through a resister
4
Start-Up and Shutdown
When the EN pin is tied to V , and V reaches
R ) connected to Ground for this to function properly.
IN
IN
6
approximately 2.4V, the regulator begins to switch. The
inductor current limit is gradually increased to ensure proper
soft-start operation.
V
O
When the EN pin is connected to a logic low, the ISL97536 is
in the shutdown mode. All the control circuitry and both
MIN
25ns
RSI
MOSFETs are off, and V
falls to zero. In this mode, the
OUT
total input current is less than 1µA.
100ms
100ms
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
POR
FIGURE 18. RSI AND POR TIMING DIAGRAM
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop as load demand
increases. When the output voltage drops 30mV below the
reference voltage, the converter will shutdown for a period of
time, approximated by Equation 1, and then restart. If the
overcurrent condition still exists, it will repeat the shutdown-
wait-restart event. This is called a “hiccup” event. The
Output Voltage Selection
Users can set the output voltage of the variable version with
a resister divider, which can be chosen based on the
following formula:
R
⎛
⎞
⎟
⎠
2
V
= 0.8 × 1 + ------
⎜
O
(EQ. 2)
R
⎝
1
FN6279.0
October 5, 2006
7
ISL97536
lead at a frequency of ~2.5kHz. The zero will always appear
Component Selection
at lower frequency than the pole and follow the equation
below:
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
Capacitors must be chosen in the range of 10µF to 40µF,
multilayer ceramic capacitors with X5R or X7R rating for
both the input and output capacitors, and inductors in the
range of 1.5µH to 2.2µH.
1
f
= ----------------------
Z
2πR C
(EQ. 5)
2
4
Over a normal range of R (~10-100k), C will range from
2
4
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R
1
The RMS current present at the input capacitor is decided by
the following formula:
and R , which is solely determined by the desired output set
2
point. The equation below shows the pole frequency
relationship:
V
× (V – V )
IN O
O
-----------------------------------------------
I
=
× I
INRMS
O
(EQ. 3)
V
IN
1
f
= ---------------------------------------
P
2π(R R )C
4
(EQ. 6)
1
2
This is about half of the output current I for all the V . This
O
O
input capacitor must be able to handle this current.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
The inductor peak-to-peak ripple current is given as:
(V – V ) × V
O
IN
O
∆I = -------------------------------------------
IL
L × V × f
(EQ. 4)
IN
S
1. Separate the Power Ground ( ) and Signal Ground
(
); connect them only at one point right at the pins
L is the inductance
the switching frequency (nominally 1.4MHz)
2. Place the input capacitor as close to V and PGND pins
IN
f
S
as possible
3. Make the following PC traces as small as possible:
- from LX pin to L
The inductor must be able to handle I for the RMS load
O
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
- from C to PGND
O
4. If used, connect the trace from the FB pin to R and R
1
2
as close as possible
In addition to decoupling capacitors and inductor value, it is
5. Maximize the copper area around the PGND pin
important to properly size the phase-lead capacitor C
4
6. Place several via holes under the chip to additional
ground plane to improve heat dissipation
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
The demo board is a good example of layout based on this
outline. Please refer to the ISL97536 Application Brief.
general rule of thumb, C should be sized to start the phase-
4
FN6279.0
October 5, 2006
8
ISL97536
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
N
A
A1
A2
b
-
±0.05
-
±0.09
-
E
E1
PIN #1
I.D.
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
E
±0.15
-
1
B
(N/2)
E1
e
±0.10
2, 3
Basic
-
L
±0.15
-
e
H
C
L1
N
Basic
-
SEATING
PLANE
Reference
-
Rev. C 6/99
M
C A B
b
0.08
0.10 C
NOTES:
N LEADS
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
L1
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3° ±3°
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6279.0
October 5, 2006
9
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